Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver core code | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* | |
36 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
37 | * | |
38 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
39 | * controller driver implementing the "Gadget" API; OTG support is | |
40 | * in the works. These are normal Linux-USB controller drivers which | |
41 | * use IRQs and have no dedicated thread. | |
42 | * | |
43 | * This version of the driver has only been used with products from | |
44 | * Texas Instruments. Those products integrate the Inventra logic | |
45 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
46 | * needs to be reflected in this driver. | |
47 | * | |
48 | * | |
49 | * NOTE: the original Mentor code here was pretty much a collection | |
50 | * of mechanisms that don't seem to have been fully integrated/working | |
51 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
52 | * Key open issues include: | |
53 | * | |
54 | * - Lack of host-side transaction scheduling, for all transfer types. | |
55 | * The hardware doesn't do it; instead, software must. | |
56 | * | |
57 | * This is not an issue for OTG devices that don't support external | |
58 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
59 | * "multipoint" support doesn't scale in the expected ways. That | |
60 | * includes DaVinci EVM in a common non-OTG mode. | |
61 | * | |
62 | * * Control and bulk use dedicated endpoints, and there's as | |
63 | * yet no mechanism to either (a) reclaim the hardware when | |
64 | * peripherals are NAKing, which gets complicated with bulk | |
65 | * endpoints, or (b) use more than a single bulk endpoint in | |
66 | * each direction. | |
67 | * | |
68 | * RESULT: one device may be perceived as blocking another one. | |
69 | * | |
70 | * * Interrupt and isochronous will dynamically allocate endpoint | |
71 | * hardware, but (a) there's no record keeping for bandwidth; | |
72 | * (b) in the common case that few endpoints are available, there | |
73 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
74 | * | |
75 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
76 | * some hardware configurations, no faults will be reported. | |
77 | * At the other extreme, the bandwidth capabilities which do | |
78 | * exist tend to be severely undercommitted. You can't yet hook | |
79 | * up both a keyboard and a mouse to an external USB hub. | |
80 | */ | |
81 | ||
82 | /* | |
83 | * This gets many kinds of configuration information: | |
84 | * - Kconfig for everything user-configurable | |
550a7375 FB |
85 | * - platform_device for addressing, irq, and platform_data |
86 | * - platform_data is mostly for board-specific informarion | |
c767c1c6 | 87 | * (plus recentrly, SOC or family details) |
550a7375 FB |
88 | * |
89 | * Most of the conditional compilation will (someday) vanish. | |
90 | */ | |
91 | ||
92 | #include <linux/module.h> | |
93 | #include <linux/kernel.h> | |
94 | #include <linux/sched.h> | |
95 | #include <linux/slab.h> | |
96 | #include <linux/init.h> | |
97 | #include <linux/list.h> | |
98 | #include <linux/kobject.h> | |
9303961f | 99 | #include <linux/prefetch.h> |
550a7375 FB |
100 | #include <linux/platform_device.h> |
101 | #include <linux/io.h> | |
102 | ||
550a7375 FB |
103 | #include "musb_core.h" |
104 | ||
f7f9d63e | 105 | #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) |
550a7375 FB |
106 | |
107 | ||
550a7375 FB |
108 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" |
109 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
110 | ||
e8164f64 | 111 | #define MUSB_VERSION "6.0" |
550a7375 FB |
112 | |
113 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
114 | ||
05ac10dd | 115 | #define MUSB_DRIVER_NAME "musb-hdrc" |
550a7375 FB |
116 | const char musb_driver_name[] = MUSB_DRIVER_NAME; |
117 | ||
118 | MODULE_DESCRIPTION(DRIVER_INFO); | |
119 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
120 | MODULE_LICENSE("GPL"); | |
121 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
122 | ||
123 | ||
124 | /*-------------------------------------------------------------------------*/ | |
125 | ||
126 | static inline struct musb *dev_to_musb(struct device *dev) | |
127 | { | |
550a7375 | 128 | return dev_get_drvdata(dev); |
550a7375 FB |
129 | } |
130 | ||
131 | /*-------------------------------------------------------------------------*/ | |
132 | ||
ffb865b1 | 133 | #ifndef CONFIG_BLACKFIN |
86753811 | 134 | static int musb_ulpi_read(struct usb_phy *otg, u32 offset) |
ffb865b1 HK |
135 | { |
136 | void __iomem *addr = otg->io_priv; | |
137 | int i = 0; | |
138 | u8 r; | |
139 | u8 power; | |
140 | ||
141 | /* Make sure the transceiver is not in low power mode */ | |
142 | power = musb_readb(addr, MUSB_POWER); | |
143 | power &= ~MUSB_POWER_SUSPENDM; | |
144 | musb_writeb(addr, MUSB_POWER, power); | |
145 | ||
146 | /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the | |
147 | * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. | |
148 | */ | |
149 | ||
150 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
151 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, | |
152 | MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); | |
153 | ||
154 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
155 | & MUSB_ULPI_REG_CMPLT)) { | |
156 | i++; | |
5c8a86e1 | 157 | if (i == 10000) |
ffb865b1 | 158 | return -ETIMEDOUT; |
ffb865b1 HK |
159 | |
160 | } | |
161 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
162 | r &= ~MUSB_ULPI_REG_CMPLT; | |
163 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
164 | ||
165 | return musb_readb(addr, MUSB_ULPI_REG_DATA); | |
166 | } | |
167 | ||
86753811 | 168 | static int musb_ulpi_write(struct usb_phy *otg, |
ffb865b1 HK |
169 | u32 offset, u32 data) |
170 | { | |
171 | void __iomem *addr = otg->io_priv; | |
172 | int i = 0; | |
173 | u8 r = 0; | |
174 | u8 power; | |
175 | ||
176 | /* Make sure the transceiver is not in low power mode */ | |
177 | power = musb_readb(addr, MUSB_POWER); | |
178 | power &= ~MUSB_POWER_SUSPENDM; | |
179 | musb_writeb(addr, MUSB_POWER, power); | |
180 | ||
181 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
182 | musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); | |
183 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); | |
184 | ||
185 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
186 | & MUSB_ULPI_REG_CMPLT)) { | |
187 | i++; | |
5c8a86e1 | 188 | if (i == 10000) |
ffb865b1 | 189 | return -ETIMEDOUT; |
ffb865b1 HK |
190 | } |
191 | ||
192 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
193 | r &= ~MUSB_ULPI_REG_CMPLT; | |
194 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | #else | |
f2263db7 MF |
199 | #define musb_ulpi_read NULL |
200 | #define musb_ulpi_write NULL | |
ffb865b1 HK |
201 | #endif |
202 | ||
203 | static struct otg_io_access_ops musb_ulpi_access = { | |
204 | .read = musb_ulpi_read, | |
205 | .write = musb_ulpi_write, | |
206 | }; | |
207 | ||
208 | /*-------------------------------------------------------------------------*/ | |
209 | ||
7c925546 | 210 | #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) |
c6cf8b00 | 211 | |
550a7375 FB |
212 | /* |
213 | * Load an endpoint's FIFO | |
214 | */ | |
215 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
216 | { | |
5c8a86e1 | 217 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
218 | void __iomem *fifo = hw_ep->fifo; |
219 | ||
220 | prefetch((u8 *)src); | |
221 | ||
5c8a86e1 | 222 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
223 | 'T', hw_ep->epnum, fifo, len, src); |
224 | ||
225 | /* we can't assume unaligned reads work */ | |
226 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
227 | u16 index = 0; | |
228 | ||
229 | /* best case is 32bit-aligned source address */ | |
230 | if ((0x02 & (unsigned long) src) == 0) { | |
231 | if (len >= 4) { | |
232 | writesl(fifo, src + index, len >> 2); | |
233 | index += len & ~0x03; | |
234 | } | |
235 | if (len & 0x02) { | |
236 | musb_writew(fifo, 0, *(u16 *)&src[index]); | |
237 | index += 2; | |
238 | } | |
239 | } else { | |
240 | if (len >= 2) { | |
241 | writesw(fifo, src + index, len >> 1); | |
242 | index += len & ~0x01; | |
243 | } | |
244 | } | |
245 | if (len & 0x01) | |
246 | musb_writeb(fifo, 0, src[index]); | |
247 | } else { | |
248 | /* byte aligned */ | |
249 | writesb(fifo, src, len); | |
250 | } | |
251 | } | |
252 | ||
843bb1d0 | 253 | #if !defined(CONFIG_USB_MUSB_AM35X) |
550a7375 FB |
254 | /* |
255 | * Unload an endpoint's FIFO | |
256 | */ | |
257 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
258 | { | |
5c8a86e1 | 259 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
260 | void __iomem *fifo = hw_ep->fifo; |
261 | ||
5c8a86e1 | 262 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
263 | 'R', hw_ep->epnum, fifo, len, dst); |
264 | ||
265 | /* we can't assume unaligned writes work */ | |
266 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
267 | u16 index = 0; | |
268 | ||
269 | /* best case is 32bit-aligned destination address */ | |
270 | if ((0x02 & (unsigned long) dst) == 0) { | |
271 | if (len >= 4) { | |
272 | readsl(fifo, dst, len >> 2); | |
273 | index = len & ~0x03; | |
274 | } | |
275 | if (len & 0x02) { | |
276 | *(u16 *)&dst[index] = musb_readw(fifo, 0); | |
277 | index += 2; | |
278 | } | |
279 | } else { | |
280 | if (len >= 2) { | |
281 | readsw(fifo, dst, len >> 1); | |
282 | index = len & ~0x01; | |
283 | } | |
284 | } | |
285 | if (len & 0x01) | |
286 | dst[index] = musb_readb(fifo, 0); | |
287 | } else { | |
288 | /* byte aligned */ | |
289 | readsb(fifo, dst, len); | |
290 | } | |
291 | } | |
843bb1d0 | 292 | #endif |
550a7375 FB |
293 | |
294 | #endif /* normal PIO */ | |
295 | ||
296 | ||
297 | /*-------------------------------------------------------------------------*/ | |
298 | ||
299 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
300 | static const u8 musb_test_packet[53] = { | |
301 | /* implicit SYNC then DATA0 to start */ | |
302 | ||
303 | /* JKJKJKJK x9 */ | |
304 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
305 | /* JJKKJJKK x8 */ | |
306 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
307 | /* JJJJKKKK x8 */ | |
308 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
309 | /* JJJJJJJKKKKKKK x8 */ | |
310 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
311 | /* JJJJJJJK x8 */ | |
312 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
313 | /* JKKKKKKK x10, JK */ | |
314 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
315 | ||
316 | /* implicit CRC16 then EOP to end */ | |
317 | }; | |
318 | ||
319 | void musb_load_testpacket(struct musb *musb) | |
320 | { | |
321 | void __iomem *regs = musb->endpoints[0].regs; | |
322 | ||
323 | musb_ep_select(musb->mregs, 0); | |
324 | musb_write_fifo(musb->control_ep, | |
325 | sizeof(musb_test_packet), musb_test_packet); | |
326 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
327 | } | |
328 | ||
329 | /*-------------------------------------------------------------------------*/ | |
330 | ||
550a7375 FB |
331 | /* |
332 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
333 | */ | |
334 | void musb_otg_timer_func(unsigned long data) | |
335 | { | |
336 | struct musb *musb = (struct musb *)data; | |
337 | unsigned long flags; | |
338 | ||
339 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 340 | switch (musb->xceiv->state) { |
550a7375 | 341 | case OTG_STATE_B_WAIT_ACON: |
5c8a86e1 | 342 | dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); |
550a7375 | 343 | musb_g_disconnect(musb); |
84e250ff | 344 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
345 | musb->is_active = 0; |
346 | break; | |
ab983f2a | 347 | case OTG_STATE_A_SUSPEND: |
550a7375 | 348 | case OTG_STATE_A_WAIT_BCON: |
5c8a86e1 | 349 | dev_dbg(musb->controller, "HNP: %s timeout\n", |
3df00453 | 350 | otg_state_string(musb->xceiv->state)); |
743411b3 | 351 | musb_platform_set_vbus(musb, 0); |
ab983f2a | 352 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
353 | break; |
354 | default: | |
5c8a86e1 | 355 | dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", |
3df00453 | 356 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
357 | } |
358 | musb->ignore_disconnect = 0; | |
359 | spin_unlock_irqrestore(&musb->lock, flags); | |
360 | } | |
361 | ||
550a7375 | 362 | /* |
f7f9d63e | 363 | * Stops the HNP transition. Caller must take care of locking. |
550a7375 FB |
364 | */ |
365 | void musb_hnp_stop(struct musb *musb) | |
366 | { | |
367 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
368 | void __iomem *mbase = musb->mregs; | |
369 | u8 reg; | |
370 | ||
5c8a86e1 | 371 | dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); |
ab983f2a | 372 | |
84e250ff | 373 | switch (musb->xceiv->state) { |
550a7375 | 374 | case OTG_STATE_A_PERIPHERAL: |
550a7375 | 375 | musb_g_disconnect(musb); |
5c8a86e1 | 376 | dev_dbg(musb->controller, "HNP: back to %s\n", |
3df00453 | 377 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
378 | break; |
379 | case OTG_STATE_B_HOST: | |
5c8a86e1 | 380 | dev_dbg(musb->controller, "HNP: Disabling HR\n"); |
550a7375 | 381 | hcd->self.is_b_host = 0; |
84e250ff | 382 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
383 | MUSB_DEV_MODE(musb); |
384 | reg = musb_readb(mbase, MUSB_POWER); | |
385 | reg |= MUSB_POWER_SUSPENDM; | |
386 | musb_writeb(mbase, MUSB_POWER, reg); | |
387 | /* REVISIT: Start SESSION_REQUEST here? */ | |
388 | break; | |
389 | default: | |
5c8a86e1 | 390 | dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", |
3df00453 | 391 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
392 | } |
393 | ||
394 | /* | |
395 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
396 | * which cause occasional OPT A "Did not receive reset after connect" | |
397 | * errors. | |
398 | */ | |
749da5f8 | 399 | musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); |
550a7375 FB |
400 | } |
401 | ||
550a7375 FB |
402 | /* |
403 | * Interrupt Service Routine to record USB "global" interrupts. | |
404 | * Since these do not happen often and signify things of | |
405 | * paramount importance, it seems OK to check them individually; | |
406 | * the order of the tests is specified in the manual | |
407 | * | |
408 | * @param musb instance pointer | |
409 | * @param int_usb register contents | |
410 | * @param devctl | |
411 | * @param power | |
412 | */ | |
413 | ||
550a7375 FB |
414 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, |
415 | u8 devctl, u8 power) | |
416 | { | |
d445b6da | 417 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 | 418 | irqreturn_t handled = IRQ_NONE; |
550a7375 | 419 | |
5c8a86e1 | 420 | dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, |
550a7375 FB |
421 | int_usb); |
422 | ||
423 | /* in host mode, the peripheral may issue remote wakeup. | |
424 | * in peripheral mode, the host may resume the link. | |
425 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
426 | */ | |
427 | if (int_usb & MUSB_INTR_RESUME) { | |
428 | handled = IRQ_HANDLED; | |
5c8a86e1 | 429 | dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); |
550a7375 FB |
430 | |
431 | if (devctl & MUSB_DEVCTL_HM) { | |
aa471456 FB |
432 | void __iomem *mbase = musb->mregs; |
433 | ||
84e250ff | 434 | switch (musb->xceiv->state) { |
550a7375 FB |
435 | case OTG_STATE_A_SUSPEND: |
436 | /* remote wakeup? later, GetPortStatus | |
437 | * will stop RESUME signaling | |
438 | */ | |
439 | ||
440 | if (power & MUSB_POWER_SUSPENDM) { | |
441 | /* spurious */ | |
442 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
5c8a86e1 | 443 | dev_dbg(musb->controller, "Spurious SUSPENDM\n"); |
550a7375 FB |
444 | break; |
445 | } | |
446 | ||
447 | power &= ~MUSB_POWER_SUSPENDM; | |
448 | musb_writeb(mbase, MUSB_POWER, | |
449 | power | MUSB_POWER_RESUME); | |
450 | ||
451 | musb->port1_status |= | |
452 | (USB_PORT_STAT_C_SUSPEND << 16) | |
453 | | MUSB_PORT_STAT_RESUME; | |
454 | musb->rh_timer = jiffies | |
455 | + msecs_to_jiffies(20); | |
456 | ||
84e250ff | 457 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
458 | musb->is_active = 1; |
459 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
460 | break; | |
461 | case OTG_STATE_B_WAIT_ACON: | |
84e250ff | 462 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
463 | musb->is_active = 1; |
464 | MUSB_DEV_MODE(musb); | |
465 | break; | |
466 | default: | |
467 | WARNING("bogus %s RESUME (%s)\n", | |
468 | "host", | |
3df00453 | 469 | otg_state_string(musb->xceiv->state)); |
550a7375 | 470 | } |
550a7375 | 471 | } else { |
84e250ff | 472 | switch (musb->xceiv->state) { |
550a7375 FB |
473 | case OTG_STATE_A_SUSPEND: |
474 | /* possibly DISCONNECT is upcoming */ | |
84e250ff | 475 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
476 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); |
477 | break; | |
550a7375 FB |
478 | case OTG_STATE_B_WAIT_ACON: |
479 | case OTG_STATE_B_PERIPHERAL: | |
480 | /* disconnect while suspended? we may | |
481 | * not get a disconnect irq... | |
482 | */ | |
483 | if ((devctl & MUSB_DEVCTL_VBUS) | |
484 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
485 | ) { | |
486 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
487 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
488 | break; | |
489 | } | |
490 | musb_g_resume(musb); | |
491 | break; | |
492 | case OTG_STATE_B_IDLE: | |
493 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
494 | break; | |
550a7375 FB |
495 | default: |
496 | WARNING("bogus %s RESUME (%s)\n", | |
497 | "peripheral", | |
3df00453 | 498 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
499 | } |
500 | } | |
501 | } | |
502 | ||
550a7375 FB |
503 | /* see manual for the order of the tests */ |
504 | if (int_usb & MUSB_INTR_SESSREQ) { | |
aa471456 FB |
505 | void __iomem *mbase = musb->mregs; |
506 | ||
19aab56c HK |
507 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS |
508 | && (devctl & MUSB_DEVCTL_BDEVICE)) { | |
5c8a86e1 | 509 | dev_dbg(musb->controller, "SessReq while on B state\n"); |
a6038ee7 HK |
510 | return IRQ_HANDLED; |
511 | } | |
512 | ||
5c8a86e1 | 513 | dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", |
3df00453 | 514 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
515 | |
516 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
517 | * is removed) SRP. responses are time critical: | |
518 | * - turn on VBUS (with silicon-specific mechanism) | |
519 | * - go through A_WAIT_VRISE | |
520 | * - ... to A_WAIT_BCON. | |
521 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
522 | */ | |
523 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
524 | musb->ep0_stage = MUSB_EP0_START; | |
84e250ff | 525 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 | 526 | MUSB_HST_MODE(musb); |
743411b3 | 527 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
528 | |
529 | handled = IRQ_HANDLED; | |
530 | } | |
531 | ||
532 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
533 | int ignore = 0; | |
534 | ||
535 | /* During connection as an A-Device, we may see a short | |
536 | * current spikes causing voltage drop, because of cable | |
537 | * and peripheral capacitance combined with vbus draw. | |
538 | * (So: less common with truly self-powered devices, where | |
539 | * vbus doesn't act like a power supply.) | |
540 | * | |
541 | * Such spikes are short; usually less than ~500 usec, max | |
542 | * of ~2 msec. That is, they're not sustained overcurrent | |
543 | * errors, though they're reported using VBUSERROR irqs. | |
544 | * | |
545 | * Workarounds: (a) hardware: use self powered devices. | |
546 | * (b) software: ignore non-repeated VBUS errors. | |
547 | * | |
548 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
549 | * make trouble here, keeping VBUS < 4.4V ? | |
550 | */ | |
84e250ff | 551 | switch (musb->xceiv->state) { |
550a7375 FB |
552 | case OTG_STATE_A_HOST: |
553 | /* recovery is dicey once we've gotten past the | |
554 | * initial stages of enumeration, but if VBUS | |
555 | * stayed ok at the other end of the link, and | |
556 | * another reset is due (at least for high speed, | |
557 | * to redo the chirp etc), it might work OK... | |
558 | */ | |
559 | case OTG_STATE_A_WAIT_BCON: | |
560 | case OTG_STATE_A_WAIT_VRISE: | |
561 | if (musb->vbuserr_retry) { | |
aa471456 FB |
562 | void __iomem *mbase = musb->mregs; |
563 | ||
550a7375 FB |
564 | musb->vbuserr_retry--; |
565 | ignore = 1; | |
566 | devctl |= MUSB_DEVCTL_SESSION; | |
567 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
568 | } else { | |
569 | musb->port1_status |= | |
749da5f8 AS |
570 | USB_PORT_STAT_OVERCURRENT |
571 | | (USB_PORT_STAT_C_OVERCURRENT << 16); | |
550a7375 FB |
572 | } |
573 | break; | |
574 | default: | |
575 | break; | |
576 | } | |
577 | ||
5c8a86e1 | 578 | dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", |
3df00453 | 579 | otg_state_string(musb->xceiv->state), |
550a7375 FB |
580 | devctl, |
581 | ({ char *s; | |
582 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
583 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
584 | s = "<SessEnd"; break; | |
585 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
586 | s = "<AValid"; break; | |
587 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
588 | s = "<VBusValid"; break; | |
589 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
590 | default: | |
591 | s = "VALID"; break; | |
592 | }; s; }), | |
593 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, | |
594 | musb->port1_status); | |
595 | ||
596 | /* go through A_WAIT_VFALL then start a new session */ | |
597 | if (!ignore) | |
743411b3 | 598 | musb_platform_set_vbus(musb, 0); |
550a7375 FB |
599 | handled = IRQ_HANDLED; |
600 | } | |
601 | ||
1c25fda4 | 602 | if (int_usb & MUSB_INTR_SUSPEND) { |
5c8a86e1 | 603 | dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", |
3df00453 | 604 | otg_state_string(musb->xceiv->state), devctl, power); |
1c25fda4 AM |
605 | handled = IRQ_HANDLED; |
606 | ||
607 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
608 | case OTG_STATE_A_PERIPHERAL: |
609 | /* We also come here if the cable is removed, since | |
610 | * this silicon doesn't report ID-no-longer-grounded. | |
611 | * | |
612 | * We depend on T(a_wait_bcon) to shut us down, and | |
613 | * hope users don't do anything dicey during this | |
614 | * undesired detour through A_WAIT_BCON. | |
615 | */ | |
616 | musb_hnp_stop(musb); | |
617 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
618 | musb_root_disconnect(musb); | |
619 | musb_platform_try_idle(musb, jiffies | |
620 | + msecs_to_jiffies(musb->a_wait_bcon | |
621 | ? : OTG_TIME_A_WAIT_BCON)); | |
622 | ||
623 | break; | |
1c25fda4 AM |
624 | case OTG_STATE_B_IDLE: |
625 | if (!musb->is_active) | |
626 | break; | |
627 | case OTG_STATE_B_PERIPHERAL: | |
628 | musb_g_suspend(musb); | |
629 | musb->is_active = is_otg_enabled(musb) | |
d445b6da | 630 | && otg->gadget->b_hnp_enable; |
1c25fda4 | 631 | if (musb->is_active) { |
1c25fda4 | 632 | musb->xceiv->state = OTG_STATE_B_WAIT_ACON; |
5c8a86e1 | 633 | dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); |
1c25fda4 AM |
634 | mod_timer(&musb->otg_timer, jiffies |
635 | + msecs_to_jiffies( | |
636 | OTG_TIME_B_ASE0_BRST)); | |
1c25fda4 AM |
637 | } |
638 | break; | |
639 | case OTG_STATE_A_WAIT_BCON: | |
640 | if (musb->a_wait_bcon != 0) | |
641 | musb_platform_try_idle(musb, jiffies | |
642 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
643 | break; | |
644 | case OTG_STATE_A_HOST: | |
645 | musb->xceiv->state = OTG_STATE_A_SUSPEND; | |
646 | musb->is_active = is_otg_enabled(musb) | |
d445b6da | 647 | && otg->host->b_hnp_enable; |
1c25fda4 AM |
648 | break; |
649 | case OTG_STATE_B_HOST: | |
650 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
5c8a86e1 | 651 | dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); |
1c25fda4 AM |
652 | break; |
653 | default: | |
654 | /* "should not happen" */ | |
655 | musb->is_active = 0; | |
656 | break; | |
657 | } | |
658 | } | |
659 | ||
550a7375 FB |
660 | if (int_usb & MUSB_INTR_CONNECT) { |
661 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
662 | ||
663 | handled = IRQ_HANDLED; | |
664 | musb->is_active = 1; | |
550a7375 FB |
665 | |
666 | musb->ep0_stage = MUSB_EP0_START; | |
667 | ||
550a7375 FB |
668 | /* flush endpoints when transitioning from Device Mode */ |
669 | if (is_peripheral_active(musb)) { | |
670 | /* REVISIT HNP; just force disconnect */ | |
671 | } | |
d709d22e AKG |
672 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); |
673 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
674 | musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); | |
550a7375 FB |
675 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |
676 | |USB_PORT_STAT_HIGH_SPEED | |
677 | |USB_PORT_STAT_ENABLE | |
678 | ); | |
679 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
680 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
681 | ||
682 | /* high vs full speed is just a guess until after reset */ | |
683 | if (devctl & MUSB_DEVCTL_LSDEV) | |
684 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
685 | ||
550a7375 | 686 | /* indicate new connection to OTG machine */ |
84e250ff | 687 | switch (musb->xceiv->state) { |
550a7375 FB |
688 | case OTG_STATE_B_PERIPHERAL: |
689 | if (int_usb & MUSB_INTR_SUSPEND) { | |
5c8a86e1 | 690 | dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); |
550a7375 | 691 | int_usb &= ~MUSB_INTR_SUSPEND; |
1de00dae | 692 | goto b_host; |
550a7375 | 693 | } else |
5c8a86e1 | 694 | dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); |
550a7375 FB |
695 | break; |
696 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 697 | dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); |
1de00dae | 698 | b_host: |
84e250ff | 699 | musb->xceiv->state = OTG_STATE_B_HOST; |
550a7375 | 700 | hcd->self.is_b_host = 1; |
1de00dae DB |
701 | musb->ignore_disconnect = 0; |
702 | del_timer(&musb->otg_timer); | |
550a7375 FB |
703 | break; |
704 | default: | |
705 | if ((devctl & MUSB_DEVCTL_VBUS) | |
706 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
84e250ff | 707 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
708 | hcd->self.is_b_host = 0; |
709 | } | |
710 | break; | |
711 | } | |
1de00dae DB |
712 | |
713 | /* poke the root hub */ | |
714 | MUSB_HST_MODE(musb); | |
715 | if (hcd->status_urb) | |
716 | usb_hcd_poll_rh_status(hcd); | |
717 | else | |
718 | usb_hcd_resume_root_hub(hcd); | |
719 | ||
5c8a86e1 | 720 | dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", |
3df00453 | 721 | otg_state_string(musb->xceiv->state), devctl); |
550a7375 | 722 | } |
550a7375 | 723 | |
1c25fda4 | 724 | if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { |
5c8a86e1 | 725 | dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", |
3df00453 | 726 | otg_state_string(musb->xceiv->state), |
1c25fda4 AM |
727 | MUSB_MODE(musb), devctl); |
728 | handled = IRQ_HANDLED; | |
729 | ||
730 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
731 | case OTG_STATE_A_HOST: |
732 | case OTG_STATE_A_SUSPEND: | |
733 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
734 | musb_root_disconnect(musb); | |
735 | if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) | |
736 | musb_platform_try_idle(musb, jiffies | |
737 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
738 | break; | |
1c25fda4 AM |
739 | case OTG_STATE_B_HOST: |
740 | /* REVISIT this behaves for "real disconnect" | |
741 | * cases; make sure the other transitions from | |
742 | * from B_HOST act right too. The B_HOST code | |
743 | * in hnp_stop() is currently not used... | |
744 | */ | |
745 | musb_root_disconnect(musb); | |
746 | musb_to_hcd(musb)->self.is_b_host = 0; | |
747 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; | |
748 | MUSB_DEV_MODE(musb); | |
749 | musb_g_disconnect(musb); | |
750 | break; | |
751 | case OTG_STATE_A_PERIPHERAL: | |
752 | musb_hnp_stop(musb); | |
753 | musb_root_disconnect(musb); | |
754 | /* FALLTHROUGH */ | |
755 | case OTG_STATE_B_WAIT_ACON: | |
756 | /* FALLTHROUGH */ | |
1c25fda4 AM |
757 | case OTG_STATE_B_PERIPHERAL: |
758 | case OTG_STATE_B_IDLE: | |
759 | musb_g_disconnect(musb); | |
760 | break; | |
1c25fda4 AM |
761 | default: |
762 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
3df00453 | 763 | otg_state_string(musb->xceiv->state)); |
1c25fda4 AM |
764 | break; |
765 | } | |
766 | } | |
767 | ||
550a7375 FB |
768 | /* mentor saves a bit: bus reset and babble share the same irq. |
769 | * only host sees babble; only peripheral sees bus reset. | |
770 | */ | |
771 | if (int_usb & MUSB_INTR_RESET) { | |
1c25fda4 | 772 | handled = IRQ_HANDLED; |
550a7375 FB |
773 | if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { |
774 | /* | |
775 | * Looks like non-HS BABBLE can be ignored, but | |
776 | * HS BABBLE is an error condition. For HS the solution | |
777 | * is to avoid babble in the first place and fix what | |
778 | * caused BABBLE. When HS BABBLE happens we can only | |
779 | * stop the session. | |
780 | */ | |
781 | if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) | |
5c8a86e1 | 782 | dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); |
550a7375 FB |
783 | else { |
784 | ERR("Stopping host session -- babble\n"); | |
1c25fda4 | 785 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
550a7375 FB |
786 | } |
787 | } else if (is_peripheral_capable()) { | |
5c8a86e1 | 788 | dev_dbg(musb->controller, "BUS RESET as %s\n", |
3df00453 | 789 | otg_state_string(musb->xceiv->state)); |
84e250ff | 790 | switch (musb->xceiv->state) { |
550a7375 FB |
791 | case OTG_STATE_A_SUSPEND: |
792 | /* We need to ignore disconnect on suspend | |
793 | * otherwise tusb 2.0 won't reconnect after a | |
794 | * power cycle, which breaks otg compliance. | |
795 | */ | |
796 | musb->ignore_disconnect = 1; | |
797 | musb_g_reset(musb); | |
798 | /* FALLTHROUGH */ | |
799 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
f7f9d63e | 800 | /* never use invalid T(a_wait_bcon) */ |
5c8a86e1 | 801 | dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", |
3df00453 AG |
802 | otg_state_string(musb->xceiv->state), |
803 | TA_WAIT_BCON(musb)); | |
f7f9d63e DB |
804 | mod_timer(&musb->otg_timer, jiffies |
805 | + msecs_to_jiffies(TA_WAIT_BCON(musb))); | |
550a7375 FB |
806 | break; |
807 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae DB |
808 | musb->ignore_disconnect = 0; |
809 | del_timer(&musb->otg_timer); | |
810 | musb_g_reset(musb); | |
550a7375 FB |
811 | break; |
812 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 813 | dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", |
3df00453 | 814 | otg_state_string(musb->xceiv->state)); |
84e250ff | 815 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
816 | musb_g_reset(musb); |
817 | break; | |
550a7375 | 818 | case OTG_STATE_B_IDLE: |
84e250ff | 819 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
820 | /* FALLTHROUGH */ |
821 | case OTG_STATE_B_PERIPHERAL: | |
822 | musb_g_reset(musb); | |
823 | break; | |
824 | default: | |
5c8a86e1 | 825 | dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", |
3df00453 | 826 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
827 | } |
828 | } | |
550a7375 | 829 | } |
550a7375 FB |
830 | |
831 | #if 0 | |
832 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
833 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
834 | * limits of a given frame or microframe. | |
835 | * | |
836 | * It's not needed for peripheral side, which dedicates endpoints; | |
837 | * though it _might_ use SOF irqs for other purposes. | |
838 | * | |
839 | * And it's not currently needed for host side, which also dedicates | |
840 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
841 | * to support ISO transfers yet. | |
842 | */ | |
843 | if (int_usb & MUSB_INTR_SOF) { | |
844 | void __iomem *mbase = musb->mregs; | |
845 | struct musb_hw_ep *ep; | |
846 | u8 epnum; | |
847 | u16 frame; | |
848 | ||
5c8a86e1 | 849 | dev_dbg(musb->controller, "START_OF_FRAME\n"); |
550a7375 FB |
850 | handled = IRQ_HANDLED; |
851 | ||
852 | /* start any periodic Tx transfers waiting for current frame */ | |
853 | frame = musb_readw(mbase, MUSB_FRAME); | |
854 | ep = musb->endpoints; | |
855 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
856 | && (musb->epmask >= (1 << epnum)); | |
857 | epnum++, ep++) { | |
858 | /* | |
859 | * FIXME handle framecounter wraps (12 bits) | |
860 | * eliminate duplicated StartUrb logic | |
861 | */ | |
862 | if (ep->dwWaitFrame >= frame) { | |
863 | ep->dwWaitFrame = 0; | |
864 | pr_debug("SOF --> periodic TX%s on %d\n", | |
865 | ep->tx_channel ? " DMA" : "", | |
866 | epnum); | |
867 | if (!ep->tx_channel) | |
868 | musb_h_tx_start(musb, epnum); | |
869 | else | |
870 | cppi_hostdma_start(musb, epnum); | |
871 | } | |
872 | } /* end of for loop */ | |
873 | } | |
874 | #endif | |
875 | ||
1c25fda4 | 876 | schedule_work(&musb->irq_work); |
550a7375 FB |
877 | |
878 | return handled; | |
879 | } | |
880 | ||
881 | /*-------------------------------------------------------------------------*/ | |
882 | ||
883 | /* | |
884 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
885 | */ | |
886 | void musb_start(struct musb *musb) | |
887 | { | |
888 | void __iomem *regs = musb->mregs; | |
889 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
890 | ||
5c8a86e1 | 891 | dev_dbg(musb->controller, "<== devctl %02x\n", devctl); |
550a7375 FB |
892 | |
893 | /* Set INT enable registers, enable interrupts */ | |
894 | musb_writew(regs, MUSB_INTRTXE, musb->epmask); | |
895 | musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
896 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); | |
897 | ||
898 | musb_writeb(regs, MUSB_TESTMODE, 0); | |
899 | ||
900 | /* put into basic highspeed mode and start session */ | |
901 | musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE | |
550a7375 FB |
902 | | MUSB_POWER_HSENAB |
903 | /* ENSUSPEND wedges tusb */ | |
904 | /* | MUSB_POWER_ENSUSPEND */ | |
905 | ); | |
906 | ||
907 | musb->is_active = 0; | |
908 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
909 | devctl &= ~MUSB_DEVCTL_SESSION; | |
910 | ||
911 | if (is_otg_enabled(musb)) { | |
912 | /* session started after: | |
913 | * (a) ID-grounded irq, host mode; | |
914 | * (b) vbus present/connect IRQ, peripheral mode; | |
915 | * (c) peripheral initiates, using SRP | |
916 | */ | |
917 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
918 | musb->is_active = 1; | |
919 | else | |
920 | devctl |= MUSB_DEVCTL_SESSION; | |
921 | ||
922 | } else if (is_host_enabled(musb)) { | |
923 | /* assume ID pin is hard-wired to ground */ | |
924 | devctl |= MUSB_DEVCTL_SESSION; | |
925 | ||
926 | } else /* peripheral is enabled */ { | |
927 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
928 | musb->is_active = 1; | |
929 | } | |
930 | musb_platform_enable(musb); | |
931 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
932 | } | |
933 | ||
934 | ||
935 | static void musb_generic_disable(struct musb *musb) | |
936 | { | |
937 | void __iomem *mbase = musb->mregs; | |
938 | u16 temp; | |
939 | ||
940 | /* disable interrupts */ | |
941 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
942 | musb_writew(mbase, MUSB_INTRTXE, 0); | |
943 | musb_writew(mbase, MUSB_INTRRXE, 0); | |
944 | ||
945 | /* off */ | |
946 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
947 | ||
948 | /* flush pending interrupts */ | |
949 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
950 | temp = musb_readw(mbase, MUSB_INTRTX); | |
951 | temp = musb_readw(mbase, MUSB_INTRRX); | |
952 | ||
953 | } | |
954 | ||
955 | /* | |
956 | * Make the HDRC stop (disable interrupts, etc.); | |
957 | * reversible by musb_start | |
958 | * called on gadget driver unregister | |
959 | * with controller locked, irqs blocked | |
960 | * acts as a NOP unless some role activated the hardware | |
961 | */ | |
962 | void musb_stop(struct musb *musb) | |
963 | { | |
964 | /* stop IRQs, timers, ... */ | |
965 | musb_platform_disable(musb); | |
966 | musb_generic_disable(musb); | |
5c8a86e1 | 967 | dev_dbg(musb->controller, "HDRC disabled\n"); |
550a7375 FB |
968 | |
969 | /* FIXME | |
970 | * - mark host and/or peripheral drivers unusable/inactive | |
971 | * - disable DMA (and enable it in HdrcStart) | |
972 | * - make sure we can musb_start() after musb_stop(); with | |
973 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
974 | * - ... | |
975 | */ | |
976 | musb_platform_try_idle(musb, 0); | |
977 | } | |
978 | ||
979 | static void musb_shutdown(struct platform_device *pdev) | |
980 | { | |
981 | struct musb *musb = dev_to_musb(&pdev->dev); | |
982 | unsigned long flags; | |
983 | ||
4f9edd2d | 984 | pm_runtime_get_sync(musb->controller); |
24307cae GI |
985 | |
986 | musb_gadget_cleanup(musb); | |
987 | ||
550a7375 FB |
988 | spin_lock_irqsave(&musb->lock, flags); |
989 | musb_platform_disable(musb); | |
990 | musb_generic_disable(musb); | |
550a7375 FB |
991 | spin_unlock_irqrestore(&musb->lock, flags); |
992 | ||
120d074c GI |
993 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) |
994 | usb_remove_hcd(musb_to_hcd(musb)); | |
995 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
996 | musb_platform_exit(musb); | |
120d074c | 997 | |
4f9edd2d | 998 | pm_runtime_put(musb->controller); |
550a7375 FB |
999 | /* FIXME power down */ |
1000 | } | |
1001 | ||
1002 | ||
1003 | /*-------------------------------------------------------------------------*/ | |
1004 | ||
1005 | /* | |
1006 | * The silicon either has hard-wired endpoint configurations, or else | |
1007 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
c767c1c6 DB |
1008 | * writing only the dynamic sizing is very well tested. Since we switched |
1009 | * away from compile-time hardware parameters, we can no longer rely on | |
1010 | * dead code elimination to leave only the relevant one in the object file. | |
550a7375 FB |
1011 | * |
1012 | * We don't currently use dynamic fifo setup capability to do anything | |
1013 | * more than selecting one of a bunch of predefined configurations. | |
1014 | */ | |
ee34e51a FB |
1015 | #if defined(CONFIG_USB_MUSB_TUSB6010) \ |
1016 | || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ | |
1017 | || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ | |
1018 | || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ | |
1019 | || defined(CONFIG_USB_MUSB_AM35X) \ | |
1020 | || defined(CONFIG_USB_MUSB_AM35X_MODULE) | |
550a7375 | 1021 | static ushort __initdata fifo_mode = 4; |
ee34e51a FB |
1022 | #elif defined(CONFIG_USB_MUSB_UX500) \ |
1023 | || defined(CONFIG_USB_MUSB_UX500_MODULE) | |
4bc36fd3 | 1024 | static ushort __initdata fifo_mode = 5; |
550a7375 FB |
1025 | #else |
1026 | static ushort __initdata fifo_mode = 2; | |
1027 | #endif | |
1028 | ||
1029 | /* "modprobe ... fifo_mode=1" etc */ | |
1030 | module_param(fifo_mode, ushort, 0); | |
1031 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
1032 | ||
550a7375 FB |
1033 | /* |
1034 | * tables defining fifo_mode values. define more if you like. | |
1035 | * for host side, make sure both halves of ep1 are set up. | |
1036 | */ | |
1037 | ||
1038 | /* mode 0 - fits in 2KB */ | |
e6c213b2 | 1039 | static struct musb_fifo_cfg __initdata mode_0_cfg[] = { |
550a7375 FB |
1040 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1041 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1042 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1043 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1044 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1045 | }; | |
1046 | ||
1047 | /* mode 1 - fits in 4KB */ | |
e6c213b2 | 1048 | static struct musb_fifo_cfg __initdata mode_1_cfg[] = { |
550a7375 FB |
1049 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1050 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1051 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1052 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1053 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1054 | }; | |
1055 | ||
1056 | /* mode 2 - fits in 4KB */ | |
e6c213b2 | 1057 | static struct musb_fifo_cfg __initdata mode_2_cfg[] = { |
550a7375 FB |
1058 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1059 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1060 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1061 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1062 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1063 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1064 | }; | |
1065 | ||
1066 | /* mode 3 - fits in 4KB */ | |
e6c213b2 | 1067 | static struct musb_fifo_cfg __initdata mode_3_cfg[] = { |
550a7375 FB |
1068 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1069 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1070 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1071 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1072 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1073 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1074 | }; | |
1075 | ||
1076 | /* mode 4 - fits in 16KB */ | |
e6c213b2 | 1077 | static struct musb_fifo_cfg __initdata mode_4_cfg[] = { |
550a7375 FB |
1078 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1079 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1080 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1081 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1082 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1083 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1084 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1085 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1086 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1087 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1088 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1089 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1090 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1091 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1092 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1093 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1094 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1095 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
a483d706 AKG |
1096 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, |
1097 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, | |
1098 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, | |
1099 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, | |
1100 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, | |
1101 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, | |
1102 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, | |
550a7375 FB |
1103 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
1104 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1105 | }; | |
1106 | ||
3b151526 | 1107 | /* mode 5 - fits in 8KB */ |
e6c213b2 | 1108 | static struct musb_fifo_cfg __initdata mode_5_cfg[] = { |
3b151526 AKG |
1109 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1110 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1111 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1112 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1113 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1114 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1115 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1116 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1117 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1118 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1119 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, | |
1120 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, | |
1121 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, | |
1122 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, | |
1123 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, | |
1124 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, | |
1125 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, | |
1126 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, | |
1127 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, | |
1128 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, | |
1129 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, | |
1130 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, | |
1131 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, | |
1132 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, | |
1133 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1134 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1135 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1136 | }; | |
550a7375 FB |
1137 | |
1138 | /* | |
1139 | * configure a fifo; for non-shared endpoints, this may be called | |
1140 | * once for a tx fifo and once for an rx fifo. | |
1141 | * | |
1142 | * returns negative errno or offset for next fifo. | |
1143 | */ | |
1144 | static int __init | |
1145 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, | |
e6c213b2 | 1146 | const struct musb_fifo_cfg *cfg, u16 offset) |
550a7375 FB |
1147 | { |
1148 | void __iomem *mbase = musb->mregs; | |
1149 | int size = 0; | |
1150 | u16 maxpacket = cfg->maxpacket; | |
1151 | u16 c_off = offset >> 3; | |
1152 | u8 c_size; | |
1153 | ||
1154 | /* expect hw_ep has already been zero-initialized */ | |
1155 | ||
1156 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1157 | maxpacket = 1 << size; | |
1158 | ||
1159 | c_size = size - 3; | |
1160 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1161 | if ((offset + (maxpacket << 1)) > |
1162 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1163 | return -EMSGSIZE; |
1164 | c_size |= MUSB_FIFOSZ_DPB; | |
1165 | } else { | |
ca6d1b13 | 1166 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1167 | return -EMSGSIZE; |
1168 | } | |
1169 | ||
1170 | /* configure the FIFO */ | |
1171 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1172 | ||
550a7375 FB |
1173 | /* EP0 reserved endpoint for control, bidirectional; |
1174 | * EP1 reserved for bulk, two unidirection halves. | |
1175 | */ | |
1176 | if (hw_ep->epnum == 1) | |
1177 | musb->bulk_ep = hw_ep; | |
1178 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
550a7375 FB |
1179 | switch (cfg->style) { |
1180 | case FIFO_TX: | |
c6cf8b00 BW |
1181 | musb_write_txfifosz(mbase, c_size); |
1182 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1183 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1184 | hw_ep->max_packet_sz_tx = maxpacket; | |
1185 | break; | |
1186 | case FIFO_RX: | |
c6cf8b00 BW |
1187 | musb_write_rxfifosz(mbase, c_size); |
1188 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1189 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1190 | hw_ep->max_packet_sz_rx = maxpacket; | |
1191 | break; | |
1192 | case FIFO_RXTX: | |
c6cf8b00 BW |
1193 | musb_write_txfifosz(mbase, c_size); |
1194 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1195 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1196 | hw_ep->max_packet_sz_rx = maxpacket; | |
1197 | ||
c6cf8b00 BW |
1198 | musb_write_rxfifosz(mbase, c_size); |
1199 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1200 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
1201 | hw_ep->max_packet_sz_tx = maxpacket; | |
1202 | ||
1203 | hw_ep->is_shared_fifo = true; | |
1204 | break; | |
1205 | } | |
1206 | ||
1207 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1208 | * which happens to be ok | |
1209 | */ | |
1210 | musb->epmask |= (1 << hw_ep->epnum); | |
1211 | ||
1212 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1213 | } | |
1214 | ||
e6c213b2 | 1215 | static struct musb_fifo_cfg __initdata ep0_cfg = { |
550a7375 FB |
1216 | .style = FIFO_RXTX, .maxpacket = 64, |
1217 | }; | |
1218 | ||
1219 | static int __init ep_config_from_table(struct musb *musb) | |
1220 | { | |
e6c213b2 | 1221 | const struct musb_fifo_cfg *cfg; |
550a7375 FB |
1222 | unsigned i, n; |
1223 | int offset; | |
1224 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1225 | ||
e6c213b2 FB |
1226 | if (musb->config->fifo_cfg) { |
1227 | cfg = musb->config->fifo_cfg; | |
1228 | n = musb->config->fifo_cfg_size; | |
1229 | goto done; | |
1230 | } | |
1231 | ||
550a7375 FB |
1232 | switch (fifo_mode) { |
1233 | default: | |
1234 | fifo_mode = 0; | |
1235 | /* FALLTHROUGH */ | |
1236 | case 0: | |
1237 | cfg = mode_0_cfg; | |
1238 | n = ARRAY_SIZE(mode_0_cfg); | |
1239 | break; | |
1240 | case 1: | |
1241 | cfg = mode_1_cfg; | |
1242 | n = ARRAY_SIZE(mode_1_cfg); | |
1243 | break; | |
1244 | case 2: | |
1245 | cfg = mode_2_cfg; | |
1246 | n = ARRAY_SIZE(mode_2_cfg); | |
1247 | break; | |
1248 | case 3: | |
1249 | cfg = mode_3_cfg; | |
1250 | n = ARRAY_SIZE(mode_3_cfg); | |
1251 | break; | |
1252 | case 4: | |
1253 | cfg = mode_4_cfg; | |
1254 | n = ARRAY_SIZE(mode_4_cfg); | |
1255 | break; | |
3b151526 AKG |
1256 | case 5: |
1257 | cfg = mode_5_cfg; | |
1258 | n = ARRAY_SIZE(mode_5_cfg); | |
1259 | break; | |
550a7375 FB |
1260 | } |
1261 | ||
1262 | printk(KERN_DEBUG "%s: setup fifo_mode %d\n", | |
1263 | musb_driver_name, fifo_mode); | |
1264 | ||
1265 | ||
e6c213b2 | 1266 | done: |
550a7375 FB |
1267 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); |
1268 | /* assert(offset > 0) */ | |
1269 | ||
1270 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1271 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1272 | */ |
1273 | ||
1274 | for (i = 0; i < n; i++) { | |
1275 | u8 epn = cfg->hw_ep_num; | |
1276 | ||
ca6d1b13 | 1277 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1278 | pr_debug("%s: invalid ep %d\n", |
1279 | musb_driver_name, epn); | |
bb1c9ef1 | 1280 | return -EINVAL; |
550a7375 FB |
1281 | } |
1282 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1283 | if (offset < 0) { | |
1284 | pr_debug("%s: mem overrun, ep %d\n", | |
1285 | musb_driver_name, epn); | |
1286 | return -EINVAL; | |
1287 | } | |
1288 | epn++; | |
1289 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1290 | } | |
1291 | ||
1292 | printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", | |
1293 | musb_driver_name, | |
ca6d1b13 FB |
1294 | n + 1, musb->config->num_eps * 2 - 1, |
1295 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 | 1296 | |
550a7375 FB |
1297 | if (!musb->bulk_ep) { |
1298 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1299 | return -EINVAL; | |
1300 | } | |
550a7375 FB |
1301 | |
1302 | return 0; | |
1303 | } | |
1304 | ||
1305 | ||
1306 | /* | |
1307 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1308 | * @param musb the controller | |
1309 | */ | |
1310 | static int __init ep_config_from_hw(struct musb *musb) | |
1311 | { | |
c6cf8b00 | 1312 | u8 epnum = 0; |
550a7375 FB |
1313 | struct musb_hw_ep *hw_ep; |
1314 | void *mbase = musb->mregs; | |
c6cf8b00 | 1315 | int ret = 0; |
550a7375 | 1316 | |
5c8a86e1 | 1317 | dev_dbg(musb->controller, "<== static silicon ep config\n"); |
550a7375 FB |
1318 | |
1319 | /* FIXME pick up ep0 maxpacket size */ | |
1320 | ||
ca6d1b13 | 1321 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1322 | musb_ep_select(mbase, epnum); |
1323 | hw_ep = musb->endpoints + epnum; | |
1324 | ||
c6cf8b00 BW |
1325 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
1326 | if (ret < 0) | |
550a7375 | 1327 | break; |
550a7375 FB |
1328 | |
1329 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1330 | ||
550a7375 FB |
1331 | /* pick an RX/TX endpoint for bulk */ |
1332 | if (hw_ep->max_packet_sz_tx < 512 | |
1333 | || hw_ep->max_packet_sz_rx < 512) | |
1334 | continue; | |
1335 | ||
1336 | /* REVISIT: this algorithm is lazy, we should at least | |
1337 | * try to pick a double buffered endpoint. | |
1338 | */ | |
1339 | if (musb->bulk_ep) | |
1340 | continue; | |
1341 | musb->bulk_ep = hw_ep; | |
550a7375 FB |
1342 | } |
1343 | ||
550a7375 FB |
1344 | if (!musb->bulk_ep) { |
1345 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1346 | return -EINVAL; | |
1347 | } | |
550a7375 FB |
1348 | |
1349 | return 0; | |
1350 | } | |
1351 | ||
1352 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1353 | ||
1354 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1355 | * configure endpoints, or take their config from silicon | |
1356 | */ | |
1357 | static int __init musb_core_init(u16 musb_type, struct musb *musb) | |
1358 | { | |
550a7375 FB |
1359 | u8 reg; |
1360 | char *type; | |
0ea52ff4 | 1361 | char aInfo[90], aRevision[32], aDate[12]; |
550a7375 FB |
1362 | void __iomem *mbase = musb->mregs; |
1363 | int status = 0; | |
1364 | int i; | |
1365 | ||
1366 | /* log core options (read using indexed model) */ | |
c6cf8b00 | 1367 | reg = musb_read_configdata(mbase); |
550a7375 FB |
1368 | |
1369 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
51bf0d0e | 1370 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { |
550a7375 | 1371 | strcat(aInfo, ", dyn FIFOs"); |
51bf0d0e AKG |
1372 | musb->dyn_fifo = true; |
1373 | } | |
550a7375 FB |
1374 | if (reg & MUSB_CONFIGDATA_MPRXE) { |
1375 | strcat(aInfo, ", bulk combine"); | |
550a7375 | 1376 | musb->bulk_combine = true; |
550a7375 FB |
1377 | } |
1378 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1379 | strcat(aInfo, ", bulk split"); | |
550a7375 | 1380 | musb->bulk_split = true; |
550a7375 FB |
1381 | } |
1382 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1383 | strcat(aInfo, ", HB-ISO Rx"); | |
a483d706 | 1384 | musb->hb_iso_rx = true; |
550a7375 FB |
1385 | } |
1386 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1387 | strcat(aInfo, ", HB-ISO Tx"); | |
a483d706 | 1388 | musb->hb_iso_tx = true; |
550a7375 FB |
1389 | } |
1390 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1391 | strcat(aInfo, ", SoftConn"); | |
1392 | ||
1393 | printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", | |
1394 | musb_driver_name, reg, aInfo); | |
1395 | ||
550a7375 | 1396 | aDate[0] = 0; |
550a7375 FB |
1397 | if (MUSB_CONTROLLER_MHDRC == musb_type) { |
1398 | musb->is_multipoint = 1; | |
1399 | type = "M"; | |
1400 | } else { | |
1401 | musb->is_multipoint = 0; | |
1402 | type = ""; | |
550a7375 FB |
1403 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB |
1404 | printk(KERN_ERR | |
1405 | "%s: kernel must blacklist external hubs\n", | |
1406 | musb_driver_name); | |
550a7375 FB |
1407 | #endif |
1408 | } | |
1409 | ||
1410 | /* log release info */ | |
32c3b94e AG |
1411 | musb->hwvers = musb_read_hwvers(mbase); |
1412 | snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), | |
1413 | MUSB_HWVERS_MINOR(musb->hwvers), | |
1414 | (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); | |
550a7375 FB |
1415 | printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", |
1416 | musb_driver_name, type, aRevision, aDate); | |
1417 | ||
1418 | /* configure ep0 */ | |
c6cf8b00 | 1419 | musb_configure_ep0(musb); |
550a7375 FB |
1420 | |
1421 | /* discover endpoint configuration */ | |
1422 | musb->nr_endpoints = 1; | |
1423 | musb->epmask = 1; | |
1424 | ||
ad517e9e FB |
1425 | if (musb->dyn_fifo) |
1426 | status = ep_config_from_table(musb); | |
1427 | else | |
1428 | status = ep_config_from_hw(musb); | |
550a7375 FB |
1429 | |
1430 | if (status < 0) | |
1431 | return status; | |
1432 | ||
1433 | /* finish init, and print endpoint config */ | |
1434 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1435 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1436 | ||
1437 | hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; | |
9a35f876 | 1438 | #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) |
550a7375 FB |
1439 | hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); |
1440 | hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); | |
1441 | hw_ep->fifo_sync_va = | |
1442 | musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); | |
1443 | ||
1444 | if (i == 0) | |
1445 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1446 | else | |
1447 | hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); | |
1448 | #endif | |
1449 | ||
1450 | hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; | |
c6cf8b00 | 1451 | hw_ep->target_regs = musb_read_target_reg_base(i, mbase); |
550a7375 FB |
1452 | hw_ep->rx_reinit = 1; |
1453 | hw_ep->tx_reinit = 1; | |
550a7375 FB |
1454 | |
1455 | if (hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1456 | dev_dbg(musb->controller, |
550a7375 FB |
1457 | "%s: hw_ep %d%s, %smax %d\n", |
1458 | musb_driver_name, i, | |
1459 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1460 | hw_ep->tx_double_buffered | |
1461 | ? "doublebuffer, " : "", | |
1462 | hw_ep->max_packet_sz_tx); | |
1463 | } | |
1464 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
5c8a86e1 | 1465 | dev_dbg(musb->controller, |
550a7375 FB |
1466 | "%s: hw_ep %d%s, %smax %d\n", |
1467 | musb_driver_name, i, | |
1468 | "rx", | |
1469 | hw_ep->rx_double_buffered | |
1470 | ? "doublebuffer, " : "", | |
1471 | hw_ep->max_packet_sz_rx); | |
1472 | } | |
1473 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
5c8a86e1 | 1474 | dev_dbg(musb->controller, "hw_ep %d not configured\n", i); |
550a7375 FB |
1475 | } |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
1480 | /*-------------------------------------------------------------------------*/ | |
1481 | ||
59b479e0 | 1482 | #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ |
d0678594 | 1483 | defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) |
550a7375 FB |
1484 | |
1485 | static irqreturn_t generic_interrupt(int irq, void *__hci) | |
1486 | { | |
1487 | unsigned long flags; | |
1488 | irqreturn_t retval = IRQ_NONE; | |
1489 | struct musb *musb = __hci; | |
1490 | ||
1491 | spin_lock_irqsave(&musb->lock, flags); | |
1492 | ||
1493 | musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); | |
1494 | musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); | |
1495 | musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); | |
1496 | ||
1497 | if (musb->int_usb || musb->int_tx || musb->int_rx) | |
1498 | retval = musb_interrupt(musb); | |
1499 | ||
1500 | spin_unlock_irqrestore(&musb->lock, flags); | |
1501 | ||
a5073b52 | 1502 | return retval; |
550a7375 FB |
1503 | } |
1504 | ||
1505 | #else | |
1506 | #define generic_interrupt NULL | |
1507 | #endif | |
1508 | ||
1509 | /* | |
1510 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1511 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1512 | * will be assigned, and the irq will already have been acked. | |
1513 | * | |
1514 | * called in irq context with spinlock held, irqs blocked | |
1515 | */ | |
1516 | irqreturn_t musb_interrupt(struct musb *musb) | |
1517 | { | |
1518 | irqreturn_t retval = IRQ_NONE; | |
1519 | u8 devctl, power; | |
1520 | int ep_num; | |
1521 | u32 reg; | |
1522 | ||
1523 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1524 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1525 | ||
5c8a86e1 | 1526 | dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", |
550a7375 FB |
1527 | (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", |
1528 | musb->int_usb, musb->int_tx, musb->int_rx); | |
1529 | ||
1530 | /* the core can interrupt us for multiple reasons; docs have | |
1531 | * a generic interrupt flowchart to follow | |
1532 | */ | |
7d9645fd | 1533 | if (musb->int_usb) |
550a7375 FB |
1534 | retval |= musb_stage0_irq(musb, musb->int_usb, |
1535 | devctl, power); | |
1536 | ||
1537 | /* "stage 1" is handling endpoint irqs */ | |
1538 | ||
1539 | /* handle endpoint 0 first */ | |
1540 | if (musb->int_tx & 1) { | |
1541 | if (devctl & MUSB_DEVCTL_HM) | |
1542 | retval |= musb_h_ep0_irq(musb); | |
1543 | else | |
1544 | retval |= musb_g_ep0_irq(musb); | |
1545 | } | |
1546 | ||
1547 | /* RX on endpoints 1-15 */ | |
1548 | reg = musb->int_rx >> 1; | |
1549 | ep_num = 1; | |
1550 | while (reg) { | |
1551 | if (reg & 1) { | |
1552 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1553 | /* REVISIT just retval = ep->rx_irq(...) */ | |
1554 | retval = IRQ_HANDLED; | |
1555 | if (devctl & MUSB_DEVCTL_HM) { | |
1556 | if (is_host_capable()) | |
1557 | musb_host_rx(musb, ep_num); | |
1558 | } else { | |
1559 | if (is_peripheral_capable()) | |
1560 | musb_g_rx(musb, ep_num); | |
1561 | } | |
1562 | } | |
1563 | ||
1564 | reg >>= 1; | |
1565 | ep_num++; | |
1566 | } | |
1567 | ||
1568 | /* TX on endpoints 1-15 */ | |
1569 | reg = musb->int_tx >> 1; | |
1570 | ep_num = 1; | |
1571 | while (reg) { | |
1572 | if (reg & 1) { | |
1573 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1574 | /* REVISIT just retval |= ep->tx_irq(...) */ | |
1575 | retval = IRQ_HANDLED; | |
1576 | if (devctl & MUSB_DEVCTL_HM) { | |
1577 | if (is_host_capable()) | |
1578 | musb_host_tx(musb, ep_num); | |
1579 | } else { | |
1580 | if (is_peripheral_capable()) | |
1581 | musb_g_tx(musb, ep_num); | |
1582 | } | |
1583 | } | |
1584 | reg >>= 1; | |
1585 | ep_num++; | |
1586 | } | |
1587 | ||
550a7375 FB |
1588 | return retval; |
1589 | } | |
981430a1 | 1590 | EXPORT_SYMBOL_GPL(musb_interrupt); |
550a7375 FB |
1591 | |
1592 | #ifndef CONFIG_MUSB_PIO_ONLY | |
90ab5ee9 | 1593 | static bool __initdata use_dma = 1; |
550a7375 FB |
1594 | |
1595 | /* "modprobe ... use_dma=0" etc */ | |
1596 | module_param(use_dma, bool, 0); | |
1597 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
1598 | ||
1599 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1600 | { | |
1601 | u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1602 | ||
1603 | /* called with controller lock already held */ | |
1604 | ||
1605 | if (!epnum) { | |
1606 | #ifndef CONFIG_USB_TUSB_OMAP_DMA | |
1607 | if (!is_cppi_enabled()) { | |
1608 | /* endpoint 0 */ | |
1609 | if (devctl & MUSB_DEVCTL_HM) | |
1610 | musb_h_ep0_irq(musb); | |
1611 | else | |
1612 | musb_g_ep0_irq(musb); | |
1613 | } | |
1614 | #endif | |
1615 | } else { | |
1616 | /* endpoints 1..15 */ | |
1617 | if (transmit) { | |
1618 | if (devctl & MUSB_DEVCTL_HM) { | |
1619 | if (is_host_capable()) | |
1620 | musb_host_tx(musb, epnum); | |
1621 | } else { | |
1622 | if (is_peripheral_capable()) | |
1623 | musb_g_tx(musb, epnum); | |
1624 | } | |
1625 | } else { | |
1626 | /* receive */ | |
1627 | if (devctl & MUSB_DEVCTL_HM) { | |
1628 | if (is_host_capable()) | |
1629 | musb_host_rx(musb, epnum); | |
1630 | } else { | |
1631 | if (is_peripheral_capable()) | |
1632 | musb_g_rx(musb, epnum); | |
1633 | } | |
1634 | } | |
1635 | } | |
1636 | } | |
9a35f876 | 1637 | EXPORT_SYMBOL_GPL(musb_dma_completion); |
550a7375 FB |
1638 | |
1639 | #else | |
1640 | #define use_dma 0 | |
1641 | #endif | |
1642 | ||
1643 | /*-------------------------------------------------------------------------*/ | |
1644 | ||
1645 | #ifdef CONFIG_SYSFS | |
1646 | ||
1647 | static ssize_t | |
1648 | musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1649 | { | |
1650 | struct musb *musb = dev_to_musb(dev); | |
1651 | unsigned long flags; | |
1652 | int ret = -EINVAL; | |
1653 | ||
1654 | spin_lock_irqsave(&musb->lock, flags); | |
3df00453 | 1655 | ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1656 | spin_unlock_irqrestore(&musb->lock, flags); |
1657 | ||
1658 | return ret; | |
1659 | } | |
1660 | ||
1661 | static ssize_t | |
1662 | musb_mode_store(struct device *dev, struct device_attribute *attr, | |
1663 | const char *buf, size_t n) | |
1664 | { | |
1665 | struct musb *musb = dev_to_musb(dev); | |
1666 | unsigned long flags; | |
96a274d1 | 1667 | int status; |
550a7375 FB |
1668 | |
1669 | spin_lock_irqsave(&musb->lock, flags); | |
96a274d1 DB |
1670 | if (sysfs_streq(buf, "host")) |
1671 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
1672 | else if (sysfs_streq(buf, "peripheral")) | |
1673 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1674 | else if (sysfs_streq(buf, "otg")) | |
1675 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
1676 | else | |
1677 | status = -EINVAL; | |
550a7375 FB |
1678 | spin_unlock_irqrestore(&musb->lock, flags); |
1679 | ||
96a274d1 | 1680 | return (status == 0) ? n : status; |
550a7375 FB |
1681 | } |
1682 | static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); | |
1683 | ||
1684 | static ssize_t | |
1685 | musb_vbus_store(struct device *dev, struct device_attribute *attr, | |
1686 | const char *buf, size_t n) | |
1687 | { | |
1688 | struct musb *musb = dev_to_musb(dev); | |
1689 | unsigned long flags; | |
1690 | unsigned long val; | |
1691 | ||
1692 | if (sscanf(buf, "%lu", &val) < 1) { | |
b3b1cc3b | 1693 | dev_err(dev, "Invalid VBUS timeout ms value\n"); |
550a7375 FB |
1694 | return -EINVAL; |
1695 | } | |
1696 | ||
1697 | spin_lock_irqsave(&musb->lock, flags); | |
f7f9d63e DB |
1698 | /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ |
1699 | musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; | |
84e250ff | 1700 | if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) |
550a7375 FB |
1701 | musb->is_active = 0; |
1702 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1703 | spin_unlock_irqrestore(&musb->lock, flags); | |
1704 | ||
1705 | return n; | |
1706 | } | |
1707 | ||
1708 | static ssize_t | |
1709 | musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1710 | { | |
1711 | struct musb *musb = dev_to_musb(dev); | |
1712 | unsigned long flags; | |
1713 | unsigned long val; | |
1714 | int vbus; | |
1715 | ||
1716 | spin_lock_irqsave(&musb->lock, flags); | |
1717 | val = musb->a_wait_bcon; | |
f7f9d63e DB |
1718 | /* FIXME get_vbus_status() is normally #defined as false... |
1719 | * and is effectively TUSB-specific. | |
1720 | */ | |
550a7375 FB |
1721 | vbus = musb_platform_get_vbus_status(musb); |
1722 | spin_unlock_irqrestore(&musb->lock, flags); | |
1723 | ||
f7f9d63e | 1724 | return sprintf(buf, "Vbus %s, timeout %lu msec\n", |
550a7375 FB |
1725 | vbus ? "on" : "off", val); |
1726 | } | |
1727 | static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); | |
1728 | ||
550a7375 FB |
1729 | /* Gadget drivers can't know that a host is connected so they might want |
1730 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1731 | */ | |
1732 | static ssize_t | |
1733 | musb_srp_store(struct device *dev, struct device_attribute *attr, | |
1734 | const char *buf, size_t n) | |
1735 | { | |
1736 | struct musb *musb = dev_to_musb(dev); | |
1737 | unsigned short srp; | |
1738 | ||
1739 | if (sscanf(buf, "%hu", &srp) != 1 | |
1740 | || (srp != 1)) { | |
b3b1cc3b | 1741 | dev_err(dev, "SRP: Value must be 1\n"); |
550a7375 FB |
1742 | return -EINVAL; |
1743 | } | |
1744 | ||
1745 | if (srp == 1) | |
1746 | musb_g_wakeup(musb); | |
1747 | ||
1748 | return n; | |
1749 | } | |
1750 | static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); | |
1751 | ||
94375751 FB |
1752 | static struct attribute *musb_attributes[] = { |
1753 | &dev_attr_mode.attr, | |
1754 | &dev_attr_vbus.attr, | |
94375751 | 1755 | &dev_attr_srp.attr, |
94375751 FB |
1756 | NULL |
1757 | }; | |
1758 | ||
1759 | static const struct attribute_group musb_attr_group = { | |
1760 | .attrs = musb_attributes, | |
1761 | }; | |
1762 | ||
550a7375 FB |
1763 | #endif /* sysfs */ |
1764 | ||
1765 | /* Only used to provide driver mode change events */ | |
1766 | static void musb_irq_work(struct work_struct *data) | |
1767 | { | |
1768 | struct musb *musb = container_of(data, struct musb, irq_work); | |
1769 | static int old_state; | |
1770 | ||
84e250ff DB |
1771 | if (musb->xceiv->state != old_state) { |
1772 | old_state = musb->xceiv->state; | |
550a7375 FB |
1773 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); |
1774 | } | |
1775 | } | |
1776 | ||
1777 | /* -------------------------------------------------------------------------- | |
1778 | * Init support | |
1779 | */ | |
1780 | ||
1781 | static struct musb *__init | |
ca6d1b13 FB |
1782 | allocate_instance(struct device *dev, |
1783 | struct musb_hdrc_config *config, void __iomem *mbase) | |
550a7375 FB |
1784 | { |
1785 | struct musb *musb; | |
1786 | struct musb_hw_ep *ep; | |
1787 | int epnum; | |
550a7375 FB |
1788 | struct usb_hcd *hcd; |
1789 | ||
427c4f33 | 1790 | hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); |
550a7375 FB |
1791 | if (!hcd) |
1792 | return NULL; | |
1793 | /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ | |
1794 | ||
1795 | musb = hcd_to_musb(hcd); | |
1796 | INIT_LIST_HEAD(&musb->control); | |
1797 | INIT_LIST_HEAD(&musb->in_bulk); | |
1798 | INIT_LIST_HEAD(&musb->out_bulk); | |
1799 | ||
1800 | hcd->uses_new_polling = 1; | |
ec95d35a | 1801 | hcd->has_tt = 1; |
550a7375 FB |
1802 | |
1803 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; | |
f7f9d63e | 1804 | musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; |
456bb169 | 1805 | dev_set_drvdata(dev, musb); |
550a7375 FB |
1806 | musb->mregs = mbase; |
1807 | musb->ctrl_base = mbase; | |
1808 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1809 | musb->config = config; |
02582b92 | 1810 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
550a7375 | 1811 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1812 | epnum < musb->config->num_eps; |
550a7375 | 1813 | epnum++, ep++) { |
550a7375 FB |
1814 | ep->musb = musb; |
1815 | ep->epnum = epnum; | |
1816 | } | |
1817 | ||
1818 | musb->controller = dev; | |
743411b3 | 1819 | |
550a7375 FB |
1820 | return musb; |
1821 | } | |
1822 | ||
1823 | static void musb_free(struct musb *musb) | |
1824 | { | |
1825 | /* this has multiple entry modes. it handles fault cleanup after | |
1826 | * probe(), where things may be partially set up, as well as rmmod | |
1827 | * cleanup after everything's been de-activated. | |
1828 | */ | |
1829 | ||
1830 | #ifdef CONFIG_SYSFS | |
94375751 | 1831 | sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); |
550a7375 FB |
1832 | #endif |
1833 | ||
97a39896 AKG |
1834 | if (musb->nIrq >= 0) { |
1835 | if (musb->irq_wake) | |
1836 | disable_irq_wake(musb->nIrq); | |
550a7375 FB |
1837 | free_irq(musb->nIrq, musb); |
1838 | } | |
1839 | if (is_dma_capable() && musb->dma_controller) { | |
1840 | struct dma_controller *c = musb->dma_controller; | |
1841 | ||
1842 | (void) c->stop(c); | |
1843 | dma_controller_destroy(c); | |
1844 | } | |
1845 | ||
550a7375 | 1846 | kfree(musb); |
550a7375 FB |
1847 | } |
1848 | ||
1849 | /* | |
1850 | * Perform generic per-controller initialization. | |
1851 | * | |
1852 | * @pDevice: the controller (already clocked, etc) | |
1853 | * @nIrq: irq | |
1854 | * @mregs: virtual address of controller registers, | |
1855 | * not yet corrected for platform-specific offsets | |
1856 | */ | |
1857 | static int __init | |
1858 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) | |
1859 | { | |
1860 | int status; | |
1861 | struct musb *musb; | |
1862 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
1863 | ||
1864 | /* The driver might handle more features than the board; OK. | |
1865 | * Fail when the board needs a feature that's not enabled. | |
1866 | */ | |
1867 | if (!plat) { | |
1868 | dev_dbg(dev, "no platform_data?\n"); | |
34e2beb2 SS |
1869 | status = -ENODEV; |
1870 | goto fail0; | |
550a7375 | 1871 | } |
34e2beb2 | 1872 | |
550a7375 | 1873 | /* allocate */ |
ca6d1b13 | 1874 | musb = allocate_instance(dev, plat->config, ctrl); |
34e2beb2 SS |
1875 | if (!musb) { |
1876 | status = -ENOMEM; | |
1877 | goto fail0; | |
1878 | } | |
550a7375 | 1879 | |
7acc6197 HH |
1880 | pm_runtime_use_autosuspend(musb->controller); |
1881 | pm_runtime_set_autosuspend_delay(musb->controller, 200); | |
1882 | pm_runtime_enable(musb->controller); | |
1883 | ||
550a7375 FB |
1884 | spin_lock_init(&musb->lock); |
1885 | musb->board_mode = plat->mode; | |
1886 | musb->board_set_power = plat->set_power; | |
550a7375 | 1887 | musb->min_power = plat->min_power; |
f7ec9437 | 1888 | musb->ops = plat->platform_ops; |
550a7375 | 1889 | |
84e250ff DB |
1890 | /* The musb_platform_init() call: |
1891 | * - adjusts musb->mregs and musb->isr if needed, | |
1892 | * - may initialize an integrated tranceiver | |
1893 | * - initializes musb->xceiv, usually by otg_get_transceiver() | |
84e250ff | 1894 | * - stops powering VBUS |
84e250ff | 1895 | * |
7c9d440e | 1896 | * There are various transceiver configurations. Blackfin, |
84e250ff DB |
1897 | * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses |
1898 | * external/discrete ones in various flavors (twl4030 family, | |
1899 | * isp1504, non-OTG, etc) mostly hooking up through ULPI. | |
550a7375 FB |
1900 | */ |
1901 | musb->isr = generic_interrupt; | |
ea65df57 | 1902 | status = musb_platform_init(musb); |
550a7375 | 1903 | if (status < 0) |
03491761 | 1904 | goto fail1; |
34e2beb2 | 1905 | |
550a7375 FB |
1906 | if (!musb->isr) { |
1907 | status = -ENODEV; | |
34e2beb2 | 1908 | goto fail3; |
550a7375 FB |
1909 | } |
1910 | ||
ffb865b1 HK |
1911 | if (!musb->xceiv->io_ops) { |
1912 | musb->xceiv->io_priv = musb->mregs; | |
1913 | musb->xceiv->io_ops = &musb_ulpi_access; | |
1914 | } | |
1915 | ||
550a7375 FB |
1916 | #ifndef CONFIG_MUSB_PIO_ONLY |
1917 | if (use_dma && dev->dma_mask) { | |
1918 | struct dma_controller *c; | |
1919 | ||
1920 | c = dma_controller_create(musb, musb->mregs); | |
1921 | musb->dma_controller = c; | |
1922 | if (c) | |
1923 | (void) c->start(c); | |
1924 | } | |
1925 | #endif | |
1926 | /* ideally this would be abstracted in platform setup */ | |
1927 | if (!is_dma_capable() || !musb->dma_controller) | |
1928 | dev->dma_mask = NULL; | |
1929 | ||
1930 | /* be sure interrupts are disabled before connecting ISR */ | |
1931 | musb_platform_disable(musb); | |
1932 | musb_generic_disable(musb); | |
1933 | ||
1934 | /* setup musb parts of the core (especially endpoints) */ | |
ca6d1b13 | 1935 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
1936 | ? MUSB_CONTROLLER_MHDRC |
1937 | : MUSB_CONTROLLER_HDRC, musb); | |
1938 | if (status < 0) | |
34e2beb2 | 1939 | goto fail3; |
550a7375 | 1940 | |
f7f9d63e | 1941 | setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); |
f7f9d63e | 1942 | |
550a7375 FB |
1943 | /* Init IRQ workqueue before request_irq */ |
1944 | INIT_WORK(&musb->irq_work, musb_irq_work); | |
1945 | ||
1946 | /* attach to the IRQ */ | |
427c4f33 | 1947 | if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { |
550a7375 FB |
1948 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
1949 | status = -ENODEV; | |
34e2beb2 | 1950 | goto fail3; |
550a7375 FB |
1951 | } |
1952 | musb->nIrq = nIrq; | |
1953 | /* FIXME this handles wakeup irqs wrong */ | |
c48a5155 FB |
1954 | if (enable_irq_wake(nIrq) == 0) { |
1955 | musb->irq_wake = 1; | |
550a7375 | 1956 | device_init_wakeup(dev, 1); |
c48a5155 FB |
1957 | } else { |
1958 | musb->irq_wake = 0; | |
1959 | } | |
550a7375 | 1960 | |
84e250ff DB |
1961 | /* host side needs more setup */ |
1962 | if (is_host_enabled(musb)) { | |
550a7375 FB |
1963 | struct usb_hcd *hcd = musb_to_hcd(musb); |
1964 | ||
84e250ff DB |
1965 | otg_set_host(musb->xceiv, &hcd->self); |
1966 | ||
1967 | if (is_otg_enabled(musb)) | |
550a7375 | 1968 | hcd->self.otg_port = 1; |
d445b6da | 1969 | musb->xceiv->otg->host = &hcd->self; |
550a7375 | 1970 | hcd->power_budget = 2 * (plat->power ? : 250); |
5fc4e779 AKG |
1971 | |
1972 | /* program PHY to use external vBus if required */ | |
1973 | if (plat->extvbus) { | |
adb3ee42 | 1974 | u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); |
5fc4e779 | 1975 | busctl |= MUSB_ULPI_USE_EXTVBUS; |
adb3ee42 | 1976 | musb_write_ulpi_buscontrol(musb->mregs, busctl); |
5fc4e779 | 1977 | } |
550a7375 | 1978 | } |
550a7375 FB |
1979 | |
1980 | /* For the host-only role, we can activate right away. | |
1981 | * (We expect the ID pin to be forcibly grounded!!) | |
1982 | * Otherwise, wait till the gadget driver hooks up. | |
1983 | */ | |
1984 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) { | |
07a8cdd2 AG |
1985 | struct usb_hcd *hcd = musb_to_hcd(musb); |
1986 | ||
550a7375 | 1987 | MUSB_HST_MODE(musb); |
d445b6da | 1988 | musb->xceiv->otg->default_a = 1; |
84e250ff | 1989 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 FB |
1990 | |
1991 | status = usb_add_hcd(musb_to_hcd(musb), -1, 0); | |
1992 | ||
07a8cdd2 | 1993 | hcd->self.uses_pio_for_control = 1; |
5c8a86e1 | 1994 | dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", |
550a7375 FB |
1995 | "HOST", status, |
1996 | musb_readb(musb->mregs, MUSB_DEVCTL), | |
1997 | (musb_readb(musb->mregs, MUSB_DEVCTL) | |
1998 | & MUSB_DEVCTL_BDEVICE | |
1999 | ? 'B' : 'A')); | |
2000 | ||
2001 | } else /* peripheral is enabled */ { | |
2002 | MUSB_DEV_MODE(musb); | |
d445b6da | 2003 | musb->xceiv->otg->default_a = 0; |
84e250ff | 2004 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
2005 | |
2006 | status = musb_gadget_setup(musb); | |
2007 | ||
5c8a86e1 | 2008 | dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", |
550a7375 FB |
2009 | is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", |
2010 | status, | |
2011 | musb_readb(musb->mregs, MUSB_DEVCTL)); | |
2012 | ||
2013 | } | |
461972d8 | 2014 | if (status < 0) |
34e2beb2 | 2015 | goto fail3; |
550a7375 | 2016 | |
7f7f9e2a FB |
2017 | status = musb_init_debugfs(musb); |
2018 | if (status < 0) | |
b0f9da7e | 2019 | goto fail4; |
7f7f9e2a | 2020 | |
550a7375 | 2021 | #ifdef CONFIG_SYSFS |
94375751 | 2022 | status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); |
28c2c51c | 2023 | if (status) |
b0f9da7e | 2024 | goto fail5; |
461972d8 | 2025 | #endif |
550a7375 | 2026 | |
ab3bbfa1 FB |
2027 | dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", |
2028 | ({char *s; | |
2029 | switch (musb->board_mode) { | |
2030 | case MUSB_HOST: s = "Host"; break; | |
2031 | case MUSB_PERIPHERAL: s = "Peripheral"; break; | |
2032 | default: s = "OTG"; break; | |
2033 | }; s; }), | |
2034 | ctrl, | |
2035 | (is_dma_capable() && musb->dma_controller) | |
2036 | ? "DMA" : "PIO", | |
2037 | musb->nIrq); | |
2038 | ||
28c2c51c | 2039 | return 0; |
550a7375 | 2040 | |
b0f9da7e FB |
2041 | fail5: |
2042 | musb_exit_debugfs(musb); | |
2043 | ||
34e2beb2 SS |
2044 | fail4: |
2045 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) | |
2046 | usb_remove_hcd(musb_to_hcd(musb)); | |
2047 | else | |
2048 | musb_gadget_cleanup(musb); | |
2049 | ||
2050 | fail3: | |
2051 | if (musb->irq_wake) | |
2052 | device_init_wakeup(dev, 0); | |
550a7375 | 2053 | musb_platform_exit(musb); |
28c2c51c | 2054 | |
34e2beb2 SS |
2055 | fail1: |
2056 | dev_err(musb->controller, | |
2057 | "musb_init_controller failed with status %d\n", status); | |
2058 | ||
28c2c51c FB |
2059 | musb_free(musb); |
2060 | ||
34e2beb2 SS |
2061 | fail0: |
2062 | ||
28c2c51c FB |
2063 | return status; |
2064 | ||
550a7375 FB |
2065 | } |
2066 | ||
2067 | /*-------------------------------------------------------------------------*/ | |
2068 | ||
2069 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2070 | * bridge to a platform device; this driver then suffices. | |
2071 | */ | |
2072 | ||
2073 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2074 | static u64 *orig_dma_mask; | |
2075 | #endif | |
2076 | ||
2077 | static int __init musb_probe(struct platform_device *pdev) | |
2078 | { | |
2079 | struct device *dev = &pdev->dev; | |
fcf173e4 | 2080 | int irq = platform_get_irq_byname(pdev, "mc"); |
da5108e1 | 2081 | int status; |
550a7375 FB |
2082 | struct resource *iomem; |
2083 | void __iomem *base; | |
2084 | ||
2085 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
541079de | 2086 | if (!iomem || irq <= 0) |
550a7375 FB |
2087 | return -ENODEV; |
2088 | ||
195e9e46 | 2089 | base = ioremap(iomem->start, resource_size(iomem)); |
550a7375 FB |
2090 | if (!base) { |
2091 | dev_err(dev, "ioremap failed\n"); | |
2092 | return -ENOMEM; | |
2093 | } | |
2094 | ||
2095 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2096 | /* clobbered by use_dma=n */ | |
2097 | orig_dma_mask = dev->dma_mask; | |
2098 | #endif | |
da5108e1 FB |
2099 | status = musb_init_controller(dev, irq, base); |
2100 | if (status < 0) | |
2101 | iounmap(base); | |
2102 | ||
2103 | return status; | |
550a7375 FB |
2104 | } |
2105 | ||
e3060b17 | 2106 | static int __exit musb_remove(struct platform_device *pdev) |
550a7375 FB |
2107 | { |
2108 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2109 | void __iomem *ctrl_base = musb->ctrl_base; | |
2110 | ||
2111 | /* this gets called on rmmod. | |
2112 | * - Host mode: host may still be active | |
2113 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2114 | * - OTG mode: both roles are deactivated (or never-activated) | |
2115 | */ | |
7acc6197 | 2116 | pm_runtime_get_sync(musb->controller); |
7f7f9e2a | 2117 | musb_exit_debugfs(musb); |
550a7375 | 2118 | musb_shutdown(pdev); |
461972d8 | 2119 | |
7acc6197 | 2120 | pm_runtime_put(musb->controller); |
550a7375 FB |
2121 | musb_free(musb); |
2122 | iounmap(ctrl_base); | |
2123 | device_init_wakeup(&pdev->dev, 0); | |
2124 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2125 | pdev->dev.dma_mask = orig_dma_mask; | |
2126 | #endif | |
2127 | return 0; | |
2128 | } | |
2129 | ||
2130 | #ifdef CONFIG_PM | |
2131 | ||
3c8a5fcc | 2132 | static void musb_save_context(struct musb *musb) |
4f712e01 AKG |
2133 | { |
2134 | int i; | |
2135 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2136 | void __iomem *epio; |
4f712e01 AKG |
2137 | |
2138 | if (is_host_enabled(musb)) { | |
7421107b FB |
2139 | musb->context.frame = musb_readw(musb_base, MUSB_FRAME); |
2140 | musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); | |
2141 | musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
4f712e01 | 2142 | } |
7421107b FB |
2143 | musb->context.power = musb_readb(musb_base, MUSB_POWER); |
2144 | musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); | |
2145 | musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); | |
2146 | musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); | |
2147 | musb->context.index = musb_readb(musb_base, MUSB_INDEX); | |
2148 | musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); | |
4f712e01 | 2149 | |
ae9b2ad2 | 2150 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2151 | struct musb_hw_ep *hw_ep; |
2152 | ||
2153 | hw_ep = &musb->endpoints[i]; | |
2154 | if (!hw_ep) | |
2155 | continue; | |
2156 | ||
2157 | epio = hw_ep->regs; | |
2158 | if (!epio) | |
2159 | continue; | |
2160 | ||
ea737554 | 2161 | musb_writeb(musb_base, MUSB_INDEX, i); |
7421107b | 2162 | musb->context.index_regs[i].txmaxp = |
ae9b2ad2 | 2163 | musb_readw(epio, MUSB_TXMAXP); |
7421107b | 2164 | musb->context.index_regs[i].txcsr = |
ae9b2ad2 | 2165 | musb_readw(epio, MUSB_TXCSR); |
7421107b | 2166 | musb->context.index_regs[i].rxmaxp = |
ae9b2ad2 | 2167 | musb_readw(epio, MUSB_RXMAXP); |
7421107b | 2168 | musb->context.index_regs[i].rxcsr = |
ae9b2ad2 | 2169 | musb_readw(epio, MUSB_RXCSR); |
4f712e01 AKG |
2170 | |
2171 | if (musb->dyn_fifo) { | |
7421107b | 2172 | musb->context.index_regs[i].txfifoadd = |
4f712e01 | 2173 | musb_read_txfifoadd(musb_base); |
7421107b | 2174 | musb->context.index_regs[i].rxfifoadd = |
4f712e01 | 2175 | musb_read_rxfifoadd(musb_base); |
7421107b | 2176 | musb->context.index_regs[i].txfifosz = |
4f712e01 | 2177 | musb_read_txfifosz(musb_base); |
7421107b | 2178 | musb->context.index_regs[i].rxfifosz = |
4f712e01 AKG |
2179 | musb_read_rxfifosz(musb_base); |
2180 | } | |
2181 | if (is_host_enabled(musb)) { | |
7421107b | 2182 | musb->context.index_regs[i].txtype = |
ae9b2ad2 | 2183 | musb_readb(epio, MUSB_TXTYPE); |
7421107b | 2184 | musb->context.index_regs[i].txinterval = |
ae9b2ad2 | 2185 | musb_readb(epio, MUSB_TXINTERVAL); |
7421107b | 2186 | musb->context.index_regs[i].rxtype = |
ae9b2ad2 | 2187 | musb_readb(epio, MUSB_RXTYPE); |
7421107b | 2188 | musb->context.index_regs[i].rxinterval = |
ae9b2ad2 | 2189 | musb_readb(epio, MUSB_RXINTERVAL); |
4f712e01 | 2190 | |
7421107b | 2191 | musb->context.index_regs[i].txfunaddr = |
4f712e01 | 2192 | musb_read_txfunaddr(musb_base, i); |
7421107b | 2193 | musb->context.index_regs[i].txhubaddr = |
4f712e01 | 2194 | musb_read_txhubaddr(musb_base, i); |
7421107b | 2195 | musb->context.index_regs[i].txhubport = |
4f712e01 AKG |
2196 | musb_read_txhubport(musb_base, i); |
2197 | ||
7421107b | 2198 | musb->context.index_regs[i].rxfunaddr = |
4f712e01 | 2199 | musb_read_rxfunaddr(musb_base, i); |
7421107b | 2200 | musb->context.index_regs[i].rxhubaddr = |
4f712e01 | 2201 | musb_read_rxhubaddr(musb_base, i); |
7421107b | 2202 | musb->context.index_regs[i].rxhubport = |
4f712e01 AKG |
2203 | musb_read_rxhubport(musb_base, i); |
2204 | } | |
2205 | } | |
4f712e01 AKG |
2206 | } |
2207 | ||
3c8a5fcc | 2208 | static void musb_restore_context(struct musb *musb) |
4f712e01 AKG |
2209 | { |
2210 | int i; | |
2211 | void __iomem *musb_base = musb->mregs; | |
2212 | void __iomem *ep_target_regs; | |
ae9b2ad2 | 2213 | void __iomem *epio; |
4f712e01 | 2214 | |
4f712e01 | 2215 | if (is_host_enabled(musb)) { |
7421107b FB |
2216 | musb_writew(musb_base, MUSB_FRAME, musb->context.frame); |
2217 | musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); | |
2218 | musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); | |
4f712e01 | 2219 | } |
7421107b FB |
2220 | musb_writeb(musb_base, MUSB_POWER, musb->context.power); |
2221 | musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); | |
2222 | musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); | |
2223 | musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); | |
2224 | musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); | |
4f712e01 | 2225 | |
ae9b2ad2 | 2226 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2227 | struct musb_hw_ep *hw_ep; |
2228 | ||
2229 | hw_ep = &musb->endpoints[i]; | |
2230 | if (!hw_ep) | |
2231 | continue; | |
2232 | ||
2233 | epio = hw_ep->regs; | |
2234 | if (!epio) | |
2235 | continue; | |
2236 | ||
ea737554 | 2237 | musb_writeb(musb_base, MUSB_INDEX, i); |
ae9b2ad2 | 2238 | musb_writew(epio, MUSB_TXMAXP, |
7421107b | 2239 | musb->context.index_regs[i].txmaxp); |
ae9b2ad2 | 2240 | musb_writew(epio, MUSB_TXCSR, |
7421107b | 2241 | musb->context.index_regs[i].txcsr); |
ae9b2ad2 | 2242 | musb_writew(epio, MUSB_RXMAXP, |
7421107b | 2243 | musb->context.index_regs[i].rxmaxp); |
ae9b2ad2 | 2244 | musb_writew(epio, MUSB_RXCSR, |
7421107b | 2245 | musb->context.index_regs[i].rxcsr); |
4f712e01 AKG |
2246 | |
2247 | if (musb->dyn_fifo) { | |
2248 | musb_write_txfifosz(musb_base, | |
7421107b | 2249 | musb->context.index_regs[i].txfifosz); |
4f712e01 | 2250 | musb_write_rxfifosz(musb_base, |
7421107b | 2251 | musb->context.index_regs[i].rxfifosz); |
4f712e01 | 2252 | musb_write_txfifoadd(musb_base, |
7421107b | 2253 | musb->context.index_regs[i].txfifoadd); |
4f712e01 | 2254 | musb_write_rxfifoadd(musb_base, |
7421107b | 2255 | musb->context.index_regs[i].rxfifoadd); |
4f712e01 AKG |
2256 | } |
2257 | ||
2258 | if (is_host_enabled(musb)) { | |
ae9b2ad2 | 2259 | musb_writeb(epio, MUSB_TXTYPE, |
7421107b | 2260 | musb->context.index_regs[i].txtype); |
ae9b2ad2 | 2261 | musb_writeb(epio, MUSB_TXINTERVAL, |
7421107b | 2262 | musb->context.index_regs[i].txinterval); |
ae9b2ad2 | 2263 | musb_writeb(epio, MUSB_RXTYPE, |
7421107b | 2264 | musb->context.index_regs[i].rxtype); |
ae9b2ad2 | 2265 | musb_writeb(epio, MUSB_RXINTERVAL, |
4f712e01 | 2266 | |
7421107b | 2267 | musb->context.index_regs[i].rxinterval); |
4f712e01 | 2268 | musb_write_txfunaddr(musb_base, i, |
7421107b | 2269 | musb->context.index_regs[i].txfunaddr); |
4f712e01 | 2270 | musb_write_txhubaddr(musb_base, i, |
7421107b | 2271 | musb->context.index_regs[i].txhubaddr); |
4f712e01 | 2272 | musb_write_txhubport(musb_base, i, |
7421107b | 2273 | musb->context.index_regs[i].txhubport); |
4f712e01 AKG |
2274 | |
2275 | ep_target_regs = | |
2276 | musb_read_target_reg_base(i, musb_base); | |
2277 | ||
2278 | musb_write_rxfunaddr(ep_target_regs, | |
7421107b | 2279 | musb->context.index_regs[i].rxfunaddr); |
4f712e01 | 2280 | musb_write_rxhubaddr(ep_target_regs, |
7421107b | 2281 | musb->context.index_regs[i].rxhubaddr); |
4f712e01 | 2282 | musb_write_rxhubport(ep_target_regs, |
7421107b | 2283 | musb->context.index_regs[i].rxhubport); |
4f712e01 AKG |
2284 | } |
2285 | } | |
3c5fec75 | 2286 | musb_writeb(musb_base, MUSB_INDEX, musb->context.index); |
4f712e01 AKG |
2287 | } |
2288 | ||
48fea965 | 2289 | static int musb_suspend(struct device *dev) |
550a7375 | 2290 | { |
8220796d | 2291 | struct musb *musb = dev_to_musb(dev); |
550a7375 | 2292 | unsigned long flags; |
550a7375 | 2293 | |
550a7375 FB |
2294 | spin_lock_irqsave(&musb->lock, flags); |
2295 | ||
2296 | if (is_peripheral_active(musb)) { | |
2297 | /* FIXME force disconnect unless we know USB will wake | |
2298 | * the system up quickly enough to respond ... | |
2299 | */ | |
2300 | } else if (is_host_active(musb)) { | |
2301 | /* we know all the children are suspended; sometimes | |
2302 | * they will even be wakeup-enabled. | |
2303 | */ | |
2304 | } | |
2305 | ||
550a7375 FB |
2306 | spin_unlock_irqrestore(&musb->lock, flags); |
2307 | return 0; | |
2308 | } | |
2309 | ||
48fea965 | 2310 | static int musb_resume_noirq(struct device *dev) |
550a7375 | 2311 | { |
550a7375 | 2312 | /* for static cmos like DaVinci, register values were preserved |
0ec8fd70 KK |
2313 | * unless for some reason the whole soc powered down or the USB |
2314 | * module got reset through the PSC (vs just being disabled). | |
550a7375 | 2315 | */ |
550a7375 FB |
2316 | return 0; |
2317 | } | |
2318 | ||
7acc6197 HH |
2319 | static int musb_runtime_suspend(struct device *dev) |
2320 | { | |
2321 | struct musb *musb = dev_to_musb(dev); | |
2322 | ||
2323 | musb_save_context(musb); | |
2324 | ||
2325 | return 0; | |
2326 | } | |
2327 | ||
2328 | static int musb_runtime_resume(struct device *dev) | |
2329 | { | |
2330 | struct musb *musb = dev_to_musb(dev); | |
2331 | static int first = 1; | |
2332 | ||
2333 | /* | |
2334 | * When pm_runtime_get_sync called for the first time in driver | |
2335 | * init, some of the structure is still not initialized which is | |
2336 | * used in restore function. But clock needs to be | |
2337 | * enabled before any register access, so | |
2338 | * pm_runtime_get_sync has to be called. | |
2339 | * Also context restore without save does not make | |
2340 | * any sense | |
2341 | */ | |
2342 | if (!first) | |
2343 | musb_restore_context(musb); | |
2344 | first = 0; | |
2345 | ||
2346 | return 0; | |
2347 | } | |
2348 | ||
47145210 | 2349 | static const struct dev_pm_ops musb_dev_pm_ops = { |
48fea965 MD |
2350 | .suspend = musb_suspend, |
2351 | .resume_noirq = musb_resume_noirq, | |
7acc6197 HH |
2352 | .runtime_suspend = musb_runtime_suspend, |
2353 | .runtime_resume = musb_runtime_resume, | |
48fea965 MD |
2354 | }; |
2355 | ||
2356 | #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) | |
550a7375 | 2357 | #else |
48fea965 | 2358 | #define MUSB_DEV_PM_OPS NULL |
550a7375 FB |
2359 | #endif |
2360 | ||
2361 | static struct platform_driver musb_driver = { | |
2362 | .driver = { | |
2363 | .name = (char *)musb_driver_name, | |
2364 | .bus = &platform_bus_type, | |
2365 | .owner = THIS_MODULE, | |
48fea965 | 2366 | .pm = MUSB_DEV_PM_OPS, |
550a7375 | 2367 | }, |
e3060b17 | 2368 | .remove = __exit_p(musb_remove), |
550a7375 | 2369 | .shutdown = musb_shutdown, |
550a7375 FB |
2370 | }; |
2371 | ||
2372 | /*-------------------------------------------------------------------------*/ | |
2373 | ||
2374 | static int __init musb_init(void) | |
2375 | { | |
550a7375 FB |
2376 | if (usb_disabled()) |
2377 | return 0; | |
550a7375 FB |
2378 | |
2379 | pr_info("%s: version " MUSB_VERSION ", " | |
550a7375 | 2380 | "?dma?" |
550a7375 | 2381 | ", " |
62285963 | 2382 | "otg (peripheral+host)", |
5c8a86e1 | 2383 | musb_driver_name); |
550a7375 FB |
2384 | return platform_driver_probe(&musb_driver, musb_probe); |
2385 | } | |
2386 | ||
34f32c97 DB |
2387 | /* make us init after usbcore and i2c (transceivers, regulators, etc) |
2388 | * and before usb gadget and host-side drivers start to register | |
550a7375 | 2389 | */ |
34f32c97 | 2390 | fs_initcall(musb_init); |
550a7375 FB |
2391 | |
2392 | static void __exit musb_cleanup(void) | |
2393 | { | |
2394 | platform_driver_unregister(&musb_driver); | |
2395 | } | |
2396 | module_exit(musb_cleanup); |