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usb: chipidea: move the lock initialization to core file
[linux-block.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375 85 * - platform_device for addressing, irq, and platform_data
5ae477b0 86 * - platform_data is mostly for board-specific information
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
550a7375
FB		 96#include <linux/list.h>
97#include <linux/kobject.h>
9303961f 98#include <linux/prefetch.h>
550a7375
FB		 99#include <linux/platform_device.h>
100#include <linux/io.h>
8d2421e6 101#include <linux/dma-mapping.h>
309be239 102#include <linux/usb.h>
550a7375 103
550a7375 104#include "musb_core.h"
c74173fd 105#include "musb_trace.h"
550a7375 106
f7f9d63e 107#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 108
109
550a7375
FB		 110#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
111#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
112
e8164f64 113#define MUSB_VERSION "6.0"
550a7375
FB		 114
115#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
116
05ac10dd 117#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 118const char musb_driver_name[] = MUSB_DRIVER_NAME;
119
120MODULE_DESCRIPTION(DRIVER_INFO);
121MODULE_AUTHOR(DRIVER_AUTHOR);
122MODULE_LICENSE("GPL");
123MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124
125
126/*-------------------------------------------------------------------------*/
127
128static inline struct musb *dev_to_musb(struct device *dev)
129{
550a7375 130 return dev_get_drvdata(dev);
550a7375
FB		 131}
132
133/*-------------------------------------------------------------------------*/
134
ffb865b1 135#ifndef CONFIG_BLACKFIN
705e63d2 136static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
ffb865b1 137{
b96d3b08 138 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 139 int i = 0;
140 u8 r;
141 u8 power;
bf070bc1
GI		 142 int ret;
143
144 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 145
146 /* Make sure the transceiver is not in low power mode */
147 power = musb_readb(addr, MUSB_POWER);
148 power &= ~MUSB_POWER_SUSPENDM;
149 musb_writeb(addr, MUSB_POWER, power);
150
151 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
152 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
153 */
154
705e63d2 155 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
ffb865b1
HK		 156 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
157 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
158
159 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
160 & MUSB_ULPI_REG_CMPLT)) {
161 i++;
bf070bc1
GI		 162 if (i == 10000) {
163 ret = -ETIMEDOUT;
164 goto out;
165 }
ffb865b1
HK		 166
167 }
168 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
169 r &= ~MUSB_ULPI_REG_CMPLT;
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
171
bf070bc1
GI		 172 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
173
174out:
175 pm_runtime_put(phy->io_dev);
176
177 return ret;
ffb865b1
HK		 178}
179
705e63d2 180static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
ffb865b1 181{
b96d3b08 182 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 183 int i = 0;
184 u8 r = 0;
185 u8 power;
bf070bc1
GI		 186 int ret = 0;
187
188 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 189
190 /* Make sure the transceiver is not in low power mode */
191 power = musb_readb(addr, MUSB_POWER);
192 power &= ~MUSB_POWER_SUSPENDM;
193 musb_writeb(addr, MUSB_POWER, power);
194
705e63d2
UKK		 195 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
196 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
ffb865b1
HK		 197 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
198
199 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
200 & MUSB_ULPI_REG_CMPLT)) {
201 i++;
bf070bc1
GI		 202 if (i == 10000) {
203 ret = -ETIMEDOUT;
204 goto out;
205 }
ffb865b1
HK		 206 }
207
208 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
209 r &= ~MUSB_ULPI_REG_CMPLT;
210 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
211
bf070bc1
GI		 212out:
213 pm_runtime_put(phy->io_dev);
214
215 return ret;
ffb865b1
HK		 216}
217#else
f2263db7
MF		 218#define musb_ulpi_read NULL
219#define musb_ulpi_write NULL
ffb865b1
HK		 220#endif
221
b96d3b08 222static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 223 .read = musb_ulpi_read,
224 .write = musb_ulpi_write,
225};
226
227/*-------------------------------------------------------------------------*/
228
1b40fc57
TL		 229static u32 musb_default_fifo_offset(u8 epnum)
230{
231 return 0x20 + (epnum * 4);
232}
233
d026e9c7
TL		 234/* "flat" mapping: each endpoint has its own i/o address */
235static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
236{
237}
238
239static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
240{
241 return 0x100 + (0x10 * epnum) + offset;
242}
243
244/* "indexed" mapping: INDEX register controls register bank select */
245static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
246{
247 musb_writeb(mbase, MUSB_INDEX, epnum);
248}
249
250static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
251{
252 return 0x10 + offset;
253}
254
6cc2af6d
HG		 255static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
256{
257 return 0x80 + (0x08 * epnum) + offset;
258}
259
1b40fc57
TL		 260static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
261{
c74173fd
BL		 262 u8 data = __raw_readb(addr + offset);
263
264 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
265 return data;
1b40fc57
TL		 266}
267
268static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
269{
c74173fd 270 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 271 __raw_writeb(data, addr + offset);
272}
273
274static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
275{
c74173fd
BL		 276 u16 data = __raw_readw(addr + offset);
277
278 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
279 return data;
1b40fc57
TL		 280}
281
282static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
283{
c74173fd 284 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 285 __raw_writew(data, addr + offset);
286}
287
288static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
289{
c74173fd
BL		 290 u32 data = __raw_readl(addr + offset);
291
292 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
293 return data;
1b40fc57
TL		 294}
295
296static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
297{
c74173fd 298 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 299 __raw_writel(data, addr + offset);
300}
c6cf8b00 301
550a7375
FB		 302/*
303 * Load an endpoint's FIFO
304 */
1b40fc57
TL		 305static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
306 const u8 *src)
550a7375 307{
5c8a86e1 308 struct musb *musb = hw_ep->musb;
550a7375
FB		 309 void __iomem *fifo = hw_ep->fifo;
310
603fe2b2
AKG		 311 if (unlikely(len == 0))
312 return;
313
550a7375
FB		 314 prefetch((u8 *)src);
315
5c8a86e1 316 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 317 'T', hw_ep->epnum, fifo, len, src);
318
319 /* we can't assume unaligned reads work */
320 if (likely((0x01 & (unsigned long) src) == 0)) {
321 u16 index = 0;
322
323 /* best case is 32bit-aligned source address */
324 if ((0x02 & (unsigned long) src) == 0) {
325 if (len >= 4) {
2bf0a8f6 326 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 327 index += len & ~0x03;
328 }
329 if (len & 0x02) {
be780381 330 __raw_writew(*(u16 *)&src[index], fifo);
550a7375
FB		 331 index += 2;
332 }
333 } else {
334 if (len >= 2) {
2bf0a8f6 335 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 336 index += len & ~0x01;
337 }
338 }
339 if (len & 0x01)
be780381 340 __raw_writeb(src[index], fifo);
550a7375
FB		 341 } else {
342 /* byte aligned */
2bf0a8f6 343 iowrite8_rep(fifo, src, len);
550a7375
FB		 344 }
345}
346
347/*
348 * Unload an endpoint's FIFO
349 */
1b40fc57 350static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
550a7375 351{
5c8a86e1 352 struct musb *musb = hw_ep->musb;
550a7375
FB		 353 void __iomem *fifo = hw_ep->fifo;
354
603fe2b2
AKG		 355 if (unlikely(len == 0))
356 return;
357
5c8a86e1 358 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 359 'R', hw_ep->epnum, fifo, len, dst);
360
361 /* we can't assume unaligned writes work */
362 if (likely((0x01 & (unsigned long) dst) == 0)) {
363 u16 index = 0;
364
365 /* best case is 32bit-aligned destination address */
366 if ((0x02 & (unsigned long) dst) == 0) {
367 if (len >= 4) {
2bf0a8f6 368 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 369 index = len & ~0x03;
370 }
371 if (len & 0x02) {
be780381 372 *(u16 *)&dst[index] = __raw_readw(fifo);
550a7375
FB		 373 index += 2;
374 }
375 } else {
376 if (len >= 2) {
2bf0a8f6 377 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 378 index = len & ~0x01;
379 }
380 }
381 if (len & 0x01)
be780381 382 dst[index] = __raw_readb(fifo);
550a7375
FB		 383 } else {
384 /* byte aligned */
2bf0a8f6 385 ioread8_rep(fifo, dst, len);
550a7375
FB		 386 }
387}
388
1b40fc57
TL		 389/*
390 * Old style IO functions
391 */
392u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
393EXPORT_SYMBOL_GPL(musb_readb);
394
395void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
396EXPORT_SYMBOL_GPL(musb_writeb);
550a7375 397
1b40fc57
TL		 398u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
399EXPORT_SYMBOL_GPL(musb_readw);
400
401void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
402EXPORT_SYMBOL_GPL(musb_writew);
403
404u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
405EXPORT_SYMBOL_GPL(musb_readl);
406
407void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
408EXPORT_SYMBOL_GPL(musb_writel);
409
7f6283ed
TL		 410#ifndef CONFIG_MUSB_PIO_ONLY
411struct dma_controller *
412(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
413EXPORT_SYMBOL(musb_dma_controller_create);
414
415void (*musb_dma_controller_destroy)(struct dma_controller *c);
416EXPORT_SYMBOL(musb_dma_controller_destroy);
417#endif
418
1b40fc57
TL		 419/*
420 * New style IO functions
421 */
422void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
423{
424 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
425}
426
427void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
428{
429 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
430}
550a7375
FB		 431
432/*-------------------------------------------------------------------------*/
433
434/* for high speed test mode; see USB 2.0 spec 7.1.20 */
435static const u8 musb_test_packet[53] = {
436 /* implicit SYNC then DATA0 to start */
437
438 /* JKJKJKJK x9 */
439 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
440 /* JJKKJJKK x8 */
441 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
442 /* JJJJKKKK x8 */
443 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
444 /* JJJJJJJKKKKKKK x8 */
445 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
446 /* JJJJJJJK x8 */
447 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
448 /* JKKKKKKK x10, JK */
449 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
450
451 /* implicit CRC16 then EOP to end */
452};
453
454void musb_load_testpacket(struct musb *musb)
455{
456 void __iomem *regs = musb->endpoints[0].regs;
457
458 musb_ep_select(musb->mregs, 0);
459 musb_write_fifo(musb->control_ep,
460 sizeof(musb_test_packet), musb_test_packet);
461 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
462}
463
464/*-------------------------------------------------------------------------*/
465
550a7375
FB		 466/*
467 * Handles OTG hnp timeouts, such as b_ase0_brst
468 */
a156544b 469static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 470{
471 struct musb *musb = (struct musb *)data;
472 unsigned long flags;
473
474 spin_lock_irqsave(&musb->lock, flags);
e47d9254 475 switch (musb->xceiv->otg->state) {
550a7375 476 case OTG_STATE_B_WAIT_ACON:
b99d3659
BL		 477 musb_dbg(musb,
478 "HNP: b_wait_acon timeout; back to b_peripheral");
550a7375 479 musb_g_disconnect(musb);
e47d9254 480 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 481 musb->is_active = 0;
482 break;
ab983f2a 483 case OTG_STATE_A_SUSPEND:
550a7375 484 case OTG_STATE_A_WAIT_BCON:
b99d3659 485 musb_dbg(musb, "HNP: %s timeout",
e47d9254 486 usb_otg_state_string(musb->xceiv->otg->state));
743411b3 487 musb_platform_set_vbus(musb, 0);
e47d9254 488 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 489 break;
490 default:
b99d3659 491 musb_dbg(musb, "HNP: Unhandled mode %s",
e47d9254 492 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 493 }
550a7375
FB		 494 spin_unlock_irqrestore(&musb->lock, flags);
495}
496
550a7375 497/*
f7f9d63e 498 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 499 */
500void musb_hnp_stop(struct musb *musb)
501{
8b125df5 502 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 503 void __iomem *mbase = musb->mregs;
504 u8 reg;
505
b99d3659 506 musb_dbg(musb, "HNP: stop from %s",
e47d9254 507 usb_otg_state_string(musb->xceiv->otg->state));
ab983f2a 508
e47d9254 509 switch (musb->xceiv->otg->state) {
550a7375 510 case OTG_STATE_A_PERIPHERAL:
550a7375 511 musb_g_disconnect(musb);
b99d3659 512 musb_dbg(musb, "HNP: back to %s",
e47d9254 513 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 514 break;
515 case OTG_STATE_B_HOST:
b99d3659 516 musb_dbg(musb, "HNP: Disabling HR");
74c2e936
DM		 517 if (hcd)
518 hcd->self.is_b_host = 0;
e47d9254 519 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 520 MUSB_DEV_MODE(musb);
521 reg = musb_readb(mbase, MUSB_POWER);
522 reg |= MUSB_POWER_SUSPENDM;
523 musb_writeb(mbase, MUSB_POWER, reg);
524 /* REVISIT: Start SESSION_REQUEST here? */
525 break;
526 default:
b99d3659 527 musb_dbg(musb, "HNP: Stopping in unknown state %s",
e47d9254 528 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 529 }
530
531 /*
532 * When returning to A state after HNP, avoid hub_port_rebounce(),
533 * which cause occasional OPT A "Did not receive reset after connect"
534 * errors.
535 */
749da5f8 536 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 537}
538
83b8f5b8 539static void musb_recover_from_babble(struct musb *musb);
e1eb3eb8 540
550a7375
FB		 541/*
542 * Interrupt Service Routine to record USB "global" interrupts.
543 * Since these do not happen often and signify things of
544 * paramount importance, it seems OK to check them individually;
545 * the order of the tests is specified in the manual
546 *
547 * @param musb instance pointer
548 * @param int_usb register contents
549 * @param devctl
550 * @param power
551 */
552
550a7375 553static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 554 u8 devctl)
550a7375
FB		 555{
556 irqreturn_t handled = IRQ_NONE;
550a7375 557
b99d3659 558 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
550a7375
FB		 559
560 /* in host mode, the peripheral may issue remote wakeup.
561 * in peripheral mode, the host may resume the link.
562 * spurious RESUME irqs happen too, paired with SUSPEND.
563 */
564 if (int_usb & MUSB_INTR_RESUME) {
565 handled = IRQ_HANDLED;
b99d3659 566 musb_dbg(musb, "RESUME (%s)",
0acff6b8 567 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 568
569 if (devctl & MUSB_DEVCTL_HM) {
e47d9254 570 switch (musb->xceiv->otg->state) {
550a7375
FB		 571 case OTG_STATE_A_SUSPEND:
572 /* remote wakeup? later, GetPortStatus
573 * will stop RESUME signaling
574 */
575
550a7375
FB		 576 musb->port1_status |=
577 (USB_PORT_STAT_C_SUSPEND << 16)
578 | MUSB_PORT_STAT_RESUME;
30d361bf 579 musb->rh_timer = jiffies
309be239 580 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
baadd52f 581 musb->need_finish_resume = 1;
550a7375 582
e47d9254 583 musb->xceiv->otg->state = OTG_STATE_A_HOST;
550a7375 584 musb->is_active = 1;
9298b4aa 585 musb_host_resume_root_hub(musb);
550a7375
FB		 586 break;
587 case OTG_STATE_B_WAIT_ACON:
e47d9254 588 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 589 musb->is_active = 1;
590 MUSB_DEV_MODE(musb);
591 break;
592 default:
593 WARNING("bogus %s RESUME (%s)\n",
594 "host",
e47d9254 595 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 596 }
550a7375 597 } else {
e47d9254 598 switch (musb->xceiv->otg->state) {
550a7375
FB		 599 case OTG_STATE_A_SUSPEND:
600 /* possibly DISCONNECT is upcoming */
e47d9254 601 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44 602 musb_host_resume_root_hub(musb);
550a7375 603 break;
550a7375
FB		 604 case OTG_STATE_B_WAIT_ACON:
605 case OTG_STATE_B_PERIPHERAL:
606 /* disconnect while suspended? we may
607 * not get a disconnect irq...
608 */
609 if ((devctl & MUSB_DEVCTL_VBUS)
610 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
611 ) {
612 musb->int_usb |= MUSB_INTR_DISCONNECT;
613 musb->int_usb &= ~MUSB_INTR_SUSPEND;
614 break;
615 }
616 musb_g_resume(musb);
617 break;
618 case OTG_STATE_B_IDLE:
619 musb->int_usb &= ~MUSB_INTR_SUSPEND;
620 break;
550a7375
FB		 621 default:
622 WARNING("bogus %s RESUME (%s)\n",
623 "peripheral",
e47d9254 624 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 625 }
626 }
627 }
628
550a7375
FB		 629 /* see manual for the order of the tests */
630 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 631 void __iomem *mbase = musb->mregs;
632
19aab56c
HK		 633 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
634 && (devctl & MUSB_DEVCTL_BDEVICE)) {
b99d3659 635 musb_dbg(musb, "SessReq while on B state");
a6038ee7
HK		 636 return IRQ_HANDLED;
637 }
638
b99d3659 639 musb_dbg(musb, "SESSION_REQUEST (%s)",
e47d9254 640 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 641
642 /* IRQ arrives from ID pin sense or (later, if VBUS power
643 * is removed) SRP. responses are time critical:
644 * - turn on VBUS (with silicon-specific mechanism)
645 * - go through A_WAIT_VRISE
646 * - ... to A_WAIT_BCON.
647 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
648 */
649 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
650 musb->ep0_stage = MUSB_EP0_START;
e47d9254 651 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
550a7375 652 MUSB_HST_MODE(musb);
743411b3 653 musb_platform_set_vbus(musb, 1);
550a7375
FB		 654
655 handled = IRQ_HANDLED;
656 }
657
658 if (int_usb & MUSB_INTR_VBUSERROR) {
659 int ignore = 0;
660
661 /* During connection as an A-Device, we may see a short
662 * current spikes causing voltage drop, because of cable
663 * and peripheral capacitance combined with vbus draw.
664 * (So: less common with truly self-powered devices, where
665 * vbus doesn't act like a power supply.)
666 *
667 * Such spikes are short; usually less than ~500 usec, max
668 * of ~2 msec. That is, they're not sustained overcurrent
669 * errors, though they're reported using VBUSERROR irqs.
670 *
671 * Workarounds: (a) hardware: use self powered devices.
672 * (b) software: ignore non-repeated VBUS errors.
673 *
674 * REVISIT: do delays from lots of DEBUG_KERNEL checks
675 * make trouble here, keeping VBUS < 4.4V ?
676 */
e47d9254 677 switch (musb->xceiv->otg->state) {
550a7375
FB		 678 case OTG_STATE_A_HOST:
679 /* recovery is dicey once we've gotten past the
680 * initial stages of enumeration, but if VBUS
681 * stayed ok at the other end of the link, and
682 * another reset is due (at least for high speed,
683 * to redo the chirp etc), it might work OK...
684 */
685 case OTG_STATE_A_WAIT_BCON:
686 case OTG_STATE_A_WAIT_VRISE:
687 if (musb->vbuserr_retry) {
aa471456
FB		 688 void __iomem *mbase = musb->mregs;
689
550a7375
FB		 690 musb->vbuserr_retry--;
691 ignore = 1;
692 devctl |= MUSB_DEVCTL_SESSION;
693 musb_writeb(mbase, MUSB_DEVCTL, devctl);
694 } else {
695 musb->port1_status |=
749da5f8
AS		 696 USB_PORT_STAT_OVERCURRENT
697 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 698 }
699 break;
700 default:
701 break;
702 }
703
54485116
GI		 704 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
705 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
e47d9254 706 usb_otg_state_string(musb->xceiv->otg->state),
550a7375
FB		 707 devctl,
708 ({ char *s;
709 switch (devctl & MUSB_DEVCTL_VBUS) {
710 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
711 s = "<SessEnd"; break;
712 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
713 s = "<AValid"; break;
714 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
715 s = "<VBusValid"; break;
716 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
717 default:
718 s = "VALID"; break;
2b84f92b 719 } s; }),
550a7375
FB		 720 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
721 musb->port1_status);
722
723 /* go through A_WAIT_VFALL then start a new session */
724 if (!ignore)
743411b3 725 musb_platform_set_vbus(musb, 0);
550a7375
FB		 726 handled = IRQ_HANDLED;
727 }
728
1c25fda4 729 if (int_usb & MUSB_INTR_SUSPEND) {
b99d3659 730 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
e47d9254 731 usb_otg_state_string(musb->xceiv->otg->state), devctl);
1c25fda4
AM		 732 handled = IRQ_HANDLED;
733
e47d9254 734 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 735 case OTG_STATE_A_PERIPHERAL:
736 /* We also come here if the cable is removed, since
737 * this silicon doesn't report ID-no-longer-grounded.
738 *
739 * We depend on T(a_wait_bcon) to shut us down, and
740 * hope users don't do anything dicey during this
741 * undesired detour through A_WAIT_BCON.
742 */
743 musb_hnp_stop(musb);
0b3eba44 744 musb_host_resume_root_hub(musb);
1c25fda4
AM		 745 musb_root_disconnect(musb);
746 musb_platform_try_idle(musb, jiffies
747 + msecs_to_jiffies(musb->a_wait_bcon
748 ? : OTG_TIME_A_WAIT_BCON));
749
750 break;
1c25fda4
AM		 751 case OTG_STATE_B_IDLE:
752 if (!musb->is_active)
753 break;
754 case OTG_STATE_B_PERIPHERAL:
755 musb_g_suspend(musb);
eee3f15d 756 musb->is_active = musb->g.b_hnp_enable;
1c25fda4 757 if (musb->is_active) {
e47d9254 758 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
b99d3659 759 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
1c25fda4
AM		 760 mod_timer(&musb->otg_timer, jiffies
761 + msecs_to_jiffies(
762 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 763 }
764 break;
765 case OTG_STATE_A_WAIT_BCON:
766 if (musb->a_wait_bcon != 0)
767 musb_platform_try_idle(musb, jiffies
768 + msecs_to_jiffies(musb->a_wait_bcon));
769 break;
770 case OTG_STATE_A_HOST:
e47d9254 771 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
eee3f15d 772 musb->is_active = musb->hcd->self.b_hnp_enable;
1c25fda4
AM		 773 break;
774 case OTG_STATE_B_HOST:
775 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
b99d3659 776 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
1c25fda4
AM		 777 break;
778 default:
779 /* "should not happen" */
780 musb->is_active = 0;
781 break;
782 }
783 }
784
550a7375 785 if (int_usb & MUSB_INTR_CONNECT) {
8b125df5 786 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 787
788 handled = IRQ_HANDLED;
789 musb->is_active = 1;
550a7375
FB		 790
791 musb->ep0_stage = MUSB_EP0_START;
792
b18d26f6
SAS		 793 musb->intrtxe = musb->epmask;
794 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 795 musb->intrrxe = musb->epmask & 0xfffe;
796 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 797 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 798 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
799 |USB_PORT_STAT_HIGH_SPEED
800 |USB_PORT_STAT_ENABLE
801 );
802 musb->port1_status |= USB_PORT_STAT_CONNECTION
803 |(USB_PORT_STAT_C_CONNECTION << 16);
804
805 /* high vs full speed is just a guess until after reset */
806 if (devctl & MUSB_DEVCTL_LSDEV)
807 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
808
550a7375 809 /* indicate new connection to OTG machine */
e47d9254 810 switch (musb->xceiv->otg->state) {
550a7375
FB		 811 case OTG_STATE_B_PERIPHERAL:
812 if (int_usb & MUSB_INTR_SUSPEND) {
b99d3659 813 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
550a7375 814 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 815 goto b_host;
550a7375 816 } else
b99d3659 817 musb_dbg(musb, "CONNECT as b_peripheral???");
550a7375
FB		 818 break;
819 case OTG_STATE_B_WAIT_ACON:
b99d3659 820 musb_dbg(musb, "HNP: CONNECT, now b_host");
1de00dae 821b_host:
e47d9254 822 musb->xceiv->otg->state = OTG_STATE_B_HOST;
74c2e936
DM		 823 if (musb->hcd)
824 musb->hcd->self.is_b_host = 1;
1de00dae 825 del_timer(&musb->otg_timer);
550a7375
FB		 826 break;
827 default:
828 if ((devctl & MUSB_DEVCTL_VBUS)
829 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
e47d9254 830 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44
DM		 831 if (hcd)
832 hcd->self.is_b_host = 0;
550a7375
FB		 833 }
834 break;
835 }
1de00dae 836
0b3eba44 837 musb_host_poke_root_hub(musb);
1de00dae 838
b99d3659 839 musb_dbg(musb, "CONNECT (%s) devctl %02x",
e47d9254 840 usb_otg_state_string(musb->xceiv->otg->state), devctl);
550a7375 841 }
550a7375 842
6d349671 843 if (int_usb & MUSB_INTR_DISCONNECT) {
b99d3659 844 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
e47d9254 845 usb_otg_state_string(musb->xceiv->otg->state),
1c25fda4
AM		 846 MUSB_MODE(musb), devctl);
847 handled = IRQ_HANDLED;
848
e47d9254 849 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 850 case OTG_STATE_A_HOST:
851 case OTG_STATE_A_SUSPEND:
0b3eba44 852 musb_host_resume_root_hub(musb);
1c25fda4 853 musb_root_disconnect(musb);
032ec49f 854 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 855 musb_platform_try_idle(musb, jiffies
856 + msecs_to_jiffies(musb->a_wait_bcon));
857 break;
1c25fda4
AM		 858 case OTG_STATE_B_HOST:
859 /* REVISIT this behaves for "real disconnect"
860 * cases; make sure the other transitions from
861 * from B_HOST act right too. The B_HOST code
862 * in hnp_stop() is currently not used...
863 */
864 musb_root_disconnect(musb);
74c2e936
DM		 865 if (musb->hcd)
866 musb->hcd->self.is_b_host = 0;
e47d9254 867 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1c25fda4
AM		 868 MUSB_DEV_MODE(musb);
869 musb_g_disconnect(musb);
870 break;
871 case OTG_STATE_A_PERIPHERAL:
872 musb_hnp_stop(musb);
873 musb_root_disconnect(musb);
874 /* FALLTHROUGH */
875 case OTG_STATE_B_WAIT_ACON:
876 /* FALLTHROUGH */
1c25fda4
AM		 877 case OTG_STATE_B_PERIPHERAL:
878 case OTG_STATE_B_IDLE:
879 musb_g_disconnect(musb);
880 break;
1c25fda4
AM		 881 default:
882 WARNING("unhandled DISCONNECT transition (%s)\n",
e47d9254 883 usb_otg_state_string(musb->xceiv->otg->state));
1c25fda4
AM		 884 break;
885 }
886 }
887
550a7375
FB		 888 /* mentor saves a bit: bus reset and babble share the same irq.
889 * only host sees babble; only peripheral sees bus reset.
890 */
891 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 892 handled = IRQ_HANDLED;
896f7ea3 893 if (devctl & MUSB_DEVCTL_HM) {
550a7375 894 /*
34754dec 895 * When BABBLE happens what we can depends on which
28378d5e
FB		 896 * platform MUSB is running, because some platforms
897 * implemented proprietary means for 'recovering' from
898 * Babble conditions. One such platform is AM335x. In
34754dec
FB		 899 * most cases, however, the only thing we can do is
900 * drop the session.
550a7375 901 */
34754dec 902 dev_err(musb->controller, "Babble\n");
d0fc0a20 903
34754dec
FB		 904 if (is_host_active(musb))
905 musb_recover_from_babble(musb);
a04d46d0 906 } else {
b99d3659 907 musb_dbg(musb, "BUS RESET as %s",
e47d9254
AT		 908 usb_otg_state_string(musb->xceiv->otg->state));
909 switch (musb->xceiv->otg->state) {
550a7375 910 case OTG_STATE_A_SUSPEND:
550a7375
FB		 911 musb_g_reset(musb);
912 /* FALLTHROUGH */
913 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 914 /* never use invalid T(a_wait_bcon) */
b99d3659 915 musb_dbg(musb, "HNP: in %s, %d msec timeout",
e47d9254 916 usb_otg_state_string(musb->xceiv->otg->state),
3df00453 917 TA_WAIT_BCON(musb));
f7f9d63e
DB		 918 mod_timer(&musb->otg_timer, jiffies
919 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 920 break;
921 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 922 del_timer(&musb->otg_timer);
923 musb_g_reset(musb);
550a7375
FB		 924 break;
925 case OTG_STATE_B_WAIT_ACON:
b99d3659 926 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
e47d9254
AT		 927 usb_otg_state_string(musb->xceiv->otg->state));
928 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 929 musb_g_reset(musb);
930 break;
550a7375 931 case OTG_STATE_B_IDLE:
e47d9254 932 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 933 /* FALLTHROUGH */
934 case OTG_STATE_B_PERIPHERAL:
935 musb_g_reset(musb);
936 break;
937 default:
b99d3659 938 musb_dbg(musb, "Unhandled BUS RESET as %s",
e47d9254 939 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 940 }
941 }
550a7375 942 }
550a7375
FB		 943
944#if 0
945/* REVISIT ... this would be for multiplexing periodic endpoints, or
946 * supporting transfer phasing to prevent exceeding ISO bandwidth
947 * limits of a given frame or microframe.
948 *
949 * It's not needed for peripheral side, which dedicates endpoints;
950 * though it _might_ use SOF irqs for other purposes.
951 *
952 * And it's not currently needed for host side, which also dedicates
953 * endpoints, relies on TX/RX interval registers, and isn't claimed
954 * to support ISO transfers yet.
955 */
956 if (int_usb & MUSB_INTR_SOF) {
957 void __iomem *mbase = musb->mregs;
958 struct musb_hw_ep *ep;
959 u8 epnum;
960 u16 frame;
961
5c8a86e1 962 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 963 handled = IRQ_HANDLED;
964
965 /* start any periodic Tx transfers waiting for current frame */
966 frame = musb_readw(mbase, MUSB_FRAME);
967 ep = musb->endpoints;
968 for (epnum = 1; (epnum < musb->nr_endpoints)
969 && (musb->epmask >= (1 << epnum));
970 epnum++, ep++) {
971 /*
972 * FIXME handle framecounter wraps (12 bits)
973 * eliminate duplicated StartUrb logic
974 */
975 if (ep->dwWaitFrame >= frame) {
976 ep->dwWaitFrame = 0;
977 pr_debug("SOF --> periodic TX%s on %d\n",
978 ep->tx_channel ? " DMA" : "",
979 epnum);
980 if (!ep->tx_channel)
981 musb_h_tx_start(musb, epnum);
982 else
983 cppi_hostdma_start(musb, epnum);
984 }
985 } /* end of for loop */
986 }
987#endif
988
1c25fda4 989 schedule_work(&musb->irq_work);
550a7375
FB		 990
991 return handled;
992}
993
994/*-------------------------------------------------------------------------*/
995
e1eb3eb8 996static void musb_disable_interrupts(struct musb *musb)
550a7375
FB		 997{
998 void __iomem *mbase = musb->mregs;
999 u16 temp;
1000
1001 /* disable interrupts */
1002 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 1003 musb->intrtxe = 0;
550a7375 1004 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 1005 musb->intrrxe = 0;
550a7375
FB		 1006 musb_writew(mbase, MUSB_INTRRXE, 0);
1007
550a7375
FB		 1008 /* flush pending interrupts */
1009 temp = musb_readb(mbase, MUSB_INTRUSB);
1010 temp = musb_readw(mbase, MUSB_INTRTX);
1011 temp = musb_readw(mbase, MUSB_INTRRX);
e1eb3eb8
FB		 1012}
1013
1014static void musb_enable_interrupts(struct musb *musb)
1015{
1016 void __iomem *regs = musb->mregs;
1017
1018 /* Set INT enable registers, enable interrupts */
1019 musb->intrtxe = musb->epmask;
1020 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1021 musb->intrrxe = musb->epmask & 0xfffe;
1022 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1023 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 1024
1025}
1026
e1eb3eb8
FB		 1027static void musb_generic_disable(struct musb *musb)
1028{
1029 void __iomem *mbase = musb->mregs;
1030
1031 musb_disable_interrupts(musb);
1032
1033 /* off */
1034 musb_writeb(mbase, MUSB_DEVCTL, 0);
1035}
1036
001dd84a
SAS		 1037/*
1038 * Program the HDRC to start (enable interrupts, dma, etc.).
1039 */
1040void musb_start(struct musb *musb)
1041{
1042 void __iomem *regs = musb->mregs;
1043 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
9b753764 1044 u8 power;
001dd84a 1045
b99d3659 1046 musb_dbg(musb, "<== devctl %02x", devctl);
001dd84a 1047
e1eb3eb8 1048 musb_enable_interrupts(musb);
001dd84a
SAS		 1049 musb_writeb(regs, MUSB_TESTMODE, 0);
1050
9b753764
BL		 1051 power = MUSB_POWER_ISOUPDATE;
1052 /*
1053 * treating UNKNOWN as unspecified maximum speed, in which case
1054 * we will default to high-speed.
1055 */
1056 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1057 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1058 power |= MUSB_POWER_HSENAB;
1059 musb_writeb(regs, MUSB_POWER, power);
001dd84a
SAS		 1060
1061 musb->is_active = 0;
1062 devctl = musb_readb(regs, MUSB_DEVCTL);
1063 devctl &= ~MUSB_DEVCTL_SESSION;
1064
1065 /* session started after:
1066 * (a) ID-grounded irq, host mode;
1067 * (b) vbus present/connect IRQ, peripheral mode;
1068 * (c) peripheral initiates, using SRP
1069 */
1070 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
40af177e 1071 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
001dd84a
SAS		 1072 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1073 musb->is_active = 1;
1074 } else {
1075 devctl |= MUSB_DEVCTL_SESSION;
1076 }
1077
1078 musb_platform_enable(musb);
1079 musb_writeb(regs, MUSB_DEVCTL, devctl);
1080}
1081
550a7375
FB		 1082/*
1083 * Make the HDRC stop (disable interrupts, etc.);
1084 * reversible by musb_start
1085 * called on gadget driver unregister
1086 * with controller locked, irqs blocked
1087 * acts as a NOP unless some role activated the hardware
1088 */
1089void musb_stop(struct musb *musb)
1090{
1091 /* stop IRQs, timers, ... */
1092 musb_platform_disable(musb);
1093 musb_generic_disable(musb);
b99d3659 1094 musb_dbg(musb, "HDRC disabled");
550a7375
FB		 1095
1096 /* FIXME
1097 * - mark host and/or peripheral drivers unusable/inactive
1098 * - disable DMA (and enable it in HdrcStart)
1099 * - make sure we can musb_start() after musb_stop(); with
1100 * OTG mode, gadget driver module rmmod/modprobe cycles that
1101 * - ...
1102 */
1103 musb_platform_try_idle(musb, 0);
1104}
1105
550a7375
FB		 1106/*-------------------------------------------------------------------------*/
1107
1108/*
1109 * The silicon either has hard-wired endpoint configurations, or else
1110 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1111 * writing only the dynamic sizing is very well tested. Since we switched
1112 * away from compile-time hardware parameters, we can no longer rely on
1113 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1114 *
1115 * We don't currently use dynamic fifo setup capability to do anything
1116 * more than selecting one of a bunch of predefined configurations.
1117 */
8a77f05a 1118static ushort fifo_mode;
550a7375
FB		 1119
1120/* "modprobe ... fifo_mode=1" etc */
1121module_param(fifo_mode, ushort, 0);
1122MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1123
550a7375
FB		 1124/*
1125 * tables defining fifo_mode values. define more if you like.
1126 * for host side, make sure both halves of ep1 are set up.
1127 */
1128
1129/* mode 0 - fits in 2KB */
d3608b6d 1130static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1131{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1132{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1133{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1134{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1135{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1136};
1137
1138/* mode 1 - fits in 4KB */
d3608b6d 1139static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1140{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1141{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1142{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1143{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1144{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1145};
1146
1147/* mode 2 - fits in 4KB */
d3608b6d 1148static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1149{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1150{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1151{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1152{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1153{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1154{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1155};
1156
1157/* mode 3 - fits in 4KB */
d3608b6d 1158static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1159{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1160{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1161{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1162{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1163{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1164{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1165};
1166
1167/* mode 4 - fits in 16KB */
d3608b6d 1168static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1169{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1170{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1171{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1172{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1173{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1174{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1175{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1176{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1177{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1178{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1179{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1180{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1181{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1182{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1183{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1184{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1185{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1186{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1187{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1188{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1189{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1190{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1191{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1192{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1193{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1194{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1195{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1196};
1197
3b151526 1198/* mode 5 - fits in 8KB */
d3608b6d 1199static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1200{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1201{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1202{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1203{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1204{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1205{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1206{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1207{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1208{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1209{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1210{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1211{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1212{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1213{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1214{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1215{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1216{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1217{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1218{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1219{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1220{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1221{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1222{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1223{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1224{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1225{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1226{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1227};
550a7375
FB		 1228
1229/*
1230 * configure a fifo; for non-shared endpoints, this may be called
1231 * once for a tx fifo and once for an rx fifo.
1232 *
1233 * returns negative errno or offset for next fifo.
1234 */
41ac7b3a 1235static int
550a7375 1236fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1237 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1238{
1239 void __iomem *mbase = musb->mregs;
1240 int size = 0;
1241 u16 maxpacket = cfg->maxpacket;
1242 u16 c_off = offset >> 3;
1243 u8 c_size;
1244
1245 /* expect hw_ep has already been zero-initialized */
1246
1247 size = ffs(max(maxpacket, (u16) 8)) - 1;
1248 maxpacket = 1 << size;
1249
1250 c_size = size - 3;
1251 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1252 if ((offset + (maxpacket << 1)) >
1253 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1254 return -EMSGSIZE;
1255 c_size |= MUSB_FIFOSZ_DPB;
1256 } else {
ca6d1b13 1257 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1258 return -EMSGSIZE;
1259 }
1260
1261 /* configure the FIFO */
1262 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1263
550a7375 1264 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1265 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1266 */
1267 if (hw_ep->epnum == 1)
1268 musb->bulk_ep = hw_ep;
1269 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1270 switch (cfg->style) {
1271 case FIFO_TX:
c6cf8b00
BW		 1272 musb_write_txfifosz(mbase, c_size);
1273 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1274 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1275 hw_ep->max_packet_sz_tx = maxpacket;
1276 break;
1277 case FIFO_RX:
c6cf8b00
BW		 1278 musb_write_rxfifosz(mbase, c_size);
1279 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1280 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1281 hw_ep->max_packet_sz_rx = maxpacket;
1282 break;
1283 case FIFO_RXTX:
c6cf8b00
BW		 1284 musb_write_txfifosz(mbase, c_size);
1285 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1286 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1287 hw_ep->max_packet_sz_rx = maxpacket;
1288
c6cf8b00
BW		 1289 musb_write_rxfifosz(mbase, c_size);
1290 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1291 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1292 hw_ep->max_packet_sz_tx = maxpacket;
1293
1294 hw_ep->is_shared_fifo = true;
1295 break;
1296 }
1297
1298 /* NOTE rx and tx endpoint irqs aren't managed separately,
1299 * which happens to be ok
1300 */
1301 musb->epmask |= (1 << hw_ep->epnum);
1302
1303 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1304}
1305
d3608b6d 1306static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1307 .style = FIFO_RXTX, .maxpacket = 64,
1308};
1309
41ac7b3a 1310static int ep_config_from_table(struct musb *musb)
550a7375 1311{
e6c213b2 1312 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1313 unsigned i, n;
1314 int offset;
1315 struct musb_hw_ep *hw_ep = musb->endpoints;
1316
e6c213b2
FB		 1317 if (musb->config->fifo_cfg) {
1318 cfg = musb->config->fifo_cfg;
1319 n = musb->config->fifo_cfg_size;
1320 goto done;
1321 }
1322
550a7375
FB		 1323 switch (fifo_mode) {
1324 default:
1325 fifo_mode = 0;
1326 /* FALLTHROUGH */
1327 case 0:
1328 cfg = mode_0_cfg;
1329 n = ARRAY_SIZE(mode_0_cfg);
1330 break;
1331 case 1:
1332 cfg = mode_1_cfg;
1333 n = ARRAY_SIZE(mode_1_cfg);
1334 break;
1335 case 2:
1336 cfg = mode_2_cfg;
1337 n = ARRAY_SIZE(mode_2_cfg);
1338 break;
1339 case 3:
1340 cfg = mode_3_cfg;
1341 n = ARRAY_SIZE(mode_3_cfg);
1342 break;
1343 case 4:
1344 cfg = mode_4_cfg;
1345 n = ARRAY_SIZE(mode_4_cfg);
1346 break;
3b151526
AKG		 1347 case 5:
1348 cfg = mode_5_cfg;
1349 n = ARRAY_SIZE(mode_5_cfg);
1350 break;
550a7375
FB		 1351 }
1352
3ff4b573 1353 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
550a7375
FB		 1354
1355
e6c213b2 1356done:
550a7375
FB		 1357 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1358 /* assert(offset > 0) */
1359
1360 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1361 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1362 */
1363
1364 for (i = 0; i < n; i++) {
1365 u8 epn = cfg->hw_ep_num;
1366
ca6d1b13 1367 if (epn >= musb->config->num_eps) {
550a7375
FB		 1368 pr_debug("%s: invalid ep %d\n",
1369 musb_driver_name, epn);
bb1c9ef1 1370 return -EINVAL;
550a7375
FB		 1371 }
1372 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1373 if (offset < 0) {
1374 pr_debug("%s: mem overrun, ep %d\n",
1375 musb_driver_name, epn);
f69dfa1f 1376 return offset;
550a7375
FB		 1377 }
1378 epn++;
1379 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1380 }
1381
3ff4b573 1382 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
550a7375 1383 musb_driver_name,
ca6d1b13
FB		 1384 n + 1, musb->config->num_eps * 2 - 1,
1385 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1386
550a7375
FB		 1387 if (!musb->bulk_ep) {
1388 pr_debug("%s: missing bulk\n", musb_driver_name);
1389 return -EINVAL;
1390 }
550a7375
FB		 1391
1392 return 0;
1393}
1394
1395
1396/*
1397 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1398 * @param musb the controller
1399 */
41ac7b3a 1400static int ep_config_from_hw(struct musb *musb)
550a7375 1401{
c6cf8b00 1402 u8 epnum = 0;
550a7375 1403 struct musb_hw_ep *hw_ep;
a156544b 1404 void __iomem *mbase = musb->mregs;
c6cf8b00 1405 int ret = 0;
550a7375 1406
b99d3659 1407 musb_dbg(musb, "<== static silicon ep config");
550a7375
FB		 1408
1409 /* FIXME pick up ep0 maxpacket size */
1410
ca6d1b13 1411 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1412 musb_ep_select(mbase, epnum);
1413 hw_ep = musb->endpoints + epnum;
1414
c6cf8b00
BW		 1415 ret = musb_read_fifosize(musb, hw_ep, epnum);
1416 if (ret < 0)
550a7375 1417 break;
550a7375
FB		 1418
1419 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1420
550a7375
FB		 1421 /* pick an RX/TX endpoint for bulk */
1422 if (hw_ep->max_packet_sz_tx < 512
1423 || hw_ep->max_packet_sz_rx < 512)
1424 continue;
1425
1426 /* REVISIT: this algorithm is lazy, we should at least
1427 * try to pick a double buffered endpoint.
1428 */
1429 if (musb->bulk_ep)
1430 continue;
1431 musb->bulk_ep = hw_ep;
550a7375
FB		 1432 }
1433
550a7375
FB		 1434 if (!musb->bulk_ep) {
1435 pr_debug("%s: missing bulk\n", musb_driver_name);
1436 return -EINVAL;
1437 }
550a7375
FB		 1438
1439 return 0;
1440}
1441
1442enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1443
1444/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1445 * configure endpoints, or take their config from silicon
1446 */
41ac7b3a 1447static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1448{
550a7375
FB		 1449 u8 reg;
1450 char *type;
21b031fb 1451 char aInfo[90];
550a7375
FB		 1452 void __iomem *mbase = musb->mregs;
1453 int status = 0;
1454 int i;
1455
1456 /* log core options (read using indexed model) */
c6cf8b00 1457 reg = musb_read_configdata(mbase);
550a7375
FB		 1458
1459 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1460 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1461 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1462 musb->dyn_fifo = true;
1463 }
550a7375
FB		 1464 if (reg & MUSB_CONFIGDATA_MPRXE) {
1465 strcat(aInfo, ", bulk combine");
550a7375 1466 musb->bulk_combine = true;
550a7375
FB		 1467 }
1468 if (reg & MUSB_CONFIGDATA_MPTXE) {
1469 strcat(aInfo, ", bulk split");
550a7375 1470 musb->bulk_split = true;
550a7375
FB		 1471 }
1472 if (reg & MUSB_CONFIGDATA_HBRXE) {
1473 strcat(aInfo, ", HB-ISO Rx");
a483d706 1474 musb->hb_iso_rx = true;
550a7375
FB		 1475 }
1476 if (reg & MUSB_CONFIGDATA_HBTXE) {
1477 strcat(aInfo, ", HB-ISO Tx");
a483d706 1478 musb->hb_iso_tx = true;
550a7375
FB		 1479 }
1480 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1481 strcat(aInfo, ", SoftConn");
1482
3ff4b573 1483 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
550a7375 1484
550a7375
FB		 1485 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1486 musb->is_multipoint = 1;
1487 type = "M";
1488 } else {
1489 musb->is_multipoint = 0;
1490 type = "";
550a7375 1491#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
3ff4b573
RV		 1492 pr_err("%s: kernel must blacklist external hubs\n",
1493 musb_driver_name);
550a7375
FB		 1494#endif
1495 }
1496
1497 /* log release info */
32c3b94e 1498 musb->hwvers = musb_read_hwvers(mbase);
21b031fb
RV		 1499 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1500 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1501 MUSB_HWVERS_MINOR(musb->hwvers),
1502 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1503
1504 /* configure ep0 */
c6cf8b00 1505 musb_configure_ep0(musb);
550a7375
FB		 1506
1507 /* discover endpoint configuration */
1508 musb->nr_endpoints = 1;
1509 musb->epmask = 1;
1510
ad517e9e
FB		 1511 if (musb->dyn_fifo)
1512 status = ep_config_from_table(musb);
1513 else
1514 status = ep_config_from_hw(musb);
550a7375
FB		 1515
1516 if (status < 0)
1517 return status;
1518
1519 /* finish init, and print endpoint config */
1520 for (i = 0; i < musb->nr_endpoints; i++) {
1521 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1522
1b40fc57 1523 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
ebf39920 1524#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1b40fc57
TL		 1525 if (musb->io.quirks & MUSB_IN_TUSB) {
1526 hw_ep->fifo_async = musb->async + 0x400 +
1527 musb->io.fifo_offset(i);
1528 hw_ep->fifo_sync = musb->sync + 0x400 +
1529 musb->io.fifo_offset(i);
1530 hw_ep->fifo_sync_va =
1531 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1532
1533 if (i == 0)
1534 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1535 else
1536 hw_ep->conf = mbase + 0x400 +
1537 (((i - 1) & 0xf) << 2);
1538 }
550a7375
FB		 1539#endif
1540
d026e9c7 1541 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
550a7375
FB		 1542 hw_ep->rx_reinit = 1;
1543 hw_ep->tx_reinit = 1;
550a7375
FB		 1544
1545 if (hw_ep->max_packet_sz_tx) {
b99d3659 1546 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
550a7375
FB		 1547 musb_driver_name, i,
1548 hw_ep->is_shared_fifo ? "shared" : "tx",
1549 hw_ep->tx_double_buffered
1550 ? "doublebuffer, " : "",
1551 hw_ep->max_packet_sz_tx);
1552 }
1553 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
b99d3659 1554 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
550a7375
FB		 1555 musb_driver_name, i,
1556 "rx",
1557 hw_ep->rx_double_buffered
1558 ? "doublebuffer, " : "",
1559 hw_ep->max_packet_sz_rx);
1560 }
1561 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
b99d3659 1562 musb_dbg(musb, "hw_ep %d not configured", i);
550a7375
FB		 1563 }
1564
1565 return 0;
1566}
1567
1568/*-------------------------------------------------------------------------*/
1569
550a7375
FB		 1570/*
1571 * handle all the irqs defined by the HDRC core. for now we expect: other
1572 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1573 * will be assigned, and the irq will already have been acked.
1574 *
1575 * called in irq context with spinlock held, irqs blocked
1576 */
1577irqreturn_t musb_interrupt(struct musb *musb)
1578{
1579 irqreturn_t retval = IRQ_NONE;
31a0ede0
FB		 1580 unsigned long status;
1581 unsigned long epnum;
b11e94d0 1582 u8 devctl;
31a0ede0
FB		 1583
1584 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1585 return IRQ_NONE;
550a7375
FB		 1586
1587 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1588
cfb9a1bc 1589 trace_musb_isr(musb);
550a7375 1590
e3c93e1a
FB		 1591 /**
1592 * According to Mentor Graphics' documentation, flowchart on page 98,
1593 * IRQ should be handled as follows:
1594 *
1595 * . Resume IRQ
1596 * . Session Request IRQ
1597 * . VBUS Error IRQ
1598 * . Suspend IRQ
1599 * . Connect IRQ
1600 * . Disconnect IRQ
1601 * . Reset/Babble IRQ
1602 * . SOF IRQ (we're not using this one)
1603 * . Endpoint 0 IRQ
1604 * . TX Endpoints
1605 * . RX Endpoints
1606 *
1607 * We will be following that flowchart in order to avoid any problems
1608 * that might arise with internal Finite State Machine.
550a7375 1609 */
e3c93e1a 1610
7d9645fd 1611 if (musb->int_usb)
31a0ede0 1612 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
550a7375 1613
550a7375 1614 if (musb->int_tx & 1) {
c03da38d 1615 if (is_host_active(musb))
550a7375
FB		 1616 retval |= musb_h_ep0_irq(musb);
1617 else
1618 retval |= musb_g_ep0_irq(musb);
31a0ede0
FB		 1619
1620 /* we have just handled endpoint 0 IRQ, clear it */
1621 musb->int_tx &= ~BIT(0);
550a7375
FB		 1622 }
1623
31a0ede0
FB		 1624 status = musb->int_tx;
1625
1626 for_each_set_bit(epnum, &status, 16) {
1627 retval = IRQ_HANDLED;
1628 if (is_host_active(musb))
1629 musb_host_tx(musb, epnum);
1630 else
1631 musb_g_tx(musb, epnum);
550a7375
FB		 1632 }
1633
31a0ede0 1634 status = musb->int_rx;
e3c93e1a 1635
31a0ede0
FB		 1636 for_each_set_bit(epnum, &status, 16) {
1637 retval = IRQ_HANDLED;
1638 if (is_host_active(musb))
1639 musb_host_rx(musb, epnum);
1640 else
1641 musb_g_rx(musb, epnum);
550a7375
FB		 1642 }
1643
550a7375
FB		 1644 return retval;
1645}
981430a1 1646EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1647
1648#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1649static bool use_dma = 1;
550a7375
FB		 1650
1651/* "modprobe ... use_dma=0" etc */
51676c8d 1652module_param(use_dma, bool, 0644);
550a7375
FB		 1653MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1654
1655void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1656{
550a7375
FB		 1657 /* called with controller lock already held */
1658
1659 if (!epnum) {
f8e9f34f 1660 if (!is_cppi_enabled(musb)) {
550a7375 1661 /* endpoint 0 */
c03da38d 1662 if (is_host_active(musb))
550a7375
FB		 1663 musb_h_ep0_irq(musb);
1664 else
1665 musb_g_ep0_irq(musb);
1666 }
550a7375
FB		 1667 } else {
1668 /* endpoints 1..15 */
1669 if (transmit) {
c03da38d 1670 if (is_host_active(musb))
a04d46d0
FB		 1671 musb_host_tx(musb, epnum);
1672 else
1673 musb_g_tx(musb, epnum);
550a7375
FB		 1674 } else {
1675 /* receive */
c03da38d 1676 if (is_host_active(musb))
a04d46d0
FB		 1677 musb_host_rx(musb, epnum);
1678 else
1679 musb_g_rx(musb, epnum);
550a7375
FB		 1680 }
1681 }
1682}
9a35f876 1683EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1684
1685#else
1686#define use_dma 0
1687#endif
1688
12b7db2b 1689static int (*musb_phy_callback)(enum musb_vbus_id_status status);
8055555f
TL		 1690
1691/*
1692 * musb_mailbox - optional phy notifier function
1693 * @status phy state change
1694 *
1695 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1696 * disabled at the point the phy_callback is registered or unregistered.
1697 */
12b7db2b 1698int musb_mailbox(enum musb_vbus_id_status status)
8055555f
TL		 1699{
1700 if (musb_phy_callback)
12b7db2b 1701 return musb_phy_callback(status);
8055555f 1702
12b7db2b 1703 return -ENODEV;
8055555f
TL		 1704};
1705EXPORT_SYMBOL_GPL(musb_mailbox);
1706
550a7375
FB		 1707/*-------------------------------------------------------------------------*/
1708
550a7375
FB		 1709static ssize_t
1710musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1711{
1712 struct musb *musb = dev_to_musb(dev);
1713 unsigned long flags;
1714 int ret = -EINVAL;
1715
1716 spin_lock_irqsave(&musb->lock, flags);
e47d9254 1717 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 1718 spin_unlock_irqrestore(&musb->lock, flags);
1719
1720 return ret;
1721}
1722
1723static ssize_t
1724musb_mode_store(struct device *dev, struct device_attribute *attr,
1725 const char *buf, size_t n)
1726{
1727 struct musb *musb = dev_to_musb(dev);
1728 unsigned long flags;
96a274d1 1729 int status;
550a7375
FB		 1730
1731 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1732 if (sysfs_streq(buf, "host"))
1733 status = musb_platform_set_mode(musb, MUSB_HOST);
1734 else if (sysfs_streq(buf, "peripheral"))
1735 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1736 else if (sysfs_streq(buf, "otg"))
1737 status = musb_platform_set_mode(musb, MUSB_OTG);
1738 else
1739 status = -EINVAL;
550a7375
FB		 1740 spin_unlock_irqrestore(&musb->lock, flags);
1741
96a274d1 1742 return (status == 0) ? n : status;
550a7375
FB		 1743}
1744static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1745
1746static ssize_t
1747musb_vbus_store(struct device *dev, struct device_attribute *attr,
1748 const char *buf, size_t n)
1749{
1750 struct musb *musb = dev_to_musb(dev);
1751 unsigned long flags;
1752 unsigned long val;
1753
1754 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1755 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1756 return -EINVAL;
1757 }
1758
1759 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1760 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1761 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
e47d9254 1762 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1763 musb->is_active = 0;
1764 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1765 spin_unlock_irqrestore(&musb->lock, flags);
1766
1767 return n;
1768}
1769
1770static ssize_t
1771musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1772{
1773 struct musb *musb = dev_to_musb(dev);
1774 unsigned long flags;
1775 unsigned long val;
1776 int vbus;
3bbafac8 1777 u8 devctl;
550a7375
FB		 1778
1779 spin_lock_irqsave(&musb->lock, flags);
1780 val = musb->a_wait_bcon;
1781 vbus = musb_platform_get_vbus_status(musb);
3bbafac8
RA		 1782 if (vbus < 0) {
1783 /* Use default MUSB method by means of DEVCTL register */
1784 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1785 if ((devctl & MUSB_DEVCTL_VBUS)
1786 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1787 vbus = 1;
1788 else
1789 vbus = 0;
1790 }
550a7375
FB		 1791 spin_unlock_irqrestore(&musb->lock, flags);
1792
f7f9d63e 1793 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1794 vbus ? "on" : "off", val);
1795}
1796static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1797
550a7375
FB		 1798/* Gadget drivers can't know that a host is connected so they might want
1799 * to start SRP, but users can. This allows userspace to trigger SRP.
1800 */
1801static ssize_t
1802musb_srp_store(struct device *dev, struct device_attribute *attr,
1803 const char *buf, size_t n)
1804{
1805 struct musb *musb = dev_to_musb(dev);
1806 unsigned short srp;
1807
1808 if (sscanf(buf, "%hu", &srp) != 1
1809 || (srp != 1)) {
b3b1cc3b 1810 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1811 return -EINVAL;
1812 }
1813
1814 if (srp == 1)
1815 musb_g_wakeup(musb);
1816
1817 return n;
1818}
1819static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1820
94375751
FB		 1821static struct attribute *musb_attributes[] = {
1822 &dev_attr_mode.attr,
1823 &dev_attr_vbus.attr,
94375751 1824 &dev_attr_srp.attr,
94375751
FB		 1825 NULL
1826};
1827
1828static const struct attribute_group musb_attr_group = {
1829 .attrs = musb_attributes,
1830};
1831
467d5c98
TL		 1832#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1833 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1834 MUSB_DEVCTL_SESSION)
1835#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1836 MUSB_DEVCTL_SESSION)
1837
1838/*
1839 * Check the musb devctl session bit to determine if we want to
1840 * allow PM runtime for the device. In general, we want to keep things
1841 * active when the session bit is set except after host disconnect.
1842 *
1843 * Only called from musb_irq_work. If this ever needs to get called
1844 * elsewhere, proper locking must be implemented for musb->session.
1845 */
1846static void musb_pm_runtime_check_session(struct musb *musb)
1847{
1848 u8 devctl, s;
1849 int error;
1850
1851 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1852
1853 /* Handle session status quirks first */
1854 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
1855 MUSB_DEVCTL_HR;
1856 switch (devctl & ~s) {
1857 case MUSB_QUIRK_B_INVALID_VBUS_91:
2b9a8c40
TL		 1858 if (!musb->session && !musb->quirk_invalid_vbus) {
1859 musb->quirk_invalid_vbus = true;
1860 musb_dbg(musb,
1861 "First invalid vbus, assume no session");
1862 return;
1863 }
1864 break;
467d5c98
TL		 1865 case MUSB_QUIRK_A_DISCONNECT_19:
1866 if (!musb->session)
1867 break;
1868 musb_dbg(musb, "Allow PM on possible host mode disconnect");
1869 pm_runtime_mark_last_busy(musb->controller);
1870 pm_runtime_put_autosuspend(musb->controller);
1871 musb->session = false;
1872 return;
1873 default:
1874 break;
1875 }
1876
1877 /* No need to do anything if session has not changed */
1878 s = devctl & MUSB_DEVCTL_SESSION;
1879 if (s == musb->session)
1880 return;
1881
1882 /* Block PM or allow PM? */
1883 if (s) {
1884 musb_dbg(musb, "Block PM on active session: %02x", devctl);
1885 error = pm_runtime_get_sync(musb->controller);
1886 if (error < 0)
1887 dev_err(musb->controller, "Could not enable: %i\n",
1888 error);
1889 } else {
1890 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
2b9a8c40 1891 musb->quirk_invalid_vbus = false;
467d5c98
TL		 1892 pm_runtime_mark_last_busy(musb->controller);
1893 pm_runtime_put_autosuspend(musb->controller);
1894 }
1895
1896 musb->session = s;
1897}
1898
550a7375
FB		 1899/* Only used to provide driver mode change events */
1900static void musb_irq_work(struct work_struct *data)
1901{
1902 struct musb *musb = container_of(data, struct musb, irq_work);
550a7375 1903
467d5c98
TL		 1904 musb_pm_runtime_check_session(musb);
1905
e47d9254
AT		 1906 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1907 musb->xceiv_old_state = musb->xceiv->otg->state;
550a7375
FB		 1908 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1909 }
1910}
1911
83b8f5b8 1912static void musb_recover_from_babble(struct musb *musb)
ca88fc2e 1913{
b4dc38fd
FB		 1914 int ret;
1915 u8 devctl;
ca88fc2e 1916
0244336f
FB		 1917 musb_disable_interrupts(musb);
1918
83b8f5b8
FB		 1919 /*
1920 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1921 * it some slack and wait for 10us.
1922 */
1923 udelay(10);
1924
b28a6432 1925 ret = musb_platform_recover(musb);
ba7ee8bb
FB		 1926 if (ret) {
1927 musb_enable_interrupts(musb);
d871c622 1928 return;
ba7ee8bb 1929 }
ca88fc2e 1930
b4dc38fd
FB		 1931 /* drop session bit */
1932 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1933 devctl &= ~MUSB_DEVCTL_SESSION;
1934 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
ca88fc2e 1935
b4dc38fd
FB		 1936 /* tell usbcore about it */
1937 musb_root_disconnect(musb);
ca88fc2e
DM		 1938
1939 /*
d871c622
GC		 1940 * When a babble condition occurs, the musb controller
1941 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1942 */
1943 if (musb->dyn_fifo)
b4dc38fd 1944 ret = ep_config_from_table(musb);
ca88fc2e 1945 else
b4dc38fd 1946 ret = ep_config_from_hw(musb);
ca88fc2e 1947
b4dc38fd
FB		 1948 /* restart session */
1949 if (ret == 0)
ca88fc2e
DM		 1950 musb_start(musb);
1951}
1952
550a7375
FB		 1953/* --------------------------------------------------------------------------
1954 * Init support
1955 */
1956
41ac7b3a 1957static struct musb *allocate_instance(struct device *dev,
ead22caf 1958 const struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1959{
1960 struct musb *musb;
1961 struct musb_hw_ep *ep;
1962 int epnum;
74c2e936 1963 int ret;
550a7375 1964
74c2e936
DM		 1965 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1966 if (!musb)
550a7375 1967 return NULL;
550a7375 1968
550a7375
FB		 1969 INIT_LIST_HEAD(&musb->control);
1970 INIT_LIST_HEAD(&musb->in_bulk);
1971 INIT_LIST_HEAD(&musb->out_bulk);
1972
550a7375 1973 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1974 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 1975 musb->mregs = mbase;
1976 musb->ctrl_base = mbase;
1977 musb->nIrq = -ENODEV;
ca6d1b13 1978 musb->config = config;
02582b92 1979 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1980 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1981 epnum < musb->config->num_eps;
550a7375 1982 epnum++, ep++) {
550a7375
FB		 1983 ep->musb = musb;
1984 ep->epnum = epnum;
1985 }
1986
1987 musb->controller = dev;
743411b3 1988
74c2e936
DM		 1989 ret = musb_host_alloc(musb);
1990 if (ret < 0)
1991 goto err_free;
1992
1993 dev_set_drvdata(dev, musb);
1994
550a7375 1995 return musb;
74c2e936
DM		 1996
1997err_free:
1998 return NULL;
550a7375
FB		 1999}
2000
2001static void musb_free(struct musb *musb)
2002{
2003 /* this has multiple entry modes. it handles fault cleanup after
2004 * probe(), where things may be partially set up, as well as rmmod
2005 * cleanup after everything's been de-activated.
2006 */
2007
2008#ifdef CONFIG_SYSFS
94375751 2009 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 2010#endif
2011
97a39896
AKG		 2012 if (musb->nIrq >= 0) {
2013 if (musb->irq_wake)
2014 disable_irq_wake(musb->nIrq);
550a7375
FB		 2015 free_irq(musb->nIrq, musb);
2016 }
550a7375 2017
74c2e936 2018 musb_host_free(musb);
550a7375
FB		 2019}
2020
8ed1fb79
DM		 2021static void musb_deassert_reset(struct work_struct *work)
2022{
2023 struct musb *musb;
2024 unsigned long flags;
2025
2026 musb = container_of(work, struct musb, deassert_reset_work.work);
2027
2028 spin_lock_irqsave(&musb->lock, flags);
2029
2030 if (musb->port1_status & USB_PORT_STAT_RESET)
2031 musb_port_reset(musb, false);
2032
2033 spin_unlock_irqrestore(&musb->lock, flags);
2034}
2035
550a7375
FB		 2036/*
2037 * Perform generic per-controller initialization.
2038 *
28dd924a
SS		 2039 * @dev: the controller (already clocked, etc)
2040 * @nIrq: IRQ number
2041 * @ctrl: virtual address of controller registers,
550a7375
FB		 2042 * not yet corrected for platform-specific offsets
2043 */
41ac7b3a 2044static int
550a7375
FB		 2045musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2046{
2047 int status;
2048 struct musb *musb;
c1a7d67c 2049 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 2050
2051 /* The driver might handle more features than the board; OK.
2052 * Fail when the board needs a feature that's not enabled.
2053 */
2054 if (!plat) {
b99d3659 2055 dev_err(dev, "no platform_data?\n");
34e2beb2
SS		 2056 status = -ENODEV;
2057 goto fail0;
550a7375 2058 }
34e2beb2 2059
550a7375 2060 /* allocate */
ca6d1b13 2061 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 2062 if (!musb) {
2063 status = -ENOMEM;
2064 goto fail0;
2065 }
550a7375
FB		 2066
2067 spin_lock_init(&musb->lock);
550a7375 2068 musb->board_set_power = plat->set_power;
550a7375 2069 musb->min_power = plat->min_power;
f7ec9437 2070 musb->ops = plat->platform_ops;
9ad96e69 2071 musb->port_mode = plat->mode;
550a7375 2072
1b40fc57
TL		 2073 /*
2074 * Initialize the default IO functions. At least omap2430 needs
2075 * these early. We initialize the platform specific IO functions
2076 * later on.
2077 */
2078 musb_readb = musb_default_readb;
2079 musb_writeb = musb_default_writeb;
2080 musb_readw = musb_default_readw;
2081 musb_writew = musb_default_writew;
2082 musb_readl = musb_default_readl;
2083 musb_writel = musb_default_writel;
2084
84e250ff 2085 /* The musb_platform_init() call:
baef653a
PDS		 2086 * - adjusts musb->mregs
2087 * - sets the musb->isr
5ae477b0 2088 * - may initialize an integrated transceiver
721002ec 2089 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 2090 * - stops powering VBUS
84e250ff 2091 *
7c9d440e 2092 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 2093 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2094 * external/discrete ones in various flavors (twl4030 family,
2095 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 2096 */
ea65df57 2097 status = musb_platform_init(musb);
550a7375 2098 if (status < 0)
03491761 2099 goto fail1;
34e2beb2 2100
550a7375
FB		 2101 if (!musb->isr) {
2102 status = -ENODEV;
c04352a5 2103 goto fail2;
550a7375
FB		 2104 }
2105
1b40fc57
TL		 2106 if (musb->ops->quirks)
2107 musb->io.quirks = musb->ops->quirks;
2108
da96cfc1 2109 /* Most devices use indexed offset or flat offset */
d026e9c7
TL		 2110 if (musb->io.quirks & MUSB_INDEXED_EP) {
2111 musb->io.ep_offset = musb_indexed_ep_offset;
2112 musb->io.ep_select = musb_indexed_ep_select;
2113 } else {
2114 musb->io.ep_offset = musb_flat_ep_offset;
2115 musb->io.ep_select = musb_flat_ep_select;
2116 }
2117
da96cfc1
BH		 2118 /* At least tusb6010 has its own offsets */
2119 if (musb->ops->ep_offset)
2120 musb->io.ep_offset = musb->ops->ep_offset;
2121 if (musb->ops->ep_select)
2122 musb->io.ep_select = musb->ops->ep_select;
2123
8a77f05a
TL		 2124 if (musb->ops->fifo_mode)
2125 fifo_mode = musb->ops->fifo_mode;
2126 else
2127 fifo_mode = 4;
2128
1b40fc57
TL		 2129 if (musb->ops->fifo_offset)
2130 musb->io.fifo_offset = musb->ops->fifo_offset;
2131 else
2132 musb->io.fifo_offset = musb_default_fifo_offset;
2133
6cc2af6d
HG		 2134 if (musb->ops->busctl_offset)
2135 musb->io.busctl_offset = musb->ops->busctl_offset;
2136 else
2137 musb->io.busctl_offset = musb_default_busctl_offset;
2138
1b40fc57
TL		 2139 if (musb->ops->readb)
2140 musb_readb = musb->ops->readb;
2141 if (musb->ops->writeb)
2142 musb_writeb = musb->ops->writeb;
2143 if (musb->ops->readw)
2144 musb_readw = musb->ops->readw;
2145 if (musb->ops->writew)
2146 musb_writew = musb->ops->writew;
2147 if (musb->ops->readl)
2148 musb_readl = musb->ops->readl;
2149 if (musb->ops->writel)
2150 musb_writel = musb->ops->writel;
2151
7f6283ed
TL		 2152#ifndef CONFIG_MUSB_PIO_ONLY
2153 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2154 dev_err(dev, "DMA controller not set\n");
7d32cdef 2155 status = -ENODEV;
7f6283ed
TL		 2156 goto fail2;
2157 }
2158 musb_dma_controller_create = musb->ops->dma_init;
2159 musb_dma_controller_destroy = musb->ops->dma_exit;
2160#endif
2161
1b40fc57
TL		 2162 if (musb->ops->read_fifo)
2163 musb->io.read_fifo = musb->ops->read_fifo;
2164 else
2165 musb->io.read_fifo = musb_default_read_fifo;
2166
2167 if (musb->ops->write_fifo)
2168 musb->io.write_fifo = musb->ops->write_fifo;
2169 else
2170 musb->io.write_fifo = musb_default_write_fifo;
2171
ffb865b1 2172 if (!musb->xceiv->io_ops) {
bf070bc1 2173 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 2174 musb->xceiv->io_priv = musb->mregs;
2175 musb->xceiv->io_ops = &musb_ulpi_access;
2176 }
2177
8055555f
TL		 2178 if (musb->ops->phy_callback)
2179 musb_phy_callback = musb->ops->phy_callback;
2180
f730f205
TL		 2181 /*
2182 * We need musb_read/write functions initialized for PM.
2183 * Note that at least 2430 glue needs autosuspend delay
2184 * somewhere above 300 ms for the hardware to idle properly
2185 * after disconnecting the cable in host mode. Let's use
2186 * 500 ms for some margin.
2187 */
2188 pm_runtime_use_autosuspend(musb->controller);
2189 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2190 pm_runtime_enable(musb->controller);
c04352a5
GI		 2191 pm_runtime_get_sync(musb->controller);
2192
39cee200
UKK		 2193 status = usb_phy_init(musb->xceiv);
2194 if (status < 0)
2195 goto err_usb_phy_init;
2196
48054147 2197 if (use_dma && dev->dma_mask) {
7f6283ed
TL		 2198 musb->dma_controller =
2199 musb_dma_controller_create(musb, musb->mregs);
48054147
SAS		 2200 if (IS_ERR(musb->dma_controller)) {
2201 status = PTR_ERR(musb->dma_controller);
2202 goto fail2_5;
2203 }
2204 }
550a7375
FB		 2205
2206 /* be sure interrupts are disabled before connecting ISR */
2207 musb_platform_disable(musb);
2208 musb_generic_disable(musb);
2209
66fadea5
SAS		 2210 /* Init IRQ workqueue before request_irq */
2211 INIT_WORK(&musb->irq_work, musb_irq_work);
8ed1fb79
DM		 2212 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2213 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 2214
550a7375 2215 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 2216 status = musb_core_init(plat->config->multipoint
550a7375
FB		 2217 ? MUSB_CONTROLLER_MHDRC
2218 : MUSB_CONTROLLER_HDRC, musb);
2219 if (status < 0)
34e2beb2 2220 goto fail3;
550a7375 2221
f7f9d63e 2222 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 2223
550a7375 2224 /* attach to the IRQ */
427c4f33 2225 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 2226 dev_err(dev, "request_irq %d failed!\n", nIrq);
2227 status = -ENODEV;
34e2beb2 2228 goto fail3;
550a7375
FB		 2229 }
2230 musb->nIrq = nIrq;
032ec49f 2231 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2232 if (enable_irq_wake(nIrq) == 0) {
2233 musb->irq_wake = 1;
550a7375 2234 device_init_wakeup(dev, 1);
c48a5155
FB		 2235 } else {
2236 musb->irq_wake = 0;
2237 }
550a7375 2238
032ec49f
FB		 2239 /* program PHY to use external vBus if required */
2240 if (plat->extvbus) {
2241 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2242 busctl |= MUSB_ULPI_USE_EXTVBUS;
2243 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 2244 }
550a7375 2245
e5615112
GI		 2246 if (musb->xceiv->otg->default_a) {
2247 MUSB_HST_MODE(musb);
e47d9254 2248 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
e5615112
GI		 2249 } else {
2250 MUSB_DEV_MODE(musb);
e47d9254 2251 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
e5615112 2252 }
550a7375 2253
6c5f6a6f
DM		 2254 switch (musb->port_mode) {
2255 case MUSB_PORT_MODE_HOST:
2256 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 2257 if (status < 0)
2258 goto fail3;
2259 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f
DM		 2260 break;
2261 case MUSB_PORT_MODE_GADGET:
2262 status = musb_gadget_setup(musb);
2df6761e
FB		 2263 if (status < 0)
2264 goto fail3;
2265 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f
DM		 2266 break;
2267 case MUSB_PORT_MODE_DUAL_ROLE:
2268 status = musb_host_setup(musb, plat->power);
2269 if (status < 0)
2270 goto fail3;
2271 status = musb_gadget_setup(musb);
2df6761e 2272 if (status) {
0d2dd7ea 2273 musb_host_cleanup(musb);
2df6761e
FB		 2274 goto fail3;
2275 }
2276 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2277 break;
2278 default:
2279 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2280 break;
2281 }
550a7375 2282
461972d8 2283 if (status < 0)
34e2beb2 2284 goto fail3;
550a7375 2285
7f7f9e2a
FB		 2286 status = musb_init_debugfs(musb);
2287 if (status < 0)
b0f9da7e 2288 goto fail4;
7f7f9e2a 2289
94375751 2290 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2291 if (status)
b0f9da7e 2292 goto fail5;
550a7375 2293
7099dbc5
TL		 2294 pm_runtime_mark_last_busy(musb->controller);
2295 pm_runtime_put_autosuspend(musb->controller);
c04352a5 2296
28c2c51c 2297 return 0;
550a7375 2298
b0f9da7e
FB		 2299fail5:
2300 musb_exit_debugfs(musb);
2301
34e2beb2 2302fail4:
032ec49f 2303 musb_gadget_cleanup(musb);
0d2dd7ea 2304 musb_host_cleanup(musb);
34e2beb2
SS		 2305
2306fail3:
66fadea5 2307 cancel_work_sync(&musb->irq_work);
8ed1fb79
DM		 2308 cancel_delayed_work_sync(&musb->finish_resume_work);
2309 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b 2310 if (musb->dma_controller)
7f6283ed 2311 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2312
48054147 2313fail2_5:
39cee200
UKK		 2314 usb_phy_shutdown(musb->xceiv);
2315
2316err_usb_phy_init:
7099dbc5 2317 pm_runtime_dont_use_autosuspend(musb->controller);
c04352a5 2318 pm_runtime_put_sync(musb->controller);
f730f205 2319 pm_runtime_disable(musb->controller);
c04352a5
GI		 2320
2321fail2:
34e2beb2
SS		 2322 if (musb->irq_wake)
2323 device_init_wakeup(dev, 0);
550a7375 2324 musb_platform_exit(musb);
28c2c51c 2325
34e2beb2
SS		 2326fail1:
2327 dev_err(musb->controller,
2328 "musb_init_controller failed with status %d\n", status);
2329
28c2c51c
FB		 2330 musb_free(musb);
2331
34e2beb2
SS		 2332fail0:
2333
28c2c51c
FB		 2334 return status;
2335
550a7375
FB		 2336}
2337
2338/*-------------------------------------------------------------------------*/
2339
2340/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2341 * bridge to a platform device; this driver then suffices.
2342 */
41ac7b3a 2343static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2344{
2345 struct device *dev = &pdev->dev;
fcf173e4 2346 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2347 struct resource *iomem;
2348 void __iomem *base;
2349
1f79b26c 2350 if (irq <= 0)
550a7375
FB		 2351 return -ENODEV;
2352
1f79b26c 2353 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b42f7f30
FB		 2354 base = devm_ioremap_resource(dev, iomem);
2355 if (IS_ERR(base))
2356 return PTR_ERR(base);
550a7375 2357
b42f7f30 2358 return musb_init_controller(dev, irq, base);
550a7375
FB		 2359}
2360
fb4e98ab 2361static int musb_remove(struct platform_device *pdev)
550a7375 2362{
8d2421e6
AKG		 2363 struct device *dev = &pdev->dev;
2364 struct musb *musb = dev_to_musb(dev);
302f6802 2365 unsigned long flags;
550a7375
FB		 2366
2367 /* this gets called on rmmod.
2368 * - Host mode: host may still be active
2369 * - Peripheral mode: peripheral is deactivated (or never-activated)
2370 * - OTG mode: both roles are deactivated (or never-activated)
2371 */
7f7f9e2a 2372 musb_exit_debugfs(musb);
302f6802 2373
f730f205
TL		 2374 cancel_work_sync(&musb->irq_work);
2375 cancel_delayed_work_sync(&musb->finish_resume_work);
2376 cancel_delayed_work_sync(&musb->deassert_reset_work);
302f6802
TL		 2377 pm_runtime_get_sync(musb->controller);
2378 musb_host_cleanup(musb);
2379 musb_gadget_cleanup(musb);
2380 spin_lock_irqsave(&musb->lock, flags);
2381 musb_platform_disable(musb);
2382 musb_generic_disable(musb);
2383 spin_unlock_irqrestore(&musb->lock, flags);
2384 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
f730f205
TL		 2385 pm_runtime_dont_use_autosuspend(musb->controller);
2386 pm_runtime_put_sync(musb->controller);
2387 pm_runtime_disable(musb->controller);
302f6802 2388 musb_platform_exit(musb);
8055555f 2389 musb_phy_callback = NULL;
8d1aad74 2390 if (musb->dma_controller)
7f6283ed 2391 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2392 usb_phy_shutdown(musb->xceiv);
550a7375 2393 musb_free(musb);
8d2421e6 2394 device_init_wakeup(dev, 0);
550a7375
FB		 2395 return 0;
2396}
2397
2398#ifdef CONFIG_PM
2399
3c8a5fcc 2400static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2401{
2402 int i;
2403 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2404 void __iomem *epio;
4f712e01 2405
032ec49f
FB		 2406 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2407 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2408 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2409 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2410 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2411 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2412 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2413
ae9b2ad2 2414 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2415 struct musb_hw_ep *hw_ep;
2416
2417 hw_ep = &musb->endpoints[i];
2418 if (!hw_ep)
2419 continue;
2420
2421 epio = hw_ep->regs;
2422 if (!epio)
2423 continue;
2424
ea737554 2425 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2426 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2427 musb_readw(epio, MUSB_TXMAXP);
7421107b 2428 musb->context.index_regs[i].txcsr =
ae9b2ad2 2429 musb_readw(epio, MUSB_TXCSR);
7421107b 2430 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2431 musb_readw(epio, MUSB_RXMAXP);
7421107b 2432 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2433 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2434
2435 if (musb->dyn_fifo) {
7421107b 2436 musb->context.index_regs[i].txfifoadd =
4f712e01 2437 musb_read_txfifoadd(musb_base);
7421107b 2438 musb->context.index_regs[i].rxfifoadd =
4f712e01 2439 musb_read_rxfifoadd(musb_base);
7421107b 2440 musb->context.index_regs[i].txfifosz =
4f712e01 2441 musb_read_txfifosz(musb_base);
7421107b 2442 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2443 musb_read_rxfifosz(musb_base);
2444 }
032ec49f
FB		 2445
2446 musb->context.index_regs[i].txtype =
2447 musb_readb(epio, MUSB_TXTYPE);
2448 musb->context.index_regs[i].txinterval =
2449 musb_readb(epio, MUSB_TXINTERVAL);
2450 musb->context.index_regs[i].rxtype =
2451 musb_readb(epio, MUSB_RXTYPE);
2452 musb->context.index_regs[i].rxinterval =
2453 musb_readb(epio, MUSB_RXINTERVAL);
2454
2455 musb->context.index_regs[i].txfunaddr =
6cc2af6d 2456 musb_read_txfunaddr(musb, i);
032ec49f 2457 musb->context.index_regs[i].txhubaddr =
6cc2af6d 2458 musb_read_txhubaddr(musb, i);
032ec49f 2459 musb->context.index_regs[i].txhubport =
6cc2af6d 2460 musb_read_txhubport(musb, i);
032ec49f
FB		 2461
2462 musb->context.index_regs[i].rxfunaddr =
6cc2af6d 2463 musb_read_rxfunaddr(musb, i);
032ec49f 2464 musb->context.index_regs[i].rxhubaddr =
6cc2af6d 2465 musb_read_rxhubaddr(musb, i);
032ec49f 2466 musb->context.index_regs[i].rxhubport =
6cc2af6d 2467 musb_read_rxhubport(musb, i);
4f712e01 2468 }
4f712e01
AKG		 2469}
2470
3c8a5fcc 2471static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2472{
2473 int i;
2474 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2475 void __iomem *epio;
33f8d75f 2476 u8 power;
4f712e01 2477
032ec49f
FB		 2478 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2479 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2480 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
33f8d75f
RQ		 2481
2482 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2483 power = musb_readb(musb_base, MUSB_POWER);
2484 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2485 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2486 power |= musb->context.power;
2487 musb_writeb(musb_base, MUSB_POWER, power);
2488
b18d26f6 2489 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2490 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b 2491 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
84ac5d11
BL		 2492 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2493 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2494
ae9b2ad2 2495 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2496 struct musb_hw_ep *hw_ep;
2497
2498 hw_ep = &musb->endpoints[i];
2499 if (!hw_ep)
2500 continue;
2501
2502 epio = hw_ep->regs;
2503 if (!epio)
2504 continue;
2505
ea737554 2506 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2507 musb_writew(epio, MUSB_TXMAXP,
7421107b 2508 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2509 musb_writew(epio, MUSB_TXCSR,
7421107b 2510 musb->context.index_regs[i].txcsr);
ae9b2ad2 2511 musb_writew(epio, MUSB_RXMAXP,
7421107b 2512 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2513 musb_writew(epio, MUSB_RXCSR,
7421107b 2514 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2515
2516 if (musb->dyn_fifo) {
2517 musb_write_txfifosz(musb_base,
7421107b 2518 musb->context.index_regs[i].txfifosz);
4f712e01 2519 musb_write_rxfifosz(musb_base,
7421107b 2520 musb->context.index_regs[i].rxfifosz);
4f712e01 2521 musb_write_txfifoadd(musb_base,
7421107b 2522 musb->context.index_regs[i].txfifoadd);
4f712e01 2523 musb_write_rxfifoadd(musb_base,
7421107b 2524 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2525 }
2526
032ec49f 2527 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2528 musb->context.index_regs[i].txtype);
032ec49f 2529 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2530 musb->context.index_regs[i].txinterval);
032ec49f 2531 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2532 musb->context.index_regs[i].rxtype);
032ec49f 2533 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2534
032ec49f 2535 musb->context.index_regs[i].rxinterval);
6cc2af6d 2536 musb_write_txfunaddr(musb, i,
7421107b 2537 musb->context.index_regs[i].txfunaddr);
6cc2af6d 2538 musb_write_txhubaddr(musb, i,
7421107b 2539 musb->context.index_regs[i].txhubaddr);
6cc2af6d 2540 musb_write_txhubport(musb, i,
7421107b 2541 musb->context.index_regs[i].txhubport);
4f712e01 2542
6cc2af6d 2543 musb_write_rxfunaddr(musb, i,
7421107b 2544 musb->context.index_regs[i].rxfunaddr);
6cc2af6d 2545 musb_write_rxhubaddr(musb, i,
7421107b 2546 musb->context.index_regs[i].rxhubaddr);
6cc2af6d 2547 musb_write_rxhubport(musb, i,
7421107b 2548 musb->context.index_regs[i].rxhubport);
4f712e01 2549 }
3c5fec75 2550 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2551}
2552
48fea965 2553static int musb_suspend(struct device *dev)
550a7375 2554{
8220796d 2555 struct musb *musb = dev_to_musb(dev);
550a7375 2556 unsigned long flags;
550a7375 2557
6fc6f4b8
PH		 2558 musb_platform_disable(musb);
2559 musb_generic_disable(musb);
2560
550a7375
FB		 2561 spin_lock_irqsave(&musb->lock, flags);
2562
2563 if (is_peripheral_active(musb)) {
2564 /* FIXME force disconnect unless we know USB will wake
2565 * the system up quickly enough to respond ...
2566 */
2567 } else if (is_host_active(musb)) {
2568 /* we know all the children are suspended; sometimes
2569 * they will even be wakeup-enabled.
2570 */
2571 }
2572
c338412b
DM		 2573 musb_save_context(musb);
2574
550a7375
FB		 2575 spin_unlock_irqrestore(&musb->lock, flags);
2576 return 0;
2577}
2578
3e87d9a3 2579static int musb_resume(struct device *dev)
550a7375 2580{
c338412b 2581 struct musb *musb = dev_to_musb(dev);
b87fd2f7
SAS		 2582 u8 devctl;
2583 u8 mask;
c338412b
DM		 2584
2585 /*
2586 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2587 * unless for some reason the whole soc powered down or the USB
2588 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2589 *
2590 * For the DSPS glue layer though, a full register restore has to
2591 * be done. As it shouldn't harm other platforms, we do it
2592 * unconditionally.
550a7375 2593 */
c338412b
DM		 2594
2595 musb_restore_context(musb);
2596
b87fd2f7
SAS		 2597 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2598 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2599 if ((devctl & mask) != (musb->context.devctl & mask))
2600 musb->port1_status = 0;
baadd52f
SAS		 2601 if (musb->need_finish_resume) {
2602 musb->need_finish_resume = 0;
2603 schedule_delayed_work(&musb->finish_resume_work,
309be239 2604 msecs_to_jiffies(USB_RESUME_TIMEOUT));
baadd52f 2605 }
a1fc1920
SAS		 2606
2607 /*
2608 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2609 * out of suspend
2610 */
2611 pm_runtime_disable(dev);
2612 pm_runtime_set_active(dev);
2613 pm_runtime_enable(dev);
6fc6f4b8
PH		 2614
2615 musb_start(musb);
2616
550a7375
FB		 2617 return 0;
2618}
2619
7acc6197
HH		 2620static int musb_runtime_suspend(struct device *dev)
2621{
2622 struct musb *musb = dev_to_musb(dev);
2623
2624 musb_save_context(musb);
2625
2626 return 0;
2627}
2628
2629static int musb_runtime_resume(struct device *dev)
2630{
2631 struct musb *musb = dev_to_musb(dev);
2632 static int first = 1;
2633
2634 /*
2635 * When pm_runtime_get_sync called for the first time in driver
2636 * init, some of the structure is still not initialized which is
2637 * used in restore function. But clock needs to be
2638 * enabled before any register access, so
2639 * pm_runtime_get_sync has to be called.
2640 * Also context restore without save does not make
2641 * any sense
2642 */
2643 if (!first)
2644 musb_restore_context(musb);
2645 first = 0;
2646
9298b4aa
BL		 2647 if (musb->need_finish_resume) {
2648 musb->need_finish_resume = 0;
2649 schedule_delayed_work(&musb->finish_resume_work,
309be239 2650 msecs_to_jiffies(USB_RESUME_TIMEOUT));
9298b4aa
BL		 2651 }
2652
7acc6197
HH		 2653 return 0;
2654}
2655
47145210 2656static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965 2657 .suspend = musb_suspend,
3e87d9a3 2658 .resume = musb_resume,
7acc6197
HH		 2659 .runtime_suspend = musb_runtime_suspend,
2660 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2661};
2662
2663#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2664#else
48fea965 2665#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2666#endif
2667
2668static struct platform_driver musb_driver = {
2669 .driver = {
2670 .name = (char *)musb_driver_name,
2671 .bus = &platform_bus_type,
48fea965 2672 .pm = MUSB_DEV_PM_OPS,
550a7375 2673 },
e9e8c85e 2674 .probe = musb_probe,
7690417d 2675 .remove = musb_remove,
550a7375
FB		 2676};
2677
89f836a8 2678module_platform_driver(musb_driver);
Linux 6.x block layer and io_uring tree(s)