Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver core code | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* | |
36 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
37 | * | |
38 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
39 | * controller driver implementing the "Gadget" API; OTG support is | |
40 | * in the works. These are normal Linux-USB controller drivers which | |
41 | * use IRQs and have no dedicated thread. | |
42 | * | |
43 | * This version of the driver has only been used with products from | |
44 | * Texas Instruments. Those products integrate the Inventra logic | |
45 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
46 | * needs to be reflected in this driver. | |
47 | * | |
48 | * | |
49 | * NOTE: the original Mentor code here was pretty much a collection | |
50 | * of mechanisms that don't seem to have been fully integrated/working | |
51 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
52 | * Key open issues include: | |
53 | * | |
54 | * - Lack of host-side transaction scheduling, for all transfer types. | |
55 | * The hardware doesn't do it; instead, software must. | |
56 | * | |
57 | * This is not an issue for OTG devices that don't support external | |
58 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
59 | * "multipoint" support doesn't scale in the expected ways. That | |
60 | * includes DaVinci EVM in a common non-OTG mode. | |
61 | * | |
62 | * * Control and bulk use dedicated endpoints, and there's as | |
63 | * yet no mechanism to either (a) reclaim the hardware when | |
64 | * peripherals are NAKing, which gets complicated with bulk | |
65 | * endpoints, or (b) use more than a single bulk endpoint in | |
66 | * each direction. | |
67 | * | |
68 | * RESULT: one device may be perceived as blocking another one. | |
69 | * | |
70 | * * Interrupt and isochronous will dynamically allocate endpoint | |
71 | * hardware, but (a) there's no record keeping for bandwidth; | |
72 | * (b) in the common case that few endpoints are available, there | |
73 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
74 | * | |
75 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
76 | * some hardware configurations, no faults will be reported. | |
77 | * At the other extreme, the bandwidth capabilities which do | |
78 | * exist tend to be severely undercommitted. You can't yet hook | |
79 | * up both a keyboard and a mouse to an external USB hub. | |
80 | */ | |
81 | ||
82 | /* | |
83 | * This gets many kinds of configuration information: | |
84 | * - Kconfig for everything user-configurable | |
550a7375 | 85 | * - platform_device for addressing, irq, and platform_data |
5ae477b0 | 86 | * - platform_data is mostly for board-specific information |
c767c1c6 | 87 | * (plus recentrly, SOC or family details) |
550a7375 FB |
88 | * |
89 | * Most of the conditional compilation will (someday) vanish. | |
90 | */ | |
91 | ||
92 | #include <linux/module.h> | |
93 | #include <linux/kernel.h> | |
94 | #include <linux/sched.h> | |
95 | #include <linux/slab.h> | |
550a7375 FB |
96 | #include <linux/list.h> |
97 | #include <linux/kobject.h> | |
9303961f | 98 | #include <linux/prefetch.h> |
550a7375 FB |
99 | #include <linux/platform_device.h> |
100 | #include <linux/io.h> | |
8d2421e6 | 101 | #include <linux/dma-mapping.h> |
550a7375 | 102 | |
550a7375 FB |
103 | #include "musb_core.h" |
104 | ||
f7f9d63e | 105 | #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) |
550a7375 FB |
106 | |
107 | ||
550a7375 FB |
108 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" |
109 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
110 | ||
e8164f64 | 111 | #define MUSB_VERSION "6.0" |
550a7375 FB |
112 | |
113 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
114 | ||
05ac10dd | 115 | #define MUSB_DRIVER_NAME "musb-hdrc" |
550a7375 FB |
116 | const char musb_driver_name[] = MUSB_DRIVER_NAME; |
117 | ||
118 | MODULE_DESCRIPTION(DRIVER_INFO); | |
119 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
120 | MODULE_LICENSE("GPL"); | |
121 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
122 | ||
123 | ||
124 | /*-------------------------------------------------------------------------*/ | |
125 | ||
126 | static inline struct musb *dev_to_musb(struct device *dev) | |
127 | { | |
550a7375 | 128 | return dev_get_drvdata(dev); |
550a7375 FB |
129 | } |
130 | ||
131 | /*-------------------------------------------------------------------------*/ | |
132 | ||
ffb865b1 | 133 | #ifndef CONFIG_BLACKFIN |
b96d3b08 | 134 | static int musb_ulpi_read(struct usb_phy *phy, u32 offset) |
ffb865b1 | 135 | { |
b96d3b08 | 136 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
137 | int i = 0; |
138 | u8 r; | |
139 | u8 power; | |
bf070bc1 GI |
140 | int ret; |
141 | ||
142 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
143 | |
144 | /* Make sure the transceiver is not in low power mode */ | |
145 | power = musb_readb(addr, MUSB_POWER); | |
146 | power &= ~MUSB_POWER_SUSPENDM; | |
147 | musb_writeb(addr, MUSB_POWER, power); | |
148 | ||
149 | /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the | |
150 | * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. | |
151 | */ | |
152 | ||
153 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
154 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, | |
155 | MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); | |
156 | ||
157 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
158 | & MUSB_ULPI_REG_CMPLT)) { | |
159 | i++; | |
bf070bc1 GI |
160 | if (i == 10000) { |
161 | ret = -ETIMEDOUT; | |
162 | goto out; | |
163 | } | |
ffb865b1 HK |
164 | |
165 | } | |
166 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
167 | r &= ~MUSB_ULPI_REG_CMPLT; | |
168 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
169 | ||
bf070bc1 GI |
170 | ret = musb_readb(addr, MUSB_ULPI_REG_DATA); |
171 | ||
172 | out: | |
173 | pm_runtime_put(phy->io_dev); | |
174 | ||
175 | return ret; | |
ffb865b1 HK |
176 | } |
177 | ||
b96d3b08 | 178 | static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) |
ffb865b1 | 179 | { |
b96d3b08 | 180 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
181 | int i = 0; |
182 | u8 r = 0; | |
183 | u8 power; | |
bf070bc1 GI |
184 | int ret = 0; |
185 | ||
186 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
187 | |
188 | /* Make sure the transceiver is not in low power mode */ | |
189 | power = musb_readb(addr, MUSB_POWER); | |
190 | power &= ~MUSB_POWER_SUSPENDM; | |
191 | musb_writeb(addr, MUSB_POWER, power); | |
192 | ||
193 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
194 | musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); | |
195 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); | |
196 | ||
197 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
198 | & MUSB_ULPI_REG_CMPLT)) { | |
199 | i++; | |
bf070bc1 GI |
200 | if (i == 10000) { |
201 | ret = -ETIMEDOUT; | |
202 | goto out; | |
203 | } | |
ffb865b1 HK |
204 | } |
205 | ||
206 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
207 | r &= ~MUSB_ULPI_REG_CMPLT; | |
208 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
209 | ||
bf070bc1 GI |
210 | out: |
211 | pm_runtime_put(phy->io_dev); | |
212 | ||
213 | return ret; | |
ffb865b1 HK |
214 | } |
215 | #else | |
f2263db7 MF |
216 | #define musb_ulpi_read NULL |
217 | #define musb_ulpi_write NULL | |
ffb865b1 HK |
218 | #endif |
219 | ||
b96d3b08 | 220 | static struct usb_phy_io_ops musb_ulpi_access = { |
ffb865b1 HK |
221 | .read = musb_ulpi_read, |
222 | .write = musb_ulpi_write, | |
223 | }; | |
224 | ||
225 | /*-------------------------------------------------------------------------*/ | |
226 | ||
7c925546 | 227 | #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) |
c6cf8b00 | 228 | |
550a7375 FB |
229 | /* |
230 | * Load an endpoint's FIFO | |
231 | */ | |
232 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
233 | { | |
5c8a86e1 | 234 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
235 | void __iomem *fifo = hw_ep->fifo; |
236 | ||
603fe2b2 AKG |
237 | if (unlikely(len == 0)) |
238 | return; | |
239 | ||
550a7375 FB |
240 | prefetch((u8 *)src); |
241 | ||
5c8a86e1 | 242 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
243 | 'T', hw_ep->epnum, fifo, len, src); |
244 | ||
245 | /* we can't assume unaligned reads work */ | |
246 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
247 | u16 index = 0; | |
248 | ||
249 | /* best case is 32bit-aligned source address */ | |
250 | if ((0x02 & (unsigned long) src) == 0) { | |
251 | if (len >= 4) { | |
2bf0a8f6 | 252 | iowrite32_rep(fifo, src + index, len >> 2); |
550a7375 FB |
253 | index += len & ~0x03; |
254 | } | |
255 | if (len & 0x02) { | |
256 | musb_writew(fifo, 0, *(u16 *)&src[index]); | |
257 | index += 2; | |
258 | } | |
259 | } else { | |
260 | if (len >= 2) { | |
2bf0a8f6 | 261 | iowrite16_rep(fifo, src + index, len >> 1); |
550a7375 FB |
262 | index += len & ~0x01; |
263 | } | |
264 | } | |
265 | if (len & 0x01) | |
266 | musb_writeb(fifo, 0, src[index]); | |
267 | } else { | |
268 | /* byte aligned */ | |
2bf0a8f6 | 269 | iowrite8_rep(fifo, src, len); |
550a7375 FB |
270 | } |
271 | } | |
272 | ||
843bb1d0 | 273 | #if !defined(CONFIG_USB_MUSB_AM35X) |
550a7375 FB |
274 | /* |
275 | * Unload an endpoint's FIFO | |
276 | */ | |
277 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
278 | { | |
5c8a86e1 | 279 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
280 | void __iomem *fifo = hw_ep->fifo; |
281 | ||
603fe2b2 AKG |
282 | if (unlikely(len == 0)) |
283 | return; | |
284 | ||
5c8a86e1 | 285 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
286 | 'R', hw_ep->epnum, fifo, len, dst); |
287 | ||
288 | /* we can't assume unaligned writes work */ | |
289 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
290 | u16 index = 0; | |
291 | ||
292 | /* best case is 32bit-aligned destination address */ | |
293 | if ((0x02 & (unsigned long) dst) == 0) { | |
294 | if (len >= 4) { | |
2bf0a8f6 | 295 | ioread32_rep(fifo, dst, len >> 2); |
550a7375 FB |
296 | index = len & ~0x03; |
297 | } | |
298 | if (len & 0x02) { | |
299 | *(u16 *)&dst[index] = musb_readw(fifo, 0); | |
300 | index += 2; | |
301 | } | |
302 | } else { | |
303 | if (len >= 2) { | |
2bf0a8f6 | 304 | ioread16_rep(fifo, dst, len >> 1); |
550a7375 FB |
305 | index = len & ~0x01; |
306 | } | |
307 | } | |
308 | if (len & 0x01) | |
309 | dst[index] = musb_readb(fifo, 0); | |
310 | } else { | |
311 | /* byte aligned */ | |
2bf0a8f6 | 312 | ioread8_rep(fifo, dst, len); |
550a7375 FB |
313 | } |
314 | } | |
843bb1d0 | 315 | #endif |
550a7375 FB |
316 | |
317 | #endif /* normal PIO */ | |
318 | ||
319 | ||
320 | /*-------------------------------------------------------------------------*/ | |
321 | ||
322 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
323 | static const u8 musb_test_packet[53] = { | |
324 | /* implicit SYNC then DATA0 to start */ | |
325 | ||
326 | /* JKJKJKJK x9 */ | |
327 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
328 | /* JJKKJJKK x8 */ | |
329 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
330 | /* JJJJKKKK x8 */ | |
331 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
332 | /* JJJJJJJKKKKKKK x8 */ | |
333 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
334 | /* JJJJJJJK x8 */ | |
335 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
336 | /* JKKKKKKK x10, JK */ | |
337 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
338 | ||
339 | /* implicit CRC16 then EOP to end */ | |
340 | }; | |
341 | ||
342 | void musb_load_testpacket(struct musb *musb) | |
343 | { | |
344 | void __iomem *regs = musb->endpoints[0].regs; | |
345 | ||
346 | musb_ep_select(musb->mregs, 0); | |
347 | musb_write_fifo(musb->control_ep, | |
348 | sizeof(musb_test_packet), musb_test_packet); | |
349 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
350 | } | |
351 | ||
352 | /*-------------------------------------------------------------------------*/ | |
353 | ||
550a7375 FB |
354 | /* |
355 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
356 | */ | |
a156544b | 357 | static void musb_otg_timer_func(unsigned long data) |
550a7375 FB |
358 | { |
359 | struct musb *musb = (struct musb *)data; | |
360 | unsigned long flags; | |
361 | ||
362 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 363 | switch (musb->xceiv->state) { |
550a7375 | 364 | case OTG_STATE_B_WAIT_ACON: |
5c8a86e1 | 365 | dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); |
550a7375 | 366 | musb_g_disconnect(musb); |
84e250ff | 367 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
368 | musb->is_active = 0; |
369 | break; | |
ab983f2a | 370 | case OTG_STATE_A_SUSPEND: |
550a7375 | 371 | case OTG_STATE_A_WAIT_BCON: |
5c8a86e1 | 372 | dev_dbg(musb->controller, "HNP: %s timeout\n", |
42c0bf1c | 373 | usb_otg_state_string(musb->xceiv->state)); |
743411b3 | 374 | musb_platform_set_vbus(musb, 0); |
ab983f2a | 375 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
376 | break; |
377 | default: | |
5c8a86e1 | 378 | dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", |
42c0bf1c | 379 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 | 380 | } |
550a7375 FB |
381 | spin_unlock_irqrestore(&musb->lock, flags); |
382 | } | |
383 | ||
550a7375 | 384 | /* |
f7f9d63e | 385 | * Stops the HNP transition. Caller must take care of locking. |
550a7375 FB |
386 | */ |
387 | void musb_hnp_stop(struct musb *musb) | |
388 | { | |
8b125df5 | 389 | struct usb_hcd *hcd = musb->hcd; |
550a7375 FB |
390 | void __iomem *mbase = musb->mregs; |
391 | u8 reg; | |
392 | ||
42c0bf1c FB |
393 | dev_dbg(musb->controller, "HNP: stop from %s\n", |
394 | usb_otg_state_string(musb->xceiv->state)); | |
ab983f2a | 395 | |
84e250ff | 396 | switch (musb->xceiv->state) { |
550a7375 | 397 | case OTG_STATE_A_PERIPHERAL: |
550a7375 | 398 | musb_g_disconnect(musb); |
5c8a86e1 | 399 | dev_dbg(musb->controller, "HNP: back to %s\n", |
42c0bf1c | 400 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
401 | break; |
402 | case OTG_STATE_B_HOST: | |
5c8a86e1 | 403 | dev_dbg(musb->controller, "HNP: Disabling HR\n"); |
74c2e936 DM |
404 | if (hcd) |
405 | hcd->self.is_b_host = 0; | |
84e250ff | 406 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
407 | MUSB_DEV_MODE(musb); |
408 | reg = musb_readb(mbase, MUSB_POWER); | |
409 | reg |= MUSB_POWER_SUSPENDM; | |
410 | musb_writeb(mbase, MUSB_POWER, reg); | |
411 | /* REVISIT: Start SESSION_REQUEST here? */ | |
412 | break; | |
413 | default: | |
5c8a86e1 | 414 | dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", |
42c0bf1c | 415 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
416 | } |
417 | ||
418 | /* | |
419 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
420 | * which cause occasional OPT A "Did not receive reset after connect" | |
421 | * errors. | |
422 | */ | |
749da5f8 | 423 | musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); |
550a7375 FB |
424 | } |
425 | ||
550a7375 FB |
426 | /* |
427 | * Interrupt Service Routine to record USB "global" interrupts. | |
428 | * Since these do not happen often and signify things of | |
429 | * paramount importance, it seems OK to check them individually; | |
430 | * the order of the tests is specified in the manual | |
431 | * | |
432 | * @param musb instance pointer | |
433 | * @param int_usb register contents | |
434 | * @param devctl | |
435 | * @param power | |
436 | */ | |
437 | ||
550a7375 | 438 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, |
b11e94d0 | 439 | u8 devctl) |
550a7375 | 440 | { |
d445b6da | 441 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 | 442 | irqreturn_t handled = IRQ_NONE; |
550a7375 | 443 | |
b11e94d0 | 444 | dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl, |
550a7375 FB |
445 | int_usb); |
446 | ||
447 | /* in host mode, the peripheral may issue remote wakeup. | |
448 | * in peripheral mode, the host may resume the link. | |
449 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
450 | */ | |
451 | if (int_usb & MUSB_INTR_RESUME) { | |
452 | handled = IRQ_HANDLED; | |
42c0bf1c | 453 | dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
454 | |
455 | if (devctl & MUSB_DEVCTL_HM) { | |
aa471456 | 456 | void __iomem *mbase = musb->mregs; |
b11e94d0 | 457 | u8 power; |
aa471456 | 458 | |
84e250ff | 459 | switch (musb->xceiv->state) { |
550a7375 FB |
460 | case OTG_STATE_A_SUSPEND: |
461 | /* remote wakeup? later, GetPortStatus | |
462 | * will stop RESUME signaling | |
463 | */ | |
464 | ||
b11e94d0 | 465 | power = musb_readb(musb->mregs, MUSB_POWER); |
550a7375 FB |
466 | if (power & MUSB_POWER_SUSPENDM) { |
467 | /* spurious */ | |
468 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
5c8a86e1 | 469 | dev_dbg(musb->controller, "Spurious SUSPENDM\n"); |
550a7375 FB |
470 | break; |
471 | } | |
472 | ||
473 | power &= ~MUSB_POWER_SUSPENDM; | |
474 | musb_writeb(mbase, MUSB_POWER, | |
475 | power | MUSB_POWER_RESUME); | |
476 | ||
477 | musb->port1_status |= | |
478 | (USB_PORT_STAT_C_SUSPEND << 16) | |
479 | | MUSB_PORT_STAT_RESUME; | |
30d361bf DM |
480 | musb->rh_timer = jiffies |
481 | + msecs_to_jiffies(20); | |
8ed1fb79 | 482 | schedule_delayed_work( |
9ccfaf74 DM |
483 | &musb->finish_resume_work, |
484 | msecs_to_jiffies(20)); | |
550a7375 | 485 | |
84e250ff | 486 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 | 487 | musb->is_active = 1; |
0b3eba44 | 488 | musb_host_resume_root_hub(musb); |
550a7375 FB |
489 | break; |
490 | case OTG_STATE_B_WAIT_ACON: | |
84e250ff | 491 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
492 | musb->is_active = 1; |
493 | MUSB_DEV_MODE(musb); | |
494 | break; | |
495 | default: | |
496 | WARNING("bogus %s RESUME (%s)\n", | |
497 | "host", | |
42c0bf1c | 498 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 | 499 | } |
550a7375 | 500 | } else { |
84e250ff | 501 | switch (musb->xceiv->state) { |
550a7375 FB |
502 | case OTG_STATE_A_SUSPEND: |
503 | /* possibly DISCONNECT is upcoming */ | |
84e250ff | 504 | musb->xceiv->state = OTG_STATE_A_HOST; |
0b3eba44 | 505 | musb_host_resume_root_hub(musb); |
550a7375 | 506 | break; |
550a7375 FB |
507 | case OTG_STATE_B_WAIT_ACON: |
508 | case OTG_STATE_B_PERIPHERAL: | |
509 | /* disconnect while suspended? we may | |
510 | * not get a disconnect irq... | |
511 | */ | |
512 | if ((devctl & MUSB_DEVCTL_VBUS) | |
513 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
514 | ) { | |
515 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
516 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
517 | break; | |
518 | } | |
519 | musb_g_resume(musb); | |
520 | break; | |
521 | case OTG_STATE_B_IDLE: | |
522 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
523 | break; | |
550a7375 FB |
524 | default: |
525 | WARNING("bogus %s RESUME (%s)\n", | |
526 | "peripheral", | |
42c0bf1c | 527 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
528 | } |
529 | } | |
530 | } | |
531 | ||
550a7375 FB |
532 | /* see manual for the order of the tests */ |
533 | if (int_usb & MUSB_INTR_SESSREQ) { | |
aa471456 FB |
534 | void __iomem *mbase = musb->mregs; |
535 | ||
19aab56c HK |
536 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS |
537 | && (devctl & MUSB_DEVCTL_BDEVICE)) { | |
5c8a86e1 | 538 | dev_dbg(musb->controller, "SessReq while on B state\n"); |
a6038ee7 HK |
539 | return IRQ_HANDLED; |
540 | } | |
541 | ||
5c8a86e1 | 542 | dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", |
42c0bf1c | 543 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
544 | |
545 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
546 | * is removed) SRP. responses are time critical: | |
547 | * - turn on VBUS (with silicon-specific mechanism) | |
548 | * - go through A_WAIT_VRISE | |
549 | * - ... to A_WAIT_BCON. | |
550 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
551 | */ | |
552 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
553 | musb->ep0_stage = MUSB_EP0_START; | |
84e250ff | 554 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 | 555 | MUSB_HST_MODE(musb); |
743411b3 | 556 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
557 | |
558 | handled = IRQ_HANDLED; | |
559 | } | |
560 | ||
561 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
562 | int ignore = 0; | |
563 | ||
564 | /* During connection as an A-Device, we may see a short | |
565 | * current spikes causing voltage drop, because of cable | |
566 | * and peripheral capacitance combined with vbus draw. | |
567 | * (So: less common with truly self-powered devices, where | |
568 | * vbus doesn't act like a power supply.) | |
569 | * | |
570 | * Such spikes are short; usually less than ~500 usec, max | |
571 | * of ~2 msec. That is, they're not sustained overcurrent | |
572 | * errors, though they're reported using VBUSERROR irqs. | |
573 | * | |
574 | * Workarounds: (a) hardware: use self powered devices. | |
575 | * (b) software: ignore non-repeated VBUS errors. | |
576 | * | |
577 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
578 | * make trouble here, keeping VBUS < 4.4V ? | |
579 | */ | |
84e250ff | 580 | switch (musb->xceiv->state) { |
550a7375 FB |
581 | case OTG_STATE_A_HOST: |
582 | /* recovery is dicey once we've gotten past the | |
583 | * initial stages of enumeration, but if VBUS | |
584 | * stayed ok at the other end of the link, and | |
585 | * another reset is due (at least for high speed, | |
586 | * to redo the chirp etc), it might work OK... | |
587 | */ | |
588 | case OTG_STATE_A_WAIT_BCON: | |
589 | case OTG_STATE_A_WAIT_VRISE: | |
590 | if (musb->vbuserr_retry) { | |
aa471456 FB |
591 | void __iomem *mbase = musb->mregs; |
592 | ||
550a7375 FB |
593 | musb->vbuserr_retry--; |
594 | ignore = 1; | |
595 | devctl |= MUSB_DEVCTL_SESSION; | |
596 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
597 | } else { | |
598 | musb->port1_status |= | |
749da5f8 AS |
599 | USB_PORT_STAT_OVERCURRENT |
600 | | (USB_PORT_STAT_C_OVERCURRENT << 16); | |
550a7375 FB |
601 | } |
602 | break; | |
603 | default: | |
604 | break; | |
605 | } | |
606 | ||
54485116 GI |
607 | dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, |
608 | "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", | |
42c0bf1c | 609 | usb_otg_state_string(musb->xceiv->state), |
550a7375 FB |
610 | devctl, |
611 | ({ char *s; | |
612 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
613 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
614 | s = "<SessEnd"; break; | |
615 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
616 | s = "<AValid"; break; | |
617 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
618 | s = "<VBusValid"; break; | |
619 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
620 | default: | |
621 | s = "VALID"; break; | |
2b84f92b | 622 | } s; }), |
550a7375 FB |
623 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, |
624 | musb->port1_status); | |
625 | ||
626 | /* go through A_WAIT_VFALL then start a new session */ | |
627 | if (!ignore) | |
743411b3 | 628 | musb_platform_set_vbus(musb, 0); |
550a7375 FB |
629 | handled = IRQ_HANDLED; |
630 | } | |
631 | ||
1c25fda4 | 632 | if (int_usb & MUSB_INTR_SUSPEND) { |
b11e94d0 | 633 | dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n", |
42c0bf1c | 634 | usb_otg_state_string(musb->xceiv->state), devctl); |
1c25fda4 AM |
635 | handled = IRQ_HANDLED; |
636 | ||
637 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
638 | case OTG_STATE_A_PERIPHERAL: |
639 | /* We also come here if the cable is removed, since | |
640 | * this silicon doesn't report ID-no-longer-grounded. | |
641 | * | |
642 | * We depend on T(a_wait_bcon) to shut us down, and | |
643 | * hope users don't do anything dicey during this | |
644 | * undesired detour through A_WAIT_BCON. | |
645 | */ | |
646 | musb_hnp_stop(musb); | |
0b3eba44 | 647 | musb_host_resume_root_hub(musb); |
1c25fda4 AM |
648 | musb_root_disconnect(musb); |
649 | musb_platform_try_idle(musb, jiffies | |
650 | + msecs_to_jiffies(musb->a_wait_bcon | |
651 | ? : OTG_TIME_A_WAIT_BCON)); | |
652 | ||
653 | break; | |
1c25fda4 AM |
654 | case OTG_STATE_B_IDLE: |
655 | if (!musb->is_active) | |
656 | break; | |
657 | case OTG_STATE_B_PERIPHERAL: | |
658 | musb_g_suspend(musb); | |
032ec49f | 659 | musb->is_active = otg->gadget->b_hnp_enable; |
1c25fda4 | 660 | if (musb->is_active) { |
1c25fda4 | 661 | musb->xceiv->state = OTG_STATE_B_WAIT_ACON; |
5c8a86e1 | 662 | dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); |
1c25fda4 AM |
663 | mod_timer(&musb->otg_timer, jiffies |
664 | + msecs_to_jiffies( | |
665 | OTG_TIME_B_ASE0_BRST)); | |
1c25fda4 AM |
666 | } |
667 | break; | |
668 | case OTG_STATE_A_WAIT_BCON: | |
669 | if (musb->a_wait_bcon != 0) | |
670 | musb_platform_try_idle(musb, jiffies | |
671 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
672 | break; | |
673 | case OTG_STATE_A_HOST: | |
674 | musb->xceiv->state = OTG_STATE_A_SUSPEND; | |
032ec49f | 675 | musb->is_active = otg->host->b_hnp_enable; |
1c25fda4 AM |
676 | break; |
677 | case OTG_STATE_B_HOST: | |
678 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
5c8a86e1 | 679 | dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); |
1c25fda4 AM |
680 | break; |
681 | default: | |
682 | /* "should not happen" */ | |
683 | musb->is_active = 0; | |
684 | break; | |
685 | } | |
686 | } | |
687 | ||
550a7375 | 688 | if (int_usb & MUSB_INTR_CONNECT) { |
8b125df5 | 689 | struct usb_hcd *hcd = musb->hcd; |
550a7375 FB |
690 | |
691 | handled = IRQ_HANDLED; | |
692 | musb->is_active = 1; | |
550a7375 FB |
693 | |
694 | musb->ep0_stage = MUSB_EP0_START; | |
695 | ||
550a7375 FB |
696 | /* flush endpoints when transitioning from Device Mode */ |
697 | if (is_peripheral_active(musb)) { | |
698 | /* REVISIT HNP; just force disconnect */ | |
699 | } | |
b18d26f6 SAS |
700 | musb->intrtxe = musb->epmask; |
701 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); | |
af5ec14d SAS |
702 | musb->intrrxe = musb->epmask & 0xfffe; |
703 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); | |
d709d22e | 704 | musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); |
550a7375 FB |
705 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |
706 | |USB_PORT_STAT_HIGH_SPEED | |
707 | |USB_PORT_STAT_ENABLE | |
708 | ); | |
709 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
710 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
711 | ||
712 | /* high vs full speed is just a guess until after reset */ | |
713 | if (devctl & MUSB_DEVCTL_LSDEV) | |
714 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
715 | ||
550a7375 | 716 | /* indicate new connection to OTG machine */ |
84e250ff | 717 | switch (musb->xceiv->state) { |
550a7375 FB |
718 | case OTG_STATE_B_PERIPHERAL: |
719 | if (int_usb & MUSB_INTR_SUSPEND) { | |
5c8a86e1 | 720 | dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); |
550a7375 | 721 | int_usb &= ~MUSB_INTR_SUSPEND; |
1de00dae | 722 | goto b_host; |
550a7375 | 723 | } else |
5c8a86e1 | 724 | dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); |
550a7375 FB |
725 | break; |
726 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 727 | dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); |
1de00dae | 728 | b_host: |
84e250ff | 729 | musb->xceiv->state = OTG_STATE_B_HOST; |
74c2e936 DM |
730 | if (musb->hcd) |
731 | musb->hcd->self.is_b_host = 1; | |
1de00dae | 732 | del_timer(&musb->otg_timer); |
550a7375 FB |
733 | break; |
734 | default: | |
735 | if ((devctl & MUSB_DEVCTL_VBUS) | |
736 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
84e250ff | 737 | musb->xceiv->state = OTG_STATE_A_HOST; |
0b3eba44 DM |
738 | if (hcd) |
739 | hcd->self.is_b_host = 0; | |
550a7375 FB |
740 | } |
741 | break; | |
742 | } | |
1de00dae | 743 | |
0b3eba44 | 744 | musb_host_poke_root_hub(musb); |
1de00dae | 745 | |
5c8a86e1 | 746 | dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", |
42c0bf1c | 747 | usb_otg_state_string(musb->xceiv->state), devctl); |
550a7375 | 748 | } |
550a7375 | 749 | |
6d349671 | 750 | if (int_usb & MUSB_INTR_DISCONNECT) { |
5c8a86e1 | 751 | dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", |
42c0bf1c | 752 | usb_otg_state_string(musb->xceiv->state), |
1c25fda4 AM |
753 | MUSB_MODE(musb), devctl); |
754 | handled = IRQ_HANDLED; | |
755 | ||
756 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
757 | case OTG_STATE_A_HOST: |
758 | case OTG_STATE_A_SUSPEND: | |
0b3eba44 | 759 | musb_host_resume_root_hub(musb); |
1c25fda4 | 760 | musb_root_disconnect(musb); |
032ec49f | 761 | if (musb->a_wait_bcon != 0) |
1c25fda4 AM |
762 | musb_platform_try_idle(musb, jiffies |
763 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
764 | break; | |
1c25fda4 AM |
765 | case OTG_STATE_B_HOST: |
766 | /* REVISIT this behaves for "real disconnect" | |
767 | * cases; make sure the other transitions from | |
768 | * from B_HOST act right too. The B_HOST code | |
769 | * in hnp_stop() is currently not used... | |
770 | */ | |
771 | musb_root_disconnect(musb); | |
74c2e936 DM |
772 | if (musb->hcd) |
773 | musb->hcd->self.is_b_host = 0; | |
1c25fda4 AM |
774 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
775 | MUSB_DEV_MODE(musb); | |
776 | musb_g_disconnect(musb); | |
777 | break; | |
778 | case OTG_STATE_A_PERIPHERAL: | |
779 | musb_hnp_stop(musb); | |
780 | musb_root_disconnect(musb); | |
781 | /* FALLTHROUGH */ | |
782 | case OTG_STATE_B_WAIT_ACON: | |
783 | /* FALLTHROUGH */ | |
1c25fda4 AM |
784 | case OTG_STATE_B_PERIPHERAL: |
785 | case OTG_STATE_B_IDLE: | |
786 | musb_g_disconnect(musb); | |
787 | break; | |
1c25fda4 AM |
788 | default: |
789 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
42c0bf1c | 790 | usb_otg_state_string(musb->xceiv->state)); |
1c25fda4 AM |
791 | break; |
792 | } | |
793 | } | |
794 | ||
550a7375 FB |
795 | /* mentor saves a bit: bus reset and babble share the same irq. |
796 | * only host sees babble; only peripheral sees bus reset. | |
797 | */ | |
798 | if (int_usb & MUSB_INTR_RESET) { | |
1c25fda4 | 799 | handled = IRQ_HANDLED; |
a04d46d0 | 800 | if ((devctl & MUSB_DEVCTL_HM) != 0) { |
550a7375 FB |
801 | /* |
802 | * Looks like non-HS BABBLE can be ignored, but | |
803 | * HS BABBLE is an error condition. For HS the solution | |
804 | * is to avoid babble in the first place and fix what | |
805 | * caused BABBLE. When HS BABBLE happens we can only | |
806 | * stop the session. | |
807 | */ | |
808 | if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) | |
5c8a86e1 | 809 | dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); |
550a7375 FB |
810 | else { |
811 | ERR("Stopping host session -- babble\n"); | |
1c25fda4 | 812 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
550a7375 | 813 | } |
a04d46d0 | 814 | } else { |
5c8a86e1 | 815 | dev_dbg(musb->controller, "BUS RESET as %s\n", |
42c0bf1c | 816 | usb_otg_state_string(musb->xceiv->state)); |
84e250ff | 817 | switch (musb->xceiv->state) { |
550a7375 | 818 | case OTG_STATE_A_SUSPEND: |
550a7375 FB |
819 | musb_g_reset(musb); |
820 | /* FALLTHROUGH */ | |
821 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
f7f9d63e | 822 | /* never use invalid T(a_wait_bcon) */ |
5c8a86e1 | 823 | dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", |
42c0bf1c | 824 | usb_otg_state_string(musb->xceiv->state), |
3df00453 | 825 | TA_WAIT_BCON(musb)); |
f7f9d63e DB |
826 | mod_timer(&musb->otg_timer, jiffies |
827 | + msecs_to_jiffies(TA_WAIT_BCON(musb))); | |
550a7375 FB |
828 | break; |
829 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae DB |
830 | del_timer(&musb->otg_timer); |
831 | musb_g_reset(musb); | |
550a7375 FB |
832 | break; |
833 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 834 | dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", |
42c0bf1c | 835 | usb_otg_state_string(musb->xceiv->state)); |
84e250ff | 836 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
837 | musb_g_reset(musb); |
838 | break; | |
550a7375 | 839 | case OTG_STATE_B_IDLE: |
84e250ff | 840 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
841 | /* FALLTHROUGH */ |
842 | case OTG_STATE_B_PERIPHERAL: | |
843 | musb_g_reset(musb); | |
844 | break; | |
845 | default: | |
5c8a86e1 | 846 | dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", |
42c0bf1c | 847 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
848 | } |
849 | } | |
550a7375 | 850 | } |
550a7375 FB |
851 | |
852 | #if 0 | |
853 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
854 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
855 | * limits of a given frame or microframe. | |
856 | * | |
857 | * It's not needed for peripheral side, which dedicates endpoints; | |
858 | * though it _might_ use SOF irqs for other purposes. | |
859 | * | |
860 | * And it's not currently needed for host side, which also dedicates | |
861 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
862 | * to support ISO transfers yet. | |
863 | */ | |
864 | if (int_usb & MUSB_INTR_SOF) { | |
865 | void __iomem *mbase = musb->mregs; | |
866 | struct musb_hw_ep *ep; | |
867 | u8 epnum; | |
868 | u16 frame; | |
869 | ||
5c8a86e1 | 870 | dev_dbg(musb->controller, "START_OF_FRAME\n"); |
550a7375 FB |
871 | handled = IRQ_HANDLED; |
872 | ||
873 | /* start any periodic Tx transfers waiting for current frame */ | |
874 | frame = musb_readw(mbase, MUSB_FRAME); | |
875 | ep = musb->endpoints; | |
876 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
877 | && (musb->epmask >= (1 << epnum)); | |
878 | epnum++, ep++) { | |
879 | /* | |
880 | * FIXME handle framecounter wraps (12 bits) | |
881 | * eliminate duplicated StartUrb logic | |
882 | */ | |
883 | if (ep->dwWaitFrame >= frame) { | |
884 | ep->dwWaitFrame = 0; | |
885 | pr_debug("SOF --> periodic TX%s on %d\n", | |
886 | ep->tx_channel ? " DMA" : "", | |
887 | epnum); | |
888 | if (!ep->tx_channel) | |
889 | musb_h_tx_start(musb, epnum); | |
890 | else | |
891 | cppi_hostdma_start(musb, epnum); | |
892 | } | |
893 | } /* end of for loop */ | |
894 | } | |
895 | #endif | |
896 | ||
1c25fda4 | 897 | schedule_work(&musb->irq_work); |
550a7375 FB |
898 | |
899 | return handled; | |
900 | } | |
901 | ||
902 | /*-------------------------------------------------------------------------*/ | |
903 | ||
550a7375 FB |
904 | static void musb_generic_disable(struct musb *musb) |
905 | { | |
906 | void __iomem *mbase = musb->mregs; | |
907 | u16 temp; | |
908 | ||
909 | /* disable interrupts */ | |
910 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
b18d26f6 | 911 | musb->intrtxe = 0; |
550a7375 | 912 | musb_writew(mbase, MUSB_INTRTXE, 0); |
af5ec14d | 913 | musb->intrrxe = 0; |
550a7375 FB |
914 | musb_writew(mbase, MUSB_INTRRXE, 0); |
915 | ||
916 | /* off */ | |
917 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
918 | ||
919 | /* flush pending interrupts */ | |
920 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
921 | temp = musb_readw(mbase, MUSB_INTRTX); | |
922 | temp = musb_readw(mbase, MUSB_INTRRX); | |
923 | ||
924 | } | |
925 | ||
001dd84a SAS |
926 | /* |
927 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
928 | */ | |
929 | void musb_start(struct musb *musb) | |
930 | { | |
931 | void __iomem *regs = musb->mregs; | |
932 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
933 | ||
934 | dev_dbg(musb->controller, "<== devctl %02x\n", devctl); | |
935 | ||
936 | /* Set INT enable registers, enable interrupts */ | |
937 | musb->intrtxe = musb->epmask; | |
938 | musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); | |
939 | musb->intrrxe = musb->epmask & 0xfffe; | |
940 | musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); | |
941 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); | |
942 | ||
943 | musb_writeb(regs, MUSB_TESTMODE, 0); | |
944 | ||
945 | /* put into basic highspeed mode and start session */ | |
946 | musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE | |
947 | | MUSB_POWER_HSENAB | |
948 | /* ENSUSPEND wedges tusb */ | |
949 | /* | MUSB_POWER_ENSUSPEND */ | |
950 | ); | |
951 | ||
952 | musb->is_active = 0; | |
953 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
954 | devctl &= ~MUSB_DEVCTL_SESSION; | |
955 | ||
956 | /* session started after: | |
957 | * (a) ID-grounded irq, host mode; | |
958 | * (b) vbus present/connect IRQ, peripheral mode; | |
959 | * (c) peripheral initiates, using SRP | |
960 | */ | |
961 | if (musb->port_mode != MUSB_PORT_MODE_HOST && | |
962 | (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) { | |
963 | musb->is_active = 1; | |
964 | } else { | |
965 | devctl |= MUSB_DEVCTL_SESSION; | |
966 | } | |
967 | ||
968 | musb_platform_enable(musb); | |
969 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
970 | } | |
971 | ||
550a7375 FB |
972 | /* |
973 | * Make the HDRC stop (disable interrupts, etc.); | |
974 | * reversible by musb_start | |
975 | * called on gadget driver unregister | |
976 | * with controller locked, irqs blocked | |
977 | * acts as a NOP unless some role activated the hardware | |
978 | */ | |
979 | void musb_stop(struct musb *musb) | |
980 | { | |
981 | /* stop IRQs, timers, ... */ | |
982 | musb_platform_disable(musb); | |
983 | musb_generic_disable(musb); | |
5c8a86e1 | 984 | dev_dbg(musb->controller, "HDRC disabled\n"); |
550a7375 FB |
985 | |
986 | /* FIXME | |
987 | * - mark host and/or peripheral drivers unusable/inactive | |
988 | * - disable DMA (and enable it in HdrcStart) | |
989 | * - make sure we can musb_start() after musb_stop(); with | |
990 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
991 | * - ... | |
992 | */ | |
993 | musb_platform_try_idle(musb, 0); | |
994 | } | |
995 | ||
996 | static void musb_shutdown(struct platform_device *pdev) | |
997 | { | |
998 | struct musb *musb = dev_to_musb(&pdev->dev); | |
999 | unsigned long flags; | |
1000 | ||
4f9edd2d | 1001 | pm_runtime_get_sync(musb->controller); |
24307cae | 1002 | |
2cc65fea | 1003 | musb_host_cleanup(musb); |
24307cae GI |
1004 | musb_gadget_cleanup(musb); |
1005 | ||
550a7375 FB |
1006 | spin_lock_irqsave(&musb->lock, flags); |
1007 | musb_platform_disable(musb); | |
1008 | musb_generic_disable(musb); | |
550a7375 FB |
1009 | spin_unlock_irqrestore(&musb->lock, flags); |
1010 | ||
120d074c GI |
1011 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
1012 | musb_platform_exit(musb); | |
120d074c | 1013 | |
4f9edd2d | 1014 | pm_runtime_put(musb->controller); |
550a7375 FB |
1015 | /* FIXME power down */ |
1016 | } | |
1017 | ||
1018 | ||
1019 | /*-------------------------------------------------------------------------*/ | |
1020 | ||
1021 | /* | |
1022 | * The silicon either has hard-wired endpoint configurations, or else | |
1023 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
c767c1c6 DB |
1024 | * writing only the dynamic sizing is very well tested. Since we switched |
1025 | * away from compile-time hardware parameters, we can no longer rely on | |
1026 | * dead code elimination to leave only the relevant one in the object file. | |
550a7375 FB |
1027 | * |
1028 | * We don't currently use dynamic fifo setup capability to do anything | |
1029 | * more than selecting one of a bunch of predefined configurations. | |
1030 | */ | |
ee34e51a FB |
1031 | #if defined(CONFIG_USB_MUSB_TUSB6010) \ |
1032 | || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ | |
1033 | || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ | |
1034 | || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ | |
1035 | || defined(CONFIG_USB_MUSB_AM35X) \ | |
9ecb8875 AKG |
1036 | || defined(CONFIG_USB_MUSB_AM35X_MODULE) \ |
1037 | || defined(CONFIG_USB_MUSB_DSPS) \ | |
1038 | || defined(CONFIG_USB_MUSB_DSPS_MODULE) | |
d3608b6d | 1039 | static ushort fifo_mode = 4; |
ee34e51a FB |
1040 | #elif defined(CONFIG_USB_MUSB_UX500) \ |
1041 | || defined(CONFIG_USB_MUSB_UX500_MODULE) | |
d3608b6d | 1042 | static ushort fifo_mode = 5; |
550a7375 | 1043 | #else |
d3608b6d | 1044 | static ushort fifo_mode = 2; |
550a7375 FB |
1045 | #endif |
1046 | ||
1047 | /* "modprobe ... fifo_mode=1" etc */ | |
1048 | module_param(fifo_mode, ushort, 0); | |
1049 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
1050 | ||
550a7375 FB |
1051 | /* |
1052 | * tables defining fifo_mode values. define more if you like. | |
1053 | * for host side, make sure both halves of ep1 are set up. | |
1054 | */ | |
1055 | ||
1056 | /* mode 0 - fits in 2KB */ | |
d3608b6d | 1057 | static struct musb_fifo_cfg mode_0_cfg[] = { |
550a7375 FB |
1058 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1059 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1060 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1061 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1062 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1063 | }; | |
1064 | ||
1065 | /* mode 1 - fits in 4KB */ | |
d3608b6d | 1066 | static struct musb_fifo_cfg mode_1_cfg[] = { |
550a7375 FB |
1067 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1068 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1069 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1070 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1071 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1072 | }; | |
1073 | ||
1074 | /* mode 2 - fits in 4KB */ | |
d3608b6d | 1075 | static struct musb_fifo_cfg mode_2_cfg[] = { |
550a7375 FB |
1076 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1077 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1078 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1079 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1080 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1081 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1082 | }; | |
1083 | ||
1084 | /* mode 3 - fits in 4KB */ | |
d3608b6d | 1085 | static struct musb_fifo_cfg mode_3_cfg[] = { |
550a7375 FB |
1086 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1087 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1088 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1089 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1090 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1091 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1092 | }; | |
1093 | ||
1094 | /* mode 4 - fits in 16KB */ | |
d3608b6d | 1095 | static struct musb_fifo_cfg mode_4_cfg[] = { |
550a7375 FB |
1096 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1097 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1098 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1099 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1100 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1101 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1102 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1103 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1104 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1105 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1106 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1107 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1108 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1109 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1110 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1111 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1112 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1113 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
a483d706 AKG |
1114 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, |
1115 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, | |
1116 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, | |
1117 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, | |
1118 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, | |
1119 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, | |
1120 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, | |
550a7375 FB |
1121 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
1122 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1123 | }; | |
1124 | ||
3b151526 | 1125 | /* mode 5 - fits in 8KB */ |
d3608b6d | 1126 | static struct musb_fifo_cfg mode_5_cfg[] = { |
3b151526 AKG |
1127 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1128 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1129 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1130 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1131 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1132 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1133 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1134 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1135 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1136 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1137 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, | |
1138 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, | |
1139 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, | |
1140 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, | |
1141 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, | |
1142 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, | |
1143 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, | |
1144 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, | |
1145 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, | |
1146 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, | |
1147 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, | |
1148 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, | |
1149 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, | |
1150 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, | |
1151 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1152 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1153 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1154 | }; | |
550a7375 FB |
1155 | |
1156 | /* | |
1157 | * configure a fifo; for non-shared endpoints, this may be called | |
1158 | * once for a tx fifo and once for an rx fifo. | |
1159 | * | |
1160 | * returns negative errno or offset for next fifo. | |
1161 | */ | |
41ac7b3a | 1162 | static int |
550a7375 | 1163 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, |
e6c213b2 | 1164 | const struct musb_fifo_cfg *cfg, u16 offset) |
550a7375 FB |
1165 | { |
1166 | void __iomem *mbase = musb->mregs; | |
1167 | int size = 0; | |
1168 | u16 maxpacket = cfg->maxpacket; | |
1169 | u16 c_off = offset >> 3; | |
1170 | u8 c_size; | |
1171 | ||
1172 | /* expect hw_ep has already been zero-initialized */ | |
1173 | ||
1174 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1175 | maxpacket = 1 << size; | |
1176 | ||
1177 | c_size = size - 3; | |
1178 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1179 | if ((offset + (maxpacket << 1)) > |
1180 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1181 | return -EMSGSIZE; |
1182 | c_size |= MUSB_FIFOSZ_DPB; | |
1183 | } else { | |
ca6d1b13 | 1184 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1185 | return -EMSGSIZE; |
1186 | } | |
1187 | ||
1188 | /* configure the FIFO */ | |
1189 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1190 | ||
550a7375 | 1191 | /* EP0 reserved endpoint for control, bidirectional; |
5ae477b0 | 1192 | * EP1 reserved for bulk, two unidirectional halves. |
550a7375 FB |
1193 | */ |
1194 | if (hw_ep->epnum == 1) | |
1195 | musb->bulk_ep = hw_ep; | |
1196 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
550a7375 FB |
1197 | switch (cfg->style) { |
1198 | case FIFO_TX: | |
c6cf8b00 BW |
1199 | musb_write_txfifosz(mbase, c_size); |
1200 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1201 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1202 | hw_ep->max_packet_sz_tx = maxpacket; | |
1203 | break; | |
1204 | case FIFO_RX: | |
c6cf8b00 BW |
1205 | musb_write_rxfifosz(mbase, c_size); |
1206 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1207 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1208 | hw_ep->max_packet_sz_rx = maxpacket; | |
1209 | break; | |
1210 | case FIFO_RXTX: | |
c6cf8b00 BW |
1211 | musb_write_txfifosz(mbase, c_size); |
1212 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1213 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1214 | hw_ep->max_packet_sz_rx = maxpacket; | |
1215 | ||
c6cf8b00 BW |
1216 | musb_write_rxfifosz(mbase, c_size); |
1217 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1218 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
1219 | hw_ep->max_packet_sz_tx = maxpacket; | |
1220 | ||
1221 | hw_ep->is_shared_fifo = true; | |
1222 | break; | |
1223 | } | |
1224 | ||
1225 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1226 | * which happens to be ok | |
1227 | */ | |
1228 | musb->epmask |= (1 << hw_ep->epnum); | |
1229 | ||
1230 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1231 | } | |
1232 | ||
d3608b6d | 1233 | static struct musb_fifo_cfg ep0_cfg = { |
550a7375 FB |
1234 | .style = FIFO_RXTX, .maxpacket = 64, |
1235 | }; | |
1236 | ||
41ac7b3a | 1237 | static int ep_config_from_table(struct musb *musb) |
550a7375 | 1238 | { |
e6c213b2 | 1239 | const struct musb_fifo_cfg *cfg; |
550a7375 FB |
1240 | unsigned i, n; |
1241 | int offset; | |
1242 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1243 | ||
e6c213b2 FB |
1244 | if (musb->config->fifo_cfg) { |
1245 | cfg = musb->config->fifo_cfg; | |
1246 | n = musb->config->fifo_cfg_size; | |
1247 | goto done; | |
1248 | } | |
1249 | ||
550a7375 FB |
1250 | switch (fifo_mode) { |
1251 | default: | |
1252 | fifo_mode = 0; | |
1253 | /* FALLTHROUGH */ | |
1254 | case 0: | |
1255 | cfg = mode_0_cfg; | |
1256 | n = ARRAY_SIZE(mode_0_cfg); | |
1257 | break; | |
1258 | case 1: | |
1259 | cfg = mode_1_cfg; | |
1260 | n = ARRAY_SIZE(mode_1_cfg); | |
1261 | break; | |
1262 | case 2: | |
1263 | cfg = mode_2_cfg; | |
1264 | n = ARRAY_SIZE(mode_2_cfg); | |
1265 | break; | |
1266 | case 3: | |
1267 | cfg = mode_3_cfg; | |
1268 | n = ARRAY_SIZE(mode_3_cfg); | |
1269 | break; | |
1270 | case 4: | |
1271 | cfg = mode_4_cfg; | |
1272 | n = ARRAY_SIZE(mode_4_cfg); | |
1273 | break; | |
3b151526 AKG |
1274 | case 5: |
1275 | cfg = mode_5_cfg; | |
1276 | n = ARRAY_SIZE(mode_5_cfg); | |
1277 | break; | |
550a7375 FB |
1278 | } |
1279 | ||
1280 | printk(KERN_DEBUG "%s: setup fifo_mode %d\n", | |
1281 | musb_driver_name, fifo_mode); | |
1282 | ||
1283 | ||
e6c213b2 | 1284 | done: |
550a7375 FB |
1285 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); |
1286 | /* assert(offset > 0) */ | |
1287 | ||
1288 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1289 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1290 | */ |
1291 | ||
1292 | for (i = 0; i < n; i++) { | |
1293 | u8 epn = cfg->hw_ep_num; | |
1294 | ||
ca6d1b13 | 1295 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1296 | pr_debug("%s: invalid ep %d\n", |
1297 | musb_driver_name, epn); | |
bb1c9ef1 | 1298 | return -EINVAL; |
550a7375 FB |
1299 | } |
1300 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1301 | if (offset < 0) { | |
1302 | pr_debug("%s: mem overrun, ep %d\n", | |
1303 | musb_driver_name, epn); | |
f69dfa1f | 1304 | return offset; |
550a7375 FB |
1305 | } |
1306 | epn++; | |
1307 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1308 | } | |
1309 | ||
1310 | printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", | |
1311 | musb_driver_name, | |
ca6d1b13 FB |
1312 | n + 1, musb->config->num_eps * 2 - 1, |
1313 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 | 1314 | |
550a7375 FB |
1315 | if (!musb->bulk_ep) { |
1316 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1317 | return -EINVAL; | |
1318 | } | |
550a7375 FB |
1319 | |
1320 | return 0; | |
1321 | } | |
1322 | ||
1323 | ||
1324 | /* | |
1325 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1326 | * @param musb the controller | |
1327 | */ | |
41ac7b3a | 1328 | static int ep_config_from_hw(struct musb *musb) |
550a7375 | 1329 | { |
c6cf8b00 | 1330 | u8 epnum = 0; |
550a7375 | 1331 | struct musb_hw_ep *hw_ep; |
a156544b | 1332 | void __iomem *mbase = musb->mregs; |
c6cf8b00 | 1333 | int ret = 0; |
550a7375 | 1334 | |
5c8a86e1 | 1335 | dev_dbg(musb->controller, "<== static silicon ep config\n"); |
550a7375 FB |
1336 | |
1337 | /* FIXME pick up ep0 maxpacket size */ | |
1338 | ||
ca6d1b13 | 1339 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1340 | musb_ep_select(mbase, epnum); |
1341 | hw_ep = musb->endpoints + epnum; | |
1342 | ||
c6cf8b00 BW |
1343 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
1344 | if (ret < 0) | |
550a7375 | 1345 | break; |
550a7375 FB |
1346 | |
1347 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1348 | ||
550a7375 FB |
1349 | /* pick an RX/TX endpoint for bulk */ |
1350 | if (hw_ep->max_packet_sz_tx < 512 | |
1351 | || hw_ep->max_packet_sz_rx < 512) | |
1352 | continue; | |
1353 | ||
1354 | /* REVISIT: this algorithm is lazy, we should at least | |
1355 | * try to pick a double buffered endpoint. | |
1356 | */ | |
1357 | if (musb->bulk_ep) | |
1358 | continue; | |
1359 | musb->bulk_ep = hw_ep; | |
550a7375 FB |
1360 | } |
1361 | ||
550a7375 FB |
1362 | if (!musb->bulk_ep) { |
1363 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1364 | return -EINVAL; | |
1365 | } | |
550a7375 FB |
1366 | |
1367 | return 0; | |
1368 | } | |
1369 | ||
1370 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1371 | ||
1372 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1373 | * configure endpoints, or take their config from silicon | |
1374 | */ | |
41ac7b3a | 1375 | static int musb_core_init(u16 musb_type, struct musb *musb) |
550a7375 | 1376 | { |
550a7375 FB |
1377 | u8 reg; |
1378 | char *type; | |
0ea52ff4 | 1379 | char aInfo[90], aRevision[32], aDate[12]; |
550a7375 FB |
1380 | void __iomem *mbase = musb->mregs; |
1381 | int status = 0; | |
1382 | int i; | |
1383 | ||
1384 | /* log core options (read using indexed model) */ | |
c6cf8b00 | 1385 | reg = musb_read_configdata(mbase); |
550a7375 FB |
1386 | |
1387 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
51bf0d0e | 1388 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { |
550a7375 | 1389 | strcat(aInfo, ", dyn FIFOs"); |
51bf0d0e AKG |
1390 | musb->dyn_fifo = true; |
1391 | } | |
550a7375 FB |
1392 | if (reg & MUSB_CONFIGDATA_MPRXE) { |
1393 | strcat(aInfo, ", bulk combine"); | |
550a7375 | 1394 | musb->bulk_combine = true; |
550a7375 FB |
1395 | } |
1396 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1397 | strcat(aInfo, ", bulk split"); | |
550a7375 | 1398 | musb->bulk_split = true; |
550a7375 FB |
1399 | } |
1400 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1401 | strcat(aInfo, ", HB-ISO Rx"); | |
a483d706 | 1402 | musb->hb_iso_rx = true; |
550a7375 FB |
1403 | } |
1404 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1405 | strcat(aInfo, ", HB-ISO Tx"); | |
a483d706 | 1406 | musb->hb_iso_tx = true; |
550a7375 FB |
1407 | } |
1408 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1409 | strcat(aInfo, ", SoftConn"); | |
1410 | ||
1411 | printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", | |
1412 | musb_driver_name, reg, aInfo); | |
1413 | ||
550a7375 | 1414 | aDate[0] = 0; |
550a7375 FB |
1415 | if (MUSB_CONTROLLER_MHDRC == musb_type) { |
1416 | musb->is_multipoint = 1; | |
1417 | type = "M"; | |
1418 | } else { | |
1419 | musb->is_multipoint = 0; | |
1420 | type = ""; | |
550a7375 FB |
1421 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB |
1422 | printk(KERN_ERR | |
1423 | "%s: kernel must blacklist external hubs\n", | |
1424 | musb_driver_name); | |
550a7375 FB |
1425 | #endif |
1426 | } | |
1427 | ||
1428 | /* log release info */ | |
32c3b94e AG |
1429 | musb->hwvers = musb_read_hwvers(mbase); |
1430 | snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), | |
1431 | MUSB_HWVERS_MINOR(musb->hwvers), | |
1432 | (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); | |
550a7375 FB |
1433 | printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", |
1434 | musb_driver_name, type, aRevision, aDate); | |
1435 | ||
1436 | /* configure ep0 */ | |
c6cf8b00 | 1437 | musb_configure_ep0(musb); |
550a7375 FB |
1438 | |
1439 | /* discover endpoint configuration */ | |
1440 | musb->nr_endpoints = 1; | |
1441 | musb->epmask = 1; | |
1442 | ||
ad517e9e FB |
1443 | if (musb->dyn_fifo) |
1444 | status = ep_config_from_table(musb); | |
1445 | else | |
1446 | status = ep_config_from_hw(musb); | |
550a7375 FB |
1447 | |
1448 | if (status < 0) | |
1449 | return status; | |
1450 | ||
1451 | /* finish init, and print endpoint config */ | |
1452 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1453 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1454 | ||
1455 | hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; | |
9a35f876 | 1456 | #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE) |
550a7375 FB |
1457 | hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); |
1458 | hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); | |
1459 | hw_ep->fifo_sync_va = | |
1460 | musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); | |
1461 | ||
1462 | if (i == 0) | |
1463 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1464 | else | |
1465 | hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); | |
1466 | #endif | |
1467 | ||
1468 | hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; | |
c6cf8b00 | 1469 | hw_ep->target_regs = musb_read_target_reg_base(i, mbase); |
550a7375 FB |
1470 | hw_ep->rx_reinit = 1; |
1471 | hw_ep->tx_reinit = 1; | |
550a7375 FB |
1472 | |
1473 | if (hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1474 | dev_dbg(musb->controller, |
550a7375 FB |
1475 | "%s: hw_ep %d%s, %smax %d\n", |
1476 | musb_driver_name, i, | |
1477 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1478 | hw_ep->tx_double_buffered | |
1479 | ? "doublebuffer, " : "", | |
1480 | hw_ep->max_packet_sz_tx); | |
1481 | } | |
1482 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
5c8a86e1 | 1483 | dev_dbg(musb->controller, |
550a7375 FB |
1484 | "%s: hw_ep %d%s, %smax %d\n", |
1485 | musb_driver_name, i, | |
1486 | "rx", | |
1487 | hw_ep->rx_double_buffered | |
1488 | ? "doublebuffer, " : "", | |
1489 | hw_ep->max_packet_sz_rx); | |
1490 | } | |
1491 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
5c8a86e1 | 1492 | dev_dbg(musb->controller, "hw_ep %d not configured\n", i); |
550a7375 FB |
1493 | } |
1494 | ||
1495 | return 0; | |
1496 | } | |
1497 | ||
1498 | /*-------------------------------------------------------------------------*/ | |
1499 | ||
550a7375 FB |
1500 | /* |
1501 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1502 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1503 | * will be assigned, and the irq will already have been acked. | |
1504 | * | |
1505 | * called in irq context with spinlock held, irqs blocked | |
1506 | */ | |
1507 | irqreturn_t musb_interrupt(struct musb *musb) | |
1508 | { | |
1509 | irqreturn_t retval = IRQ_NONE; | |
b11e94d0 | 1510 | u8 devctl; |
550a7375 FB |
1511 | int ep_num; |
1512 | u32 reg; | |
1513 | ||
1514 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
550a7375 | 1515 | |
5c8a86e1 | 1516 | dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", |
550a7375 FB |
1517 | (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", |
1518 | musb->int_usb, musb->int_tx, musb->int_rx); | |
1519 | ||
1520 | /* the core can interrupt us for multiple reasons; docs have | |
1521 | * a generic interrupt flowchart to follow | |
1522 | */ | |
7d9645fd | 1523 | if (musb->int_usb) |
550a7375 | 1524 | retval |= musb_stage0_irq(musb, musb->int_usb, |
b11e94d0 | 1525 | devctl); |
550a7375 FB |
1526 | |
1527 | /* "stage 1" is handling endpoint irqs */ | |
1528 | ||
1529 | /* handle endpoint 0 first */ | |
1530 | if (musb->int_tx & 1) { | |
1531 | if (devctl & MUSB_DEVCTL_HM) | |
1532 | retval |= musb_h_ep0_irq(musb); | |
1533 | else | |
1534 | retval |= musb_g_ep0_irq(musb); | |
1535 | } | |
1536 | ||
1537 | /* RX on endpoints 1-15 */ | |
1538 | reg = musb->int_rx >> 1; | |
1539 | ep_num = 1; | |
1540 | while (reg) { | |
1541 | if (reg & 1) { | |
1542 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1543 | /* REVISIT just retval = ep->rx_irq(...) */ | |
1544 | retval = IRQ_HANDLED; | |
a04d46d0 FB |
1545 | if (devctl & MUSB_DEVCTL_HM) |
1546 | musb_host_rx(musb, ep_num); | |
1547 | else | |
1548 | musb_g_rx(musb, ep_num); | |
550a7375 FB |
1549 | } |
1550 | ||
1551 | reg >>= 1; | |
1552 | ep_num++; | |
1553 | } | |
1554 | ||
1555 | /* TX on endpoints 1-15 */ | |
1556 | reg = musb->int_tx >> 1; | |
1557 | ep_num = 1; | |
1558 | while (reg) { | |
1559 | if (reg & 1) { | |
1560 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1561 | /* REVISIT just retval |= ep->tx_irq(...) */ | |
1562 | retval = IRQ_HANDLED; | |
a04d46d0 FB |
1563 | if (devctl & MUSB_DEVCTL_HM) |
1564 | musb_host_tx(musb, ep_num); | |
1565 | else | |
1566 | musb_g_tx(musb, ep_num); | |
550a7375 FB |
1567 | } |
1568 | reg >>= 1; | |
1569 | ep_num++; | |
1570 | } | |
1571 | ||
550a7375 FB |
1572 | return retval; |
1573 | } | |
981430a1 | 1574 | EXPORT_SYMBOL_GPL(musb_interrupt); |
550a7375 FB |
1575 | |
1576 | #ifndef CONFIG_MUSB_PIO_ONLY | |
d3608b6d | 1577 | static bool use_dma = 1; |
550a7375 FB |
1578 | |
1579 | /* "modprobe ... use_dma=0" etc */ | |
1580 | module_param(use_dma, bool, 0); | |
1581 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
1582 | ||
1583 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1584 | { | |
1585 | u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1586 | ||
1587 | /* called with controller lock already held */ | |
1588 | ||
1589 | if (!epnum) { | |
1590 | #ifndef CONFIG_USB_TUSB_OMAP_DMA | |
1591 | if (!is_cppi_enabled()) { | |
1592 | /* endpoint 0 */ | |
1593 | if (devctl & MUSB_DEVCTL_HM) | |
1594 | musb_h_ep0_irq(musb); | |
1595 | else | |
1596 | musb_g_ep0_irq(musb); | |
1597 | } | |
1598 | #endif | |
1599 | } else { | |
1600 | /* endpoints 1..15 */ | |
1601 | if (transmit) { | |
a04d46d0 FB |
1602 | if (devctl & MUSB_DEVCTL_HM) |
1603 | musb_host_tx(musb, epnum); | |
1604 | else | |
1605 | musb_g_tx(musb, epnum); | |
550a7375 FB |
1606 | } else { |
1607 | /* receive */ | |
a04d46d0 FB |
1608 | if (devctl & MUSB_DEVCTL_HM) |
1609 | musb_host_rx(musb, epnum); | |
1610 | else | |
1611 | musb_g_rx(musb, epnum); | |
550a7375 FB |
1612 | } |
1613 | } | |
1614 | } | |
9a35f876 | 1615 | EXPORT_SYMBOL_GPL(musb_dma_completion); |
550a7375 FB |
1616 | |
1617 | #else | |
1618 | #define use_dma 0 | |
1619 | #endif | |
1620 | ||
1621 | /*-------------------------------------------------------------------------*/ | |
1622 | ||
550a7375 FB |
1623 | static ssize_t |
1624 | musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1625 | { | |
1626 | struct musb *musb = dev_to_musb(dev); | |
1627 | unsigned long flags; | |
1628 | int ret = -EINVAL; | |
1629 | ||
1630 | spin_lock_irqsave(&musb->lock, flags); | |
42c0bf1c | 1631 | ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1632 | spin_unlock_irqrestore(&musb->lock, flags); |
1633 | ||
1634 | return ret; | |
1635 | } | |
1636 | ||
1637 | static ssize_t | |
1638 | musb_mode_store(struct device *dev, struct device_attribute *attr, | |
1639 | const char *buf, size_t n) | |
1640 | { | |
1641 | struct musb *musb = dev_to_musb(dev); | |
1642 | unsigned long flags; | |
96a274d1 | 1643 | int status; |
550a7375 FB |
1644 | |
1645 | spin_lock_irqsave(&musb->lock, flags); | |
96a274d1 DB |
1646 | if (sysfs_streq(buf, "host")) |
1647 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
1648 | else if (sysfs_streq(buf, "peripheral")) | |
1649 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1650 | else if (sysfs_streq(buf, "otg")) | |
1651 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
1652 | else | |
1653 | status = -EINVAL; | |
550a7375 FB |
1654 | spin_unlock_irqrestore(&musb->lock, flags); |
1655 | ||
96a274d1 | 1656 | return (status == 0) ? n : status; |
550a7375 FB |
1657 | } |
1658 | static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); | |
1659 | ||
1660 | static ssize_t | |
1661 | musb_vbus_store(struct device *dev, struct device_attribute *attr, | |
1662 | const char *buf, size_t n) | |
1663 | { | |
1664 | struct musb *musb = dev_to_musb(dev); | |
1665 | unsigned long flags; | |
1666 | unsigned long val; | |
1667 | ||
1668 | if (sscanf(buf, "%lu", &val) < 1) { | |
b3b1cc3b | 1669 | dev_err(dev, "Invalid VBUS timeout ms value\n"); |
550a7375 FB |
1670 | return -EINVAL; |
1671 | } | |
1672 | ||
1673 | spin_lock_irqsave(&musb->lock, flags); | |
f7f9d63e DB |
1674 | /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ |
1675 | musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; | |
84e250ff | 1676 | if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) |
550a7375 FB |
1677 | musb->is_active = 0; |
1678 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1679 | spin_unlock_irqrestore(&musb->lock, flags); | |
1680 | ||
1681 | return n; | |
1682 | } | |
1683 | ||
1684 | static ssize_t | |
1685 | musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1686 | { | |
1687 | struct musb *musb = dev_to_musb(dev); | |
1688 | unsigned long flags; | |
1689 | unsigned long val; | |
1690 | int vbus; | |
1691 | ||
1692 | spin_lock_irqsave(&musb->lock, flags); | |
1693 | val = musb->a_wait_bcon; | |
f7f9d63e DB |
1694 | /* FIXME get_vbus_status() is normally #defined as false... |
1695 | * and is effectively TUSB-specific. | |
1696 | */ | |
550a7375 FB |
1697 | vbus = musb_platform_get_vbus_status(musb); |
1698 | spin_unlock_irqrestore(&musb->lock, flags); | |
1699 | ||
f7f9d63e | 1700 | return sprintf(buf, "Vbus %s, timeout %lu msec\n", |
550a7375 FB |
1701 | vbus ? "on" : "off", val); |
1702 | } | |
1703 | static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); | |
1704 | ||
550a7375 FB |
1705 | /* Gadget drivers can't know that a host is connected so they might want |
1706 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1707 | */ | |
1708 | static ssize_t | |
1709 | musb_srp_store(struct device *dev, struct device_attribute *attr, | |
1710 | const char *buf, size_t n) | |
1711 | { | |
1712 | struct musb *musb = dev_to_musb(dev); | |
1713 | unsigned short srp; | |
1714 | ||
1715 | if (sscanf(buf, "%hu", &srp) != 1 | |
1716 | || (srp != 1)) { | |
b3b1cc3b | 1717 | dev_err(dev, "SRP: Value must be 1\n"); |
550a7375 FB |
1718 | return -EINVAL; |
1719 | } | |
1720 | ||
1721 | if (srp == 1) | |
1722 | musb_g_wakeup(musb); | |
1723 | ||
1724 | return n; | |
1725 | } | |
1726 | static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); | |
1727 | ||
94375751 FB |
1728 | static struct attribute *musb_attributes[] = { |
1729 | &dev_attr_mode.attr, | |
1730 | &dev_attr_vbus.attr, | |
94375751 | 1731 | &dev_attr_srp.attr, |
94375751 FB |
1732 | NULL |
1733 | }; | |
1734 | ||
1735 | static const struct attribute_group musb_attr_group = { | |
1736 | .attrs = musb_attributes, | |
1737 | }; | |
1738 | ||
550a7375 FB |
1739 | /* Only used to provide driver mode change events */ |
1740 | static void musb_irq_work(struct work_struct *data) | |
1741 | { | |
1742 | struct musb *musb = container_of(data, struct musb, irq_work); | |
550a7375 | 1743 | |
8d2421e6 AKG |
1744 | if (musb->xceiv->state != musb->xceiv_old_state) { |
1745 | musb->xceiv_old_state = musb->xceiv->state; | |
550a7375 FB |
1746 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); |
1747 | } | |
1748 | } | |
1749 | ||
1750 | /* -------------------------------------------------------------------------- | |
1751 | * Init support | |
1752 | */ | |
1753 | ||
41ac7b3a | 1754 | static struct musb *allocate_instance(struct device *dev, |
ca6d1b13 | 1755 | struct musb_hdrc_config *config, void __iomem *mbase) |
550a7375 FB |
1756 | { |
1757 | struct musb *musb; | |
1758 | struct musb_hw_ep *ep; | |
1759 | int epnum; | |
74c2e936 | 1760 | int ret; |
550a7375 | 1761 | |
74c2e936 DM |
1762 | musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); |
1763 | if (!musb) | |
550a7375 | 1764 | return NULL; |
550a7375 | 1765 | |
550a7375 FB |
1766 | INIT_LIST_HEAD(&musb->control); |
1767 | INIT_LIST_HEAD(&musb->in_bulk); | |
1768 | INIT_LIST_HEAD(&musb->out_bulk); | |
1769 | ||
550a7375 | 1770 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; |
f7f9d63e | 1771 | musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; |
550a7375 FB |
1772 | musb->mregs = mbase; |
1773 | musb->ctrl_base = mbase; | |
1774 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1775 | musb->config = config; |
02582b92 | 1776 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
550a7375 | 1777 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1778 | epnum < musb->config->num_eps; |
550a7375 | 1779 | epnum++, ep++) { |
550a7375 FB |
1780 | ep->musb = musb; |
1781 | ep->epnum = epnum; | |
1782 | } | |
1783 | ||
1784 | musb->controller = dev; | |
743411b3 | 1785 | |
74c2e936 DM |
1786 | ret = musb_host_alloc(musb); |
1787 | if (ret < 0) | |
1788 | goto err_free; | |
1789 | ||
1790 | dev_set_drvdata(dev, musb); | |
1791 | ||
550a7375 | 1792 | return musb; |
74c2e936 DM |
1793 | |
1794 | err_free: | |
1795 | return NULL; | |
550a7375 FB |
1796 | } |
1797 | ||
1798 | static void musb_free(struct musb *musb) | |
1799 | { | |
1800 | /* this has multiple entry modes. it handles fault cleanup after | |
1801 | * probe(), where things may be partially set up, as well as rmmod | |
1802 | * cleanup after everything's been de-activated. | |
1803 | */ | |
1804 | ||
1805 | #ifdef CONFIG_SYSFS | |
94375751 | 1806 | sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); |
550a7375 FB |
1807 | #endif |
1808 | ||
97a39896 AKG |
1809 | if (musb->nIrq >= 0) { |
1810 | if (musb->irq_wake) | |
1811 | disable_irq_wake(musb->nIrq); | |
550a7375 FB |
1812 | free_irq(musb->nIrq, musb); |
1813 | } | |
550a7375 | 1814 | |
74c2e936 | 1815 | musb_host_free(musb); |
550a7375 FB |
1816 | } |
1817 | ||
8ed1fb79 DM |
1818 | static void musb_deassert_reset(struct work_struct *work) |
1819 | { | |
1820 | struct musb *musb; | |
1821 | unsigned long flags; | |
1822 | ||
1823 | musb = container_of(work, struct musb, deassert_reset_work.work); | |
1824 | ||
1825 | spin_lock_irqsave(&musb->lock, flags); | |
1826 | ||
1827 | if (musb->port1_status & USB_PORT_STAT_RESET) | |
1828 | musb_port_reset(musb, false); | |
1829 | ||
1830 | spin_unlock_irqrestore(&musb->lock, flags); | |
1831 | } | |
1832 | ||
550a7375 FB |
1833 | /* |
1834 | * Perform generic per-controller initialization. | |
1835 | * | |
28dd924a SS |
1836 | * @dev: the controller (already clocked, etc) |
1837 | * @nIrq: IRQ number | |
1838 | * @ctrl: virtual address of controller registers, | |
550a7375 FB |
1839 | * not yet corrected for platform-specific offsets |
1840 | */ | |
41ac7b3a | 1841 | static int |
550a7375 FB |
1842 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) |
1843 | { | |
1844 | int status; | |
1845 | struct musb *musb; | |
c1a7d67c | 1846 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
550a7375 FB |
1847 | |
1848 | /* The driver might handle more features than the board; OK. | |
1849 | * Fail when the board needs a feature that's not enabled. | |
1850 | */ | |
1851 | if (!plat) { | |
1852 | dev_dbg(dev, "no platform_data?\n"); | |
34e2beb2 SS |
1853 | status = -ENODEV; |
1854 | goto fail0; | |
550a7375 | 1855 | } |
34e2beb2 | 1856 | |
550a7375 | 1857 | /* allocate */ |
ca6d1b13 | 1858 | musb = allocate_instance(dev, plat->config, ctrl); |
34e2beb2 SS |
1859 | if (!musb) { |
1860 | status = -ENOMEM; | |
1861 | goto fail0; | |
1862 | } | |
550a7375 | 1863 | |
7acc6197 HH |
1864 | pm_runtime_use_autosuspend(musb->controller); |
1865 | pm_runtime_set_autosuspend_delay(musb->controller, 200); | |
1866 | pm_runtime_enable(musb->controller); | |
1867 | ||
550a7375 | 1868 | spin_lock_init(&musb->lock); |
550a7375 | 1869 | musb->board_set_power = plat->set_power; |
550a7375 | 1870 | musb->min_power = plat->min_power; |
f7ec9437 | 1871 | musb->ops = plat->platform_ops; |
9ad96e69 | 1872 | musb->port_mode = plat->mode; |
550a7375 | 1873 | |
84e250ff | 1874 | /* The musb_platform_init() call: |
baef653a PDS |
1875 | * - adjusts musb->mregs |
1876 | * - sets the musb->isr | |
5ae477b0 | 1877 | * - may initialize an integrated transceiver |
721002ec | 1878 | * - initializes musb->xceiv, usually by otg_get_phy() |
84e250ff | 1879 | * - stops powering VBUS |
84e250ff | 1880 | * |
7c9d440e | 1881 | * There are various transceiver configurations. Blackfin, |
84e250ff DB |
1882 | * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses |
1883 | * external/discrete ones in various flavors (twl4030 family, | |
1884 | * isp1504, non-OTG, etc) mostly hooking up through ULPI. | |
550a7375 | 1885 | */ |
ea65df57 | 1886 | status = musb_platform_init(musb); |
550a7375 | 1887 | if (status < 0) |
03491761 | 1888 | goto fail1; |
34e2beb2 | 1889 | |
550a7375 FB |
1890 | if (!musb->isr) { |
1891 | status = -ENODEV; | |
c04352a5 | 1892 | goto fail2; |
550a7375 FB |
1893 | } |
1894 | ||
ffb865b1 | 1895 | if (!musb->xceiv->io_ops) { |
bf070bc1 | 1896 | musb->xceiv->io_dev = musb->controller; |
ffb865b1 HK |
1897 | musb->xceiv->io_priv = musb->mregs; |
1898 | musb->xceiv->io_ops = &musb_ulpi_access; | |
1899 | } | |
1900 | ||
c04352a5 GI |
1901 | pm_runtime_get_sync(musb->controller); |
1902 | ||
48054147 | 1903 | if (use_dma && dev->dma_mask) { |
66c01883 | 1904 | musb->dma_controller = dma_controller_create(musb, musb->mregs); |
48054147 SAS |
1905 | if (IS_ERR(musb->dma_controller)) { |
1906 | status = PTR_ERR(musb->dma_controller); | |
1907 | goto fail2_5; | |
1908 | } | |
1909 | } | |
550a7375 FB |
1910 | |
1911 | /* be sure interrupts are disabled before connecting ISR */ | |
1912 | musb_platform_disable(musb); | |
1913 | musb_generic_disable(musb); | |
1914 | ||
66fadea5 SAS |
1915 | /* Init IRQ workqueue before request_irq */ |
1916 | INIT_WORK(&musb->irq_work, musb_irq_work); | |
8ed1fb79 DM |
1917 | INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset); |
1918 | INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume); | |
66fadea5 | 1919 | |
550a7375 | 1920 | /* setup musb parts of the core (especially endpoints) */ |
ca6d1b13 | 1921 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
1922 | ? MUSB_CONTROLLER_MHDRC |
1923 | : MUSB_CONTROLLER_HDRC, musb); | |
1924 | if (status < 0) | |
34e2beb2 | 1925 | goto fail3; |
550a7375 | 1926 | |
f7f9d63e | 1927 | setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); |
f7f9d63e | 1928 | |
550a7375 | 1929 | /* attach to the IRQ */ |
427c4f33 | 1930 | if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { |
550a7375 FB |
1931 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
1932 | status = -ENODEV; | |
34e2beb2 | 1933 | goto fail3; |
550a7375 FB |
1934 | } |
1935 | musb->nIrq = nIrq; | |
032ec49f | 1936 | /* FIXME this handles wakeup irqs wrong */ |
c48a5155 FB |
1937 | if (enable_irq_wake(nIrq) == 0) { |
1938 | musb->irq_wake = 1; | |
550a7375 | 1939 | device_init_wakeup(dev, 1); |
c48a5155 FB |
1940 | } else { |
1941 | musb->irq_wake = 0; | |
1942 | } | |
550a7375 | 1943 | |
032ec49f FB |
1944 | /* program PHY to use external vBus if required */ |
1945 | if (plat->extvbus) { | |
1946 | u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
1947 | busctl |= MUSB_ULPI_USE_EXTVBUS; | |
1948 | musb_write_ulpi_buscontrol(musb->mregs, busctl); | |
550a7375 | 1949 | } |
550a7375 | 1950 | |
e5615112 GI |
1951 | if (musb->xceiv->otg->default_a) { |
1952 | MUSB_HST_MODE(musb); | |
1953 | musb->xceiv->state = OTG_STATE_A_IDLE; | |
1954 | } else { | |
1955 | MUSB_DEV_MODE(musb); | |
1956 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
1957 | } | |
550a7375 | 1958 | |
6c5f6a6f DM |
1959 | switch (musb->port_mode) { |
1960 | case MUSB_PORT_MODE_HOST: | |
1961 | status = musb_host_setup(musb, plat->power); | |
2df6761e FB |
1962 | if (status < 0) |
1963 | goto fail3; | |
1964 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
6c5f6a6f DM |
1965 | break; |
1966 | case MUSB_PORT_MODE_GADGET: | |
1967 | status = musb_gadget_setup(musb); | |
2df6761e FB |
1968 | if (status < 0) |
1969 | goto fail3; | |
1970 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
6c5f6a6f DM |
1971 | break; |
1972 | case MUSB_PORT_MODE_DUAL_ROLE: | |
1973 | status = musb_host_setup(musb, plat->power); | |
1974 | if (status < 0) | |
1975 | goto fail3; | |
1976 | status = musb_gadget_setup(musb); | |
2df6761e | 1977 | if (status) { |
0d2dd7ea | 1978 | musb_host_cleanup(musb); |
2df6761e FB |
1979 | goto fail3; |
1980 | } | |
1981 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
6c5f6a6f DM |
1982 | break; |
1983 | default: | |
1984 | dev_err(dev, "unsupported port mode %d\n", musb->port_mode); | |
1985 | break; | |
1986 | } | |
550a7375 | 1987 | |
461972d8 | 1988 | if (status < 0) |
34e2beb2 | 1989 | goto fail3; |
550a7375 | 1990 | |
7f7f9e2a FB |
1991 | status = musb_init_debugfs(musb); |
1992 | if (status < 0) | |
b0f9da7e | 1993 | goto fail4; |
7f7f9e2a | 1994 | |
94375751 | 1995 | status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); |
28c2c51c | 1996 | if (status) |
b0f9da7e | 1997 | goto fail5; |
550a7375 | 1998 | |
c04352a5 GI |
1999 | pm_runtime_put(musb->controller); |
2000 | ||
28c2c51c | 2001 | return 0; |
550a7375 | 2002 | |
b0f9da7e FB |
2003 | fail5: |
2004 | musb_exit_debugfs(musb); | |
2005 | ||
34e2beb2 | 2006 | fail4: |
032ec49f | 2007 | musb_gadget_cleanup(musb); |
0d2dd7ea | 2008 | musb_host_cleanup(musb); |
34e2beb2 SS |
2009 | |
2010 | fail3: | |
66fadea5 | 2011 | cancel_work_sync(&musb->irq_work); |
8ed1fb79 DM |
2012 | cancel_delayed_work_sync(&musb->finish_resume_work); |
2013 | cancel_delayed_work_sync(&musb->deassert_reset_work); | |
f3ce4d5b SAS |
2014 | if (musb->dma_controller) |
2015 | dma_controller_destroy(musb->dma_controller); | |
48054147 | 2016 | fail2_5: |
c04352a5 GI |
2017 | pm_runtime_put_sync(musb->controller); |
2018 | ||
2019 | fail2: | |
34e2beb2 SS |
2020 | if (musb->irq_wake) |
2021 | device_init_wakeup(dev, 0); | |
550a7375 | 2022 | musb_platform_exit(musb); |
28c2c51c | 2023 | |
34e2beb2 | 2024 | fail1: |
681d1e87 | 2025 | pm_runtime_disable(musb->controller); |
34e2beb2 SS |
2026 | dev_err(musb->controller, |
2027 | "musb_init_controller failed with status %d\n", status); | |
2028 | ||
28c2c51c FB |
2029 | musb_free(musb); |
2030 | ||
34e2beb2 SS |
2031 | fail0: |
2032 | ||
28c2c51c FB |
2033 | return status; |
2034 | ||
550a7375 FB |
2035 | } |
2036 | ||
2037 | /*-------------------------------------------------------------------------*/ | |
2038 | ||
2039 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2040 | * bridge to a platform device; this driver then suffices. | |
2041 | */ | |
41ac7b3a | 2042 | static int musb_probe(struct platform_device *pdev) |
550a7375 FB |
2043 | { |
2044 | struct device *dev = &pdev->dev; | |
fcf173e4 | 2045 | int irq = platform_get_irq_byname(pdev, "mc"); |
550a7375 FB |
2046 | struct resource *iomem; |
2047 | void __iomem *base; | |
2048 | ||
2049 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
541079de | 2050 | if (!iomem || irq <= 0) |
550a7375 FB |
2051 | return -ENODEV; |
2052 | ||
b42f7f30 FB |
2053 | base = devm_ioremap_resource(dev, iomem); |
2054 | if (IS_ERR(base)) | |
2055 | return PTR_ERR(base); | |
550a7375 | 2056 | |
b42f7f30 | 2057 | return musb_init_controller(dev, irq, base); |
550a7375 FB |
2058 | } |
2059 | ||
fb4e98ab | 2060 | static int musb_remove(struct platform_device *pdev) |
550a7375 | 2061 | { |
8d2421e6 AKG |
2062 | struct device *dev = &pdev->dev; |
2063 | struct musb *musb = dev_to_musb(dev); | |
550a7375 FB |
2064 | |
2065 | /* this gets called on rmmod. | |
2066 | * - Host mode: host may still be active | |
2067 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2068 | * - OTG mode: both roles are deactivated (or never-activated) | |
2069 | */ | |
7f7f9e2a | 2070 | musb_exit_debugfs(musb); |
550a7375 | 2071 | musb_shutdown(pdev); |
461972d8 | 2072 | |
8d1aad74 SAS |
2073 | if (musb->dma_controller) |
2074 | dma_controller_destroy(musb->dma_controller); | |
2075 | ||
66fadea5 | 2076 | cancel_work_sync(&musb->irq_work); |
8ed1fb79 DM |
2077 | cancel_delayed_work_sync(&musb->finish_resume_work); |
2078 | cancel_delayed_work_sync(&musb->deassert_reset_work); | |
550a7375 | 2079 | musb_free(musb); |
8d2421e6 | 2080 | device_init_wakeup(dev, 0); |
550a7375 FB |
2081 | return 0; |
2082 | } | |
2083 | ||
2084 | #ifdef CONFIG_PM | |
2085 | ||
3c8a5fcc | 2086 | static void musb_save_context(struct musb *musb) |
4f712e01 AKG |
2087 | { |
2088 | int i; | |
2089 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2090 | void __iomem *epio; |
4f712e01 | 2091 | |
032ec49f FB |
2092 | musb->context.frame = musb_readw(musb_base, MUSB_FRAME); |
2093 | musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); | |
2094 | musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
7421107b | 2095 | musb->context.power = musb_readb(musb_base, MUSB_POWER); |
7421107b FB |
2096 | musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); |
2097 | musb->context.index = musb_readb(musb_base, MUSB_INDEX); | |
2098 | musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); | |
4f712e01 | 2099 | |
ae9b2ad2 | 2100 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2101 | struct musb_hw_ep *hw_ep; |
2102 | ||
2103 | hw_ep = &musb->endpoints[i]; | |
2104 | if (!hw_ep) | |
2105 | continue; | |
2106 | ||
2107 | epio = hw_ep->regs; | |
2108 | if (!epio) | |
2109 | continue; | |
2110 | ||
ea737554 | 2111 | musb_writeb(musb_base, MUSB_INDEX, i); |
7421107b | 2112 | musb->context.index_regs[i].txmaxp = |
ae9b2ad2 | 2113 | musb_readw(epio, MUSB_TXMAXP); |
7421107b | 2114 | musb->context.index_regs[i].txcsr = |
ae9b2ad2 | 2115 | musb_readw(epio, MUSB_TXCSR); |
7421107b | 2116 | musb->context.index_regs[i].rxmaxp = |
ae9b2ad2 | 2117 | musb_readw(epio, MUSB_RXMAXP); |
7421107b | 2118 | musb->context.index_regs[i].rxcsr = |
ae9b2ad2 | 2119 | musb_readw(epio, MUSB_RXCSR); |
4f712e01 AKG |
2120 | |
2121 | if (musb->dyn_fifo) { | |
7421107b | 2122 | musb->context.index_regs[i].txfifoadd = |
4f712e01 | 2123 | musb_read_txfifoadd(musb_base); |
7421107b | 2124 | musb->context.index_regs[i].rxfifoadd = |
4f712e01 | 2125 | musb_read_rxfifoadd(musb_base); |
7421107b | 2126 | musb->context.index_regs[i].txfifosz = |
4f712e01 | 2127 | musb_read_txfifosz(musb_base); |
7421107b | 2128 | musb->context.index_regs[i].rxfifosz = |
4f712e01 AKG |
2129 | musb_read_rxfifosz(musb_base); |
2130 | } | |
032ec49f FB |
2131 | |
2132 | musb->context.index_regs[i].txtype = | |
2133 | musb_readb(epio, MUSB_TXTYPE); | |
2134 | musb->context.index_regs[i].txinterval = | |
2135 | musb_readb(epio, MUSB_TXINTERVAL); | |
2136 | musb->context.index_regs[i].rxtype = | |
2137 | musb_readb(epio, MUSB_RXTYPE); | |
2138 | musb->context.index_regs[i].rxinterval = | |
2139 | musb_readb(epio, MUSB_RXINTERVAL); | |
2140 | ||
2141 | musb->context.index_regs[i].txfunaddr = | |
2142 | musb_read_txfunaddr(musb_base, i); | |
2143 | musb->context.index_regs[i].txhubaddr = | |
2144 | musb_read_txhubaddr(musb_base, i); | |
2145 | musb->context.index_regs[i].txhubport = | |
2146 | musb_read_txhubport(musb_base, i); | |
2147 | ||
2148 | musb->context.index_regs[i].rxfunaddr = | |
2149 | musb_read_rxfunaddr(musb_base, i); | |
2150 | musb->context.index_regs[i].rxhubaddr = | |
2151 | musb_read_rxhubaddr(musb_base, i); | |
2152 | musb->context.index_regs[i].rxhubport = | |
2153 | musb_read_rxhubport(musb_base, i); | |
4f712e01 | 2154 | } |
4f712e01 AKG |
2155 | } |
2156 | ||
3c8a5fcc | 2157 | static void musb_restore_context(struct musb *musb) |
4f712e01 AKG |
2158 | { |
2159 | int i; | |
2160 | void __iomem *musb_base = musb->mregs; | |
2161 | void __iomem *ep_target_regs; | |
ae9b2ad2 | 2162 | void __iomem *epio; |
33f8d75f | 2163 | u8 power; |
4f712e01 | 2164 | |
032ec49f FB |
2165 | musb_writew(musb_base, MUSB_FRAME, musb->context.frame); |
2166 | musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); | |
2167 | musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); | |
33f8d75f RQ |
2168 | |
2169 | /* Don't affect SUSPENDM/RESUME bits in POWER reg */ | |
2170 | power = musb_readb(musb_base, MUSB_POWER); | |
2171 | power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME; | |
2172 | musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME); | |
2173 | power |= musb->context.power; | |
2174 | musb_writeb(musb_base, MUSB_POWER, power); | |
2175 | ||
b18d26f6 | 2176 | musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); |
af5ec14d | 2177 | musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); |
7421107b FB |
2178 | musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); |
2179 | musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); | |
4f712e01 | 2180 | |
ae9b2ad2 | 2181 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2182 | struct musb_hw_ep *hw_ep; |
2183 | ||
2184 | hw_ep = &musb->endpoints[i]; | |
2185 | if (!hw_ep) | |
2186 | continue; | |
2187 | ||
2188 | epio = hw_ep->regs; | |
2189 | if (!epio) | |
2190 | continue; | |
2191 | ||
ea737554 | 2192 | musb_writeb(musb_base, MUSB_INDEX, i); |
ae9b2ad2 | 2193 | musb_writew(epio, MUSB_TXMAXP, |
7421107b | 2194 | musb->context.index_regs[i].txmaxp); |
ae9b2ad2 | 2195 | musb_writew(epio, MUSB_TXCSR, |
7421107b | 2196 | musb->context.index_regs[i].txcsr); |
ae9b2ad2 | 2197 | musb_writew(epio, MUSB_RXMAXP, |
7421107b | 2198 | musb->context.index_regs[i].rxmaxp); |
ae9b2ad2 | 2199 | musb_writew(epio, MUSB_RXCSR, |
7421107b | 2200 | musb->context.index_regs[i].rxcsr); |
4f712e01 AKG |
2201 | |
2202 | if (musb->dyn_fifo) { | |
2203 | musb_write_txfifosz(musb_base, | |
7421107b | 2204 | musb->context.index_regs[i].txfifosz); |
4f712e01 | 2205 | musb_write_rxfifosz(musb_base, |
7421107b | 2206 | musb->context.index_regs[i].rxfifosz); |
4f712e01 | 2207 | musb_write_txfifoadd(musb_base, |
7421107b | 2208 | musb->context.index_regs[i].txfifoadd); |
4f712e01 | 2209 | musb_write_rxfifoadd(musb_base, |
7421107b | 2210 | musb->context.index_regs[i].rxfifoadd); |
4f712e01 AKG |
2211 | } |
2212 | ||
032ec49f | 2213 | musb_writeb(epio, MUSB_TXTYPE, |
7421107b | 2214 | musb->context.index_regs[i].txtype); |
032ec49f | 2215 | musb_writeb(epio, MUSB_TXINTERVAL, |
7421107b | 2216 | musb->context.index_regs[i].txinterval); |
032ec49f | 2217 | musb_writeb(epio, MUSB_RXTYPE, |
7421107b | 2218 | musb->context.index_regs[i].rxtype); |
032ec49f | 2219 | musb_writeb(epio, MUSB_RXINTERVAL, |
4f712e01 | 2220 | |
032ec49f FB |
2221 | musb->context.index_regs[i].rxinterval); |
2222 | musb_write_txfunaddr(musb_base, i, | |
7421107b | 2223 | musb->context.index_regs[i].txfunaddr); |
032ec49f | 2224 | musb_write_txhubaddr(musb_base, i, |
7421107b | 2225 | musb->context.index_regs[i].txhubaddr); |
032ec49f | 2226 | musb_write_txhubport(musb_base, i, |
7421107b | 2227 | musb->context.index_regs[i].txhubport); |
4f712e01 | 2228 | |
032ec49f FB |
2229 | ep_target_regs = |
2230 | musb_read_target_reg_base(i, musb_base); | |
4f712e01 | 2231 | |
032ec49f | 2232 | musb_write_rxfunaddr(ep_target_regs, |
7421107b | 2233 | musb->context.index_regs[i].rxfunaddr); |
032ec49f | 2234 | musb_write_rxhubaddr(ep_target_regs, |
7421107b | 2235 | musb->context.index_regs[i].rxhubaddr); |
032ec49f | 2236 | musb_write_rxhubport(ep_target_regs, |
7421107b | 2237 | musb->context.index_regs[i].rxhubport); |
4f712e01 | 2238 | } |
3c5fec75 | 2239 | musb_writeb(musb_base, MUSB_INDEX, musb->context.index); |
4f712e01 AKG |
2240 | } |
2241 | ||
48fea965 | 2242 | static int musb_suspend(struct device *dev) |
550a7375 | 2243 | { |
8220796d | 2244 | struct musb *musb = dev_to_musb(dev); |
550a7375 | 2245 | unsigned long flags; |
550a7375 | 2246 | |
550a7375 FB |
2247 | spin_lock_irqsave(&musb->lock, flags); |
2248 | ||
2249 | if (is_peripheral_active(musb)) { | |
2250 | /* FIXME force disconnect unless we know USB will wake | |
2251 | * the system up quickly enough to respond ... | |
2252 | */ | |
2253 | } else if (is_host_active(musb)) { | |
2254 | /* we know all the children are suspended; sometimes | |
2255 | * they will even be wakeup-enabled. | |
2256 | */ | |
2257 | } | |
2258 | ||
c338412b DM |
2259 | musb_save_context(musb); |
2260 | ||
550a7375 FB |
2261 | spin_unlock_irqrestore(&musb->lock, flags); |
2262 | return 0; | |
2263 | } | |
2264 | ||
48fea965 | 2265 | static int musb_resume_noirq(struct device *dev) |
550a7375 | 2266 | { |
c338412b DM |
2267 | struct musb *musb = dev_to_musb(dev); |
2268 | ||
2269 | /* | |
2270 | * For static cmos like DaVinci, register values were preserved | |
0ec8fd70 KK |
2271 | * unless for some reason the whole soc powered down or the USB |
2272 | * module got reset through the PSC (vs just being disabled). | |
c338412b DM |
2273 | * |
2274 | * For the DSPS glue layer though, a full register restore has to | |
2275 | * be done. As it shouldn't harm other platforms, we do it | |
2276 | * unconditionally. | |
550a7375 | 2277 | */ |
c338412b DM |
2278 | |
2279 | musb_restore_context(musb); | |
2280 | ||
550a7375 FB |
2281 | return 0; |
2282 | } | |
2283 | ||
7acc6197 HH |
2284 | static int musb_runtime_suspend(struct device *dev) |
2285 | { | |
2286 | struct musb *musb = dev_to_musb(dev); | |
2287 | ||
2288 | musb_save_context(musb); | |
2289 | ||
2290 | return 0; | |
2291 | } | |
2292 | ||
2293 | static int musb_runtime_resume(struct device *dev) | |
2294 | { | |
2295 | struct musb *musb = dev_to_musb(dev); | |
2296 | static int first = 1; | |
2297 | ||
2298 | /* | |
2299 | * When pm_runtime_get_sync called for the first time in driver | |
2300 | * init, some of the structure is still not initialized which is | |
2301 | * used in restore function. But clock needs to be | |
2302 | * enabled before any register access, so | |
2303 | * pm_runtime_get_sync has to be called. | |
2304 | * Also context restore without save does not make | |
2305 | * any sense | |
2306 | */ | |
2307 | if (!first) | |
2308 | musb_restore_context(musb); | |
2309 | first = 0; | |
2310 | ||
2311 | return 0; | |
2312 | } | |
2313 | ||
47145210 | 2314 | static const struct dev_pm_ops musb_dev_pm_ops = { |
48fea965 MD |
2315 | .suspend = musb_suspend, |
2316 | .resume_noirq = musb_resume_noirq, | |
7acc6197 HH |
2317 | .runtime_suspend = musb_runtime_suspend, |
2318 | .runtime_resume = musb_runtime_resume, | |
48fea965 MD |
2319 | }; |
2320 | ||
2321 | #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) | |
550a7375 | 2322 | #else |
48fea965 | 2323 | #define MUSB_DEV_PM_OPS NULL |
550a7375 FB |
2324 | #endif |
2325 | ||
2326 | static struct platform_driver musb_driver = { | |
2327 | .driver = { | |
2328 | .name = (char *)musb_driver_name, | |
2329 | .bus = &platform_bus_type, | |
2330 | .owner = THIS_MODULE, | |
48fea965 | 2331 | .pm = MUSB_DEV_PM_OPS, |
550a7375 | 2332 | }, |
e9e8c85e | 2333 | .probe = musb_probe, |
7690417d | 2334 | .remove = musb_remove, |
550a7375 | 2335 | .shutdown = musb_shutdown, |
550a7375 FB |
2336 | }; |
2337 | ||
89f836a8 | 2338 | module_platform_driver(musb_driver); |