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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver core code | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* | |
36 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
37 | * | |
38 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
39 | * controller driver implementing the "Gadget" API; OTG support is | |
40 | * in the works. These are normal Linux-USB controller drivers which | |
41 | * use IRQs and have no dedicated thread. | |
42 | * | |
43 | * This version of the driver has only been used with products from | |
44 | * Texas Instruments. Those products integrate the Inventra logic | |
45 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
46 | * needs to be reflected in this driver. | |
47 | * | |
48 | * | |
49 | * NOTE: the original Mentor code here was pretty much a collection | |
50 | * of mechanisms that don't seem to have been fully integrated/working | |
51 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
52 | * Key open issues include: | |
53 | * | |
54 | * - Lack of host-side transaction scheduling, for all transfer types. | |
55 | * The hardware doesn't do it; instead, software must. | |
56 | * | |
57 | * This is not an issue for OTG devices that don't support external | |
58 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
59 | * "multipoint" support doesn't scale in the expected ways. That | |
60 | * includes DaVinci EVM in a common non-OTG mode. | |
61 | * | |
62 | * * Control and bulk use dedicated endpoints, and there's as | |
63 | * yet no mechanism to either (a) reclaim the hardware when | |
64 | * peripherals are NAKing, which gets complicated with bulk | |
65 | * endpoints, or (b) use more than a single bulk endpoint in | |
66 | * each direction. | |
67 | * | |
68 | * RESULT: one device may be perceived as blocking another one. | |
69 | * | |
70 | * * Interrupt and isochronous will dynamically allocate endpoint | |
71 | * hardware, but (a) there's no record keeping for bandwidth; | |
72 | * (b) in the common case that few endpoints are available, there | |
73 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
74 | * | |
75 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
76 | * some hardware configurations, no faults will be reported. | |
77 | * At the other extreme, the bandwidth capabilities which do | |
78 | * exist tend to be severely undercommitted. You can't yet hook | |
79 | * up both a keyboard and a mouse to an external USB hub. | |
80 | */ | |
81 | ||
82 | /* | |
83 | * This gets many kinds of configuration information: | |
84 | * - Kconfig for everything user-configurable | |
85 | * - <asm/arch/hdrc_cnf.h> for SOC or family details | |
86 | * - platform_device for addressing, irq, and platform_data | |
87 | * - platform_data is mostly for board-specific informarion | |
88 | * | |
89 | * Most of the conditional compilation will (someday) vanish. | |
90 | */ | |
91 | ||
92 | #include <linux/module.h> | |
93 | #include <linux/kernel.h> | |
94 | #include <linux/sched.h> | |
95 | #include <linux/slab.h> | |
96 | #include <linux/init.h> | |
97 | #include <linux/list.h> | |
98 | #include <linux/kobject.h> | |
99 | #include <linux/platform_device.h> | |
100 | #include <linux/io.h> | |
101 | ||
102 | #ifdef CONFIG_ARM | |
103 | #include <asm/arch/hardware.h> | |
104 | #include <asm/arch/memory.h> | |
105 | #include <asm/mach-types.h> | |
106 | #endif | |
107 | ||
108 | #include "musb_core.h" | |
109 | ||
110 | ||
111 | #ifdef CONFIG_ARCH_DAVINCI | |
112 | #include "davinci.h" | |
113 | #endif | |
114 | ||
115 | ||
116 | ||
117 | #if MUSB_DEBUG > 0 | |
118 | unsigned debug = MUSB_DEBUG; | |
119 | module_param(debug, uint, 0); | |
120 | MODULE_PARM_DESC(debug, "initial debug message level"); | |
121 | ||
122 | #define MUSB_VERSION_SUFFIX "/dbg" | |
123 | #endif | |
124 | ||
125 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" | |
126 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
127 | ||
128 | #define MUSB_VERSION_BASE "6.0" | |
129 | ||
130 | #ifndef MUSB_VERSION_SUFFIX | |
131 | #define MUSB_VERSION_SUFFIX "" | |
132 | #endif | |
133 | #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX | |
134 | ||
135 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
136 | ||
137 | #define MUSB_DRIVER_NAME "musb_hdrc" | |
138 | const char musb_driver_name[] = MUSB_DRIVER_NAME; | |
139 | ||
140 | MODULE_DESCRIPTION(DRIVER_INFO); | |
141 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
142 | MODULE_LICENSE("GPL"); | |
143 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
144 | ||
145 | ||
146 | /*-------------------------------------------------------------------------*/ | |
147 | ||
148 | static inline struct musb *dev_to_musb(struct device *dev) | |
149 | { | |
150 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
151 | /* usbcore insists dev->driver_data is a "struct hcd *" */ | |
152 | return hcd_to_musb(dev_get_drvdata(dev)); | |
153 | #else | |
154 | return dev_get_drvdata(dev); | |
155 | #endif | |
156 | } | |
157 | ||
158 | /*-------------------------------------------------------------------------*/ | |
159 | ||
160 | #ifndef CONFIG_USB_TUSB6010 | |
161 | /* | |
162 | * Load an endpoint's FIFO | |
163 | */ | |
164 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
165 | { | |
166 | void __iomem *fifo = hw_ep->fifo; | |
167 | ||
168 | prefetch((u8 *)src); | |
169 | ||
170 | DBG(4, "%cX ep%d fifo %p count %d buf %p\n", | |
171 | 'T', hw_ep->epnum, fifo, len, src); | |
172 | ||
173 | /* we can't assume unaligned reads work */ | |
174 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
175 | u16 index = 0; | |
176 | ||
177 | /* best case is 32bit-aligned source address */ | |
178 | if ((0x02 & (unsigned long) src) == 0) { | |
179 | if (len >= 4) { | |
180 | writesl(fifo, src + index, len >> 2); | |
181 | index += len & ~0x03; | |
182 | } | |
183 | if (len & 0x02) { | |
184 | musb_writew(fifo, 0, *(u16 *)&src[index]); | |
185 | index += 2; | |
186 | } | |
187 | } else { | |
188 | if (len >= 2) { | |
189 | writesw(fifo, src + index, len >> 1); | |
190 | index += len & ~0x01; | |
191 | } | |
192 | } | |
193 | if (len & 0x01) | |
194 | musb_writeb(fifo, 0, src[index]); | |
195 | } else { | |
196 | /* byte aligned */ | |
197 | writesb(fifo, src, len); | |
198 | } | |
199 | } | |
200 | ||
201 | /* | |
202 | * Unload an endpoint's FIFO | |
203 | */ | |
204 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
205 | { | |
206 | void __iomem *fifo = hw_ep->fifo; | |
207 | ||
208 | DBG(4, "%cX ep%d fifo %p count %d buf %p\n", | |
209 | 'R', hw_ep->epnum, fifo, len, dst); | |
210 | ||
211 | /* we can't assume unaligned writes work */ | |
212 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
213 | u16 index = 0; | |
214 | ||
215 | /* best case is 32bit-aligned destination address */ | |
216 | if ((0x02 & (unsigned long) dst) == 0) { | |
217 | if (len >= 4) { | |
218 | readsl(fifo, dst, len >> 2); | |
219 | index = len & ~0x03; | |
220 | } | |
221 | if (len & 0x02) { | |
222 | *(u16 *)&dst[index] = musb_readw(fifo, 0); | |
223 | index += 2; | |
224 | } | |
225 | } else { | |
226 | if (len >= 2) { | |
227 | readsw(fifo, dst, len >> 1); | |
228 | index = len & ~0x01; | |
229 | } | |
230 | } | |
231 | if (len & 0x01) | |
232 | dst[index] = musb_readb(fifo, 0); | |
233 | } else { | |
234 | /* byte aligned */ | |
235 | readsb(fifo, dst, len); | |
236 | } | |
237 | } | |
238 | ||
239 | #endif /* normal PIO */ | |
240 | ||
241 | ||
242 | /*-------------------------------------------------------------------------*/ | |
243 | ||
244 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
245 | static const u8 musb_test_packet[53] = { | |
246 | /* implicit SYNC then DATA0 to start */ | |
247 | ||
248 | /* JKJKJKJK x9 */ | |
249 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
250 | /* JJKKJJKK x8 */ | |
251 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
252 | /* JJJJKKKK x8 */ | |
253 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
254 | /* JJJJJJJKKKKKKK x8 */ | |
255 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
256 | /* JJJJJJJK x8 */ | |
257 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
258 | /* JKKKKKKK x10, JK */ | |
259 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
260 | ||
261 | /* implicit CRC16 then EOP to end */ | |
262 | }; | |
263 | ||
264 | void musb_load_testpacket(struct musb *musb) | |
265 | { | |
266 | void __iomem *regs = musb->endpoints[0].regs; | |
267 | ||
268 | musb_ep_select(musb->mregs, 0); | |
269 | musb_write_fifo(musb->control_ep, | |
270 | sizeof(musb_test_packet), musb_test_packet); | |
271 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
272 | } | |
273 | ||
274 | /*-------------------------------------------------------------------------*/ | |
275 | ||
276 | const char *otg_state_string(struct musb *musb) | |
277 | { | |
278 | switch (musb->xceiv.state) { | |
279 | case OTG_STATE_A_IDLE: return "a_idle"; | |
280 | case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise"; | |
281 | case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon"; | |
282 | case OTG_STATE_A_HOST: return "a_host"; | |
283 | case OTG_STATE_A_SUSPEND: return "a_suspend"; | |
284 | case OTG_STATE_A_PERIPHERAL: return "a_peripheral"; | |
285 | case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall"; | |
286 | case OTG_STATE_A_VBUS_ERR: return "a_vbus_err"; | |
287 | case OTG_STATE_B_IDLE: return "b_idle"; | |
288 | case OTG_STATE_B_SRP_INIT: return "b_srp_init"; | |
289 | case OTG_STATE_B_PERIPHERAL: return "b_peripheral"; | |
290 | case OTG_STATE_B_WAIT_ACON: return "b_wait_acon"; | |
291 | case OTG_STATE_B_HOST: return "b_host"; | |
292 | default: return "UNDEFINED"; | |
293 | } | |
294 | } | |
295 | ||
296 | #ifdef CONFIG_USB_MUSB_OTG | |
297 | ||
298 | /* | |
299 | * See also USB_OTG_1-3.pdf 6.6.5 Timers | |
300 | * REVISIT: Are the other timers done in the hardware? | |
301 | */ | |
302 | #define TB_ASE0_BRST 100 /* Min 3.125 ms */ | |
303 | ||
304 | /* | |
305 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
306 | */ | |
307 | void musb_otg_timer_func(unsigned long data) | |
308 | { | |
309 | struct musb *musb = (struct musb *)data; | |
310 | unsigned long flags; | |
311 | ||
312 | spin_lock_irqsave(&musb->lock, flags); | |
313 | switch (musb->xceiv.state) { | |
314 | case OTG_STATE_B_WAIT_ACON: | |
315 | DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n"); | |
316 | musb_g_disconnect(musb); | |
317 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
318 | musb->is_active = 0; | |
319 | break; | |
320 | case OTG_STATE_A_WAIT_BCON: | |
321 | DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n"); | |
322 | musb_hnp_stop(musb); | |
323 | break; | |
324 | default: | |
325 | DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb)); | |
326 | } | |
327 | musb->ignore_disconnect = 0; | |
328 | spin_unlock_irqrestore(&musb->lock, flags); | |
329 | } | |
330 | ||
331 | static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0); | |
332 | ||
333 | /* | |
334 | * Stops the B-device HNP state. Caller must take care of locking. | |
335 | */ | |
336 | void musb_hnp_stop(struct musb *musb) | |
337 | { | |
338 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
339 | void __iomem *mbase = musb->mregs; | |
340 | u8 reg; | |
341 | ||
342 | switch (musb->xceiv.state) { | |
343 | case OTG_STATE_A_PERIPHERAL: | |
344 | case OTG_STATE_A_WAIT_VFALL: | |
345 | case OTG_STATE_A_WAIT_BCON: | |
346 | DBG(1, "HNP: Switching back to A-host\n"); | |
347 | musb_g_disconnect(musb); | |
348 | musb->xceiv.state = OTG_STATE_A_IDLE; | |
349 | MUSB_HST_MODE(musb); | |
350 | musb->is_active = 0; | |
351 | break; | |
352 | case OTG_STATE_B_HOST: | |
353 | DBG(1, "HNP: Disabling HR\n"); | |
354 | hcd->self.is_b_host = 0; | |
355 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
356 | MUSB_DEV_MODE(musb); | |
357 | reg = musb_readb(mbase, MUSB_POWER); | |
358 | reg |= MUSB_POWER_SUSPENDM; | |
359 | musb_writeb(mbase, MUSB_POWER, reg); | |
360 | /* REVISIT: Start SESSION_REQUEST here? */ | |
361 | break; | |
362 | default: | |
363 | DBG(1, "HNP: Stopping in unknown state %s\n", | |
364 | otg_state_string(musb)); | |
365 | } | |
366 | ||
367 | /* | |
368 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
369 | * which cause occasional OPT A "Did not receive reset after connect" | |
370 | * errors. | |
371 | */ | |
372 | musb->port1_status &= | |
373 | ~(1 << USB_PORT_FEAT_C_CONNECTION); | |
374 | } | |
375 | ||
376 | #endif | |
377 | ||
378 | /* | |
379 | * Interrupt Service Routine to record USB "global" interrupts. | |
380 | * Since these do not happen often and signify things of | |
381 | * paramount importance, it seems OK to check them individually; | |
382 | * the order of the tests is specified in the manual | |
383 | * | |
384 | * @param musb instance pointer | |
385 | * @param int_usb register contents | |
386 | * @param devctl | |
387 | * @param power | |
388 | */ | |
389 | ||
390 | #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \ | |
391 | | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \ | |
392 | | MUSB_INTR_RESET) | |
393 | ||
394 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, | |
395 | u8 devctl, u8 power) | |
396 | { | |
397 | irqreturn_t handled = IRQ_NONE; | |
398 | void __iomem *mbase = musb->mregs; | |
399 | ||
400 | DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, | |
401 | int_usb); | |
402 | ||
403 | /* in host mode, the peripheral may issue remote wakeup. | |
404 | * in peripheral mode, the host may resume the link. | |
405 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
406 | */ | |
407 | if (int_usb & MUSB_INTR_RESUME) { | |
408 | handled = IRQ_HANDLED; | |
409 | DBG(3, "RESUME (%s)\n", otg_state_string(musb)); | |
410 | ||
411 | if (devctl & MUSB_DEVCTL_HM) { | |
412 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
413 | switch (musb->xceiv.state) { | |
414 | case OTG_STATE_A_SUSPEND: | |
415 | /* remote wakeup? later, GetPortStatus | |
416 | * will stop RESUME signaling | |
417 | */ | |
418 | ||
419 | if (power & MUSB_POWER_SUSPENDM) { | |
420 | /* spurious */ | |
421 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
422 | DBG(2, "Spurious SUSPENDM\n"); | |
423 | break; | |
424 | } | |
425 | ||
426 | power &= ~MUSB_POWER_SUSPENDM; | |
427 | musb_writeb(mbase, MUSB_POWER, | |
428 | power | MUSB_POWER_RESUME); | |
429 | ||
430 | musb->port1_status |= | |
431 | (USB_PORT_STAT_C_SUSPEND << 16) | |
432 | | MUSB_PORT_STAT_RESUME; | |
433 | musb->rh_timer = jiffies | |
434 | + msecs_to_jiffies(20); | |
435 | ||
436 | musb->xceiv.state = OTG_STATE_A_HOST; | |
437 | musb->is_active = 1; | |
438 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
439 | break; | |
440 | case OTG_STATE_B_WAIT_ACON: | |
441 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
442 | musb->is_active = 1; | |
443 | MUSB_DEV_MODE(musb); | |
444 | break; | |
445 | default: | |
446 | WARNING("bogus %s RESUME (%s)\n", | |
447 | "host", | |
448 | otg_state_string(musb)); | |
449 | } | |
450 | #endif | |
451 | } else { | |
452 | switch (musb->xceiv.state) { | |
453 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
454 | case OTG_STATE_A_SUSPEND: | |
455 | /* possibly DISCONNECT is upcoming */ | |
456 | musb->xceiv.state = OTG_STATE_A_HOST; | |
457 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
458 | break; | |
459 | #endif | |
460 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
461 | case OTG_STATE_B_WAIT_ACON: | |
462 | case OTG_STATE_B_PERIPHERAL: | |
463 | /* disconnect while suspended? we may | |
464 | * not get a disconnect irq... | |
465 | */ | |
466 | if ((devctl & MUSB_DEVCTL_VBUS) | |
467 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
468 | ) { | |
469 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
470 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
471 | break; | |
472 | } | |
473 | musb_g_resume(musb); | |
474 | break; | |
475 | case OTG_STATE_B_IDLE: | |
476 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
477 | break; | |
478 | #endif | |
479 | default: | |
480 | WARNING("bogus %s RESUME (%s)\n", | |
481 | "peripheral", | |
482 | otg_state_string(musb)); | |
483 | } | |
484 | } | |
485 | } | |
486 | ||
487 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
488 | /* see manual for the order of the tests */ | |
489 | if (int_usb & MUSB_INTR_SESSREQ) { | |
490 | DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb)); | |
491 | ||
492 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
493 | * is removed) SRP. responses are time critical: | |
494 | * - turn on VBUS (with silicon-specific mechanism) | |
495 | * - go through A_WAIT_VRISE | |
496 | * - ... to A_WAIT_BCON. | |
497 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
498 | */ | |
499 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
500 | musb->ep0_stage = MUSB_EP0_START; | |
501 | musb->xceiv.state = OTG_STATE_A_IDLE; | |
502 | MUSB_HST_MODE(musb); | |
503 | musb_set_vbus(musb, 1); | |
504 | ||
505 | handled = IRQ_HANDLED; | |
506 | } | |
507 | ||
508 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
509 | int ignore = 0; | |
510 | ||
511 | /* During connection as an A-Device, we may see a short | |
512 | * current spikes causing voltage drop, because of cable | |
513 | * and peripheral capacitance combined with vbus draw. | |
514 | * (So: less common with truly self-powered devices, where | |
515 | * vbus doesn't act like a power supply.) | |
516 | * | |
517 | * Such spikes are short; usually less than ~500 usec, max | |
518 | * of ~2 msec. That is, they're not sustained overcurrent | |
519 | * errors, though they're reported using VBUSERROR irqs. | |
520 | * | |
521 | * Workarounds: (a) hardware: use self powered devices. | |
522 | * (b) software: ignore non-repeated VBUS errors. | |
523 | * | |
524 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
525 | * make trouble here, keeping VBUS < 4.4V ? | |
526 | */ | |
527 | switch (musb->xceiv.state) { | |
528 | case OTG_STATE_A_HOST: | |
529 | /* recovery is dicey once we've gotten past the | |
530 | * initial stages of enumeration, but if VBUS | |
531 | * stayed ok at the other end of the link, and | |
532 | * another reset is due (at least for high speed, | |
533 | * to redo the chirp etc), it might work OK... | |
534 | */ | |
535 | case OTG_STATE_A_WAIT_BCON: | |
536 | case OTG_STATE_A_WAIT_VRISE: | |
537 | if (musb->vbuserr_retry) { | |
538 | musb->vbuserr_retry--; | |
539 | ignore = 1; | |
540 | devctl |= MUSB_DEVCTL_SESSION; | |
541 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
542 | } else { | |
543 | musb->port1_status |= | |
544 | (1 << USB_PORT_FEAT_OVER_CURRENT) | |
545 | | (1 << USB_PORT_FEAT_C_OVER_CURRENT); | |
546 | } | |
547 | break; | |
548 | default: | |
549 | break; | |
550 | } | |
551 | ||
552 | DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", | |
553 | otg_state_string(musb), | |
554 | devctl, | |
555 | ({ char *s; | |
556 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
557 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
558 | s = "<SessEnd"; break; | |
559 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
560 | s = "<AValid"; break; | |
561 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
562 | s = "<VBusValid"; break; | |
563 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
564 | default: | |
565 | s = "VALID"; break; | |
566 | }; s; }), | |
567 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, | |
568 | musb->port1_status); | |
569 | ||
570 | /* go through A_WAIT_VFALL then start a new session */ | |
571 | if (!ignore) | |
572 | musb_set_vbus(musb, 0); | |
573 | handled = IRQ_HANDLED; | |
574 | } | |
575 | ||
576 | if (int_usb & MUSB_INTR_CONNECT) { | |
577 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
578 | ||
579 | handled = IRQ_HANDLED; | |
580 | musb->is_active = 1; | |
581 | set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); | |
582 | ||
583 | musb->ep0_stage = MUSB_EP0_START; | |
584 | ||
585 | #ifdef CONFIG_USB_MUSB_OTG | |
586 | /* flush endpoints when transitioning from Device Mode */ | |
587 | if (is_peripheral_active(musb)) { | |
588 | /* REVISIT HNP; just force disconnect */ | |
589 | } | |
590 | musb_writew(mbase, MUSB_INTRTXE, musb->epmask); | |
591 | musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
592 | musb_writeb(mbase, MUSB_INTRUSBE, 0xf7); | |
593 | #endif | |
594 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED | |
595 | |USB_PORT_STAT_HIGH_SPEED | |
596 | |USB_PORT_STAT_ENABLE | |
597 | ); | |
598 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
599 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
600 | ||
601 | /* high vs full speed is just a guess until after reset */ | |
602 | if (devctl & MUSB_DEVCTL_LSDEV) | |
603 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
604 | ||
605 | if (hcd->status_urb) | |
606 | usb_hcd_poll_rh_status(hcd); | |
607 | else | |
608 | usb_hcd_resume_root_hub(hcd); | |
609 | ||
610 | MUSB_HST_MODE(musb); | |
611 | ||
612 | /* indicate new connection to OTG machine */ | |
613 | switch (musb->xceiv.state) { | |
614 | case OTG_STATE_B_PERIPHERAL: | |
615 | if (int_usb & MUSB_INTR_SUSPEND) { | |
616 | DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n"); | |
617 | musb->xceiv.state = OTG_STATE_B_HOST; | |
618 | hcd->self.is_b_host = 1; | |
619 | int_usb &= ~MUSB_INTR_SUSPEND; | |
620 | } else | |
621 | DBG(1, "CONNECT as b_peripheral???\n"); | |
622 | break; | |
623 | case OTG_STATE_B_WAIT_ACON: | |
624 | DBG(1, "HNP: Waiting to switch to b_host state\n"); | |
625 | musb->xceiv.state = OTG_STATE_B_HOST; | |
626 | hcd->self.is_b_host = 1; | |
627 | break; | |
628 | default: | |
629 | if ((devctl & MUSB_DEVCTL_VBUS) | |
630 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
631 | musb->xceiv.state = OTG_STATE_A_HOST; | |
632 | hcd->self.is_b_host = 0; | |
633 | } | |
634 | break; | |
635 | } | |
636 | DBG(1, "CONNECT (%s) devctl %02x\n", | |
637 | otg_state_string(musb), devctl); | |
638 | } | |
639 | #endif /* CONFIG_USB_MUSB_HDRC_HCD */ | |
640 | ||
641 | /* mentor saves a bit: bus reset and babble share the same irq. | |
642 | * only host sees babble; only peripheral sees bus reset. | |
643 | */ | |
644 | if (int_usb & MUSB_INTR_RESET) { | |
645 | if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { | |
646 | /* | |
647 | * Looks like non-HS BABBLE can be ignored, but | |
648 | * HS BABBLE is an error condition. For HS the solution | |
649 | * is to avoid babble in the first place and fix what | |
650 | * caused BABBLE. When HS BABBLE happens we can only | |
651 | * stop the session. | |
652 | */ | |
653 | if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) | |
654 | DBG(1, "BABBLE devctl: %02x\n", devctl); | |
655 | else { | |
656 | ERR("Stopping host session -- babble\n"); | |
657 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
658 | } | |
659 | } else if (is_peripheral_capable()) { | |
660 | DBG(1, "BUS RESET as %s\n", otg_state_string(musb)); | |
661 | switch (musb->xceiv.state) { | |
662 | #ifdef CONFIG_USB_OTG | |
663 | case OTG_STATE_A_SUSPEND: | |
664 | /* We need to ignore disconnect on suspend | |
665 | * otherwise tusb 2.0 won't reconnect after a | |
666 | * power cycle, which breaks otg compliance. | |
667 | */ | |
668 | musb->ignore_disconnect = 1; | |
669 | musb_g_reset(musb); | |
670 | /* FALLTHROUGH */ | |
671 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
672 | DBG(1, "HNP: Setting timer as %s\n", | |
673 | otg_state_string(musb)); | |
674 | musb_otg_timer.data = (unsigned long)musb; | |
675 | mod_timer(&musb_otg_timer, jiffies | |
676 | + msecs_to_jiffies(100)); | |
677 | break; | |
678 | case OTG_STATE_A_PERIPHERAL: | |
679 | musb_hnp_stop(musb); | |
680 | break; | |
681 | case OTG_STATE_B_WAIT_ACON: | |
682 | DBG(1, "HNP: RESET (%s), to b_peripheral\n", | |
683 | otg_state_string(musb)); | |
684 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
685 | musb_g_reset(musb); | |
686 | break; | |
687 | #endif | |
688 | case OTG_STATE_B_IDLE: | |
689 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
690 | /* FALLTHROUGH */ | |
691 | case OTG_STATE_B_PERIPHERAL: | |
692 | musb_g_reset(musb); | |
693 | break; | |
694 | default: | |
695 | DBG(1, "Unhandled BUS RESET as %s\n", | |
696 | otg_state_string(musb)); | |
697 | } | |
698 | } | |
699 | ||
700 | handled = IRQ_HANDLED; | |
701 | } | |
702 | schedule_work(&musb->irq_work); | |
703 | ||
704 | return handled; | |
705 | } | |
706 | ||
707 | /* | |
708 | * Interrupt Service Routine to record USB "global" interrupts. | |
709 | * Since these do not happen often and signify things of | |
710 | * paramount importance, it seems OK to check them individually; | |
711 | * the order of the tests is specified in the manual | |
712 | * | |
713 | * @param musb instance pointer | |
714 | * @param int_usb register contents | |
715 | * @param devctl | |
716 | * @param power | |
717 | */ | |
718 | static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb, | |
719 | u8 devctl, u8 power) | |
720 | { | |
721 | irqreturn_t handled = IRQ_NONE; | |
722 | ||
723 | #if 0 | |
724 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
725 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
726 | * limits of a given frame or microframe. | |
727 | * | |
728 | * It's not needed for peripheral side, which dedicates endpoints; | |
729 | * though it _might_ use SOF irqs for other purposes. | |
730 | * | |
731 | * And it's not currently needed for host side, which also dedicates | |
732 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
733 | * to support ISO transfers yet. | |
734 | */ | |
735 | if (int_usb & MUSB_INTR_SOF) { | |
736 | void __iomem *mbase = musb->mregs; | |
737 | struct musb_hw_ep *ep; | |
738 | u8 epnum; | |
739 | u16 frame; | |
740 | ||
741 | DBG(6, "START_OF_FRAME\n"); | |
742 | handled = IRQ_HANDLED; | |
743 | ||
744 | /* start any periodic Tx transfers waiting for current frame */ | |
745 | frame = musb_readw(mbase, MUSB_FRAME); | |
746 | ep = musb->endpoints; | |
747 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
748 | && (musb->epmask >= (1 << epnum)); | |
749 | epnum++, ep++) { | |
750 | /* | |
751 | * FIXME handle framecounter wraps (12 bits) | |
752 | * eliminate duplicated StartUrb logic | |
753 | */ | |
754 | if (ep->dwWaitFrame >= frame) { | |
755 | ep->dwWaitFrame = 0; | |
756 | pr_debug("SOF --> periodic TX%s on %d\n", | |
757 | ep->tx_channel ? " DMA" : "", | |
758 | epnum); | |
759 | if (!ep->tx_channel) | |
760 | musb_h_tx_start(musb, epnum); | |
761 | else | |
762 | cppi_hostdma_start(musb, epnum); | |
763 | } | |
764 | } /* end of for loop */ | |
765 | } | |
766 | #endif | |
767 | ||
768 | if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { | |
769 | DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n", | |
770 | otg_state_string(musb), | |
771 | MUSB_MODE(musb), devctl); | |
772 | handled = IRQ_HANDLED; | |
773 | ||
774 | switch (musb->xceiv.state) { | |
775 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
776 | case OTG_STATE_A_HOST: | |
777 | case OTG_STATE_A_SUSPEND: | |
778 | musb_root_disconnect(musb); | |
779 | if (musb->a_wait_bcon != 0) | |
780 | musb_platform_try_idle(musb, jiffies | |
781 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
782 | break; | |
783 | #endif /* HOST */ | |
784 | #ifdef CONFIG_USB_MUSB_OTG | |
785 | case OTG_STATE_B_HOST: | |
786 | musb_hnp_stop(musb); | |
787 | break; | |
788 | case OTG_STATE_A_PERIPHERAL: | |
789 | musb_hnp_stop(musb); | |
790 | musb_root_disconnect(musb); | |
791 | /* FALLTHROUGH */ | |
792 | case OTG_STATE_B_WAIT_ACON: | |
793 | /* FALLTHROUGH */ | |
794 | #endif /* OTG */ | |
795 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
796 | case OTG_STATE_B_PERIPHERAL: | |
797 | case OTG_STATE_B_IDLE: | |
798 | musb_g_disconnect(musb); | |
799 | break; | |
800 | #endif /* GADGET */ | |
801 | default: | |
802 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
803 | otg_state_string(musb)); | |
804 | break; | |
805 | } | |
806 | ||
807 | schedule_work(&musb->irq_work); | |
808 | } | |
809 | ||
810 | if (int_usb & MUSB_INTR_SUSPEND) { | |
811 | DBG(1, "SUSPEND (%s) devctl %02x power %02x\n", | |
812 | otg_state_string(musb), devctl, power); | |
813 | handled = IRQ_HANDLED; | |
814 | ||
815 | switch (musb->xceiv.state) { | |
816 | #ifdef CONFIG_USB_MUSB_OTG | |
817 | case OTG_STATE_A_PERIPHERAL: | |
818 | /* | |
819 | * We cannot stop HNP here, devctl BDEVICE might be | |
820 | * still set. | |
821 | */ | |
822 | break; | |
823 | #endif | |
824 | case OTG_STATE_B_PERIPHERAL: | |
825 | musb_g_suspend(musb); | |
826 | musb->is_active = is_otg_enabled(musb) | |
827 | && musb->xceiv.gadget->b_hnp_enable; | |
828 | if (musb->is_active) { | |
829 | #ifdef CONFIG_USB_MUSB_OTG | |
830 | musb->xceiv.state = OTG_STATE_B_WAIT_ACON; | |
831 | DBG(1, "HNP: Setting timer for b_ase0_brst\n"); | |
832 | musb_otg_timer.data = (unsigned long)musb; | |
833 | mod_timer(&musb_otg_timer, jiffies | |
834 | + msecs_to_jiffies(TB_ASE0_BRST)); | |
835 | #endif | |
836 | } | |
837 | break; | |
838 | case OTG_STATE_A_WAIT_BCON: | |
839 | if (musb->a_wait_bcon != 0) | |
840 | musb_platform_try_idle(musb, jiffies | |
841 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
842 | break; | |
843 | case OTG_STATE_A_HOST: | |
844 | musb->xceiv.state = OTG_STATE_A_SUSPEND; | |
845 | musb->is_active = is_otg_enabled(musb) | |
846 | && musb->xceiv.host->b_hnp_enable; | |
847 | break; | |
848 | case OTG_STATE_B_HOST: | |
849 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
850 | DBG(1, "REVISIT: SUSPEND as B_HOST\n"); | |
851 | break; | |
852 | default: | |
853 | /* "should not happen" */ | |
854 | musb->is_active = 0; | |
855 | break; | |
856 | } | |
857 | schedule_work(&musb->irq_work); | |
858 | } | |
859 | ||
860 | ||
861 | return handled; | |
862 | } | |
863 | ||
864 | /*-------------------------------------------------------------------------*/ | |
865 | ||
866 | /* | |
867 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
868 | */ | |
869 | void musb_start(struct musb *musb) | |
870 | { | |
871 | void __iomem *regs = musb->mregs; | |
872 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
873 | ||
874 | DBG(2, "<== devctl %02x\n", devctl); | |
875 | ||
876 | /* Set INT enable registers, enable interrupts */ | |
877 | musb_writew(regs, MUSB_INTRTXE, musb->epmask); | |
878 | musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
879 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); | |
880 | ||
881 | musb_writeb(regs, MUSB_TESTMODE, 0); | |
882 | ||
883 | /* put into basic highspeed mode and start session */ | |
884 | musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE | |
885 | | MUSB_POWER_SOFTCONN | |
886 | | MUSB_POWER_HSENAB | |
887 | /* ENSUSPEND wedges tusb */ | |
888 | /* | MUSB_POWER_ENSUSPEND */ | |
889 | ); | |
890 | ||
891 | musb->is_active = 0; | |
892 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
893 | devctl &= ~MUSB_DEVCTL_SESSION; | |
894 | ||
895 | if (is_otg_enabled(musb)) { | |
896 | /* session started after: | |
897 | * (a) ID-grounded irq, host mode; | |
898 | * (b) vbus present/connect IRQ, peripheral mode; | |
899 | * (c) peripheral initiates, using SRP | |
900 | */ | |
901 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
902 | musb->is_active = 1; | |
903 | else | |
904 | devctl |= MUSB_DEVCTL_SESSION; | |
905 | ||
906 | } else if (is_host_enabled(musb)) { | |
907 | /* assume ID pin is hard-wired to ground */ | |
908 | devctl |= MUSB_DEVCTL_SESSION; | |
909 | ||
910 | } else /* peripheral is enabled */ { | |
911 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
912 | musb->is_active = 1; | |
913 | } | |
914 | musb_platform_enable(musb); | |
915 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
916 | } | |
917 | ||
918 | ||
919 | static void musb_generic_disable(struct musb *musb) | |
920 | { | |
921 | void __iomem *mbase = musb->mregs; | |
922 | u16 temp; | |
923 | ||
924 | /* disable interrupts */ | |
925 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
926 | musb_writew(mbase, MUSB_INTRTXE, 0); | |
927 | musb_writew(mbase, MUSB_INTRRXE, 0); | |
928 | ||
929 | /* off */ | |
930 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
931 | ||
932 | /* flush pending interrupts */ | |
933 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
934 | temp = musb_readw(mbase, MUSB_INTRTX); | |
935 | temp = musb_readw(mbase, MUSB_INTRRX); | |
936 | ||
937 | } | |
938 | ||
939 | /* | |
940 | * Make the HDRC stop (disable interrupts, etc.); | |
941 | * reversible by musb_start | |
942 | * called on gadget driver unregister | |
943 | * with controller locked, irqs blocked | |
944 | * acts as a NOP unless some role activated the hardware | |
945 | */ | |
946 | void musb_stop(struct musb *musb) | |
947 | { | |
948 | /* stop IRQs, timers, ... */ | |
949 | musb_platform_disable(musb); | |
950 | musb_generic_disable(musb); | |
951 | DBG(3, "HDRC disabled\n"); | |
952 | ||
953 | /* FIXME | |
954 | * - mark host and/or peripheral drivers unusable/inactive | |
955 | * - disable DMA (and enable it in HdrcStart) | |
956 | * - make sure we can musb_start() after musb_stop(); with | |
957 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
958 | * - ... | |
959 | */ | |
960 | musb_platform_try_idle(musb, 0); | |
961 | } | |
962 | ||
963 | static void musb_shutdown(struct platform_device *pdev) | |
964 | { | |
965 | struct musb *musb = dev_to_musb(&pdev->dev); | |
966 | unsigned long flags; | |
967 | ||
968 | spin_lock_irqsave(&musb->lock, flags); | |
969 | musb_platform_disable(musb); | |
970 | musb_generic_disable(musb); | |
971 | if (musb->clock) { | |
972 | clk_put(musb->clock); | |
973 | musb->clock = NULL; | |
974 | } | |
975 | spin_unlock_irqrestore(&musb->lock, flags); | |
976 | ||
977 | /* FIXME power down */ | |
978 | } | |
979 | ||
980 | ||
981 | /*-------------------------------------------------------------------------*/ | |
982 | ||
983 | /* | |
984 | * The silicon either has hard-wired endpoint configurations, or else | |
985 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
986 | * writing only the dynamic sizing is very well tested. We use normal | |
987 | * idioms to so both modes are compile-tested, but dead code elimination | |
988 | * leaves only the relevant one in the object file. | |
989 | * | |
990 | * We don't currently use dynamic fifo setup capability to do anything | |
991 | * more than selecting one of a bunch of predefined configurations. | |
992 | */ | |
550a7375 FB |
993 | #if defined(CONFIG_USB_TUSB6010) || \ |
994 | defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) | |
995 | static ushort __initdata fifo_mode = 4; | |
996 | #else | |
997 | static ushort __initdata fifo_mode = 2; | |
998 | #endif | |
999 | ||
1000 | /* "modprobe ... fifo_mode=1" etc */ | |
1001 | module_param(fifo_mode, ushort, 0); | |
1002 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
1003 | ||
1004 | ||
550a7375 FB |
1005 | enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed)); |
1006 | enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed)); | |
1007 | ||
1008 | struct fifo_cfg { | |
1009 | u8 hw_ep_num; | |
1010 | enum fifo_style style; | |
1011 | enum buf_mode mode; | |
1012 | u16 maxpacket; | |
1013 | }; | |
1014 | ||
1015 | /* | |
1016 | * tables defining fifo_mode values. define more if you like. | |
1017 | * for host side, make sure both halves of ep1 are set up. | |
1018 | */ | |
1019 | ||
1020 | /* mode 0 - fits in 2KB */ | |
1021 | static struct fifo_cfg __initdata mode_0_cfg[] = { | |
1022 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, | |
1023 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1024 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1025 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1026 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1027 | }; | |
1028 | ||
1029 | /* mode 1 - fits in 4KB */ | |
1030 | static struct fifo_cfg __initdata mode_1_cfg[] = { | |
1031 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1032 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1033 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1034 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1035 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1036 | }; | |
1037 | ||
1038 | /* mode 2 - fits in 4KB */ | |
1039 | static struct fifo_cfg __initdata mode_2_cfg[] = { | |
1040 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, | |
1041 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1042 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1043 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1044 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1045 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1046 | }; | |
1047 | ||
1048 | /* mode 3 - fits in 4KB */ | |
1049 | static struct fifo_cfg __initdata mode_3_cfg[] = { | |
1050 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1051 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1052 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1053 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1054 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1055 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1056 | }; | |
1057 | ||
1058 | /* mode 4 - fits in 16KB */ | |
1059 | static struct fifo_cfg __initdata mode_4_cfg[] = { | |
1060 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, | |
1061 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1062 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1063 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1064 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1065 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1066 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1067 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1068 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1069 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1070 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1071 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1072 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1073 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1074 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1075 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1076 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1077 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
1078 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, }, | |
1079 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, }, | |
1080 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, }, | |
1081 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, }, | |
1082 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, }, | |
1083 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, }, | |
1084 | { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, }, | |
1085 | { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, }, | |
1086 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1087 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1088 | }; | |
1089 | ||
1090 | ||
1091 | /* | |
1092 | * configure a fifo; for non-shared endpoints, this may be called | |
1093 | * once for a tx fifo and once for an rx fifo. | |
1094 | * | |
1095 | * returns negative errno or offset for next fifo. | |
1096 | */ | |
1097 | static int __init | |
1098 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, | |
1099 | const struct fifo_cfg *cfg, u16 offset) | |
1100 | { | |
1101 | void __iomem *mbase = musb->mregs; | |
1102 | int size = 0; | |
1103 | u16 maxpacket = cfg->maxpacket; | |
1104 | u16 c_off = offset >> 3; | |
1105 | u8 c_size; | |
1106 | ||
1107 | /* expect hw_ep has already been zero-initialized */ | |
1108 | ||
1109 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1110 | maxpacket = 1 << size; | |
1111 | ||
1112 | c_size = size - 3; | |
1113 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1114 | if ((offset + (maxpacket << 1)) > |
1115 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1116 | return -EMSGSIZE; |
1117 | c_size |= MUSB_FIFOSZ_DPB; | |
1118 | } else { | |
ca6d1b13 | 1119 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1120 | return -EMSGSIZE; |
1121 | } | |
1122 | ||
1123 | /* configure the FIFO */ | |
1124 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1125 | ||
1126 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1127 | /* EP0 reserved endpoint for control, bidirectional; | |
1128 | * EP1 reserved for bulk, two unidirection halves. | |
1129 | */ | |
1130 | if (hw_ep->epnum == 1) | |
1131 | musb->bulk_ep = hw_ep; | |
1132 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
1133 | #endif | |
1134 | switch (cfg->style) { | |
1135 | case FIFO_TX: | |
1136 | musb_writeb(mbase, MUSB_TXFIFOSZ, c_size); | |
1137 | musb_writew(mbase, MUSB_TXFIFOADD, c_off); | |
1138 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); | |
1139 | hw_ep->max_packet_sz_tx = maxpacket; | |
1140 | break; | |
1141 | case FIFO_RX: | |
1142 | musb_writeb(mbase, MUSB_RXFIFOSZ, c_size); | |
1143 | musb_writew(mbase, MUSB_RXFIFOADD, c_off); | |
1144 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); | |
1145 | hw_ep->max_packet_sz_rx = maxpacket; | |
1146 | break; | |
1147 | case FIFO_RXTX: | |
1148 | musb_writeb(mbase, MUSB_TXFIFOSZ, c_size); | |
1149 | musb_writew(mbase, MUSB_TXFIFOADD, c_off); | |
1150 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); | |
1151 | hw_ep->max_packet_sz_rx = maxpacket; | |
1152 | ||
1153 | musb_writeb(mbase, MUSB_RXFIFOSZ, c_size); | |
1154 | musb_writew(mbase, MUSB_RXFIFOADD, c_off); | |
1155 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; | |
1156 | hw_ep->max_packet_sz_tx = maxpacket; | |
1157 | ||
1158 | hw_ep->is_shared_fifo = true; | |
1159 | break; | |
1160 | } | |
1161 | ||
1162 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1163 | * which happens to be ok | |
1164 | */ | |
1165 | musb->epmask |= (1 << hw_ep->epnum); | |
1166 | ||
1167 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1168 | } | |
1169 | ||
1170 | static struct fifo_cfg __initdata ep0_cfg = { | |
1171 | .style = FIFO_RXTX, .maxpacket = 64, | |
1172 | }; | |
1173 | ||
1174 | static int __init ep_config_from_table(struct musb *musb) | |
1175 | { | |
1176 | const struct fifo_cfg *cfg; | |
1177 | unsigned i, n; | |
1178 | int offset; | |
1179 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1180 | ||
1181 | switch (fifo_mode) { | |
1182 | default: | |
1183 | fifo_mode = 0; | |
1184 | /* FALLTHROUGH */ | |
1185 | case 0: | |
1186 | cfg = mode_0_cfg; | |
1187 | n = ARRAY_SIZE(mode_0_cfg); | |
1188 | break; | |
1189 | case 1: | |
1190 | cfg = mode_1_cfg; | |
1191 | n = ARRAY_SIZE(mode_1_cfg); | |
1192 | break; | |
1193 | case 2: | |
1194 | cfg = mode_2_cfg; | |
1195 | n = ARRAY_SIZE(mode_2_cfg); | |
1196 | break; | |
1197 | case 3: | |
1198 | cfg = mode_3_cfg; | |
1199 | n = ARRAY_SIZE(mode_3_cfg); | |
1200 | break; | |
1201 | case 4: | |
1202 | cfg = mode_4_cfg; | |
1203 | n = ARRAY_SIZE(mode_4_cfg); | |
1204 | break; | |
1205 | } | |
1206 | ||
1207 | printk(KERN_DEBUG "%s: setup fifo_mode %d\n", | |
1208 | musb_driver_name, fifo_mode); | |
1209 | ||
1210 | ||
1211 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); | |
1212 | /* assert(offset > 0) */ | |
1213 | ||
1214 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1215 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1216 | */ |
1217 | ||
1218 | for (i = 0; i < n; i++) { | |
1219 | u8 epn = cfg->hw_ep_num; | |
1220 | ||
ca6d1b13 | 1221 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1222 | pr_debug("%s: invalid ep %d\n", |
1223 | musb_driver_name, epn); | |
1224 | continue; | |
1225 | } | |
1226 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1227 | if (offset < 0) { | |
1228 | pr_debug("%s: mem overrun, ep %d\n", | |
1229 | musb_driver_name, epn); | |
1230 | return -EINVAL; | |
1231 | } | |
1232 | epn++; | |
1233 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1234 | } | |
1235 | ||
1236 | printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", | |
1237 | musb_driver_name, | |
ca6d1b13 FB |
1238 | n + 1, musb->config->num_eps * 2 - 1, |
1239 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 FB |
1240 | |
1241 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1242 | if (!musb->bulk_ep) { | |
1243 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1244 | return -EINVAL; | |
1245 | } | |
1246 | #endif | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
1251 | ||
1252 | /* | |
1253 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1254 | * @param musb the controller | |
1255 | */ | |
1256 | static int __init ep_config_from_hw(struct musb *musb) | |
1257 | { | |
1258 | u8 epnum = 0, reg; | |
1259 | struct musb_hw_ep *hw_ep; | |
1260 | void *mbase = musb->mregs; | |
1261 | ||
1262 | DBG(2, "<== static silicon ep config\n"); | |
1263 | ||
1264 | /* FIXME pick up ep0 maxpacket size */ | |
1265 | ||
ca6d1b13 | 1266 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1267 | musb_ep_select(mbase, epnum); |
1268 | hw_ep = musb->endpoints + epnum; | |
1269 | ||
1270 | /* read from core using indexed model */ | |
1271 | reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE); | |
1272 | if (!reg) { | |
1273 | /* 0's returned when no more endpoints */ | |
1274 | break; | |
1275 | } | |
1276 | musb->nr_endpoints++; | |
1277 | musb->epmask |= (1 << epnum); | |
1278 | ||
1279 | hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f); | |
1280 | ||
1281 | /* shared TX/RX FIFO? */ | |
1282 | if ((reg & 0xf0) == 0xf0) { | |
1283 | hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx; | |
1284 | hw_ep->is_shared_fifo = true; | |
1285 | continue; | |
1286 | } else { | |
1287 | hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4); | |
1288 | hw_ep->is_shared_fifo = false; | |
1289 | } | |
1290 | ||
1291 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1292 | ||
1293 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1294 | /* pick an RX/TX endpoint for bulk */ | |
1295 | if (hw_ep->max_packet_sz_tx < 512 | |
1296 | || hw_ep->max_packet_sz_rx < 512) | |
1297 | continue; | |
1298 | ||
1299 | /* REVISIT: this algorithm is lazy, we should at least | |
1300 | * try to pick a double buffered endpoint. | |
1301 | */ | |
1302 | if (musb->bulk_ep) | |
1303 | continue; | |
1304 | musb->bulk_ep = hw_ep; | |
1305 | #endif | |
1306 | } | |
1307 | ||
1308 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1309 | if (!musb->bulk_ep) { | |
1310 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1311 | return -EINVAL; | |
1312 | } | |
1313 | #endif | |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1319 | ||
1320 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1321 | * configure endpoints, or take their config from silicon | |
1322 | */ | |
1323 | static int __init musb_core_init(u16 musb_type, struct musb *musb) | |
1324 | { | |
1325 | #ifdef MUSB_AHB_ID | |
1326 | u32 data; | |
1327 | #endif | |
1328 | u8 reg; | |
1329 | char *type; | |
1330 | u16 hwvers, rev_major, rev_minor; | |
1331 | char aInfo[78], aRevision[32], aDate[12]; | |
1332 | void __iomem *mbase = musb->mregs; | |
1333 | int status = 0; | |
1334 | int i; | |
1335 | ||
1336 | /* log core options (read using indexed model) */ | |
1337 | musb_ep_select(mbase, 0); | |
1338 | reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA); | |
1339 | ||
1340 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
1341 | if (reg & MUSB_CONFIGDATA_DYNFIFO) | |
1342 | strcat(aInfo, ", dyn FIFOs"); | |
1343 | if (reg & MUSB_CONFIGDATA_MPRXE) { | |
1344 | strcat(aInfo, ", bulk combine"); | |
1345 | #ifdef C_MP_RX | |
1346 | musb->bulk_combine = true; | |
1347 | #else | |
1348 | strcat(aInfo, " (X)"); /* no driver support */ | |
1349 | #endif | |
1350 | } | |
1351 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1352 | strcat(aInfo, ", bulk split"); | |
1353 | #ifdef C_MP_TX | |
1354 | musb->bulk_split = true; | |
1355 | #else | |
1356 | strcat(aInfo, " (X)"); /* no driver support */ | |
1357 | #endif | |
1358 | } | |
1359 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1360 | strcat(aInfo, ", HB-ISO Rx"); | |
1361 | strcat(aInfo, " (X)"); /* no driver support */ | |
1362 | } | |
1363 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1364 | strcat(aInfo, ", HB-ISO Tx"); | |
1365 | strcat(aInfo, " (X)"); /* no driver support */ | |
1366 | } | |
1367 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1368 | strcat(aInfo, ", SoftConn"); | |
1369 | ||
1370 | printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", | |
1371 | musb_driver_name, reg, aInfo); | |
1372 | ||
1373 | #ifdef MUSB_AHB_ID | |
1374 | data = musb_readl(mbase, 0x404); | |
1375 | sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff), | |
1376 | (data >> 16) & 0xff, (data >> 24) & 0xff); | |
1377 | /* FIXME ID2 and ID3 are unused */ | |
1378 | data = musb_readl(mbase, 0x408); | |
1379 | printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data); | |
1380 | data = musb_readl(mbase, 0x40c); | |
1381 | printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data); | |
1382 | reg = musb_readb(mbase, 0x400); | |
1383 | musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC; | |
1384 | #else | |
1385 | aDate[0] = 0; | |
1386 | #endif | |
1387 | if (MUSB_CONTROLLER_MHDRC == musb_type) { | |
1388 | musb->is_multipoint = 1; | |
1389 | type = "M"; | |
1390 | } else { | |
1391 | musb->is_multipoint = 0; | |
1392 | type = ""; | |
1393 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1394 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB | |
1395 | printk(KERN_ERR | |
1396 | "%s: kernel must blacklist external hubs\n", | |
1397 | musb_driver_name); | |
1398 | #endif | |
1399 | #endif | |
1400 | } | |
1401 | ||
1402 | /* log release info */ | |
1403 | hwvers = musb_readw(mbase, MUSB_HWVERS); | |
1404 | rev_major = (hwvers >> 10) & 0x1f; | |
1405 | rev_minor = hwvers & 0x3ff; | |
1406 | snprintf(aRevision, 32, "%d.%d%s", rev_major, | |
1407 | rev_minor, (hwvers & 0x8000) ? "RC" : ""); | |
1408 | printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", | |
1409 | musb_driver_name, type, aRevision, aDate); | |
1410 | ||
1411 | /* configure ep0 */ | |
1412 | musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE; | |
1413 | musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE; | |
1414 | ||
1415 | /* discover endpoint configuration */ | |
1416 | musb->nr_endpoints = 1; | |
1417 | musb->epmask = 1; | |
1418 | ||
1419 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { | |
ca6d1b13 | 1420 | if (musb->config->dyn_fifo) |
550a7375 FB |
1421 | status = ep_config_from_table(musb); |
1422 | else { | |
1423 | ERR("reconfigure software for Dynamic FIFOs\n"); | |
1424 | status = -ENODEV; | |
1425 | } | |
1426 | } else { | |
ca6d1b13 | 1427 | if (!musb->config->dyn_fifo) |
550a7375 FB |
1428 | status = ep_config_from_hw(musb); |
1429 | else { | |
1430 | ERR("reconfigure software for static FIFOs\n"); | |
1431 | return -ENODEV; | |
1432 | } | |
1433 | } | |
1434 | ||
1435 | if (status < 0) | |
1436 | return status; | |
1437 | ||
1438 | /* finish init, and print endpoint config */ | |
1439 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1440 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1441 | ||
1442 | hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; | |
1443 | #ifdef CONFIG_USB_TUSB6010 | |
1444 | hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); | |
1445 | hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); | |
1446 | hw_ep->fifo_sync_va = | |
1447 | musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); | |
1448 | ||
1449 | if (i == 0) | |
1450 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1451 | else | |
1452 | hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); | |
1453 | #endif | |
1454 | ||
1455 | hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; | |
1456 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1457 | hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase; | |
1458 | hw_ep->rx_reinit = 1; | |
1459 | hw_ep->tx_reinit = 1; | |
1460 | #endif | |
1461 | ||
1462 | if (hw_ep->max_packet_sz_tx) { | |
1463 | printk(KERN_DEBUG | |
1464 | "%s: hw_ep %d%s, %smax %d\n", | |
1465 | musb_driver_name, i, | |
1466 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1467 | hw_ep->tx_double_buffered | |
1468 | ? "doublebuffer, " : "", | |
1469 | hw_ep->max_packet_sz_tx); | |
1470 | } | |
1471 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
1472 | printk(KERN_DEBUG | |
1473 | "%s: hw_ep %d%s, %smax %d\n", | |
1474 | musb_driver_name, i, | |
1475 | "rx", | |
1476 | hw_ep->rx_double_buffered | |
1477 | ? "doublebuffer, " : "", | |
1478 | hw_ep->max_packet_sz_rx); | |
1479 | } | |
1480 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
1481 | DBG(1, "hw_ep %d not configured\n", i); | |
1482 | } | |
1483 | ||
1484 | return 0; | |
1485 | } | |
1486 | ||
1487 | /*-------------------------------------------------------------------------*/ | |
1488 | ||
1489 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) | |
1490 | ||
1491 | static irqreturn_t generic_interrupt(int irq, void *__hci) | |
1492 | { | |
1493 | unsigned long flags; | |
1494 | irqreturn_t retval = IRQ_NONE; | |
1495 | struct musb *musb = __hci; | |
1496 | ||
1497 | spin_lock_irqsave(&musb->lock, flags); | |
1498 | ||
1499 | musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); | |
1500 | musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); | |
1501 | musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); | |
1502 | ||
1503 | if (musb->int_usb || musb->int_tx || musb->int_rx) | |
1504 | retval = musb_interrupt(musb); | |
1505 | ||
1506 | spin_unlock_irqrestore(&musb->lock, flags); | |
1507 | ||
1508 | /* REVISIT we sometimes get spurious IRQs on g_ep0 | |
1509 | * not clear why... | |
1510 | */ | |
1511 | if (retval != IRQ_HANDLED) | |
1512 | DBG(5, "spurious?\n"); | |
1513 | ||
1514 | return IRQ_HANDLED; | |
1515 | } | |
1516 | ||
1517 | #else | |
1518 | #define generic_interrupt NULL | |
1519 | #endif | |
1520 | ||
1521 | /* | |
1522 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1523 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1524 | * will be assigned, and the irq will already have been acked. | |
1525 | * | |
1526 | * called in irq context with spinlock held, irqs blocked | |
1527 | */ | |
1528 | irqreturn_t musb_interrupt(struct musb *musb) | |
1529 | { | |
1530 | irqreturn_t retval = IRQ_NONE; | |
1531 | u8 devctl, power; | |
1532 | int ep_num; | |
1533 | u32 reg; | |
1534 | ||
1535 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1536 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1537 | ||
1538 | DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n", | |
1539 | (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", | |
1540 | musb->int_usb, musb->int_tx, musb->int_rx); | |
1541 | ||
1542 | /* the core can interrupt us for multiple reasons; docs have | |
1543 | * a generic interrupt flowchart to follow | |
1544 | */ | |
1545 | if (musb->int_usb & STAGE0_MASK) | |
1546 | retval |= musb_stage0_irq(musb, musb->int_usb, | |
1547 | devctl, power); | |
1548 | ||
1549 | /* "stage 1" is handling endpoint irqs */ | |
1550 | ||
1551 | /* handle endpoint 0 first */ | |
1552 | if (musb->int_tx & 1) { | |
1553 | if (devctl & MUSB_DEVCTL_HM) | |
1554 | retval |= musb_h_ep0_irq(musb); | |
1555 | else | |
1556 | retval |= musb_g_ep0_irq(musb); | |
1557 | } | |
1558 | ||
1559 | /* RX on endpoints 1-15 */ | |
1560 | reg = musb->int_rx >> 1; | |
1561 | ep_num = 1; | |
1562 | while (reg) { | |
1563 | if (reg & 1) { | |
1564 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1565 | /* REVISIT just retval = ep->rx_irq(...) */ | |
1566 | retval = IRQ_HANDLED; | |
1567 | if (devctl & MUSB_DEVCTL_HM) { | |
1568 | if (is_host_capable()) | |
1569 | musb_host_rx(musb, ep_num); | |
1570 | } else { | |
1571 | if (is_peripheral_capable()) | |
1572 | musb_g_rx(musb, ep_num); | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | reg >>= 1; | |
1577 | ep_num++; | |
1578 | } | |
1579 | ||
1580 | /* TX on endpoints 1-15 */ | |
1581 | reg = musb->int_tx >> 1; | |
1582 | ep_num = 1; | |
1583 | while (reg) { | |
1584 | if (reg & 1) { | |
1585 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1586 | /* REVISIT just retval |= ep->tx_irq(...) */ | |
1587 | retval = IRQ_HANDLED; | |
1588 | if (devctl & MUSB_DEVCTL_HM) { | |
1589 | if (is_host_capable()) | |
1590 | musb_host_tx(musb, ep_num); | |
1591 | } else { | |
1592 | if (is_peripheral_capable()) | |
1593 | musb_g_tx(musb, ep_num); | |
1594 | } | |
1595 | } | |
1596 | reg >>= 1; | |
1597 | ep_num++; | |
1598 | } | |
1599 | ||
1600 | /* finish handling "global" interrupts after handling fifos */ | |
1601 | if (musb->int_usb) | |
1602 | retval |= musb_stage2_irq(musb, | |
1603 | musb->int_usb, devctl, power); | |
1604 | ||
1605 | return retval; | |
1606 | } | |
1607 | ||
1608 | ||
1609 | #ifndef CONFIG_MUSB_PIO_ONLY | |
1610 | static int __initdata use_dma = 1; | |
1611 | ||
1612 | /* "modprobe ... use_dma=0" etc */ | |
1613 | module_param(use_dma, bool, 0); | |
1614 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
1615 | ||
1616 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1617 | { | |
1618 | u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1619 | ||
1620 | /* called with controller lock already held */ | |
1621 | ||
1622 | if (!epnum) { | |
1623 | #ifndef CONFIG_USB_TUSB_OMAP_DMA | |
1624 | if (!is_cppi_enabled()) { | |
1625 | /* endpoint 0 */ | |
1626 | if (devctl & MUSB_DEVCTL_HM) | |
1627 | musb_h_ep0_irq(musb); | |
1628 | else | |
1629 | musb_g_ep0_irq(musb); | |
1630 | } | |
1631 | #endif | |
1632 | } else { | |
1633 | /* endpoints 1..15 */ | |
1634 | if (transmit) { | |
1635 | if (devctl & MUSB_DEVCTL_HM) { | |
1636 | if (is_host_capable()) | |
1637 | musb_host_tx(musb, epnum); | |
1638 | } else { | |
1639 | if (is_peripheral_capable()) | |
1640 | musb_g_tx(musb, epnum); | |
1641 | } | |
1642 | } else { | |
1643 | /* receive */ | |
1644 | if (devctl & MUSB_DEVCTL_HM) { | |
1645 | if (is_host_capable()) | |
1646 | musb_host_rx(musb, epnum); | |
1647 | } else { | |
1648 | if (is_peripheral_capable()) | |
1649 | musb_g_rx(musb, epnum); | |
1650 | } | |
1651 | } | |
1652 | } | |
1653 | } | |
1654 | ||
1655 | #else | |
1656 | #define use_dma 0 | |
1657 | #endif | |
1658 | ||
1659 | /*-------------------------------------------------------------------------*/ | |
1660 | ||
1661 | #ifdef CONFIG_SYSFS | |
1662 | ||
1663 | static ssize_t | |
1664 | musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1665 | { | |
1666 | struct musb *musb = dev_to_musb(dev); | |
1667 | unsigned long flags; | |
1668 | int ret = -EINVAL; | |
1669 | ||
1670 | spin_lock_irqsave(&musb->lock, flags); | |
1671 | ret = sprintf(buf, "%s\n", otg_state_string(musb)); | |
1672 | spin_unlock_irqrestore(&musb->lock, flags); | |
1673 | ||
1674 | return ret; | |
1675 | } | |
1676 | ||
1677 | static ssize_t | |
1678 | musb_mode_store(struct device *dev, struct device_attribute *attr, | |
1679 | const char *buf, size_t n) | |
1680 | { | |
1681 | struct musb *musb = dev_to_musb(dev); | |
1682 | unsigned long flags; | |
1683 | ||
1684 | spin_lock_irqsave(&musb->lock, flags); | |
1685 | if (!strncmp(buf, "host", 4)) | |
1686 | musb_platform_set_mode(musb, MUSB_HOST); | |
1687 | if (!strncmp(buf, "peripheral", 10)) | |
1688 | musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1689 | if (!strncmp(buf, "otg", 3)) | |
1690 | musb_platform_set_mode(musb, MUSB_OTG); | |
1691 | spin_unlock_irqrestore(&musb->lock, flags); | |
1692 | ||
1693 | return n; | |
1694 | } | |
1695 | static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); | |
1696 | ||
1697 | static ssize_t | |
1698 | musb_vbus_store(struct device *dev, struct device_attribute *attr, | |
1699 | const char *buf, size_t n) | |
1700 | { | |
1701 | struct musb *musb = dev_to_musb(dev); | |
1702 | unsigned long flags; | |
1703 | unsigned long val; | |
1704 | ||
1705 | if (sscanf(buf, "%lu", &val) < 1) { | |
1706 | printk(KERN_ERR "Invalid VBUS timeout ms value\n"); | |
1707 | return -EINVAL; | |
1708 | } | |
1709 | ||
1710 | spin_lock_irqsave(&musb->lock, flags); | |
1711 | musb->a_wait_bcon = val; | |
1712 | if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON) | |
1713 | musb->is_active = 0; | |
1714 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1715 | spin_unlock_irqrestore(&musb->lock, flags); | |
1716 | ||
1717 | return n; | |
1718 | } | |
1719 | ||
1720 | static ssize_t | |
1721 | musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1722 | { | |
1723 | struct musb *musb = dev_to_musb(dev); | |
1724 | unsigned long flags; | |
1725 | unsigned long val; | |
1726 | int vbus; | |
1727 | ||
1728 | spin_lock_irqsave(&musb->lock, flags); | |
1729 | val = musb->a_wait_bcon; | |
1730 | vbus = musb_platform_get_vbus_status(musb); | |
1731 | spin_unlock_irqrestore(&musb->lock, flags); | |
1732 | ||
1733 | return sprintf(buf, "Vbus %s, timeout %lu\n", | |
1734 | vbus ? "on" : "off", val); | |
1735 | } | |
1736 | static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); | |
1737 | ||
1738 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
1739 | ||
1740 | /* Gadget drivers can't know that a host is connected so they might want | |
1741 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1742 | */ | |
1743 | static ssize_t | |
1744 | musb_srp_store(struct device *dev, struct device_attribute *attr, | |
1745 | const char *buf, size_t n) | |
1746 | { | |
1747 | struct musb *musb = dev_to_musb(dev); | |
1748 | unsigned short srp; | |
1749 | ||
1750 | if (sscanf(buf, "%hu", &srp) != 1 | |
1751 | || (srp != 1)) { | |
1752 | printk(KERN_ERR "SRP: Value must be 1\n"); | |
1753 | return -EINVAL; | |
1754 | } | |
1755 | ||
1756 | if (srp == 1) | |
1757 | musb_g_wakeup(musb); | |
1758 | ||
1759 | return n; | |
1760 | } | |
1761 | static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); | |
1762 | ||
1763 | #endif /* CONFIG_USB_GADGET_MUSB_HDRC */ | |
1764 | ||
1765 | #endif /* sysfs */ | |
1766 | ||
1767 | /* Only used to provide driver mode change events */ | |
1768 | static void musb_irq_work(struct work_struct *data) | |
1769 | { | |
1770 | struct musb *musb = container_of(data, struct musb, irq_work); | |
1771 | static int old_state; | |
1772 | ||
1773 | if (musb->xceiv.state != old_state) { | |
1774 | old_state = musb->xceiv.state; | |
1775 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); | |
1776 | } | |
1777 | } | |
1778 | ||
1779 | /* -------------------------------------------------------------------------- | |
1780 | * Init support | |
1781 | */ | |
1782 | ||
1783 | static struct musb *__init | |
ca6d1b13 FB |
1784 | allocate_instance(struct device *dev, |
1785 | struct musb_hdrc_config *config, void __iomem *mbase) | |
550a7375 FB |
1786 | { |
1787 | struct musb *musb; | |
1788 | struct musb_hw_ep *ep; | |
1789 | int epnum; | |
1790 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1791 | struct usb_hcd *hcd; | |
1792 | ||
1793 | hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id); | |
1794 | if (!hcd) | |
1795 | return NULL; | |
1796 | /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ | |
1797 | ||
1798 | musb = hcd_to_musb(hcd); | |
1799 | INIT_LIST_HEAD(&musb->control); | |
1800 | INIT_LIST_HEAD(&musb->in_bulk); | |
1801 | INIT_LIST_HEAD(&musb->out_bulk); | |
1802 | ||
1803 | hcd->uses_new_polling = 1; | |
1804 | ||
1805 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; | |
1806 | #else | |
1807 | musb = kzalloc(sizeof *musb, GFP_KERNEL); | |
1808 | if (!musb) | |
1809 | return NULL; | |
1810 | dev_set_drvdata(dev, musb); | |
1811 | ||
1812 | #endif | |
1813 | ||
1814 | musb->mregs = mbase; | |
1815 | musb->ctrl_base = mbase; | |
1816 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1817 | musb->config = config; |
550a7375 | 1818 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1819 | epnum < musb->config->num_eps; |
550a7375 FB |
1820 | epnum++, ep++) { |
1821 | ||
1822 | ep->musb = musb; | |
1823 | ep->epnum = epnum; | |
1824 | } | |
1825 | ||
1826 | musb->controller = dev; | |
1827 | return musb; | |
1828 | } | |
1829 | ||
1830 | static void musb_free(struct musb *musb) | |
1831 | { | |
1832 | /* this has multiple entry modes. it handles fault cleanup after | |
1833 | * probe(), where things may be partially set up, as well as rmmod | |
1834 | * cleanup after everything's been de-activated. | |
1835 | */ | |
1836 | ||
1837 | #ifdef CONFIG_SYSFS | |
1838 | device_remove_file(musb->controller, &dev_attr_mode); | |
1839 | device_remove_file(musb->controller, &dev_attr_vbus); | |
1840 | #ifdef CONFIG_USB_MUSB_OTG | |
1841 | device_remove_file(musb->controller, &dev_attr_srp); | |
1842 | #endif | |
1843 | #endif | |
1844 | ||
1845 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
1846 | musb_gadget_cleanup(musb); | |
1847 | #endif | |
1848 | ||
1849 | if (musb->nIrq >= 0) { | |
1850 | disable_irq_wake(musb->nIrq); | |
1851 | free_irq(musb->nIrq, musb); | |
1852 | } | |
1853 | if (is_dma_capable() && musb->dma_controller) { | |
1854 | struct dma_controller *c = musb->dma_controller; | |
1855 | ||
1856 | (void) c->stop(c); | |
1857 | dma_controller_destroy(c); | |
1858 | } | |
1859 | ||
1860 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
1861 | musb_platform_exit(musb); | |
1862 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
1863 | ||
1864 | if (musb->clock) { | |
1865 | clk_disable(musb->clock); | |
1866 | clk_put(musb->clock); | |
1867 | } | |
1868 | ||
1869 | #ifdef CONFIG_USB_MUSB_OTG | |
1870 | put_device(musb->xceiv.dev); | |
1871 | #endif | |
1872 | ||
1873 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1874 | usb_put_hcd(musb_to_hcd(musb)); | |
1875 | #else | |
1876 | kfree(musb); | |
1877 | #endif | |
1878 | } | |
1879 | ||
1880 | /* | |
1881 | * Perform generic per-controller initialization. | |
1882 | * | |
1883 | * @pDevice: the controller (already clocked, etc) | |
1884 | * @nIrq: irq | |
1885 | * @mregs: virtual address of controller registers, | |
1886 | * not yet corrected for platform-specific offsets | |
1887 | */ | |
1888 | static int __init | |
1889 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) | |
1890 | { | |
1891 | int status; | |
1892 | struct musb *musb; | |
1893 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
1894 | ||
1895 | /* The driver might handle more features than the board; OK. | |
1896 | * Fail when the board needs a feature that's not enabled. | |
1897 | */ | |
1898 | if (!plat) { | |
1899 | dev_dbg(dev, "no platform_data?\n"); | |
1900 | return -ENODEV; | |
1901 | } | |
1902 | switch (plat->mode) { | |
1903 | case MUSB_HOST: | |
1904 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
1905 | break; | |
1906 | #else | |
1907 | goto bad_config; | |
1908 | #endif | |
1909 | case MUSB_PERIPHERAL: | |
1910 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
1911 | break; | |
1912 | #else | |
1913 | goto bad_config; | |
1914 | #endif | |
1915 | case MUSB_OTG: | |
1916 | #ifdef CONFIG_USB_MUSB_OTG | |
1917 | break; | |
1918 | #else | |
1919 | bad_config: | |
1920 | #endif | |
1921 | default: | |
1922 | dev_err(dev, "incompatible Kconfig role setting\n"); | |
1923 | return -EINVAL; | |
1924 | } | |
1925 | ||
1926 | /* allocate */ | |
ca6d1b13 | 1927 | musb = allocate_instance(dev, plat->config, ctrl); |
550a7375 FB |
1928 | if (!musb) |
1929 | return -ENOMEM; | |
1930 | ||
1931 | spin_lock_init(&musb->lock); | |
1932 | musb->board_mode = plat->mode; | |
1933 | musb->board_set_power = plat->set_power; | |
1934 | musb->set_clock = plat->set_clock; | |
1935 | musb->min_power = plat->min_power; | |
1936 | ||
1937 | /* Clock usage is chip-specific ... functional clock (DaVinci, | |
1938 | * OMAP2430), or PHY ref (some TUSB6010 boards). All this core | |
1939 | * code does is make sure a clock handle is available; platform | |
1940 | * code manages it during start/stop and suspend/resume. | |
1941 | */ | |
1942 | if (plat->clock) { | |
1943 | musb->clock = clk_get(dev, plat->clock); | |
1944 | if (IS_ERR(musb->clock)) { | |
1945 | status = PTR_ERR(musb->clock); | |
1946 | musb->clock = NULL; | |
1947 | goto fail; | |
1948 | } | |
1949 | } | |
1950 | ||
1951 | /* assume vbus is off */ | |
1952 | ||
1953 | /* platform adjusts musb->mregs and musb->isr if needed, | |
1954 | * and activates clocks | |
1955 | */ | |
1956 | musb->isr = generic_interrupt; | |
1957 | status = musb_platform_init(musb); | |
1958 | ||
1959 | if (status < 0) | |
1960 | goto fail; | |
1961 | if (!musb->isr) { | |
1962 | status = -ENODEV; | |
1963 | goto fail2; | |
1964 | } | |
1965 | ||
1966 | #ifndef CONFIG_MUSB_PIO_ONLY | |
1967 | if (use_dma && dev->dma_mask) { | |
1968 | struct dma_controller *c; | |
1969 | ||
1970 | c = dma_controller_create(musb, musb->mregs); | |
1971 | musb->dma_controller = c; | |
1972 | if (c) | |
1973 | (void) c->start(c); | |
1974 | } | |
1975 | #endif | |
1976 | /* ideally this would be abstracted in platform setup */ | |
1977 | if (!is_dma_capable() || !musb->dma_controller) | |
1978 | dev->dma_mask = NULL; | |
1979 | ||
1980 | /* be sure interrupts are disabled before connecting ISR */ | |
1981 | musb_platform_disable(musb); | |
1982 | musb_generic_disable(musb); | |
1983 | ||
1984 | /* setup musb parts of the core (especially endpoints) */ | |
ca6d1b13 | 1985 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
1986 | ? MUSB_CONTROLLER_MHDRC |
1987 | : MUSB_CONTROLLER_HDRC, musb); | |
1988 | if (status < 0) | |
1989 | goto fail2; | |
1990 | ||
1991 | /* Init IRQ workqueue before request_irq */ | |
1992 | INIT_WORK(&musb->irq_work, musb_irq_work); | |
1993 | ||
1994 | /* attach to the IRQ */ | |
1995 | if (request_irq(nIrq, musb->isr, 0, dev->bus_id, musb)) { | |
1996 | dev_err(dev, "request_irq %d failed!\n", nIrq); | |
1997 | status = -ENODEV; | |
1998 | goto fail2; | |
1999 | } | |
2000 | musb->nIrq = nIrq; | |
2001 | /* FIXME this handles wakeup irqs wrong */ | |
2002 | if (enable_irq_wake(nIrq) == 0) | |
2003 | device_init_wakeup(dev, 1); | |
2004 | ||
2005 | pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n", | |
2006 | musb_driver_name, | |
2007 | ({char *s; | |
2008 | switch (musb->board_mode) { | |
2009 | case MUSB_HOST: s = "Host"; break; | |
2010 | case MUSB_PERIPHERAL: s = "Peripheral"; break; | |
2011 | default: s = "OTG"; break; | |
2012 | }; s; }), | |
2013 | ctrl, | |
2014 | (is_dma_capable() && musb->dma_controller) | |
2015 | ? "DMA" : "PIO", | |
2016 | musb->nIrq); | |
2017 | ||
2018 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
2019 | /* host side needs more setup, except for no-host modes */ | |
2020 | if (musb->board_mode != MUSB_PERIPHERAL) { | |
2021 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
2022 | ||
2023 | if (musb->board_mode == MUSB_OTG) | |
2024 | hcd->self.otg_port = 1; | |
2025 | musb->xceiv.host = &hcd->self; | |
2026 | hcd->power_budget = 2 * (plat->power ? : 250); | |
2027 | } | |
2028 | #endif /* CONFIG_USB_MUSB_HDRC_HCD */ | |
2029 | ||
2030 | /* For the host-only role, we can activate right away. | |
2031 | * (We expect the ID pin to be forcibly grounded!!) | |
2032 | * Otherwise, wait till the gadget driver hooks up. | |
2033 | */ | |
2034 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) { | |
2035 | MUSB_HST_MODE(musb); | |
2036 | musb->xceiv.default_a = 1; | |
2037 | musb->xceiv.state = OTG_STATE_A_IDLE; | |
2038 | ||
2039 | status = usb_add_hcd(musb_to_hcd(musb), -1, 0); | |
746cdd0b FB |
2040 | if (status) |
2041 | goto fail; | |
550a7375 FB |
2042 | |
2043 | DBG(1, "%s mode, status %d, devctl %02x %c\n", | |
2044 | "HOST", status, | |
2045 | musb_readb(musb->mregs, MUSB_DEVCTL), | |
2046 | (musb_readb(musb->mregs, MUSB_DEVCTL) | |
2047 | & MUSB_DEVCTL_BDEVICE | |
2048 | ? 'B' : 'A')); | |
2049 | ||
2050 | } else /* peripheral is enabled */ { | |
2051 | MUSB_DEV_MODE(musb); | |
2052 | musb->xceiv.default_a = 0; | |
2053 | musb->xceiv.state = OTG_STATE_B_IDLE; | |
2054 | ||
2055 | status = musb_gadget_setup(musb); | |
746cdd0b FB |
2056 | if (status) |
2057 | goto fail; | |
550a7375 FB |
2058 | |
2059 | DBG(1, "%s mode, status %d, dev%02x\n", | |
2060 | is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", | |
2061 | status, | |
2062 | musb_readb(musb->mregs, MUSB_DEVCTL)); | |
2063 | ||
2064 | } | |
2065 | ||
746cdd0b FB |
2066 | return 0; |
2067 | ||
550a7375 | 2068 | fail: |
746cdd0b FB |
2069 | if (musb->clock) |
2070 | clk_put(musb->clock); | |
2071 | device_init_wakeup(dev, 0); | |
2072 | musb_free(musb); | |
2073 | return status; | |
550a7375 FB |
2074 | |
2075 | #ifdef CONFIG_SYSFS | |
2076 | status = device_create_file(dev, &dev_attr_mode); | |
2077 | status = device_create_file(dev, &dev_attr_vbus); | |
2078 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC | |
2079 | status = device_create_file(dev, &dev_attr_srp); | |
2080 | #endif /* CONFIG_USB_GADGET_MUSB_HDRC */ | |
2081 | status = 0; | |
2082 | #endif | |
2083 | ||
2084 | return status; | |
2085 | ||
2086 | fail2: | |
2087 | musb_platform_exit(musb); | |
2088 | goto fail; | |
2089 | } | |
2090 | ||
2091 | /*-------------------------------------------------------------------------*/ | |
2092 | ||
2093 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2094 | * bridge to a platform device; this driver then suffices. | |
2095 | */ | |
2096 | ||
2097 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2098 | static u64 *orig_dma_mask; | |
2099 | #endif | |
2100 | ||
2101 | static int __init musb_probe(struct platform_device *pdev) | |
2102 | { | |
2103 | struct device *dev = &pdev->dev; | |
2104 | int irq = platform_get_irq(pdev, 0); | |
2105 | struct resource *iomem; | |
2106 | void __iomem *base; | |
2107 | ||
2108 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2109 | if (!iomem || irq == 0) | |
2110 | return -ENODEV; | |
2111 | ||
2112 | base = ioremap(iomem->start, iomem->end - iomem->start + 1); | |
2113 | if (!base) { | |
2114 | dev_err(dev, "ioremap failed\n"); | |
2115 | return -ENOMEM; | |
2116 | } | |
2117 | ||
2118 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2119 | /* clobbered by use_dma=n */ | |
2120 | orig_dma_mask = dev->dma_mask; | |
2121 | #endif | |
2122 | return musb_init_controller(dev, irq, base); | |
2123 | } | |
2124 | ||
2125 | static int __devexit musb_remove(struct platform_device *pdev) | |
2126 | { | |
2127 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2128 | void __iomem *ctrl_base = musb->ctrl_base; | |
2129 | ||
2130 | /* this gets called on rmmod. | |
2131 | * - Host mode: host may still be active | |
2132 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2133 | * - OTG mode: both roles are deactivated (or never-activated) | |
2134 | */ | |
2135 | musb_shutdown(pdev); | |
550a7375 FB |
2136 | #ifdef CONFIG_USB_MUSB_HDRC_HCD |
2137 | if (musb->board_mode == MUSB_HOST) | |
2138 | usb_remove_hcd(musb_to_hcd(musb)); | |
2139 | #endif | |
2140 | musb_free(musb); | |
2141 | iounmap(ctrl_base); | |
2142 | device_init_wakeup(&pdev->dev, 0); | |
2143 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2144 | pdev->dev.dma_mask = orig_dma_mask; | |
2145 | #endif | |
2146 | return 0; | |
2147 | } | |
2148 | ||
2149 | #ifdef CONFIG_PM | |
2150 | ||
2151 | static int musb_suspend(struct platform_device *pdev, pm_message_t message) | |
2152 | { | |
2153 | unsigned long flags; | |
2154 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2155 | ||
2156 | if (!musb->clock) | |
2157 | return 0; | |
2158 | ||
2159 | spin_lock_irqsave(&musb->lock, flags); | |
2160 | ||
2161 | if (is_peripheral_active(musb)) { | |
2162 | /* FIXME force disconnect unless we know USB will wake | |
2163 | * the system up quickly enough to respond ... | |
2164 | */ | |
2165 | } else if (is_host_active(musb)) { | |
2166 | /* we know all the children are suspended; sometimes | |
2167 | * they will even be wakeup-enabled. | |
2168 | */ | |
2169 | } | |
2170 | ||
2171 | if (musb->set_clock) | |
2172 | musb->set_clock(musb->clock, 0); | |
2173 | else | |
2174 | clk_disable(musb->clock); | |
2175 | spin_unlock_irqrestore(&musb->lock, flags); | |
2176 | return 0; | |
2177 | } | |
2178 | ||
2179 | static int musb_resume(struct platform_device *pdev) | |
2180 | { | |
2181 | unsigned long flags; | |
2182 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2183 | ||
2184 | if (!musb->clock) | |
2185 | return 0; | |
2186 | ||
2187 | spin_lock_irqsave(&musb->lock, flags); | |
2188 | ||
2189 | if (musb->set_clock) | |
2190 | musb->set_clock(musb->clock, 1); | |
2191 | else | |
2192 | clk_enable(musb->clock); | |
2193 | ||
2194 | /* for static cmos like DaVinci, register values were preserved | |
2195 | * unless for some reason the whole soc powered down and we're | |
2196 | * not treating that as a whole-system restart (e.g. swsusp) | |
2197 | */ | |
2198 | spin_unlock_irqrestore(&musb->lock, flags); | |
2199 | return 0; | |
2200 | } | |
2201 | ||
2202 | #else | |
2203 | #define musb_suspend NULL | |
2204 | #define musb_resume NULL | |
2205 | #endif | |
2206 | ||
2207 | static struct platform_driver musb_driver = { | |
2208 | .driver = { | |
2209 | .name = (char *)musb_driver_name, | |
2210 | .bus = &platform_bus_type, | |
2211 | .owner = THIS_MODULE, | |
2212 | }, | |
2213 | .remove = __devexit_p(musb_remove), | |
2214 | .shutdown = musb_shutdown, | |
2215 | .suspend = musb_suspend, | |
2216 | .resume = musb_resume, | |
2217 | }; | |
2218 | ||
2219 | /*-------------------------------------------------------------------------*/ | |
2220 | ||
2221 | static int __init musb_init(void) | |
2222 | { | |
2223 | #ifdef CONFIG_USB_MUSB_HDRC_HCD | |
2224 | if (usb_disabled()) | |
2225 | return 0; | |
2226 | #endif | |
2227 | ||
2228 | pr_info("%s: version " MUSB_VERSION ", " | |
2229 | #ifdef CONFIG_MUSB_PIO_ONLY | |
2230 | "pio" | |
2231 | #elif defined(CONFIG_USB_TI_CPPI_DMA) | |
2232 | "cppi-dma" | |
2233 | #elif defined(CONFIG_USB_INVENTRA_DMA) | |
2234 | "musb-dma" | |
2235 | #elif defined(CONFIG_USB_TUSB_OMAP_DMA) | |
2236 | "tusb-omap-dma" | |
2237 | #else | |
2238 | "?dma?" | |
2239 | #endif | |
2240 | ", " | |
2241 | #ifdef CONFIG_USB_MUSB_OTG | |
2242 | "otg (peripheral+host)" | |
2243 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) | |
2244 | "peripheral" | |
2245 | #elif defined(CONFIG_USB_MUSB_HDRC_HCD) | |
2246 | "host" | |
2247 | #endif | |
2248 | ", debug=%d\n", | |
2249 | musb_driver_name, debug); | |
2250 | return platform_driver_probe(&musb_driver, musb_probe); | |
2251 | } | |
2252 | ||
2253 | /* make us init after usbcore and before usb | |
2254 | * gadget and host-side drivers start to register | |
2255 | */ | |
2256 | subsys_initcall(musb_init); | |
2257 | ||
2258 | static void __exit musb_cleanup(void) | |
2259 | { | |
2260 | platform_driver_unregister(&musb_driver); | |
2261 | } | |
2262 | module_exit(musb_cleanup); |