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usb: musb: dsps: add dsps_ prefix to sw_babble_control
[linux-block.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375 85 * - platform_device for addressing, irq, and platform_data
5ae477b0 86 * - platform_data is mostly for board-specific information
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
550a7375
FB		 96#include <linux/list.h>
97#include <linux/kobject.h>
9303961f 98#include <linux/prefetch.h>
550a7375
FB		 99#include <linux/platform_device.h>
100#include <linux/io.h>
8d2421e6 101#include <linux/dma-mapping.h>
550a7375 102
550a7375
FB		 103#include "musb_core.h"
104
f7f9d63e 105#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 106
107
550a7375
FB		 108#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
e8164f64 111#define MUSB_VERSION "6.0"
550a7375
FB		 112
113#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
05ac10dd 115#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 116const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118MODULE_DESCRIPTION(DRIVER_INFO);
119MODULE_AUTHOR(DRIVER_AUTHOR);
120MODULE_LICENSE("GPL");
121MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124/*-------------------------------------------------------------------------*/
125
126static inline struct musb *dev_to_musb(struct device *dev)
127{
550a7375 128 return dev_get_drvdata(dev);
550a7375
FB		 129}
130
131/*-------------------------------------------------------------------------*/
132
ffb865b1 133#ifndef CONFIG_BLACKFIN
b96d3b08 134static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
ffb865b1 135{
b96d3b08 136 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 137 int i = 0;
138 u8 r;
139 u8 power;
bf070bc1
GI		 140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
bf070bc1
GI		 160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
ffb865b1
HK		 164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
bf070bc1
GI		 170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
ffb865b1
HK		 176}
177
b96d3b08 178static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
ffb865b1 179{
b96d3b08 180 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 181 int i = 0;
182 u8 r = 0;
183 u8 power;
bf070bc1
GI		 184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
bf070bc1
GI		 200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
ffb865b1
HK		 204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
bf070bc1
GI		 210out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
ffb865b1
HK		 214}
215#else
f2263db7
MF		 216#define musb_ulpi_read NULL
217#define musb_ulpi_write NULL
ffb865b1
HK		 218#endif
219
b96d3b08 220static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223};
224
225/*-------------------------------------------------------------------------*/
226
1b40fc57
TL		 227static u32 musb_default_fifo_offset(u8 epnum)
228{
229 return 0x20 + (epnum * 4);
230}
231
d026e9c7
TL		 232/* "flat" mapping: each endpoint has its own i/o address */
233static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
234{
235}
236
237static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
238{
239 return 0x100 + (0x10 * epnum) + offset;
240}
241
242/* "indexed" mapping: INDEX register controls register bank select */
243static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
244{
245 musb_writeb(mbase, MUSB_INDEX, epnum);
246}
247
248static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
249{
250 return 0x10 + offset;
251}
252
1b40fc57
TL		 253static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
254{
255 return __raw_readb(addr + offset);
256}
257
258static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
259{
260 __raw_writeb(data, addr + offset);
261}
262
263static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264{
265 return __raw_readw(addr + offset);
266}
267
268static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
269{
270 __raw_writew(data, addr + offset);
271}
272
273static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
274{
275 return __raw_readl(addr + offset);
276}
277
278static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
279{
280 __raw_writel(data, addr + offset);
281}
c6cf8b00 282
550a7375
FB		 283/*
284 * Load an endpoint's FIFO
285 */
1b40fc57
TL		 286static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
287 const u8 *src)
550a7375 288{
5c8a86e1 289 struct musb *musb = hw_ep->musb;
550a7375
FB		 290 void __iomem *fifo = hw_ep->fifo;
291
603fe2b2
AKG		 292 if (unlikely(len == 0))
293 return;
294
550a7375
FB		 295 prefetch((u8 *)src);
296
5c8a86e1 297 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 298 'T', hw_ep->epnum, fifo, len, src);
299
300 /* we can't assume unaligned reads work */
301 if (likely((0x01 & (unsigned long) src) == 0)) {
302 u16 index = 0;
303
304 /* best case is 32bit-aligned source address */
305 if ((0x02 & (unsigned long) src) == 0) {
306 if (len >= 4) {
2bf0a8f6 307 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 308 index += len & ~0x03;
309 }
310 if (len & 0x02) {
311 musb_writew(fifo, 0, *(u16 *)&src[index]);
312 index += 2;
313 }
314 } else {
315 if (len >= 2) {
2bf0a8f6 316 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 317 index += len & ~0x01;
318 }
319 }
320 if (len & 0x01)
321 musb_writeb(fifo, 0, src[index]);
322 } else {
323 /* byte aligned */
2bf0a8f6 324 iowrite8_rep(fifo, src, len);
550a7375
FB		 325 }
326}
327
328/*
329 * Unload an endpoint's FIFO
330 */
1b40fc57 331static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
550a7375 332{
5c8a86e1 333 struct musb *musb = hw_ep->musb;
550a7375
FB		 334 void __iomem *fifo = hw_ep->fifo;
335
603fe2b2
AKG		 336 if (unlikely(len == 0))
337 return;
338
5c8a86e1 339 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 340 'R', hw_ep->epnum, fifo, len, dst);
341
342 /* we can't assume unaligned writes work */
343 if (likely((0x01 & (unsigned long) dst) == 0)) {
344 u16 index = 0;
345
346 /* best case is 32bit-aligned destination address */
347 if ((0x02 & (unsigned long) dst) == 0) {
348 if (len >= 4) {
2bf0a8f6 349 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 350 index = len & ~0x03;
351 }
352 if (len & 0x02) {
353 *(u16 *)&dst[index] = musb_readw(fifo, 0);
354 index += 2;
355 }
356 } else {
357 if (len >= 2) {
2bf0a8f6 358 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 359 index = len & ~0x01;
360 }
361 }
362 if (len & 0x01)
363 dst[index] = musb_readb(fifo, 0);
364 } else {
365 /* byte aligned */
2bf0a8f6 366 ioread8_rep(fifo, dst, len);
550a7375
FB		 367 }
368}
369
1b40fc57
TL		 370/*
371 * Old style IO functions
372 */
373u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
374EXPORT_SYMBOL_GPL(musb_readb);
375
376void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
377EXPORT_SYMBOL_GPL(musb_writeb);
550a7375 378
1b40fc57
TL		 379u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
380EXPORT_SYMBOL_GPL(musb_readw);
381
382void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
383EXPORT_SYMBOL_GPL(musb_writew);
384
385u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
386EXPORT_SYMBOL_GPL(musb_readl);
387
388void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
389EXPORT_SYMBOL_GPL(musb_writel);
390
391/*
392 * New style IO functions
393 */
394void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
395{
396 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
397}
398
399void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
400{
401 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
402}
550a7375
FB		 403
404/*-------------------------------------------------------------------------*/
405
406/* for high speed test mode; see USB 2.0 spec 7.1.20 */
407static const u8 musb_test_packet[53] = {
408 /* implicit SYNC then DATA0 to start */
409
410 /* JKJKJKJK x9 */
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
412 /* JJKKJJKK x8 */
413 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
414 /* JJJJKKKK x8 */
415 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
416 /* JJJJJJJKKKKKKK x8 */
417 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
418 /* JJJJJJJK x8 */
419 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
420 /* JKKKKKKK x10, JK */
421 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
422
423 /* implicit CRC16 then EOP to end */
424};
425
426void musb_load_testpacket(struct musb *musb)
427{
428 void __iomem *regs = musb->endpoints[0].regs;
429
430 musb_ep_select(musb->mregs, 0);
431 musb_write_fifo(musb->control_ep,
432 sizeof(musb_test_packet), musb_test_packet);
433 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
434}
435
436/*-------------------------------------------------------------------------*/
437
550a7375
FB		 438/*
439 * Handles OTG hnp timeouts, such as b_ase0_brst
440 */
a156544b 441static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 442{
443 struct musb *musb = (struct musb *)data;
444 unsigned long flags;
445
446 spin_lock_irqsave(&musb->lock, flags);
e47d9254 447 switch (musb->xceiv->otg->state) {
550a7375 448 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 449 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
550a7375 450 musb_g_disconnect(musb);
e47d9254 451 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 452 musb->is_active = 0;
453 break;
ab983f2a 454 case OTG_STATE_A_SUSPEND:
550a7375 455 case OTG_STATE_A_WAIT_BCON:
5c8a86e1 456 dev_dbg(musb->controller, "HNP: %s timeout\n",
e47d9254 457 usb_otg_state_string(musb->xceiv->otg->state));
743411b3 458 musb_platform_set_vbus(musb, 0);
e47d9254 459 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 460 break;
461 default:
5c8a86e1 462 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
e47d9254 463 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 464 }
550a7375
FB		 465 spin_unlock_irqrestore(&musb->lock, flags);
466}
467
550a7375 468/*
f7f9d63e 469 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 470 */
471void musb_hnp_stop(struct musb *musb)
472{
8b125df5 473 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 474 void __iomem *mbase = musb->mregs;
475 u8 reg;
476
42c0bf1c 477 dev_dbg(musb->controller, "HNP: stop from %s\n",
e47d9254 478 usb_otg_state_string(musb->xceiv->otg->state));
ab983f2a 479
e47d9254 480 switch (musb->xceiv->otg->state) {
550a7375 481 case OTG_STATE_A_PERIPHERAL:
550a7375 482 musb_g_disconnect(musb);
5c8a86e1 483 dev_dbg(musb->controller, "HNP: back to %s\n",
e47d9254 484 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 485 break;
486 case OTG_STATE_B_HOST:
5c8a86e1 487 dev_dbg(musb->controller, "HNP: Disabling HR\n");
74c2e936
DM		 488 if (hcd)
489 hcd->self.is_b_host = 0;
e47d9254 490 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 491 MUSB_DEV_MODE(musb);
492 reg = musb_readb(mbase, MUSB_POWER);
493 reg |= MUSB_POWER_SUSPENDM;
494 musb_writeb(mbase, MUSB_POWER, reg);
495 /* REVISIT: Start SESSION_REQUEST here? */
496 break;
497 default:
5c8a86e1 498 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
e47d9254 499 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 500 }
501
502 /*
503 * When returning to A state after HNP, avoid hub_port_rebounce(),
504 * which cause occasional OPT A "Did not receive reset after connect"
505 * errors.
506 */
749da5f8 507 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 508}
509
f905bc68 510static void musb_generic_disable(struct musb *musb);
550a7375
FB		 511/*
512 * Interrupt Service Routine to record USB "global" interrupts.
513 * Since these do not happen often and signify things of
514 * paramount importance, it seems OK to check them individually;
515 * the order of the tests is specified in the manual
516 *
517 * @param musb instance pointer
518 * @param int_usb register contents
519 * @param devctl
520 * @param power
521 */
522
550a7375 523static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 524 u8 devctl)
550a7375
FB		 525{
526 irqreturn_t handled = IRQ_NONE;
550a7375 527
b11e94d0 528 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
550a7375
FB		 529 int_usb);
530
531 /* in host mode, the peripheral may issue remote wakeup.
532 * in peripheral mode, the host may resume the link.
533 * spurious RESUME irqs happen too, paired with SUSPEND.
534 */
535 if (int_usb & MUSB_INTR_RESUME) {
536 handled = IRQ_HANDLED;
0acff6b8
FB		 537 dev_dbg(musb->controller, "RESUME (%s)\n",
538 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 539
540 if (devctl & MUSB_DEVCTL_HM) {
e47d9254 541 switch (musb->xceiv->otg->state) {
550a7375
FB		 542 case OTG_STATE_A_SUSPEND:
543 /* remote wakeup? later, GetPortStatus
544 * will stop RESUME signaling
545 */
546
550a7375
FB		 547 musb->port1_status |=
548 (USB_PORT_STAT_C_SUSPEND << 16)
549 | MUSB_PORT_STAT_RESUME;
30d361bf
DM		 550 musb->rh_timer = jiffies
551 + msecs_to_jiffies(20);
baadd52f 552 musb->need_finish_resume = 1;
550a7375 553
e47d9254 554 musb->xceiv->otg->state = OTG_STATE_A_HOST;
550a7375 555 musb->is_active = 1;
9298b4aa 556 musb_host_resume_root_hub(musb);
550a7375
FB		 557 break;
558 case OTG_STATE_B_WAIT_ACON:
e47d9254 559 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 560 musb->is_active = 1;
561 MUSB_DEV_MODE(musb);
562 break;
563 default:
564 WARNING("bogus %s RESUME (%s)\n",
565 "host",
e47d9254 566 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 567 }
550a7375 568 } else {
e47d9254 569 switch (musb->xceiv->otg->state) {
550a7375
FB		 570 case OTG_STATE_A_SUSPEND:
571 /* possibly DISCONNECT is upcoming */
e47d9254 572 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44 573 musb_host_resume_root_hub(musb);
550a7375 574 break;
550a7375
FB		 575 case OTG_STATE_B_WAIT_ACON:
576 case OTG_STATE_B_PERIPHERAL:
577 /* disconnect while suspended? we may
578 * not get a disconnect irq...
579 */
580 if ((devctl & MUSB_DEVCTL_VBUS)
581 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
582 ) {
583 musb->int_usb |= MUSB_INTR_DISCONNECT;
584 musb->int_usb &= ~MUSB_INTR_SUSPEND;
585 break;
586 }
587 musb_g_resume(musb);
588 break;
589 case OTG_STATE_B_IDLE:
590 musb->int_usb &= ~MUSB_INTR_SUSPEND;
591 break;
550a7375
FB		 592 default:
593 WARNING("bogus %s RESUME (%s)\n",
594 "peripheral",
e47d9254 595 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 596 }
597 }
598 }
599
550a7375
FB		 600 /* see manual for the order of the tests */
601 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 602 void __iomem *mbase = musb->mregs;
603
19aab56c
HK		 604 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
605 && (devctl & MUSB_DEVCTL_BDEVICE)) {
5c8a86e1 606 dev_dbg(musb->controller, "SessReq while on B state\n");
a6038ee7
HK		 607 return IRQ_HANDLED;
608 }
609
5c8a86e1 610 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
e47d9254 611 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 612
613 /* IRQ arrives from ID pin sense or (later, if VBUS power
614 * is removed) SRP. responses are time critical:
615 * - turn on VBUS (with silicon-specific mechanism)
616 * - go through A_WAIT_VRISE
617 * - ... to A_WAIT_BCON.
618 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
619 */
620 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
621 musb->ep0_stage = MUSB_EP0_START;
e47d9254 622 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
550a7375 623 MUSB_HST_MODE(musb);
743411b3 624 musb_platform_set_vbus(musb, 1);
550a7375
FB		 625
626 handled = IRQ_HANDLED;
627 }
628
629 if (int_usb & MUSB_INTR_VBUSERROR) {
630 int ignore = 0;
631
632 /* During connection as an A-Device, we may see a short
633 * current spikes causing voltage drop, because of cable
634 * and peripheral capacitance combined with vbus draw.
635 * (So: less common with truly self-powered devices, where
636 * vbus doesn't act like a power supply.)
637 *
638 * Such spikes are short; usually less than ~500 usec, max
639 * of ~2 msec. That is, they're not sustained overcurrent
640 * errors, though they're reported using VBUSERROR irqs.
641 *
642 * Workarounds: (a) hardware: use self powered devices.
643 * (b) software: ignore non-repeated VBUS errors.
644 *
645 * REVISIT: do delays from lots of DEBUG_KERNEL checks
646 * make trouble here, keeping VBUS < 4.4V ?
647 */
e47d9254 648 switch (musb->xceiv->otg->state) {
550a7375
FB		 649 case OTG_STATE_A_HOST:
650 /* recovery is dicey once we've gotten past the
651 * initial stages of enumeration, but if VBUS
652 * stayed ok at the other end of the link, and
653 * another reset is due (at least for high speed,
654 * to redo the chirp etc), it might work OK...
655 */
656 case OTG_STATE_A_WAIT_BCON:
657 case OTG_STATE_A_WAIT_VRISE:
658 if (musb->vbuserr_retry) {
aa471456
FB		 659 void __iomem *mbase = musb->mregs;
660
550a7375
FB		 661 musb->vbuserr_retry--;
662 ignore = 1;
663 devctl |= MUSB_DEVCTL_SESSION;
664 musb_writeb(mbase, MUSB_DEVCTL, devctl);
665 } else {
666 musb->port1_status |=
749da5f8
AS		 667 USB_PORT_STAT_OVERCURRENT
668 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 669 }
670 break;
671 default:
672 break;
673 }
674
54485116
GI		 675 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
676 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
e47d9254 677 usb_otg_state_string(musb->xceiv->otg->state),
550a7375
FB		 678 devctl,
679 ({ char *s;
680 switch (devctl & MUSB_DEVCTL_VBUS) {
681 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
682 s = "<SessEnd"; break;
683 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
684 s = "<AValid"; break;
685 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
686 s = "<VBusValid"; break;
687 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
688 default:
689 s = "VALID"; break;
2b84f92b 690 } s; }),
550a7375
FB		 691 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
692 musb->port1_status);
693
694 /* go through A_WAIT_VFALL then start a new session */
695 if (!ignore)
743411b3 696 musb_platform_set_vbus(musb, 0);
550a7375
FB		 697 handled = IRQ_HANDLED;
698 }
699
1c25fda4 700 if (int_usb & MUSB_INTR_SUSPEND) {
b11e94d0 701 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
e47d9254 702 usb_otg_state_string(musb->xceiv->otg->state), devctl);
1c25fda4
AM		 703 handled = IRQ_HANDLED;
704
e47d9254 705 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 706 case OTG_STATE_A_PERIPHERAL:
707 /* We also come here if the cable is removed, since
708 * this silicon doesn't report ID-no-longer-grounded.
709 *
710 * We depend on T(a_wait_bcon) to shut us down, and
711 * hope users don't do anything dicey during this
712 * undesired detour through A_WAIT_BCON.
713 */
714 musb_hnp_stop(musb);
0b3eba44 715 musb_host_resume_root_hub(musb);
1c25fda4
AM		 716 musb_root_disconnect(musb);
717 musb_platform_try_idle(musb, jiffies
718 + msecs_to_jiffies(musb->a_wait_bcon
719 ? : OTG_TIME_A_WAIT_BCON));
720
721 break;
1c25fda4
AM		 722 case OTG_STATE_B_IDLE:
723 if (!musb->is_active)
724 break;
725 case OTG_STATE_B_PERIPHERAL:
726 musb_g_suspend(musb);
eee3f15d 727 musb->is_active = musb->g.b_hnp_enable;
1c25fda4 728 if (musb->is_active) {
e47d9254 729 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
5c8a86e1 730 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
1c25fda4
AM		 731 mod_timer(&musb->otg_timer, jiffies
732 + msecs_to_jiffies(
733 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 734 }
735 break;
736 case OTG_STATE_A_WAIT_BCON:
737 if (musb->a_wait_bcon != 0)
738 musb_platform_try_idle(musb, jiffies
739 + msecs_to_jiffies(musb->a_wait_bcon));
740 break;
741 case OTG_STATE_A_HOST:
e47d9254 742 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
eee3f15d 743 musb->is_active = musb->hcd->self.b_hnp_enable;
1c25fda4
AM		 744 break;
745 case OTG_STATE_B_HOST:
746 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
5c8a86e1 747 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
1c25fda4
AM		 748 break;
749 default:
750 /* "should not happen" */
751 musb->is_active = 0;
752 break;
753 }
754 }
755
550a7375 756 if (int_usb & MUSB_INTR_CONNECT) {
8b125df5 757 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 758
759 handled = IRQ_HANDLED;
760 musb->is_active = 1;
550a7375
FB		 761
762 musb->ep0_stage = MUSB_EP0_START;
763
b18d26f6
SAS		 764 musb->intrtxe = musb->epmask;
765 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 766 musb->intrrxe = musb->epmask & 0xfffe;
767 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 768 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 769 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
770 |USB_PORT_STAT_HIGH_SPEED
771 |USB_PORT_STAT_ENABLE
772 );
773 musb->port1_status |= USB_PORT_STAT_CONNECTION
774 |(USB_PORT_STAT_C_CONNECTION << 16);
775
776 /* high vs full speed is just a guess until after reset */
777 if (devctl & MUSB_DEVCTL_LSDEV)
778 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
779
550a7375 780 /* indicate new connection to OTG machine */
e47d9254 781 switch (musb->xceiv->otg->state) {
550a7375
FB		 782 case OTG_STATE_B_PERIPHERAL:
783 if (int_usb & MUSB_INTR_SUSPEND) {
5c8a86e1 784 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
550a7375 785 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 786 goto b_host;
550a7375 787 } else
5c8a86e1 788 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
550a7375
FB		 789 break;
790 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 791 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
1de00dae 792b_host:
e47d9254 793 musb->xceiv->otg->state = OTG_STATE_B_HOST;
74c2e936
DM		 794 if (musb->hcd)
795 musb->hcd->self.is_b_host = 1;
1de00dae 796 del_timer(&musb->otg_timer);
550a7375
FB		 797 break;
798 default:
799 if ((devctl & MUSB_DEVCTL_VBUS)
800 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
e47d9254 801 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44
DM		 802 if (hcd)
803 hcd->self.is_b_host = 0;
550a7375
FB		 804 }
805 break;
806 }
1de00dae 807
0b3eba44 808 musb_host_poke_root_hub(musb);
1de00dae 809
5c8a86e1 810 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
e47d9254 811 usb_otg_state_string(musb->xceiv->otg->state), devctl);
550a7375 812 }
550a7375 813
6d349671 814 if (int_usb & MUSB_INTR_DISCONNECT) {
5c8a86e1 815 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
e47d9254 816 usb_otg_state_string(musb->xceiv->otg->state),
1c25fda4
AM		 817 MUSB_MODE(musb), devctl);
818 handled = IRQ_HANDLED;
819
e47d9254 820 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 821 case OTG_STATE_A_HOST:
822 case OTG_STATE_A_SUSPEND:
0b3eba44 823 musb_host_resume_root_hub(musb);
1c25fda4 824 musb_root_disconnect(musb);
032ec49f 825 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 826 musb_platform_try_idle(musb, jiffies
827 + msecs_to_jiffies(musb->a_wait_bcon));
828 break;
1c25fda4
AM		 829 case OTG_STATE_B_HOST:
830 /* REVISIT this behaves for "real disconnect"
831 * cases; make sure the other transitions from
832 * from B_HOST act right too. The B_HOST code
833 * in hnp_stop() is currently not used...
834 */
835 musb_root_disconnect(musb);
74c2e936
DM		 836 if (musb->hcd)
837 musb->hcd->self.is_b_host = 0;
e47d9254 838 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1c25fda4
AM		 839 MUSB_DEV_MODE(musb);
840 musb_g_disconnect(musb);
841 break;
842 case OTG_STATE_A_PERIPHERAL:
843 musb_hnp_stop(musb);
844 musb_root_disconnect(musb);
845 /* FALLTHROUGH */
846 case OTG_STATE_B_WAIT_ACON:
847 /* FALLTHROUGH */
1c25fda4
AM		 848 case OTG_STATE_B_PERIPHERAL:
849 case OTG_STATE_B_IDLE:
850 musb_g_disconnect(musb);
851 break;
1c25fda4
AM		 852 default:
853 WARNING("unhandled DISCONNECT transition (%s)\n",
e47d9254 854 usb_otg_state_string(musb->xceiv->otg->state));
1c25fda4
AM		 855 break;
856 }
857 }
858
550a7375
FB		 859 /* mentor saves a bit: bus reset and babble share the same irq.
860 * only host sees babble; only peripheral sees bus reset.
861 */
862 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 863 handled = IRQ_HANDLED;
896f7ea3 864 if (devctl & MUSB_DEVCTL_HM) {
28378d5e
FB		 865 u8 power = musb_readl(musb->mregs, MUSB_POWER);
866
550a7375
FB		 867 /*
868 * Looks like non-HS BABBLE can be ignored, but
28378d5e
FB		 869 * HS BABBLE is an error condition.
870 *
871 * For HS the solution is to avoid babble in the first
872 * place and fix what caused BABBLE.
873 *
874 * When HS BABBLE happens what we can depends on which
875 * platform MUSB is running, because some platforms
876 * implemented proprietary means for 'recovering' from
877 * Babble conditions. One such platform is AM335x. In
878 * most cases, however, the only thing we can do is drop
879 * the session.
550a7375 880 */
28378d5e 881 if (power & MUSB_POWER_HSMODE) {
52b9e6eb 882 dev_err(musb->controller, "Babble\n");
d0fc0a20
FB		 883
884 if (is_host_active(musb)) {
885 musb_generic_disable(musb);
886 schedule_delayed_work(&musb->recover_work,
887 msecs_to_jiffies(100));
888 }
550a7375 889 }
a04d46d0 890 } else {
5c8a86e1 891 dev_dbg(musb->controller, "BUS RESET as %s\n",
e47d9254
AT		 892 usb_otg_state_string(musb->xceiv->otg->state));
893 switch (musb->xceiv->otg->state) {
550a7375 894 case OTG_STATE_A_SUSPEND:
550a7375
FB		 895 musb_g_reset(musb);
896 /* FALLTHROUGH */
897 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 898 /* never use invalid T(a_wait_bcon) */
5c8a86e1 899 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
e47d9254 900 usb_otg_state_string(musb->xceiv->otg->state),
3df00453 901 TA_WAIT_BCON(musb));
f7f9d63e
DB		 902 mod_timer(&musb->otg_timer, jiffies
903 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 904 break;
905 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 906 del_timer(&musb->otg_timer);
907 musb_g_reset(musb);
550a7375
FB		 908 break;
909 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 910 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
e47d9254
AT		 911 usb_otg_state_string(musb->xceiv->otg->state));
912 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 913 musb_g_reset(musb);
914 break;
550a7375 915 case OTG_STATE_B_IDLE:
e47d9254 916 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 917 /* FALLTHROUGH */
918 case OTG_STATE_B_PERIPHERAL:
919 musb_g_reset(musb);
920 break;
921 default:
5c8a86e1 922 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
e47d9254 923 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 924 }
925 }
550a7375 926 }
550a7375
FB		 927
928#if 0
929/* REVISIT ... this would be for multiplexing periodic endpoints, or
930 * supporting transfer phasing to prevent exceeding ISO bandwidth
931 * limits of a given frame or microframe.
932 *
933 * It's not needed for peripheral side, which dedicates endpoints;
934 * though it _might_ use SOF irqs for other purposes.
935 *
936 * And it's not currently needed for host side, which also dedicates
937 * endpoints, relies on TX/RX interval registers, and isn't claimed
938 * to support ISO transfers yet.
939 */
940 if (int_usb & MUSB_INTR_SOF) {
941 void __iomem *mbase = musb->mregs;
942 struct musb_hw_ep *ep;
943 u8 epnum;
944 u16 frame;
945
5c8a86e1 946 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 947 handled = IRQ_HANDLED;
948
949 /* start any periodic Tx transfers waiting for current frame */
950 frame = musb_readw(mbase, MUSB_FRAME);
951 ep = musb->endpoints;
952 for (epnum = 1; (epnum < musb->nr_endpoints)
953 && (musb->epmask >= (1 << epnum));
954 epnum++, ep++) {
955 /*
956 * FIXME handle framecounter wraps (12 bits)
957 * eliminate duplicated StartUrb logic
958 */
959 if (ep->dwWaitFrame >= frame) {
960 ep->dwWaitFrame = 0;
961 pr_debug("SOF --> periodic TX%s on %d\n",
962 ep->tx_channel ? " DMA" : "",
963 epnum);
964 if (!ep->tx_channel)
965 musb_h_tx_start(musb, epnum);
966 else
967 cppi_hostdma_start(musb, epnum);
968 }
969 } /* end of for loop */
970 }
971#endif
972
1c25fda4 973 schedule_work(&musb->irq_work);
550a7375
FB		 974
975 return handled;
976}
977
978/*-------------------------------------------------------------------------*/
979
550a7375
FB		 980static void musb_generic_disable(struct musb *musb)
981{
982 void __iomem *mbase = musb->mregs;
983 u16 temp;
984
985 /* disable interrupts */
986 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 987 musb->intrtxe = 0;
550a7375 988 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 989 musb->intrrxe = 0;
550a7375
FB		 990 musb_writew(mbase, MUSB_INTRRXE, 0);
991
992 /* off */
993 musb_writeb(mbase, MUSB_DEVCTL, 0);
994
995 /* flush pending interrupts */
996 temp = musb_readb(mbase, MUSB_INTRUSB);
997 temp = musb_readw(mbase, MUSB_INTRTX);
998 temp = musb_readw(mbase, MUSB_INTRRX);
999
1000}
1001
001dd84a
SAS		 1002/*
1003 * Program the HDRC to start (enable interrupts, dma, etc.).
1004 */
1005void musb_start(struct musb *musb)
1006{
1007 void __iomem *regs = musb->mregs;
1008 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1009
1010 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1011
1012 /* Set INT enable registers, enable interrupts */
1013 musb->intrtxe = musb->epmask;
1014 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1015 musb->intrrxe = musb->epmask & 0xfffe;
1016 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1017 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1018
1019 musb_writeb(regs, MUSB_TESTMODE, 0);
1020
1021 /* put into basic highspeed mode and start session */
1022 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
1023 | MUSB_POWER_HSENAB
1024 /* ENSUSPEND wedges tusb */
1025 /* | MUSB_POWER_ENSUSPEND */
1026 );
1027
1028 musb->is_active = 0;
1029 devctl = musb_readb(regs, MUSB_DEVCTL);
1030 devctl &= ~MUSB_DEVCTL_SESSION;
1031
1032 /* session started after:
1033 * (a) ID-grounded irq, host mode;
1034 * (b) vbus present/connect IRQ, peripheral mode;
1035 * (c) peripheral initiates, using SRP
1036 */
1037 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1038 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1039 musb->is_active = 1;
1040 } else {
1041 devctl |= MUSB_DEVCTL_SESSION;
1042 }
1043
1044 musb_platform_enable(musb);
1045 musb_writeb(regs, MUSB_DEVCTL, devctl);
1046}
1047
550a7375
FB		 1048/*
1049 * Make the HDRC stop (disable interrupts, etc.);
1050 * reversible by musb_start
1051 * called on gadget driver unregister
1052 * with controller locked, irqs blocked
1053 * acts as a NOP unless some role activated the hardware
1054 */
1055void musb_stop(struct musb *musb)
1056{
1057 /* stop IRQs, timers, ... */
1058 musb_platform_disable(musb);
1059 musb_generic_disable(musb);
5c8a86e1 1060 dev_dbg(musb->controller, "HDRC disabled\n");
550a7375
FB		 1061
1062 /* FIXME
1063 * - mark host and/or peripheral drivers unusable/inactive
1064 * - disable DMA (and enable it in HdrcStart)
1065 * - make sure we can musb_start() after musb_stop(); with
1066 * OTG mode, gadget driver module rmmod/modprobe cycles that
1067 * - ...
1068 */
1069 musb_platform_try_idle(musb, 0);
1070}
1071
1072static void musb_shutdown(struct platform_device *pdev)
1073{
1074 struct musb *musb = dev_to_musb(&pdev->dev);
1075 unsigned long flags;
1076
4f9edd2d 1077 pm_runtime_get_sync(musb->controller);
24307cae 1078
2cc65fea 1079 musb_host_cleanup(musb);
24307cae
GI		 1080 musb_gadget_cleanup(musb);
1081
550a7375
FB		 1082 spin_lock_irqsave(&musb->lock, flags);
1083 musb_platform_disable(musb);
1084 musb_generic_disable(musb);
550a7375
FB		 1085 spin_unlock_irqrestore(&musb->lock, flags);
1086
120d074c
GI		 1087 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1088 musb_platform_exit(musb);
120d074c 1089
4f9edd2d 1090 pm_runtime_put(musb->controller);
550a7375
FB		 1091 /* FIXME power down */
1092}
1093
1094
1095/*-------------------------------------------------------------------------*/
1096
1097/*
1098 * The silicon either has hard-wired endpoint configurations, or else
1099 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1100 * writing only the dynamic sizing is very well tested. Since we switched
1101 * away from compile-time hardware parameters, we can no longer rely on
1102 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1103 *
1104 * We don't currently use dynamic fifo setup capability to do anything
1105 * more than selecting one of a bunch of predefined configurations.
1106 */
8a77f05a 1107static ushort fifo_mode;
550a7375
FB		 1108
1109/* "modprobe ... fifo_mode=1" etc */
1110module_param(fifo_mode, ushort, 0);
1111MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1112
550a7375
FB		 1113/*
1114 * tables defining fifo_mode values. define more if you like.
1115 * for host side, make sure both halves of ep1 are set up.
1116 */
1117
1118/* mode 0 - fits in 2KB */
d3608b6d 1119static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1120{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1121{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1122{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1123{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1124{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1125};
1126
1127/* mode 1 - fits in 4KB */
d3608b6d 1128static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1129{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1130{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1131{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1132{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1133{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1134};
1135
1136/* mode 2 - fits in 4KB */
d3608b6d 1137static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1138{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1139{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1140{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1141{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1142{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1143{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1144};
1145
1146/* mode 3 - fits in 4KB */
d3608b6d 1147static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1148{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1149{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1150{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1151{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1152{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1153{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1154};
1155
1156/* mode 4 - fits in 16KB */
d3608b6d 1157static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1158{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1159{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1160{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1161{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1162{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1163{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1164{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1165{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1166{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1167{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1168{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1169{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1170{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1171{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1172{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1173{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1174{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1175{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1176{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1177{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1178{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1179{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1180{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1181{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1182{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1183{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1184{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1185};
1186
3b151526 1187/* mode 5 - fits in 8KB */
d3608b6d 1188static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1189{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1190{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1191{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1192{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1193{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1194{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1195{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1196{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1197{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1198{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1199{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1200{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1201{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1202{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1203{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1204{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1205{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1206{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1207{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1208{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1209{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1210{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1211{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1212{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1213{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1214{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1215{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1216};
550a7375
FB		 1217
1218/*
1219 * configure a fifo; for non-shared endpoints, this may be called
1220 * once for a tx fifo and once for an rx fifo.
1221 *
1222 * returns negative errno or offset for next fifo.
1223 */
41ac7b3a 1224static int
550a7375 1225fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1226 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1227{
1228 void __iomem *mbase = musb->mregs;
1229 int size = 0;
1230 u16 maxpacket = cfg->maxpacket;
1231 u16 c_off = offset >> 3;
1232 u8 c_size;
1233
1234 /* expect hw_ep has already been zero-initialized */
1235
1236 size = ffs(max(maxpacket, (u16) 8)) - 1;
1237 maxpacket = 1 << size;
1238
1239 c_size = size - 3;
1240 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1241 if ((offset + (maxpacket << 1)) >
1242 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1243 return -EMSGSIZE;
1244 c_size |= MUSB_FIFOSZ_DPB;
1245 } else {
ca6d1b13 1246 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1247 return -EMSGSIZE;
1248 }
1249
1250 /* configure the FIFO */
1251 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1252
550a7375 1253 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1254 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1255 */
1256 if (hw_ep->epnum == 1)
1257 musb->bulk_ep = hw_ep;
1258 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1259 switch (cfg->style) {
1260 case FIFO_TX:
c6cf8b00
BW		 1261 musb_write_txfifosz(mbase, c_size);
1262 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1263 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1264 hw_ep->max_packet_sz_tx = maxpacket;
1265 break;
1266 case FIFO_RX:
c6cf8b00
BW		 1267 musb_write_rxfifosz(mbase, c_size);
1268 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1269 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1270 hw_ep->max_packet_sz_rx = maxpacket;
1271 break;
1272 case FIFO_RXTX:
c6cf8b00
BW		 1273 musb_write_txfifosz(mbase, c_size);
1274 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1275 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1276 hw_ep->max_packet_sz_rx = maxpacket;
1277
c6cf8b00
BW		 1278 musb_write_rxfifosz(mbase, c_size);
1279 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1280 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1281 hw_ep->max_packet_sz_tx = maxpacket;
1282
1283 hw_ep->is_shared_fifo = true;
1284 break;
1285 }
1286
1287 /* NOTE rx and tx endpoint irqs aren't managed separately,
1288 * which happens to be ok
1289 */
1290 musb->epmask |= (1 << hw_ep->epnum);
1291
1292 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1293}
1294
d3608b6d 1295static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1296 .style = FIFO_RXTX, .maxpacket = 64,
1297};
1298
41ac7b3a 1299static int ep_config_from_table(struct musb *musb)
550a7375 1300{
e6c213b2 1301 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1302 unsigned i, n;
1303 int offset;
1304 struct musb_hw_ep *hw_ep = musb->endpoints;
1305
e6c213b2
FB		 1306 if (musb->config->fifo_cfg) {
1307 cfg = musb->config->fifo_cfg;
1308 n = musb->config->fifo_cfg_size;
1309 goto done;
1310 }
1311
550a7375
FB		 1312 switch (fifo_mode) {
1313 default:
1314 fifo_mode = 0;
1315 /* FALLTHROUGH */
1316 case 0:
1317 cfg = mode_0_cfg;
1318 n = ARRAY_SIZE(mode_0_cfg);
1319 break;
1320 case 1:
1321 cfg = mode_1_cfg;
1322 n = ARRAY_SIZE(mode_1_cfg);
1323 break;
1324 case 2:
1325 cfg = mode_2_cfg;
1326 n = ARRAY_SIZE(mode_2_cfg);
1327 break;
1328 case 3:
1329 cfg = mode_3_cfg;
1330 n = ARRAY_SIZE(mode_3_cfg);
1331 break;
1332 case 4:
1333 cfg = mode_4_cfg;
1334 n = ARRAY_SIZE(mode_4_cfg);
1335 break;
3b151526
AKG		 1336 case 5:
1337 cfg = mode_5_cfg;
1338 n = ARRAY_SIZE(mode_5_cfg);
1339 break;
550a7375
FB		 1340 }
1341
1342 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1343 musb_driver_name, fifo_mode);
1344
1345
e6c213b2 1346done:
550a7375
FB		 1347 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1348 /* assert(offset > 0) */
1349
1350 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1351 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1352 */
1353
1354 for (i = 0; i < n; i++) {
1355 u8 epn = cfg->hw_ep_num;
1356
ca6d1b13 1357 if (epn >= musb->config->num_eps) {
550a7375
FB		 1358 pr_debug("%s: invalid ep %d\n",
1359 musb_driver_name, epn);
bb1c9ef1 1360 return -EINVAL;
550a7375
FB		 1361 }
1362 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1363 if (offset < 0) {
1364 pr_debug("%s: mem overrun, ep %d\n",
1365 musb_driver_name, epn);
f69dfa1f 1366 return offset;
550a7375
FB		 1367 }
1368 epn++;
1369 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1370 }
1371
1372 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1373 musb_driver_name,
ca6d1b13
FB		 1374 n + 1, musb->config->num_eps * 2 - 1,
1375 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1376
550a7375
FB		 1377 if (!musb->bulk_ep) {
1378 pr_debug("%s: missing bulk\n", musb_driver_name);
1379 return -EINVAL;
1380 }
550a7375
FB		 1381
1382 return 0;
1383}
1384
1385
1386/*
1387 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1388 * @param musb the controller
1389 */
41ac7b3a 1390static int ep_config_from_hw(struct musb *musb)
550a7375 1391{
c6cf8b00 1392 u8 epnum = 0;
550a7375 1393 struct musb_hw_ep *hw_ep;
a156544b 1394 void __iomem *mbase = musb->mregs;
c6cf8b00 1395 int ret = 0;
550a7375 1396
5c8a86e1 1397 dev_dbg(musb->controller, "<== static silicon ep config\n");
550a7375
FB		 1398
1399 /* FIXME pick up ep0 maxpacket size */
1400
ca6d1b13 1401 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1402 musb_ep_select(mbase, epnum);
1403 hw_ep = musb->endpoints + epnum;
1404
c6cf8b00
BW		 1405 ret = musb_read_fifosize(musb, hw_ep, epnum);
1406 if (ret < 0)
550a7375 1407 break;
550a7375
FB		 1408
1409 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1410
550a7375
FB		 1411 /* pick an RX/TX endpoint for bulk */
1412 if (hw_ep->max_packet_sz_tx < 512
1413 || hw_ep->max_packet_sz_rx < 512)
1414 continue;
1415
1416 /* REVISIT: this algorithm is lazy, we should at least
1417 * try to pick a double buffered endpoint.
1418 */
1419 if (musb->bulk_ep)
1420 continue;
1421 musb->bulk_ep = hw_ep;
550a7375
FB		 1422 }
1423
550a7375
FB		 1424 if (!musb->bulk_ep) {
1425 pr_debug("%s: missing bulk\n", musb_driver_name);
1426 return -EINVAL;
1427 }
550a7375
FB		 1428
1429 return 0;
1430}
1431
1432enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1433
1434/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1435 * configure endpoints, or take their config from silicon
1436 */
41ac7b3a 1437static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1438{
550a7375
FB		 1439 u8 reg;
1440 char *type;
0ea52ff4 1441 char aInfo[90], aRevision[32], aDate[12];
550a7375
FB		 1442 void __iomem *mbase = musb->mregs;
1443 int status = 0;
1444 int i;
1445
1446 /* log core options (read using indexed model) */
c6cf8b00 1447 reg = musb_read_configdata(mbase);
550a7375
FB		 1448
1449 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1450 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1451 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1452 musb->dyn_fifo = true;
1453 }
550a7375
FB		 1454 if (reg & MUSB_CONFIGDATA_MPRXE) {
1455 strcat(aInfo, ", bulk combine");
550a7375 1456 musb->bulk_combine = true;
550a7375
FB		 1457 }
1458 if (reg & MUSB_CONFIGDATA_MPTXE) {
1459 strcat(aInfo, ", bulk split");
550a7375 1460 musb->bulk_split = true;
550a7375
FB		 1461 }
1462 if (reg & MUSB_CONFIGDATA_HBRXE) {
1463 strcat(aInfo, ", HB-ISO Rx");
a483d706 1464 musb->hb_iso_rx = true;
550a7375
FB		 1465 }
1466 if (reg & MUSB_CONFIGDATA_HBTXE) {
1467 strcat(aInfo, ", HB-ISO Tx");
a483d706 1468 musb->hb_iso_tx = true;
550a7375
FB		 1469 }
1470 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1471 strcat(aInfo, ", SoftConn");
1472
1473 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1474 musb_driver_name, reg, aInfo);
1475
550a7375 1476 aDate[0] = 0;
550a7375
FB		 1477 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1478 musb->is_multipoint = 1;
1479 type = "M";
1480 } else {
1481 musb->is_multipoint = 0;
1482 type = "";
550a7375
FB		 1483#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1484 printk(KERN_ERR
1485 "%s: kernel must blacklist external hubs\n",
1486 musb_driver_name);
550a7375
FB		 1487#endif
1488 }
1489
1490 /* log release info */
32c3b94e
AG		 1491 musb->hwvers = musb_read_hwvers(mbase);
1492 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1493 MUSB_HWVERS_MINOR(musb->hwvers),
1494 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1495 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1496 musb_driver_name, type, aRevision, aDate);
1497
1498 /* configure ep0 */
c6cf8b00 1499 musb_configure_ep0(musb);
550a7375
FB		 1500
1501 /* discover endpoint configuration */
1502 musb->nr_endpoints = 1;
1503 musb->epmask = 1;
1504
ad517e9e
FB		 1505 if (musb->dyn_fifo)
1506 status = ep_config_from_table(musb);
1507 else
1508 status = ep_config_from_hw(musb);
550a7375
FB		 1509
1510 if (status < 0)
1511 return status;
1512
1513 /* finish init, and print endpoint config */
1514 for (i = 0; i < musb->nr_endpoints; i++) {
1515 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1516
1b40fc57 1517 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
ebf39920 1518#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1b40fc57
TL		 1519 if (musb->io.quirks & MUSB_IN_TUSB) {
1520 hw_ep->fifo_async = musb->async + 0x400 +
1521 musb->io.fifo_offset(i);
1522 hw_ep->fifo_sync = musb->sync + 0x400 +
1523 musb->io.fifo_offset(i);
1524 hw_ep->fifo_sync_va =
1525 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1526
1527 if (i == 0)
1528 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1529 else
1530 hw_ep->conf = mbase + 0x400 +
1531 (((i - 1) & 0xf) << 2);
1532 }
550a7375
FB		 1533#endif
1534
d026e9c7 1535 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
c6cf8b00 1536 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
550a7375
FB		 1537 hw_ep->rx_reinit = 1;
1538 hw_ep->tx_reinit = 1;
550a7375
FB		 1539
1540 if (hw_ep->max_packet_sz_tx) {
5c8a86e1 1541 dev_dbg(musb->controller,
550a7375
FB		 1542 "%s: hw_ep %d%s, %smax %d\n",
1543 musb_driver_name, i,
1544 hw_ep->is_shared_fifo ? "shared" : "tx",
1545 hw_ep->tx_double_buffered
1546 ? "doublebuffer, " : "",
1547 hw_ep->max_packet_sz_tx);
1548 }
1549 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
5c8a86e1 1550 dev_dbg(musb->controller,
550a7375
FB		 1551 "%s: hw_ep %d%s, %smax %d\n",
1552 musb_driver_name, i,
1553 "rx",
1554 hw_ep->rx_double_buffered
1555 ? "doublebuffer, " : "",
1556 hw_ep->max_packet_sz_rx);
1557 }
1558 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
5c8a86e1 1559 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
550a7375
FB		 1560 }
1561
1562 return 0;
1563}
1564
1565/*-------------------------------------------------------------------------*/
1566
550a7375
FB		 1567/*
1568 * handle all the irqs defined by the HDRC core. for now we expect: other
1569 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1570 * will be assigned, and the irq will already have been acked.
1571 *
1572 * called in irq context with spinlock held, irqs blocked
1573 */
1574irqreturn_t musb_interrupt(struct musb *musb)
1575{
1576 irqreturn_t retval = IRQ_NONE;
31a0ede0
FB		 1577 unsigned long status;
1578 unsigned long epnum;
b11e94d0 1579 u8 devctl;
31a0ede0
FB		 1580
1581 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1582 return IRQ_NONE;
550a7375
FB		 1583
1584 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1585
5c8a86e1 1586 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
c03da38d 1587 is_host_active(musb) ? "host" : "peripheral",
550a7375
FB		 1588 musb->int_usb, musb->int_tx, musb->int_rx);
1589
e3c93e1a
FB		 1590 /**
1591 * According to Mentor Graphics' documentation, flowchart on page 98,
1592 * IRQ should be handled as follows:
1593 *
1594 * . Resume IRQ
1595 * . Session Request IRQ
1596 * . VBUS Error IRQ
1597 * . Suspend IRQ
1598 * . Connect IRQ
1599 * . Disconnect IRQ
1600 * . Reset/Babble IRQ
1601 * . SOF IRQ (we're not using this one)
1602 * . Endpoint 0 IRQ
1603 * . TX Endpoints
1604 * . RX Endpoints
1605 *
1606 * We will be following that flowchart in order to avoid any problems
1607 * that might arise with internal Finite State Machine.
550a7375 1608 */
e3c93e1a 1609
7d9645fd 1610 if (musb->int_usb)
31a0ede0 1611 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
550a7375 1612
550a7375 1613 if (musb->int_tx & 1) {
c03da38d 1614 if (is_host_active(musb))
550a7375
FB		 1615 retval |= musb_h_ep0_irq(musb);
1616 else
1617 retval |= musb_g_ep0_irq(musb);
31a0ede0
FB		 1618
1619 /* we have just handled endpoint 0 IRQ, clear it */
1620 musb->int_tx &= ~BIT(0);
550a7375
FB		 1621 }
1622
31a0ede0
FB		 1623 status = musb->int_tx;
1624
1625 for_each_set_bit(epnum, &status, 16) {
1626 retval = IRQ_HANDLED;
1627 if (is_host_active(musb))
1628 musb_host_tx(musb, epnum);
1629 else
1630 musb_g_tx(musb, epnum);
550a7375
FB		 1631 }
1632
31a0ede0 1633 status = musb->int_rx;
e3c93e1a 1634
31a0ede0
FB		 1635 for_each_set_bit(epnum, &status, 16) {
1636 retval = IRQ_HANDLED;
1637 if (is_host_active(musb))
1638 musb_host_rx(musb, epnum);
1639 else
1640 musb_g_rx(musb, epnum);
550a7375
FB		 1641 }
1642
550a7375
FB		 1643 return retval;
1644}
981430a1 1645EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1646
1647#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1648static bool use_dma = 1;
550a7375
FB		 1649
1650/* "modprobe ... use_dma=0" etc */
1651module_param(use_dma, bool, 0);
1652MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1653
1654void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1655{
550a7375
FB		 1656 /* called with controller lock already held */
1657
1658 if (!epnum) {
1659#ifndef CONFIG_USB_TUSB_OMAP_DMA
1660 if (!is_cppi_enabled()) {
1661 /* endpoint 0 */
c03da38d 1662 if (is_host_active(musb))
550a7375
FB		 1663 musb_h_ep0_irq(musb);
1664 else
1665 musb_g_ep0_irq(musb);
1666 }
1667#endif
1668 } else {
1669 /* endpoints 1..15 */
1670 if (transmit) {
c03da38d 1671 if (is_host_active(musb))
a04d46d0
FB		 1672 musb_host_tx(musb, epnum);
1673 else
1674 musb_g_tx(musb, epnum);
550a7375
FB		 1675 } else {
1676 /* receive */
c03da38d 1677 if (is_host_active(musb))
a04d46d0
FB		 1678 musb_host_rx(musb, epnum);
1679 else
1680 musb_g_rx(musb, epnum);
550a7375
FB		 1681 }
1682 }
1683}
9a35f876 1684EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1685
1686#else
1687#define use_dma 0
1688#endif
1689
1690/*-------------------------------------------------------------------------*/
1691
550a7375
FB		 1692static ssize_t
1693musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1694{
1695 struct musb *musb = dev_to_musb(dev);
1696 unsigned long flags;
1697 int ret = -EINVAL;
1698
1699 spin_lock_irqsave(&musb->lock, flags);
e47d9254 1700 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 1701 spin_unlock_irqrestore(&musb->lock, flags);
1702
1703 return ret;
1704}
1705
1706static ssize_t
1707musb_mode_store(struct device *dev, struct device_attribute *attr,
1708 const char *buf, size_t n)
1709{
1710 struct musb *musb = dev_to_musb(dev);
1711 unsigned long flags;
96a274d1 1712 int status;
550a7375
FB		 1713
1714 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1715 if (sysfs_streq(buf, "host"))
1716 status = musb_platform_set_mode(musb, MUSB_HOST);
1717 else if (sysfs_streq(buf, "peripheral"))
1718 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1719 else if (sysfs_streq(buf, "otg"))
1720 status = musb_platform_set_mode(musb, MUSB_OTG);
1721 else
1722 status = -EINVAL;
550a7375
FB		 1723 spin_unlock_irqrestore(&musb->lock, flags);
1724
96a274d1 1725 return (status == 0) ? n : status;
550a7375
FB		 1726}
1727static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1728
1729static ssize_t
1730musb_vbus_store(struct device *dev, struct device_attribute *attr,
1731 const char *buf, size_t n)
1732{
1733 struct musb *musb = dev_to_musb(dev);
1734 unsigned long flags;
1735 unsigned long val;
1736
1737 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1738 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1739 return -EINVAL;
1740 }
1741
1742 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1743 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1744 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
e47d9254 1745 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1746 musb->is_active = 0;
1747 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1748 spin_unlock_irqrestore(&musb->lock, flags);
1749
1750 return n;
1751}
1752
1753static ssize_t
1754musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1755{
1756 struct musb *musb = dev_to_musb(dev);
1757 unsigned long flags;
1758 unsigned long val;
1759 int vbus;
1760
1761 spin_lock_irqsave(&musb->lock, flags);
1762 val = musb->a_wait_bcon;
f7f9d63e
DB		 1763 /* FIXME get_vbus_status() is normally #defined as false...
1764 * and is effectively TUSB-specific.
1765 */
550a7375
FB		 1766 vbus = musb_platform_get_vbus_status(musb);
1767 spin_unlock_irqrestore(&musb->lock, flags);
1768
f7f9d63e 1769 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1770 vbus ? "on" : "off", val);
1771}
1772static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1773
550a7375
FB		 1774/* Gadget drivers can't know that a host is connected so they might want
1775 * to start SRP, but users can. This allows userspace to trigger SRP.
1776 */
1777static ssize_t
1778musb_srp_store(struct device *dev, struct device_attribute *attr,
1779 const char *buf, size_t n)
1780{
1781 struct musb *musb = dev_to_musb(dev);
1782 unsigned short srp;
1783
1784 if (sscanf(buf, "%hu", &srp) != 1
1785 || (srp != 1)) {
b3b1cc3b 1786 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1787 return -EINVAL;
1788 }
1789
1790 if (srp == 1)
1791 musb_g_wakeup(musb);
1792
1793 return n;
1794}
1795static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1796
94375751
FB		 1797static struct attribute *musb_attributes[] = {
1798 &dev_attr_mode.attr,
1799 &dev_attr_vbus.attr,
94375751 1800 &dev_attr_srp.attr,
94375751
FB		 1801 NULL
1802};
1803
1804static const struct attribute_group musb_attr_group = {
1805 .attrs = musb_attributes,
1806};
1807
550a7375
FB		 1808/* Only used to provide driver mode change events */
1809static void musb_irq_work(struct work_struct *data)
1810{
1811 struct musb *musb = container_of(data, struct musb, irq_work);
550a7375 1812
e47d9254
AT		 1813 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1814 musb->xceiv_old_state = musb->xceiv->otg->state;
550a7375
FB		 1815 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1816 }
1817}
1818
ca88fc2e
DM		 1819/* Recover from babble interrupt conditions */
1820static void musb_recover_work(struct work_struct *data)
1821{
675ae763 1822 struct musb *musb = container_of(data, struct musb, recover_work.work);
d871c622 1823 int status, ret;
ca88fc2e 1824
d871c622
GC		 1825 ret = musb_platform_reset(musb);
1826 if (ret)
1827 return;
ca88fc2e
DM		 1828
1829 usb_phy_vbus_off(musb->xceiv);
675ae763 1830 usleep_range(100, 200);
ca88fc2e
DM		 1831
1832 usb_phy_vbus_on(musb->xceiv);
675ae763 1833 usleep_range(100, 200);
ca88fc2e
DM		 1834
1835 /*
d871c622
GC		 1836 * When a babble condition occurs, the musb controller
1837 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1838 */
1839 if (musb->dyn_fifo)
1840 status = ep_config_from_table(musb);
1841 else
1842 status = ep_config_from_hw(musb);
1843
1844 /* start the session again */
1845 if (status == 0)
1846 musb_start(musb);
1847}
1848
550a7375
FB		 1849/* --------------------------------------------------------------------------
1850 * Init support
1851 */
1852
41ac7b3a 1853static struct musb *allocate_instance(struct device *dev,
ca6d1b13 1854 struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1855{
1856 struct musb *musb;
1857 struct musb_hw_ep *ep;
1858 int epnum;
74c2e936 1859 int ret;
550a7375 1860
74c2e936
DM		 1861 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1862 if (!musb)
550a7375 1863 return NULL;
550a7375 1864
550a7375
FB		 1865 INIT_LIST_HEAD(&musb->control);
1866 INIT_LIST_HEAD(&musb->in_bulk);
1867 INIT_LIST_HEAD(&musb->out_bulk);
1868
550a7375 1869 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1870 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 1871 musb->mregs = mbase;
1872 musb->ctrl_base = mbase;
1873 musb->nIrq = -ENODEV;
ca6d1b13 1874 musb->config = config;
02582b92 1875 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1876 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1877 epnum < musb->config->num_eps;
550a7375 1878 epnum++, ep++) {
550a7375
FB		 1879 ep->musb = musb;
1880 ep->epnum = epnum;
1881 }
1882
1883 musb->controller = dev;
743411b3 1884
74c2e936
DM		 1885 ret = musb_host_alloc(musb);
1886 if (ret < 0)
1887 goto err_free;
1888
1889 dev_set_drvdata(dev, musb);
1890
550a7375 1891 return musb;
74c2e936
DM		 1892
1893err_free:
1894 return NULL;
550a7375
FB		 1895}
1896
1897static void musb_free(struct musb *musb)
1898{
1899 /* this has multiple entry modes. it handles fault cleanup after
1900 * probe(), where things may be partially set up, as well as rmmod
1901 * cleanup after everything's been de-activated.
1902 */
1903
1904#ifdef CONFIG_SYSFS
94375751 1905 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 1906#endif
1907
97a39896
AKG		 1908 if (musb->nIrq >= 0) {
1909 if (musb->irq_wake)
1910 disable_irq_wake(musb->nIrq);
550a7375
FB		 1911 free_irq(musb->nIrq, musb);
1912 }
550a7375 1913
74c2e936 1914 musb_host_free(musb);
550a7375
FB		 1915}
1916
8ed1fb79
DM		 1917static void musb_deassert_reset(struct work_struct *work)
1918{
1919 struct musb *musb;
1920 unsigned long flags;
1921
1922 musb = container_of(work, struct musb, deassert_reset_work.work);
1923
1924 spin_lock_irqsave(&musb->lock, flags);
1925
1926 if (musb->port1_status & USB_PORT_STAT_RESET)
1927 musb_port_reset(musb, false);
1928
1929 spin_unlock_irqrestore(&musb->lock, flags);
1930}
1931
550a7375
FB		 1932/*
1933 * Perform generic per-controller initialization.
1934 *
28dd924a
SS		 1935 * @dev: the controller (already clocked, etc)
1936 * @nIrq: IRQ number
1937 * @ctrl: virtual address of controller registers,
550a7375
FB		 1938 * not yet corrected for platform-specific offsets
1939 */
41ac7b3a 1940static int
550a7375
FB		 1941musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1942{
1943 int status;
1944 struct musb *musb;
c1a7d67c 1945 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 1946
1947 /* The driver might handle more features than the board; OK.
1948 * Fail when the board needs a feature that's not enabled.
1949 */
1950 if (!plat) {
1951 dev_dbg(dev, "no platform_data?\n");
34e2beb2
SS		 1952 status = -ENODEV;
1953 goto fail0;
550a7375 1954 }
34e2beb2 1955
550a7375 1956 /* allocate */
ca6d1b13 1957 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 1958 if (!musb) {
1959 status = -ENOMEM;
1960 goto fail0;
1961 }
550a7375
FB		 1962
1963 spin_lock_init(&musb->lock);
550a7375 1964 musb->board_set_power = plat->set_power;
550a7375 1965 musb->min_power = plat->min_power;
f7ec9437 1966 musb->ops = plat->platform_ops;
9ad96e69 1967 musb->port_mode = plat->mode;
550a7375 1968
1b40fc57
TL		 1969 /*
1970 * Initialize the default IO functions. At least omap2430 needs
1971 * these early. We initialize the platform specific IO functions
1972 * later on.
1973 */
1974 musb_readb = musb_default_readb;
1975 musb_writeb = musb_default_writeb;
1976 musb_readw = musb_default_readw;
1977 musb_writew = musb_default_writew;
1978 musb_readl = musb_default_readl;
1979 musb_writel = musb_default_writel;
1980
3e43a072
FB		 1981 /* We need musb_read/write functions initialized for PM */
1982 pm_runtime_use_autosuspend(musb->controller);
1983 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1984 pm_runtime_irq_safe(musb->controller);
1985 pm_runtime_enable(musb->controller);
1986
84e250ff 1987 /* The musb_platform_init() call:
baef653a
PDS		 1988 * - adjusts musb->mregs
1989 * - sets the musb->isr
5ae477b0 1990 * - may initialize an integrated transceiver
721002ec 1991 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 1992 * - stops powering VBUS
84e250ff 1993 *
7c9d440e 1994 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 1995 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1996 * external/discrete ones in various flavors (twl4030 family,
1997 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 1998 */
ea65df57 1999 status = musb_platform_init(musb);
550a7375 2000 if (status < 0)
03491761 2001 goto fail1;
34e2beb2 2002
550a7375
FB		 2003 if (!musb->isr) {
2004 status = -ENODEV;
c04352a5 2005 goto fail2;
550a7375
FB		 2006 }
2007
1b40fc57
TL		 2008 if (musb->ops->quirks)
2009 musb->io.quirks = musb->ops->quirks;
2010
d026e9c7
TL		 2011 /* At least tusb6010 has it's own offsets.. */
2012 if (musb->ops->ep_offset)
2013 musb->io.ep_offset = musb->ops->ep_offset;
2014 if (musb->ops->ep_select)
2015 musb->io.ep_select = musb->ops->ep_select;
2016
2017 /* ..and some devices use indexed offset or flat offset */
2018 if (musb->io.quirks & MUSB_INDEXED_EP) {
2019 musb->io.ep_offset = musb_indexed_ep_offset;
2020 musb->io.ep_select = musb_indexed_ep_select;
2021 } else {
2022 musb->io.ep_offset = musb_flat_ep_offset;
2023 musb->io.ep_select = musb_flat_ep_select;
2024 }
2025
8a77f05a
TL		 2026 if (musb->ops->fifo_mode)
2027 fifo_mode = musb->ops->fifo_mode;
2028 else
2029 fifo_mode = 4;
2030
1b40fc57
TL		 2031 if (musb->ops->fifo_offset)
2032 musb->io.fifo_offset = musb->ops->fifo_offset;
2033 else
2034 musb->io.fifo_offset = musb_default_fifo_offset;
2035
2036 if (musb->ops->readb)
2037 musb_readb = musb->ops->readb;
2038 if (musb->ops->writeb)
2039 musb_writeb = musb->ops->writeb;
2040 if (musb->ops->readw)
2041 musb_readw = musb->ops->readw;
2042 if (musb->ops->writew)
2043 musb_writew = musb->ops->writew;
2044 if (musb->ops->readl)
2045 musb_readl = musb->ops->readl;
2046 if (musb->ops->writel)
2047 musb_writel = musb->ops->writel;
2048
2049 if (musb->ops->read_fifo)
2050 musb->io.read_fifo = musb->ops->read_fifo;
2051 else
2052 musb->io.read_fifo = musb_default_read_fifo;
2053
2054 if (musb->ops->write_fifo)
2055 musb->io.write_fifo = musb->ops->write_fifo;
2056 else
2057 musb->io.write_fifo = musb_default_write_fifo;
2058
ffb865b1 2059 if (!musb->xceiv->io_ops) {
bf070bc1 2060 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 2061 musb->xceiv->io_priv = musb->mregs;
2062 musb->xceiv->io_ops = &musb_ulpi_access;
2063 }
2064
c04352a5
GI		 2065 pm_runtime_get_sync(musb->controller);
2066
48054147 2067 if (use_dma && dev->dma_mask) {
66c01883 2068 musb->dma_controller = dma_controller_create(musb, musb->mregs);
48054147
SAS		 2069 if (IS_ERR(musb->dma_controller)) {
2070 status = PTR_ERR(musb->dma_controller);
2071 goto fail2_5;
2072 }
2073 }
550a7375
FB		 2074
2075 /* be sure interrupts are disabled before connecting ISR */
2076 musb_platform_disable(musb);
2077 musb_generic_disable(musb);
2078
66fadea5
SAS		 2079 /* Init IRQ workqueue before request_irq */
2080 INIT_WORK(&musb->irq_work, musb_irq_work);
675ae763 2081 INIT_DELAYED_WORK(&musb->recover_work, musb_recover_work);
8ed1fb79
DM		 2082 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2083 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 2084
550a7375 2085 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 2086 status = musb_core_init(plat->config->multipoint
550a7375
FB		 2087 ? MUSB_CONTROLLER_MHDRC
2088 : MUSB_CONTROLLER_HDRC, musb);
2089 if (status < 0)
34e2beb2 2090 goto fail3;
550a7375 2091
f7f9d63e 2092 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 2093
550a7375 2094 /* attach to the IRQ */
427c4f33 2095 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 2096 dev_err(dev, "request_irq %d failed!\n", nIrq);
2097 status = -ENODEV;
34e2beb2 2098 goto fail3;
550a7375
FB		 2099 }
2100 musb->nIrq = nIrq;
032ec49f 2101 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2102 if (enable_irq_wake(nIrq) == 0) {
2103 musb->irq_wake = 1;
550a7375 2104 device_init_wakeup(dev, 1);
c48a5155
FB		 2105 } else {
2106 musb->irq_wake = 0;
2107 }
550a7375 2108
032ec49f
FB		 2109 /* program PHY to use external vBus if required */
2110 if (plat->extvbus) {
2111 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2112 busctl |= MUSB_ULPI_USE_EXTVBUS;
2113 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 2114 }
550a7375 2115
e5615112
GI		 2116 if (musb->xceiv->otg->default_a) {
2117 MUSB_HST_MODE(musb);
e47d9254 2118 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
e5615112
GI		 2119 } else {
2120 MUSB_DEV_MODE(musb);
e47d9254 2121 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
e5615112 2122 }
550a7375 2123
6c5f6a6f
DM		 2124 switch (musb->port_mode) {
2125 case MUSB_PORT_MODE_HOST:
2126 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 2127 if (status < 0)
2128 goto fail3;
2129 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f
DM		 2130 break;
2131 case MUSB_PORT_MODE_GADGET:
2132 status = musb_gadget_setup(musb);
2df6761e
FB		 2133 if (status < 0)
2134 goto fail3;
2135 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f
DM		 2136 break;
2137 case MUSB_PORT_MODE_DUAL_ROLE:
2138 status = musb_host_setup(musb, plat->power);
2139 if (status < 0)
2140 goto fail3;
2141 status = musb_gadget_setup(musb);
2df6761e 2142 if (status) {
0d2dd7ea 2143 musb_host_cleanup(musb);
2df6761e
FB		 2144 goto fail3;
2145 }
2146 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2147 break;
2148 default:
2149 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2150 break;
2151 }
550a7375 2152
461972d8 2153 if (status < 0)
34e2beb2 2154 goto fail3;
550a7375 2155
7f7f9e2a
FB		 2156 status = musb_init_debugfs(musb);
2157 if (status < 0)
b0f9da7e 2158 goto fail4;
7f7f9e2a 2159
94375751 2160 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2161 if (status)
b0f9da7e 2162 goto fail5;
550a7375 2163
c04352a5
GI		 2164 pm_runtime_put(musb->controller);
2165
28c2c51c 2166 return 0;
550a7375 2167
b0f9da7e
FB		 2168fail5:
2169 musb_exit_debugfs(musb);
2170
34e2beb2 2171fail4:
032ec49f 2172 musb_gadget_cleanup(musb);
0d2dd7ea 2173 musb_host_cleanup(musb);
34e2beb2
SS		 2174
2175fail3:
66fadea5 2176 cancel_work_sync(&musb->irq_work);
675ae763 2177 cancel_delayed_work_sync(&musb->recover_work);
8ed1fb79
DM		 2178 cancel_delayed_work_sync(&musb->finish_resume_work);
2179 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b
SAS		 2180 if (musb->dma_controller)
2181 dma_controller_destroy(musb->dma_controller);
48054147 2182fail2_5:
c04352a5
GI		 2183 pm_runtime_put_sync(musb->controller);
2184
2185fail2:
34e2beb2
SS		 2186 if (musb->irq_wake)
2187 device_init_wakeup(dev, 0);
550a7375 2188 musb_platform_exit(musb);
28c2c51c 2189
34e2beb2 2190fail1:
681d1e87 2191 pm_runtime_disable(musb->controller);
34e2beb2
SS		 2192 dev_err(musb->controller,
2193 "musb_init_controller failed with status %d\n", status);
2194
28c2c51c
FB		 2195 musb_free(musb);
2196
34e2beb2
SS		 2197fail0:
2198
28c2c51c
FB		 2199 return status;
2200
550a7375
FB		 2201}
2202
2203/*-------------------------------------------------------------------------*/
2204
2205/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2206 * bridge to a platform device; this driver then suffices.
2207 */
41ac7b3a 2208static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2209{
2210 struct device *dev = &pdev->dev;
fcf173e4 2211 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2212 struct resource *iomem;
2213 void __iomem *base;
2214
1f79b26c 2215 if (irq <= 0)
550a7375
FB		 2216 return -ENODEV;
2217
1f79b26c 2218 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b42f7f30
FB		 2219 base = devm_ioremap_resource(dev, iomem);
2220 if (IS_ERR(base))
2221 return PTR_ERR(base);
550a7375 2222
b42f7f30 2223 return musb_init_controller(dev, irq, base);
550a7375
FB		 2224}
2225
fb4e98ab 2226static int musb_remove(struct platform_device *pdev)
550a7375 2227{
8d2421e6
AKG		 2228 struct device *dev = &pdev->dev;
2229 struct musb *musb = dev_to_musb(dev);
550a7375
FB		 2230
2231 /* this gets called on rmmod.
2232 * - Host mode: host may still be active
2233 * - Peripheral mode: peripheral is deactivated (or never-activated)
2234 * - OTG mode: both roles are deactivated (or never-activated)
2235 */
7f7f9e2a 2236 musb_exit_debugfs(musb);
550a7375 2237 musb_shutdown(pdev);
461972d8 2238
8d1aad74
SAS		 2239 if (musb->dma_controller)
2240 dma_controller_destroy(musb->dma_controller);
2241
66fadea5 2242 cancel_work_sync(&musb->irq_work);
675ae763 2243 cancel_delayed_work_sync(&musb->recover_work);
8ed1fb79
DM		 2244 cancel_delayed_work_sync(&musb->finish_resume_work);
2245 cancel_delayed_work_sync(&musb->deassert_reset_work);
550a7375 2246 musb_free(musb);
8d2421e6 2247 device_init_wakeup(dev, 0);
550a7375
FB		 2248 return 0;
2249}
2250
2251#ifdef CONFIG_PM
2252
3c8a5fcc 2253static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2254{
2255 int i;
2256 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2257 void __iomem *epio;
4f712e01 2258
032ec49f
FB		 2259 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2260 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2261 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2262 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2263 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2264 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2265 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2266
ae9b2ad2 2267 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2268 struct musb_hw_ep *hw_ep;
2269
2270 hw_ep = &musb->endpoints[i];
2271 if (!hw_ep)
2272 continue;
2273
2274 epio = hw_ep->regs;
2275 if (!epio)
2276 continue;
2277
ea737554 2278 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2279 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2280 musb_readw(epio, MUSB_TXMAXP);
7421107b 2281 musb->context.index_regs[i].txcsr =
ae9b2ad2 2282 musb_readw(epio, MUSB_TXCSR);
7421107b 2283 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2284 musb_readw(epio, MUSB_RXMAXP);
7421107b 2285 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2286 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2287
2288 if (musb->dyn_fifo) {
7421107b 2289 musb->context.index_regs[i].txfifoadd =
4f712e01 2290 musb_read_txfifoadd(musb_base);
7421107b 2291 musb->context.index_regs[i].rxfifoadd =
4f712e01 2292 musb_read_rxfifoadd(musb_base);
7421107b 2293 musb->context.index_regs[i].txfifosz =
4f712e01 2294 musb_read_txfifosz(musb_base);
7421107b 2295 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2296 musb_read_rxfifosz(musb_base);
2297 }
032ec49f
FB		 2298
2299 musb->context.index_regs[i].txtype =
2300 musb_readb(epio, MUSB_TXTYPE);
2301 musb->context.index_regs[i].txinterval =
2302 musb_readb(epio, MUSB_TXINTERVAL);
2303 musb->context.index_regs[i].rxtype =
2304 musb_readb(epio, MUSB_RXTYPE);
2305 musb->context.index_regs[i].rxinterval =
2306 musb_readb(epio, MUSB_RXINTERVAL);
2307
2308 musb->context.index_regs[i].txfunaddr =
2309 musb_read_txfunaddr(musb_base, i);
2310 musb->context.index_regs[i].txhubaddr =
2311 musb_read_txhubaddr(musb_base, i);
2312 musb->context.index_regs[i].txhubport =
2313 musb_read_txhubport(musb_base, i);
2314
2315 musb->context.index_regs[i].rxfunaddr =
2316 musb_read_rxfunaddr(musb_base, i);
2317 musb->context.index_regs[i].rxhubaddr =
2318 musb_read_rxhubaddr(musb_base, i);
2319 musb->context.index_regs[i].rxhubport =
2320 musb_read_rxhubport(musb_base, i);
4f712e01 2321 }
4f712e01
AKG		 2322}
2323
3c8a5fcc 2324static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2325{
2326 int i;
2327 void __iomem *musb_base = musb->mregs;
2328 void __iomem *ep_target_regs;
ae9b2ad2 2329 void __iomem *epio;
33f8d75f 2330 u8 power;
4f712e01 2331
032ec49f
FB		 2332 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2333 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2334 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
33f8d75f
RQ		 2335
2336 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2337 power = musb_readb(musb_base, MUSB_POWER);
2338 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2339 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2340 power |= musb->context.power;
2341 musb_writeb(musb_base, MUSB_POWER, power);
2342
b18d26f6 2343 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2344 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b
FB		 2345 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2346 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2347
ae9b2ad2 2348 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2349 struct musb_hw_ep *hw_ep;
2350
2351 hw_ep = &musb->endpoints[i];
2352 if (!hw_ep)
2353 continue;
2354
2355 epio = hw_ep->regs;
2356 if (!epio)
2357 continue;
2358
ea737554 2359 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2360 musb_writew(epio, MUSB_TXMAXP,
7421107b 2361 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2362 musb_writew(epio, MUSB_TXCSR,
7421107b 2363 musb->context.index_regs[i].txcsr);
ae9b2ad2 2364 musb_writew(epio, MUSB_RXMAXP,
7421107b 2365 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2366 musb_writew(epio, MUSB_RXCSR,
7421107b 2367 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2368
2369 if (musb->dyn_fifo) {
2370 musb_write_txfifosz(musb_base,
7421107b 2371 musb->context.index_regs[i].txfifosz);
4f712e01 2372 musb_write_rxfifosz(musb_base,
7421107b 2373 musb->context.index_regs[i].rxfifosz);
4f712e01 2374 musb_write_txfifoadd(musb_base,
7421107b 2375 musb->context.index_regs[i].txfifoadd);
4f712e01 2376 musb_write_rxfifoadd(musb_base,
7421107b 2377 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2378 }
2379
032ec49f 2380 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2381 musb->context.index_regs[i].txtype);
032ec49f 2382 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2383 musb->context.index_regs[i].txinterval);
032ec49f 2384 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2385 musb->context.index_regs[i].rxtype);
032ec49f 2386 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2387
032ec49f
FB		 2388 musb->context.index_regs[i].rxinterval);
2389 musb_write_txfunaddr(musb_base, i,
7421107b 2390 musb->context.index_regs[i].txfunaddr);
032ec49f 2391 musb_write_txhubaddr(musb_base, i,
7421107b 2392 musb->context.index_regs[i].txhubaddr);
032ec49f 2393 musb_write_txhubport(musb_base, i,
7421107b 2394 musb->context.index_regs[i].txhubport);
4f712e01 2395
032ec49f
FB		 2396 ep_target_regs =
2397 musb_read_target_reg_base(i, musb_base);
4f712e01 2398
032ec49f 2399 musb_write_rxfunaddr(ep_target_regs,
7421107b 2400 musb->context.index_regs[i].rxfunaddr);
032ec49f 2401 musb_write_rxhubaddr(ep_target_regs,
7421107b 2402 musb->context.index_regs[i].rxhubaddr);
032ec49f 2403 musb_write_rxhubport(ep_target_regs,
7421107b 2404 musb->context.index_regs[i].rxhubport);
4f712e01 2405 }
3c5fec75 2406 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2407}
2408
48fea965 2409static int musb_suspend(struct device *dev)
550a7375 2410{
8220796d 2411 struct musb *musb = dev_to_musb(dev);
550a7375 2412 unsigned long flags;
550a7375 2413
550a7375
FB		 2414 spin_lock_irqsave(&musb->lock, flags);
2415
2416 if (is_peripheral_active(musb)) {
2417 /* FIXME force disconnect unless we know USB will wake
2418 * the system up quickly enough to respond ...
2419 */
2420 } else if (is_host_active(musb)) {
2421 /* we know all the children are suspended; sometimes
2422 * they will even be wakeup-enabled.
2423 */
2424 }
2425
c338412b
DM		 2426 musb_save_context(musb);
2427
550a7375
FB		 2428 spin_unlock_irqrestore(&musb->lock, flags);
2429 return 0;
2430}
2431
3e87d9a3 2432static int musb_resume(struct device *dev)
550a7375 2433{
c338412b 2434 struct musb *musb = dev_to_musb(dev);
b87fd2f7
SAS		 2435 u8 devctl;
2436 u8 mask;
c338412b
DM		 2437
2438 /*
2439 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2440 * unless for some reason the whole soc powered down or the USB
2441 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2442 *
2443 * For the DSPS glue layer though, a full register restore has to
2444 * be done. As it shouldn't harm other platforms, we do it
2445 * unconditionally.
550a7375 2446 */
c338412b
DM		 2447
2448 musb_restore_context(musb);
2449
b87fd2f7
SAS		 2450 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2451 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2452 if ((devctl & mask) != (musb->context.devctl & mask))
2453 musb->port1_status = 0;
baadd52f
SAS		 2454 if (musb->need_finish_resume) {
2455 musb->need_finish_resume = 0;
2456 schedule_delayed_work(&musb->finish_resume_work,
2457 msecs_to_jiffies(20));
2458 }
a1fc1920
SAS		 2459
2460 /*
2461 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2462 * out of suspend
2463 */
2464 pm_runtime_disable(dev);
2465 pm_runtime_set_active(dev);
2466 pm_runtime_enable(dev);
550a7375
FB		 2467 return 0;
2468}
2469
7acc6197
HH		 2470static int musb_runtime_suspend(struct device *dev)
2471{
2472 struct musb *musb = dev_to_musb(dev);
2473
2474 musb_save_context(musb);
2475
2476 return 0;
2477}
2478
2479static int musb_runtime_resume(struct device *dev)
2480{
2481 struct musb *musb = dev_to_musb(dev);
2482 static int first = 1;
2483
2484 /*
2485 * When pm_runtime_get_sync called for the first time in driver
2486 * init, some of the structure is still not initialized which is
2487 * used in restore function. But clock needs to be
2488 * enabled before any register access, so
2489 * pm_runtime_get_sync has to be called.
2490 * Also context restore without save does not make
2491 * any sense
2492 */
2493 if (!first)
2494 musb_restore_context(musb);
2495 first = 0;
2496
9298b4aa
BL		 2497 if (musb->need_finish_resume) {
2498 musb->need_finish_resume = 0;
2499 schedule_delayed_work(&musb->finish_resume_work,
2500 msecs_to_jiffies(20));
2501 }
2502
7acc6197
HH		 2503 return 0;
2504}
2505
47145210 2506static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965 2507 .suspend = musb_suspend,
3e87d9a3 2508 .resume = musb_resume,
7acc6197
HH		 2509 .runtime_suspend = musb_runtime_suspend,
2510 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2511};
2512
2513#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2514#else
48fea965 2515#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2516#endif
2517
2518static struct platform_driver musb_driver = {
2519 .driver = {
2520 .name = (char *)musb_driver_name,
2521 .bus = &platform_bus_type,
48fea965 2522 .pm = MUSB_DEV_PM_OPS,
550a7375 2523 },
e9e8c85e 2524 .probe = musb_probe,
7690417d 2525 .remove = musb_remove,
550a7375 2526 .shutdown = musb_shutdown,
550a7375
FB		 2527};
2528
89f836a8 2529module_platform_driver(musb_driver);
Linux 6.x block layer and io_uring tree(s)