Commit | Line | Data |
---|---|---|
0c6a8818 BW |
1 | /* |
2 | * MUSB OTG controller driver for Blackfin Processors | |
3 | * | |
4 | * Copyright 2006-2008 Analog Devices Inc. | |
5 | * | |
6 | * Enter bugs at http://blackfin.uclinux.org/ | |
7 | * | |
8 | * Licensed under the GPL-2 or later. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/sched.h> | |
0c6a8818 BW |
14 | #include <linux/init.h> |
15 | #include <linux/list.h> | |
0c6a8818 BW |
16 | #include <linux/gpio.h> |
17 | #include <linux/io.h> | |
ded017ee | 18 | #include <linux/err.h> |
9cb0308e FB |
19 | #include <linux/platform_device.h> |
20 | #include <linux/dma-mapping.h> | |
ad50c1b2 | 21 | #include <linux/prefetch.h> |
78c289f8 | 22 | #include <linux/usb/nop-usb-xceiv.h> |
0c6a8818 BW |
23 | |
24 | #include <asm/cacheflush.h> | |
25 | ||
26 | #include "musb_core.h" | |
13254307 | 27 | #include "musbhsdma.h" |
0c6a8818 BW |
28 | #include "blackfin.h" |
29 | ||
a023c631 FB |
30 | struct bfin_glue { |
31 | struct device *dev; | |
32 | struct platform_device *musb; | |
33 | }; | |
fcd22e3b | 34 | #define glue_to_musb(g) platform_get_drvdata(g->musb) |
a023c631 | 35 | |
0c6a8818 BW |
36 | /* |
37 | * Load an endpoint's FIFO | |
38 | */ | |
39 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
40 | { | |
28e49705 | 41 | struct musb *musb = hw_ep->musb; |
0c6a8818 BW |
42 | void __iomem *fifo = hw_ep->fifo; |
43 | void __iomem *epio = hw_ep->regs; | |
1c4bdc01 | 44 | u8 epnum = hw_ep->epnum; |
0c6a8818 BW |
45 | |
46 | prefetch((u8 *)src); | |
47 | ||
48 | musb_writew(epio, MUSB_TXCOUNT, len); | |
49 | ||
5c8a86e1 | 50 | dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n", |
0c6a8818 BW |
51 | hw_ep->epnum, fifo, len, src, epio); |
52 | ||
53 | dump_fifo_data(src, len); | |
54 | ||
1c4bdc01 | 55 | if (!ANOMALY_05000380 && epnum != 0) { |
1ca9e9ca BW |
56 | u16 dma_reg; |
57 | ||
58 | flush_dcache_range((unsigned long)src, | |
59 | (unsigned long)(src + len)); | |
1c4bdc01 BW |
60 | |
61 | /* Setup DMA address register */ | |
1ca9e9ca | 62 | dma_reg = (u32)src; |
1c4bdc01 BW |
63 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg); |
64 | SSYNC(); | |
65 | ||
1ca9e9ca | 66 | dma_reg = (u32)src >> 16; |
1c4bdc01 BW |
67 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg); |
68 | SSYNC(); | |
69 | ||
70 | /* Setup DMA count register */ | |
71 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len); | |
72 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0); | |
73 | SSYNC(); | |
74 | ||
75 | /* Enable the DMA */ | |
76 | dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION; | |
77 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg); | |
78 | SSYNC(); | |
79 | ||
80 | /* Wait for compelete */ | |
81 | while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum))) | |
82 | cpu_relax(); | |
83 | ||
84 | /* acknowledge dma interrupt */ | |
85 | bfin_write_USB_DMA_INTERRUPT(1 << epnum); | |
86 | SSYNC(); | |
87 | ||
88 | /* Reset DMA */ | |
89 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0); | |
90 | SSYNC(); | |
91 | } else { | |
92 | SSYNC(); | |
93 | ||
94 | if (unlikely((unsigned long)src & 0x01)) | |
1ca9e9ca | 95 | outsw_8((unsigned long)fifo, src, (len + 1) >> 1); |
1c4bdc01 | 96 | else |
1ca9e9ca | 97 | outsw((unsigned long)fifo, src, (len + 1) >> 1); |
1c4bdc01 | 98 | } |
0c6a8818 | 99 | } |
0c6a8818 BW |
100 | /* |
101 | * Unload an endpoint's FIFO | |
102 | */ | |
103 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
104 | { | |
28e49705 | 105 | struct musb *musb = hw_ep->musb; |
0c6a8818 BW |
106 | void __iomem *fifo = hw_ep->fifo; |
107 | u8 epnum = hw_ep->epnum; | |
0c6a8818 | 108 | |
1c4bdc01 | 109 | if (ANOMALY_05000467 && epnum != 0) { |
1ca9e9ca | 110 | u16 dma_reg; |
1c4bdc01 | 111 | |
1ca9e9ca BW |
112 | invalidate_dcache_range((unsigned long)dst, |
113 | (unsigned long)(dst + len)); | |
1c4bdc01 BW |
114 | |
115 | /* Setup DMA address register */ | |
1ca9e9ca | 116 | dma_reg = (u32)dst; |
1c4bdc01 BW |
117 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg); |
118 | SSYNC(); | |
119 | ||
1ca9e9ca | 120 | dma_reg = (u32)dst >> 16; |
1c4bdc01 BW |
121 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg); |
122 | SSYNC(); | |
123 | ||
124 | /* Setup DMA count register */ | |
125 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len); | |
126 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0); | |
127 | SSYNC(); | |
128 | ||
129 | /* Enable the DMA */ | |
130 | dma_reg = (epnum << 4) | DMA_ENA | INT_ENA; | |
131 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg); | |
132 | SSYNC(); | |
133 | ||
134 | /* Wait for compelete */ | |
135 | while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum))) | |
136 | cpu_relax(); | |
137 | ||
138 | /* acknowledge dma interrupt */ | |
139 | bfin_write_USB_DMA_INTERRUPT(1 << epnum); | |
140 | SSYNC(); | |
141 | ||
142 | /* Reset DMA */ | |
143 | bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0); | |
144 | SSYNC(); | |
145 | } else { | |
146 | SSYNC(); | |
147 | /* Read the last byte of packet with odd size from address fifo + 4 | |
148 | * to trigger 1 byte access to EP0 FIFO. | |
149 | */ | |
150 | if (len == 1) | |
151 | *dst = (u8)inw((unsigned long)fifo + 4); | |
152 | else { | |
153 | if (unlikely((unsigned long)dst & 0x01)) | |
154 | insw_8((unsigned long)fifo, dst, len >> 1); | |
155 | else | |
156 | insw((unsigned long)fifo, dst, len >> 1); | |
157 | ||
158 | if (len & 0x01) | |
159 | *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4); | |
160 | } | |
161 | } | |
5c8a86e1 | 162 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
04f4086f MF |
163 | 'R', hw_ep->epnum, fifo, len, dst); |
164 | ||
0c6a8818 BW |
165 | dump_fifo_data(dst, len); |
166 | } | |
167 | ||
168 | static irqreturn_t blackfin_interrupt(int irq, void *__hci) | |
169 | { | |
170 | unsigned long flags; | |
171 | irqreturn_t retval = IRQ_NONE; | |
172 | struct musb *musb = __hci; | |
173 | ||
174 | spin_lock_irqsave(&musb->lock, flags); | |
175 | ||
176 | musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); | |
177 | musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); | |
178 | musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); | |
179 | ||
180 | if (musb->int_usb || musb->int_tx || musb->int_rx) { | |
181 | musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); | |
182 | musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx); | |
183 | musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx); | |
184 | retval = musb_interrupt(musb); | |
185 | } | |
186 | ||
ff927add | 187 | /* Start sampling ID pin, when plug is removed from MUSB */ |
032ec49f FB |
188 | if ((musb->xceiv->state == OTG_STATE_B_IDLE |
189 | || musb->xceiv->state == OTG_STATE_A_WAIT_BCON) || | |
68f64714 | 190 | (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) { |
ff927add CC |
191 | mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY); |
192 | musb->a_wait_bcon = TIMER_DELAY; | |
193 | } | |
194 | ||
0c6a8818 BW |
195 | spin_unlock_irqrestore(&musb->lock, flags); |
196 | ||
2f831751 | 197 | return retval; |
0c6a8818 BW |
198 | } |
199 | ||
200 | static void musb_conn_timer_handler(unsigned long _musb) | |
201 | { | |
202 | struct musb *musb = (void *)_musb; | |
203 | unsigned long flags; | |
204 | u16 val; | |
ff927add | 205 | static u8 toggle; |
0c6a8818 BW |
206 | |
207 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 208 | switch (musb->xceiv->state) { |
0c6a8818 BW |
209 | case OTG_STATE_A_IDLE: |
210 | case OTG_STATE_A_WAIT_BCON: | |
211 | /* Start a new session */ | |
212 | val = musb_readw(musb->mregs, MUSB_DEVCTL); | |
ff927add CC |
213 | val &= ~MUSB_DEVCTL_SESSION; |
214 | musb_writew(musb->mregs, MUSB_DEVCTL, val); | |
0c6a8818 BW |
215 | val |= MUSB_DEVCTL_SESSION; |
216 | musb_writew(musb->mregs, MUSB_DEVCTL, val); | |
ff927add CC |
217 | /* Check if musb is host or peripheral. */ |
218 | val = musb_readw(musb->mregs, MUSB_DEVCTL); | |
219 | ||
220 | if (!(val & MUSB_DEVCTL_BDEVICE)) { | |
221 | gpio_set_value(musb->config->gpio_vrsel, 1); | |
222 | musb->xceiv->state = OTG_STATE_A_WAIT_BCON; | |
223 | } else { | |
224 | gpio_set_value(musb->config->gpio_vrsel, 0); | |
225 | /* Ignore VBUSERROR and SUSPEND IRQ */ | |
226 | val = musb_readb(musb->mregs, MUSB_INTRUSBE); | |
227 | val &= ~MUSB_INTR_VBUSERROR; | |
228 | musb_writeb(musb->mregs, MUSB_INTRUSBE, val); | |
229 | ||
230 | val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR; | |
231 | musb_writeb(musb->mregs, MUSB_INTRUSB, val); | |
032ec49f | 232 | musb->xceiv->state = OTG_STATE_B_IDLE; |
ff927add CC |
233 | } |
234 | mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY); | |
235 | break; | |
236 | case OTG_STATE_B_IDLE: | |
032ec49f FB |
237 | /* |
238 | * Start a new session. It seems that MUSB needs taking | |
ff927add CC |
239 | * some time to recognize the type of the plug inserted? |
240 | */ | |
241 | val = musb_readw(musb->mregs, MUSB_DEVCTL); | |
242 | val |= MUSB_DEVCTL_SESSION; | |
243 | musb_writew(musb->mregs, MUSB_DEVCTL, val); | |
0c6a8818 | 244 | val = musb_readw(musb->mregs, MUSB_DEVCTL); |
ff927add | 245 | |
0c6a8818 BW |
246 | if (!(val & MUSB_DEVCTL_BDEVICE)) { |
247 | gpio_set_value(musb->config->gpio_vrsel, 1); | |
84e250ff | 248 | musb->xceiv->state = OTG_STATE_A_WAIT_BCON; |
0c6a8818 BW |
249 | } else { |
250 | gpio_set_value(musb->config->gpio_vrsel, 0); | |
251 | ||
252 | /* Ignore VBUSERROR and SUSPEND IRQ */ | |
253 | val = musb_readb(musb->mregs, MUSB_INTRUSBE); | |
254 | val &= ~MUSB_INTR_VBUSERROR; | |
255 | musb_writeb(musb->mregs, MUSB_INTRUSBE, val); | |
256 | ||
257 | val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR; | |
258 | musb_writeb(musb->mregs, MUSB_INTRUSB, val); | |
259 | ||
ff927add CC |
260 | /* Toggle the Soft Conn bit, so that we can response to |
261 | * the inserting of either A-plug or B-plug. | |
262 | */ | |
263 | if (toggle) { | |
264 | val = musb_readb(musb->mregs, MUSB_POWER); | |
265 | val &= ~MUSB_POWER_SOFTCONN; | |
266 | musb_writeb(musb->mregs, MUSB_POWER, val); | |
267 | toggle = 0; | |
268 | } else { | |
269 | val = musb_readb(musb->mregs, MUSB_POWER); | |
270 | val |= MUSB_POWER_SOFTCONN; | |
271 | musb_writeb(musb->mregs, MUSB_POWER, val); | |
272 | toggle = 1; | |
273 | } | |
274 | /* The delay time is set to 1/4 second by default, | |
275 | * shortening it, if accelerating A-plug detection | |
276 | * is needed in OTG mode. | |
277 | */ | |
278 | mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4); | |
0c6a8818 | 279 | } |
0c6a8818 | 280 | break; |
0c6a8818 | 281 | default: |
5c8a86e1 | 282 | dev_dbg(musb->controller, "%s state not handled\n", |
42c0bf1c | 283 | usb_otg_state_string(musb->xceiv->state)); |
0c6a8818 BW |
284 | break; |
285 | } | |
286 | spin_unlock_irqrestore(&musb->lock, flags); | |
287 | ||
5c8a86e1 | 288 | dev_dbg(musb->controller, "state is %s\n", |
42c0bf1c | 289 | usb_otg_state_string(musb->xceiv->state)); |
0c6a8818 BW |
290 | } |
291 | ||
743411b3 | 292 | static void bfin_musb_enable(struct musb *musb) |
0c6a8818 | 293 | { |
032ec49f | 294 | /* REVISIT is this really correct ? */ |
0c6a8818 BW |
295 | } |
296 | ||
743411b3 | 297 | static void bfin_musb_disable(struct musb *musb) |
0c6a8818 BW |
298 | { |
299 | } | |
300 | ||
743411b3 | 301 | static void bfin_musb_set_vbus(struct musb *musb, int is_on) |
0c6a8818 | 302 | { |
6ddc6dae CC |
303 | int value = musb->config->gpio_vrsel_active; |
304 | if (!is_on) | |
305 | value = !value; | |
306 | gpio_set_value(musb->config->gpio_vrsel, value); | |
0c6a8818 | 307 | |
5c8a86e1 | 308 | dev_dbg(musb->controller, "VBUS %s, devctl %02x " |
0c6a8818 | 309 | /* otg %3x conf %08x prcm %08x */ "\n", |
42c0bf1c | 310 | usb_otg_state_string(musb->xceiv->state), |
0c6a8818 BW |
311 | musb_readb(musb->mregs, MUSB_DEVCTL)); |
312 | } | |
313 | ||
86753811 | 314 | static int bfin_musb_set_power(struct usb_phy *x, unsigned mA) |
0c6a8818 BW |
315 | { |
316 | return 0; | |
317 | } | |
318 | ||
45567c28 | 319 | static int bfin_musb_vbus_status(struct musb *musb) |
0c6a8818 BW |
320 | { |
321 | return 0; | |
322 | } | |
323 | ||
743411b3 | 324 | static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode) |
0c6a8818 | 325 | { |
2002e768 | 326 | return -EIO; |
0c6a8818 BW |
327 | } |
328 | ||
13254307 MF |
329 | static int bfin_musb_adjust_channel_params(struct dma_channel *channel, |
330 | u16 packet_sz, u8 *mode, | |
331 | dma_addr_t *dma_addr, u32 *len) | |
332 | { | |
333 | struct musb_dma_channel *musb_channel = channel->private_data; | |
334 | ||
335 | /* | |
336 | * Anomaly 05000450 might cause data corruption when using DMA | |
337 | * MODE 1 transmits with short packet. So to work around this, | |
338 | * we truncate all MODE 1 transfers down to a multiple of the | |
339 | * max packet size, and then do the last short packet transfer | |
340 | * (if there is any) using MODE 0. | |
341 | */ | |
342 | if (ANOMALY_05000450) { | |
343 | if (musb_channel->transmit && *mode == 1) | |
344 | *len = *len - (*len % packet_sz); | |
345 | } | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
743411b3 | 350 | static void bfin_musb_reg_init(struct musb *musb) |
0c6a8818 | 351 | { |
d426e60d RG |
352 | if (ANOMALY_05000346) { |
353 | bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value); | |
354 | SSYNC(); | |
355 | } | |
0c6a8818 | 356 | |
d426e60d RG |
357 | if (ANOMALY_05000347) { |
358 | bfin_write_USB_APHY_CNTRL(0x0); | |
359 | SSYNC(); | |
360 | } | |
0c6a8818 | 361 | |
0c6a8818 | 362 | /* Configure PLL oscillator register */ |
9c756462 BL |
363 | bfin_write_USB_PLLOSC_CTRL(0x3080 | |
364 | ((480/musb->config->clkin) << 1)); | |
0c6a8818 BW |
365 | SSYNC(); |
366 | ||
367 | bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1); | |
368 | SSYNC(); | |
369 | ||
370 | bfin_write_USB_EP_NI0_RXMAXP(64); | |
371 | SSYNC(); | |
372 | ||
373 | bfin_write_USB_EP_NI0_TXMAXP(64); | |
374 | SSYNC(); | |
375 | ||
376 | /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/ | |
377 | bfin_write_USB_GLOBINTR(0x7); | |
378 | SSYNC(); | |
379 | ||
380 | bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA | | |
381 | EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA | | |
382 | EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA | | |
383 | EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA | | |
384 | EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA); | |
385 | SSYNC(); | |
743411b3 FB |
386 | } |
387 | ||
388 | static int bfin_musb_init(struct musb *musb) | |
389 | { | |
390 | ||
391 | /* | |
392 | * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE | |
393 | * and OTG HOST modes, while rev 1.1 and greater require PE7 to | |
394 | * be low for DEVICE mode and high for HOST mode. We set it high | |
395 | * here because we are in host mode | |
396 | */ | |
397 | ||
398 | if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) { | |
399 | printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n", | |
400 | musb->config->gpio_vrsel); | |
401 | return -ENODEV; | |
402 | } | |
403 | gpio_direction_output(musb->config->gpio_vrsel, 0); | |
404 | ||
405 | usb_nop_xceiv_register(); | |
662dca54 | 406 | musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); |
ded017ee | 407 | if (IS_ERR_OR_NULL(musb->xceiv)) { |
743411b3 | 408 | gpio_free(musb->config->gpio_vrsel); |
25736e0c | 409 | return -EPROBE_DEFER; |
743411b3 FB |
410 | } |
411 | ||
412 | bfin_musb_reg_init(musb); | |
0c6a8818 | 413 | |
032ec49f FB |
414 | setup_timer(&musb_conn_timer, musb_conn_timer_handler, |
415 | (unsigned long) musb); | |
416 | ||
417 | musb->xceiv->set_power = bfin_musb_set_power; | |
0c6a8818 BW |
418 | |
419 | musb->isr = blackfin_interrupt; | |
06624818 | 420 | musb->double_buffer_not_ok = true; |
0c6a8818 BW |
421 | |
422 | return 0; | |
423 | } | |
424 | ||
743411b3 | 425 | static int bfin_musb_exit(struct musb *musb) |
0c6a8818 | 426 | { |
0c6a8818 | 427 | gpio_free(musb->config->gpio_vrsel); |
0c6a8818 | 428 | |
721002ec | 429 | usb_put_phy(musb->xceiv); |
3daad24d | 430 | usb_nop_xceiv_unregister(); |
0c6a8818 BW |
431 | return 0; |
432 | } | |
743411b3 | 433 | |
f7ec9437 | 434 | static const struct musb_platform_ops bfin_ops = { |
743411b3 FB |
435 | .init = bfin_musb_init, |
436 | .exit = bfin_musb_exit, | |
437 | ||
438 | .enable = bfin_musb_enable, | |
439 | .disable = bfin_musb_disable, | |
440 | ||
441 | .set_mode = bfin_musb_set_mode, | |
743411b3 FB |
442 | |
443 | .vbus_status = bfin_musb_vbus_status, | |
444 | .set_vbus = bfin_musb_set_vbus, | |
13254307 MF |
445 | |
446 | .adjust_channel_params = bfin_musb_adjust_channel_params, | |
743411b3 | 447 | }; |
9cb0308e FB |
448 | |
449 | static u64 bfin_dmamask = DMA_BIT_MASK(32); | |
450 | ||
41ac7b3a | 451 | static int bfin_probe(struct platform_device *pdev) |
9cb0308e FB |
452 | { |
453 | struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; | |
454 | struct platform_device *musb; | |
a023c631 | 455 | struct bfin_glue *glue; |
9cb0308e FB |
456 | |
457 | int ret = -ENOMEM; | |
458 | ||
a023c631 FB |
459 | glue = kzalloc(sizeof(*glue), GFP_KERNEL); |
460 | if (!glue) { | |
461 | dev_err(&pdev->dev, "failed to allocate glue context\n"); | |
462 | goto err0; | |
463 | } | |
464 | ||
2f771164 | 465 | musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO); |
9cb0308e FB |
466 | if (!musb) { |
467 | dev_err(&pdev->dev, "failed to allocate musb device\n"); | |
2f771164 | 468 | goto err1; |
9cb0308e FB |
469 | } |
470 | ||
471 | musb->dev.parent = &pdev->dev; | |
472 | musb->dev.dma_mask = &bfin_dmamask; | |
473 | musb->dev.coherent_dma_mask = bfin_dmamask; | |
474 | ||
a023c631 FB |
475 | glue->dev = &pdev->dev; |
476 | glue->musb = musb; | |
477 | ||
f7ec9437 FB |
478 | pdata->platform_ops = &bfin_ops; |
479 | ||
a023c631 | 480 | platform_set_drvdata(pdev, glue); |
9cb0308e FB |
481 | |
482 | ret = platform_device_add_resources(musb, pdev->resource, | |
483 | pdev->num_resources); | |
484 | if (ret) { | |
485 | dev_err(&pdev->dev, "failed to add resources\n"); | |
65b3d52d | 486 | goto err3; |
9cb0308e FB |
487 | } |
488 | ||
489 | ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); | |
490 | if (ret) { | |
491 | dev_err(&pdev->dev, "failed to add platform_data\n"); | |
65b3d52d | 492 | goto err3; |
9cb0308e FB |
493 | } |
494 | ||
495 | ret = platform_device_add(musb); | |
496 | if (ret) { | |
497 | dev_err(&pdev->dev, "failed to register musb device\n"); | |
65b3d52d | 498 | goto err3; |
9cb0308e FB |
499 | } |
500 | ||
501 | return 0; | |
502 | ||
65b3d52d | 503 | err3: |
9cb0308e FB |
504 | platform_device_put(musb); |
505 | ||
a023c631 FB |
506 | err1: |
507 | kfree(glue); | |
508 | ||
9cb0308e FB |
509 | err0: |
510 | return ret; | |
511 | } | |
512 | ||
fb4e98ab | 513 | static int bfin_remove(struct platform_device *pdev) |
9cb0308e | 514 | { |
a023c631 | 515 | struct bfin_glue *glue = platform_get_drvdata(pdev); |
9cb0308e | 516 | |
01e40da0 | 517 | platform_device_unregister(glue->musb); |
a023c631 | 518 | kfree(glue); |
9cb0308e FB |
519 | |
520 | return 0; | |
521 | } | |
522 | ||
fcd22e3b FB |
523 | #ifdef CONFIG_PM |
524 | static int bfin_suspend(struct device *dev) | |
525 | { | |
526 | struct bfin_glue *glue = dev_get_drvdata(dev); | |
527 | struct musb *musb = glue_to_musb(glue); | |
528 | ||
529 | if (is_host_active(musb)) | |
530 | /* | |
531 | * During hibernate gpio_vrsel will change from high to low | |
532 | * low which will generate wakeup event resume the system | |
533 | * immediately. Set it to 0 before hibernate to avoid this | |
534 | * wakeup event. | |
535 | */ | |
536 | gpio_set_value(musb->config->gpio_vrsel, 0); | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | static int bfin_resume(struct device *dev) | |
542 | { | |
543 | struct bfin_glue *glue = dev_get_drvdata(dev); | |
544 | struct musb *musb = glue_to_musb(glue); | |
545 | ||
546 | bfin_musb_reg_init(musb); | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
551 | static struct dev_pm_ops bfin_pm_ops = { | |
552 | .suspend = bfin_suspend, | |
553 | .resume = bfin_resume, | |
554 | }; | |
555 | ||
8f7e7b87 | 556 | #define DEV_PM_OPS &bfin_pm_ops |
fcd22e3b FB |
557 | #else |
558 | #define DEV_PM_OPS NULL | |
559 | #endif | |
560 | ||
9cb0308e | 561 | static struct platform_driver bfin_driver = { |
e9e8c85e | 562 | .probe = bfin_probe, |
9cb0308e FB |
563 | .remove = __exit_p(bfin_remove), |
564 | .driver = { | |
417ddf86 | 565 | .name = "musb-blackfin", |
fcd22e3b | 566 | .pm = DEV_PM_OPS, |
9cb0308e FB |
567 | }, |
568 | }; | |
569 | ||
570 | MODULE_DESCRIPTION("Blackfin MUSB Glue Layer"); | |
571 | MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>"); | |
572 | MODULE_LICENSE("GPL v2"); | |
692373e1 | 573 | module_platform_driver(bfin_driver); |