Commit | Line | Data |
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eb83092c AKG |
1 | /* |
2 | * Texas Instruments AM35x "glue layer" | |
3 | * | |
4 | * Copyright (c) 2010, by Texas Instruments | |
5 | * | |
6 | * Based on the DA8xx "glue layer" code. | |
7 | * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com> | |
8 | * | |
9 | * This file is part of the Inventra Controller Driver for Linux. | |
10 | * | |
11 | * The Inventra Controller Driver for Linux is free software; you | |
12 | * can redistribute it and/or modify it under the terms of the GNU | |
13 | * General Public License version 2 as published by the Free Software | |
14 | * Foundation. | |
15 | * | |
16 | * The Inventra Controller Driver for Linux is distributed in | |
17 | * the hope that it will be useful, but WITHOUT ANY WARRANTY; | |
18 | * without even the implied warranty of MERCHANTABILITY or | |
19 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
20 | * License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with The Inventra Controller Driver for Linux ; if not, | |
24 | * write to the Free Software Foundation, Inc., 59 Temple Place, | |
25 | * Suite 330, Boston, MA 02111-1307 USA | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
ab570da2 | 30 | #include <linux/module.h> |
eb83092c | 31 | #include <linux/clk.h> |
ded017ee | 32 | #include <linux/err.h> |
eb83092c | 33 | #include <linux/io.h> |
ce40c576 FB |
34 | #include <linux/platform_device.h> |
35 | #include <linux/dma-mapping.h> | |
78c289f8 | 36 | #include <linux/usb/nop-usb-xceiv.h> |
eb83092c | 37 | |
eb83092c AKG |
38 | #include <plat/usb.h> |
39 | ||
40 | #include "musb_core.h" | |
41 | ||
42 | /* | |
43 | * AM35x specific definitions | |
44 | */ | |
45 | /* USB 2.0 OTG module registers */ | |
46 | #define USB_REVISION_REG 0x00 | |
47 | #define USB_CTRL_REG 0x04 | |
48 | #define USB_STAT_REG 0x08 | |
49 | #define USB_EMULATION_REG 0x0c | |
50 | /* 0x10 Reserved */ | |
51 | #define USB_AUTOREQ_REG 0x14 | |
52 | #define USB_SRP_FIX_TIME_REG 0x18 | |
53 | #define USB_TEARDOWN_REG 0x1c | |
54 | #define EP_INTR_SRC_REG 0x20 | |
55 | #define EP_INTR_SRC_SET_REG 0x24 | |
56 | #define EP_INTR_SRC_CLEAR_REG 0x28 | |
57 | #define EP_INTR_MASK_REG 0x2c | |
58 | #define EP_INTR_MASK_SET_REG 0x30 | |
59 | #define EP_INTR_MASK_CLEAR_REG 0x34 | |
60 | #define EP_INTR_SRC_MASKED_REG 0x38 | |
61 | #define CORE_INTR_SRC_REG 0x40 | |
62 | #define CORE_INTR_SRC_SET_REG 0x44 | |
63 | #define CORE_INTR_SRC_CLEAR_REG 0x48 | |
64 | #define CORE_INTR_MASK_REG 0x4c | |
65 | #define CORE_INTR_MASK_SET_REG 0x50 | |
66 | #define CORE_INTR_MASK_CLEAR_REG 0x54 | |
67 | #define CORE_INTR_SRC_MASKED_REG 0x58 | |
68 | /* 0x5c Reserved */ | |
69 | #define USB_END_OF_INTR_REG 0x60 | |
70 | ||
71 | /* Control register bits */ | |
72 | #define AM35X_SOFT_RESET_MASK 1 | |
73 | ||
74 | /* USB interrupt register bits */ | |
75 | #define AM35X_INTR_USB_SHIFT 16 | |
76 | #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT) | |
77 | #define AM35X_INTR_DRVVBUS 0x100 | |
78 | #define AM35X_INTR_RX_SHIFT 16 | |
79 | #define AM35X_INTR_TX_SHIFT 0 | |
80 | #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */ | |
81 | #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */ | |
82 | #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT) | |
83 | #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT) | |
84 | ||
85 | #define USB_MENTOR_CORE_OFFSET 0x400 | |
86 | ||
0919dfc1 FB |
87 | struct am35x_glue { |
88 | struct device *dev; | |
89 | struct platform_device *musb; | |
03491761 FB |
90 | struct clk *phy_clk; |
91 | struct clk *clk; | |
0919dfc1 | 92 | }; |
6f783e28 | 93 | #define glue_to_musb(g) platform_get_drvdata(g->musb) |
0919dfc1 | 94 | |
eb83092c | 95 | /* |
743411b3 | 96 | * am35x_musb_enable - enable interrupts |
eb83092c | 97 | */ |
743411b3 | 98 | static void am35x_musb_enable(struct musb *musb) |
eb83092c AKG |
99 | { |
100 | void __iomem *reg_base = musb->ctrl_base; | |
101 | u32 epmask; | |
102 | ||
103 | /* Workaround: setup IRQs through both register sets. */ | |
104 | epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) | | |
105 | ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT); | |
106 | ||
107 | musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); | |
108 | musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); | |
109 | ||
110 | /* Force the DRVVBUS IRQ so we can start polling for ID change. */ | |
032ec49f FB |
111 | musb_writel(reg_base, CORE_INTR_SRC_SET_REG, |
112 | AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT); | |
eb83092c AKG |
113 | } |
114 | ||
115 | /* | |
743411b3 | 116 | * am35x_musb_disable - disable HDRC and flush interrupts |
eb83092c | 117 | */ |
743411b3 | 118 | static void am35x_musb_disable(struct musb *musb) |
eb83092c AKG |
119 | { |
120 | void __iomem *reg_base = musb->ctrl_base; | |
121 | ||
122 | musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); | |
123 | musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, | |
124 | AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK); | |
125 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
126 | musb_writel(reg_base, USB_END_OF_INTR_REG, 0); | |
127 | } | |
128 | ||
eb83092c | 129 | #define portstate(stmt) stmt |
eb83092c | 130 | |
743411b3 | 131 | static void am35x_musb_set_vbus(struct musb *musb, int is_on) |
eb83092c AKG |
132 | { |
133 | WARN_ON(is_on && is_peripheral_active(musb)); | |
134 | } | |
135 | ||
136 | #define POLL_SECONDS 2 | |
137 | ||
138 | static struct timer_list otg_workaround; | |
139 | ||
140 | static void otg_timer(unsigned long _musb) | |
141 | { | |
142 | struct musb *musb = (void *)_musb; | |
143 | void __iomem *mregs = musb->mregs; | |
144 | u8 devctl; | |
145 | unsigned long flags; | |
146 | ||
147 | /* | |
148 | * We poll because AM35x's won't expose several OTG-critical | |
149 | * status change events (from the transceiver) otherwise. | |
150 | */ | |
151 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
5c8a86e1 | 152 | dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, |
3df00453 | 153 | otg_state_string(musb->xceiv->state)); |
eb83092c AKG |
154 | |
155 | spin_lock_irqsave(&musb->lock, flags); | |
156 | switch (musb->xceiv->state) { | |
157 | case OTG_STATE_A_WAIT_BCON: | |
158 | devctl &= ~MUSB_DEVCTL_SESSION; | |
159 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); | |
160 | ||
161 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
162 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
163 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
164 | MUSB_DEV_MODE(musb); | |
165 | } else { | |
166 | musb->xceiv->state = OTG_STATE_A_IDLE; | |
167 | MUSB_HST_MODE(musb); | |
168 | } | |
169 | break; | |
170 | case OTG_STATE_A_WAIT_VFALL: | |
171 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; | |
172 | musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, | |
173 | MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT); | |
174 | break; | |
175 | case OTG_STATE_B_IDLE: | |
eb83092c AKG |
176 | devctl = musb_readb(mregs, MUSB_DEVCTL); |
177 | if (devctl & MUSB_DEVCTL_BDEVICE) | |
178 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
179 | else | |
180 | musb->xceiv->state = OTG_STATE_A_IDLE; | |
181 | break; | |
182 | default: | |
183 | break; | |
184 | } | |
185 | spin_unlock_irqrestore(&musb->lock, flags); | |
186 | } | |
187 | ||
743411b3 | 188 | static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout) |
eb83092c AKG |
189 | { |
190 | static unsigned long last_timer; | |
191 | ||
eb83092c AKG |
192 | if (timeout == 0) |
193 | timeout = jiffies + msecs_to_jiffies(3); | |
194 | ||
195 | /* Never idle if active, or when VBUS timeout is not set as host */ | |
196 | if (musb->is_active || (musb->a_wait_bcon == 0 && | |
197 | musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) { | |
5c8a86e1 | 198 | dev_dbg(musb->controller, "%s active, deleting timer\n", |
3df00453 | 199 | otg_state_string(musb->xceiv->state)); |
eb83092c AKG |
200 | del_timer(&otg_workaround); |
201 | last_timer = jiffies; | |
202 | return; | |
203 | } | |
204 | ||
205 | if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { | |
5c8a86e1 | 206 | dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); |
eb83092c AKG |
207 | return; |
208 | } | |
209 | last_timer = timeout; | |
210 | ||
5c8a86e1 | 211 | dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", |
3df00453 AG |
212 | otg_state_string(musb->xceiv->state), |
213 | jiffies_to_msecs(timeout - jiffies)); | |
eb83092c AKG |
214 | mod_timer(&otg_workaround, timeout); |
215 | } | |
216 | ||
743411b3 | 217 | static irqreturn_t am35x_musb_interrupt(int irq, void *hci) |
eb83092c AKG |
218 | { |
219 | struct musb *musb = hci; | |
220 | void __iomem *reg_base = musb->ctrl_base; | |
a9c03783 AKG |
221 | struct device *dev = musb->controller; |
222 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
223 | struct omap_musb_board_data *data = plat->board_data; | |
d445b6da | 224 | struct usb_otg *otg = musb->xceiv->otg; |
eb83092c AKG |
225 | unsigned long flags; |
226 | irqreturn_t ret = IRQ_NONE; | |
a9c03783 | 227 | u32 epintr, usbintr; |
eb83092c AKG |
228 | |
229 | spin_lock_irqsave(&musb->lock, flags); | |
230 | ||
231 | /* Get endpoint interrupts */ | |
232 | epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); | |
233 | ||
234 | if (epintr) { | |
235 | musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr); | |
236 | ||
237 | musb->int_rx = | |
238 | (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT; | |
239 | musb->int_tx = | |
240 | (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT; | |
241 | } | |
242 | ||
243 | /* Get usb core interrupts */ | |
244 | usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG); | |
245 | if (!usbintr && !epintr) | |
246 | goto eoi; | |
247 | ||
248 | if (usbintr) { | |
249 | musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr); | |
250 | ||
251 | musb->int_usb = | |
252 | (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT; | |
253 | } | |
254 | /* | |
255 | * DRVVBUS IRQs are the only proxy we have (a very poor one!) for | |
256 | * AM35x's missing ID change IRQ. We need an ID change IRQ to | |
257 | * switch appropriately between halves of the OTG state machine. | |
258 | * Managing DEVCTL.SESSION per Mentor docs requires that we know its | |
259 | * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. | |
260 | * Also, DRVVBUS pulses for SRP (but not at 5V) ... | |
261 | */ | |
262 | if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) { | |
263 | int drvvbus = musb_readl(reg_base, USB_STAT_REG); | |
264 | void __iomem *mregs = musb->mregs; | |
265 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
266 | int err; | |
267 | ||
032ec49f | 268 | err = musb->int_usb & MUSB_INTR_VBUSERROR; |
eb83092c AKG |
269 | if (err) { |
270 | /* | |
271 | * The Mentor core doesn't debounce VBUS as needed | |
272 | * to cope with device connect current spikes. This | |
273 | * means it's not uncommon for bus-powered devices | |
274 | * to get VBUS errors during enumeration. | |
275 | * | |
276 | * This is a workaround, but newer RTL from Mentor | |
277 | * seems to allow a better one: "re"-starting sessions | |
278 | * without waiting for VBUS to stop registering in | |
279 | * devctl. | |
280 | */ | |
281 | musb->int_usb &= ~MUSB_INTR_VBUSERROR; | |
282 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; | |
283 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
284 | WARNING("VBUS error workaround (delay coming)\n"); | |
032ec49f | 285 | } else if (drvvbus) { |
eb83092c | 286 | MUSB_HST_MODE(musb); |
d445b6da | 287 | otg->default_a = 1; |
eb83092c AKG |
288 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; |
289 | portstate(musb->port1_status |= USB_PORT_STAT_POWER); | |
290 | del_timer(&otg_workaround); | |
291 | } else { | |
292 | musb->is_active = 0; | |
293 | MUSB_DEV_MODE(musb); | |
d445b6da | 294 | otg->default_a = 0; |
eb83092c AKG |
295 | musb->xceiv->state = OTG_STATE_B_IDLE; |
296 | portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); | |
297 | } | |
298 | ||
299 | /* NOTE: this must complete power-on within 100 ms. */ | |
5c8a86e1 | 300 | dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", |
eb83092c | 301 | drvvbus ? "on" : "off", |
3df00453 | 302 | otg_state_string(musb->xceiv->state), |
eb83092c AKG |
303 | err ? " ERROR" : "", |
304 | devctl); | |
305 | ret = IRQ_HANDLED; | |
306 | } | |
307 | ||
6ff1f3d3 SB |
308 | /* Drop spurious RX and TX if device is disconnected */ |
309 | if (musb->int_usb & MUSB_INTR_DISCONNECT) { | |
310 | musb->int_tx = 0; | |
311 | musb->int_rx = 0; | |
312 | } | |
313 | ||
eb83092c AKG |
314 | if (musb->int_tx || musb->int_rx || musb->int_usb) |
315 | ret |= musb_interrupt(musb); | |
316 | ||
317 | eoi: | |
318 | /* EOI needs to be written for the IRQ to be re-asserted. */ | |
319 | if (ret == IRQ_HANDLED || epintr || usbintr) { | |
320 | /* clear level interrupt */ | |
a9c03783 AKG |
321 | if (data->clear_irq) |
322 | data->clear_irq(); | |
eb83092c AKG |
323 | /* write EOI */ |
324 | musb_writel(reg_base, USB_END_OF_INTR_REG, 0); | |
325 | } | |
326 | ||
327 | /* Poll for ID change */ | |
032ec49f | 328 | if (musb->xceiv->state == OTG_STATE_B_IDLE) |
eb83092c AKG |
329 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
330 | ||
331 | spin_unlock_irqrestore(&musb->lock, flags); | |
332 | ||
333 | return ret; | |
334 | } | |
335 | ||
743411b3 | 336 | static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode) |
eb83092c | 337 | { |
a9c03783 AKG |
338 | struct device *dev = musb->controller; |
339 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
340 | struct omap_musb_board_data *data = plat->board_data; | |
341 | int retval = 0; | |
eb83092c | 342 | |
a9c03783 AKG |
343 | if (data->set_mode) |
344 | data->set_mode(musb_mode); | |
345 | else | |
346 | retval = -EIO; | |
eb83092c | 347 | |
a9c03783 | 348 | return retval; |
eb83092c AKG |
349 | } |
350 | ||
743411b3 | 351 | static int am35x_musb_init(struct musb *musb) |
eb83092c | 352 | { |
a9c03783 AKG |
353 | struct device *dev = musb->controller; |
354 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
355 | struct omap_musb_board_data *data = plat->board_data; | |
eb83092c | 356 | void __iomem *reg_base = musb->ctrl_base; |
a9c03783 | 357 | u32 rev; |
eb83092c AKG |
358 | |
359 | musb->mregs += USB_MENTOR_CORE_OFFSET; | |
360 | ||
eb83092c AKG |
361 | /* Returns zero if e.g. not clocked */ |
362 | rev = musb_readl(reg_base, USB_REVISION_REG); | |
03491761 FB |
363 | if (!rev) |
364 | return -ENODEV; | |
eb83092c AKG |
365 | |
366 | usb_nop_xceiv_register(); | |
662dca54 | 367 | musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); |
ded017ee | 368 | if (IS_ERR_OR_NULL(musb->xceiv)) |
03491761 | 369 | return -ENODEV; |
eb83092c | 370 | |
032ec49f | 371 | setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); |
eb83092c | 372 | |
a9c03783 AKG |
373 | /* Reset the musb */ |
374 | if (data->reset) | |
375 | data->reset(); | |
eb83092c AKG |
376 | |
377 | /* Reset the controller */ | |
378 | musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); | |
379 | ||
380 | /* Start the on-chip PHY and its PLL. */ | |
a9c03783 AKG |
381 | if (data->set_phy_power) |
382 | data->set_phy_power(1); | |
eb83092c AKG |
383 | |
384 | msleep(5); | |
385 | ||
743411b3 | 386 | musb->isr = am35x_musb_interrupt; |
eb83092c AKG |
387 | |
388 | /* clear level interrupt */ | |
a9c03783 AKG |
389 | if (data->clear_irq) |
390 | data->clear_irq(); | |
03491761 | 391 | |
eb83092c | 392 | return 0; |
eb83092c AKG |
393 | } |
394 | ||
743411b3 | 395 | static int am35x_musb_exit(struct musb *musb) |
eb83092c | 396 | { |
a9c03783 AKG |
397 | struct device *dev = musb->controller; |
398 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
399 | struct omap_musb_board_data *data = plat->board_data; | |
400 | ||
032ec49f | 401 | del_timer_sync(&otg_workaround); |
eb83092c | 402 | |
a9c03783 AKG |
403 | /* Shutdown the on-chip PHY and its PLL. */ |
404 | if (data->set_phy_power) | |
405 | data->set_phy_power(0); | |
eb83092c | 406 | |
721002ec | 407 | usb_put_phy(musb->xceiv); |
eb83092c AKG |
408 | usb_nop_xceiv_unregister(); |
409 | ||
eb83092c AKG |
410 | return 0; |
411 | } | |
412 | ||
843bb1d0 AKG |
413 | /* AM35x supports only 32bit read operation */ |
414 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
415 | { | |
416 | void __iomem *fifo = hw_ep->fifo; | |
417 | u32 val; | |
418 | int i; | |
419 | ||
420 | /* Read for 32bit-aligned destination address */ | |
421 | if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) { | |
422 | readsl(fifo, dst, len >> 2); | |
423 | dst += len & ~0x03; | |
424 | len &= 0x03; | |
425 | } | |
426 | /* | |
427 | * Now read the remaining 1 to 3 byte or complete length if | |
428 | * unaligned address. | |
429 | */ | |
430 | if (len > 4) { | |
431 | for (i = 0; i < (len >> 2); i++) { | |
432 | *(u32 *) dst = musb_readl(fifo, 0); | |
433 | dst += 4; | |
434 | } | |
435 | len &= 0x03; | |
436 | } | |
437 | if (len > 0) { | |
438 | val = musb_readl(fifo, 0); | |
439 | memcpy(dst, &val, len); | |
440 | } | |
441 | } | |
743411b3 | 442 | |
f7ec9437 | 443 | static const struct musb_platform_ops am35x_ops = { |
743411b3 FB |
444 | .init = am35x_musb_init, |
445 | .exit = am35x_musb_exit, | |
446 | ||
447 | .enable = am35x_musb_enable, | |
448 | .disable = am35x_musb_disable, | |
449 | ||
450 | .set_mode = am35x_musb_set_mode, | |
451 | .try_idle = am35x_musb_try_idle, | |
452 | ||
453 | .set_vbus = am35x_musb_set_vbus, | |
454 | }; | |
ce40c576 FB |
455 | |
456 | static u64 am35x_dmamask = DMA_BIT_MASK(32); | |
457 | ||
e9e8c85e | 458 | static int __devinit am35x_probe(struct platform_device *pdev) |
ce40c576 FB |
459 | { |
460 | struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; | |
461 | struct platform_device *musb; | |
0919dfc1 | 462 | struct am35x_glue *glue; |
ce40c576 | 463 | |
03491761 FB |
464 | struct clk *phy_clk; |
465 | struct clk *clk; | |
466 | ||
ce40c576 FB |
467 | int ret = -ENOMEM; |
468 | ||
0919dfc1 FB |
469 | glue = kzalloc(sizeof(*glue), GFP_KERNEL); |
470 | if (!glue) { | |
471 | dev_err(&pdev->dev, "failed to allocate glue context\n"); | |
472 | goto err0; | |
473 | } | |
474 | ||
2f771164 | 475 | musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO); |
ce40c576 FB |
476 | if (!musb) { |
477 | dev_err(&pdev->dev, "failed to allocate musb device\n"); | |
2f771164 | 478 | goto err1; |
ce40c576 FB |
479 | } |
480 | ||
03491761 FB |
481 | phy_clk = clk_get(&pdev->dev, "fck"); |
482 | if (IS_ERR(phy_clk)) { | |
483 | dev_err(&pdev->dev, "failed to get PHY clock\n"); | |
484 | ret = PTR_ERR(phy_clk); | |
65b3d52d | 485 | goto err3; |
03491761 FB |
486 | } |
487 | ||
488 | clk = clk_get(&pdev->dev, "ick"); | |
489 | if (IS_ERR(clk)) { | |
490 | dev_err(&pdev->dev, "failed to get clock\n"); | |
491 | ret = PTR_ERR(clk); | |
65b3d52d | 492 | goto err4; |
03491761 FB |
493 | } |
494 | ||
495 | ret = clk_enable(phy_clk); | |
496 | if (ret) { | |
497 | dev_err(&pdev->dev, "failed to enable PHY clock\n"); | |
65b3d52d | 498 | goto err5; |
03491761 FB |
499 | } |
500 | ||
501 | ret = clk_enable(clk); | |
502 | if (ret) { | |
503 | dev_err(&pdev->dev, "failed to enable clock\n"); | |
65b3d52d | 504 | goto err6; |
03491761 FB |
505 | } |
506 | ||
ce40c576 FB |
507 | musb->dev.parent = &pdev->dev; |
508 | musb->dev.dma_mask = &am35x_dmamask; | |
509 | musb->dev.coherent_dma_mask = am35x_dmamask; | |
510 | ||
0919dfc1 FB |
511 | glue->dev = &pdev->dev; |
512 | glue->musb = musb; | |
03491761 FB |
513 | glue->phy_clk = phy_clk; |
514 | glue->clk = clk; | |
0919dfc1 | 515 | |
f7ec9437 FB |
516 | pdata->platform_ops = &am35x_ops; |
517 | ||
0919dfc1 | 518 | platform_set_drvdata(pdev, glue); |
ce40c576 FB |
519 | |
520 | ret = platform_device_add_resources(musb, pdev->resource, | |
521 | pdev->num_resources); | |
522 | if (ret) { | |
523 | dev_err(&pdev->dev, "failed to add resources\n"); | |
65b3d52d | 524 | goto err7; |
ce40c576 FB |
525 | } |
526 | ||
527 | ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); | |
528 | if (ret) { | |
529 | dev_err(&pdev->dev, "failed to add platform_data\n"); | |
65b3d52d | 530 | goto err7; |
ce40c576 FB |
531 | } |
532 | ||
533 | ret = platform_device_add(musb); | |
534 | if (ret) { | |
535 | dev_err(&pdev->dev, "failed to register musb device\n"); | |
65b3d52d | 536 | goto err7; |
ce40c576 FB |
537 | } |
538 | ||
539 | return 0; | |
540 | ||
65b3d52d | 541 | err7: |
03491761 FB |
542 | clk_disable(clk); |
543 | ||
65b3d52d | 544 | err6: |
03491761 FB |
545 | clk_disable(phy_clk); |
546 | ||
65b3d52d | 547 | err5: |
03491761 FB |
548 | clk_put(clk); |
549 | ||
65b3d52d | 550 | err4: |
03491761 FB |
551 | clk_put(phy_clk); |
552 | ||
65b3d52d | 553 | err3: |
ce40c576 FB |
554 | platform_device_put(musb); |
555 | ||
0919dfc1 FB |
556 | err1: |
557 | kfree(glue); | |
558 | ||
ce40c576 FB |
559 | err0: |
560 | return ret; | |
561 | } | |
562 | ||
e9e8c85e | 563 | static int __devexit am35x_remove(struct platform_device *pdev) |
ce40c576 | 564 | { |
0919dfc1 | 565 | struct am35x_glue *glue = platform_get_drvdata(pdev); |
ce40c576 | 566 | |
56291515 | 567 | platform_device_unregister(glue->musb); |
03491761 FB |
568 | clk_disable(glue->clk); |
569 | clk_disable(glue->phy_clk); | |
570 | clk_put(glue->clk); | |
571 | clk_put(glue->phy_clk); | |
0919dfc1 | 572 | kfree(glue); |
ce40c576 FB |
573 | |
574 | return 0; | |
575 | } | |
576 | ||
6f783e28 FB |
577 | #ifdef CONFIG_PM |
578 | static int am35x_suspend(struct device *dev) | |
579 | { | |
580 | struct am35x_glue *glue = dev_get_drvdata(dev); | |
a9c03783 AKG |
581 | struct musb_hdrc_platform_data *plat = dev->platform_data; |
582 | struct omap_musb_board_data *data = plat->board_data; | |
583 | ||
584 | /* Shutdown the on-chip PHY and its PLL. */ | |
585 | if (data->set_phy_power) | |
586 | data->set_phy_power(0); | |
6f783e28 | 587 | |
6f783e28 FB |
588 | clk_disable(glue->phy_clk); |
589 | clk_disable(glue->clk); | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
594 | static int am35x_resume(struct device *dev) | |
595 | { | |
596 | struct am35x_glue *glue = dev_get_drvdata(dev); | |
a9c03783 AKG |
597 | struct musb_hdrc_platform_data *plat = dev->platform_data; |
598 | struct omap_musb_board_data *data = plat->board_data; | |
6f783e28 FB |
599 | int ret; |
600 | ||
a9c03783 AKG |
601 | /* Start the on-chip PHY and its PLL. */ |
602 | if (data->set_phy_power) | |
603 | data->set_phy_power(1); | |
604 | ||
6f783e28 FB |
605 | ret = clk_enable(glue->phy_clk); |
606 | if (ret) { | |
607 | dev_err(dev, "failed to enable PHY clock\n"); | |
608 | return ret; | |
609 | } | |
610 | ||
611 | ret = clk_enable(glue->clk); | |
612 | if (ret) { | |
613 | dev_err(dev, "failed to enable clock\n"); | |
614 | return ret; | |
615 | } | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
620 | static struct dev_pm_ops am35x_pm_ops = { | |
621 | .suspend = am35x_suspend, | |
622 | .resume = am35x_resume, | |
623 | }; | |
624 | ||
625 | #define DEV_PM_OPS &am35x_pm_ops | |
626 | #else | |
627 | #define DEV_PM_OPS NULL | |
628 | #endif | |
629 | ||
ce40c576 | 630 | static struct platform_driver am35x_driver = { |
e9e8c85e | 631 | .probe = am35x_probe, |
7690417d | 632 | .remove = am35x_remove, |
ce40c576 FB |
633 | .driver = { |
634 | .name = "musb-am35x", | |
6f783e28 | 635 | .pm = DEV_PM_OPS, |
ce40c576 FB |
636 | }, |
637 | }; | |
638 | ||
639 | MODULE_DESCRIPTION("AM35x MUSB Glue Layer"); | |
640 | MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); | |
641 | MODULE_LICENSE("GPL v2"); | |
a0a83eb4 | 642 | module_platform_driver(am35x_driver); |