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df2069ac CY |
1 | /* |
2 | * Copyright (C) 2016 MediaTek Inc. | |
3 | * | |
4 | * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> | |
5 | * | |
6 | * This software is licensed under the terms of the GNU General Public | |
7 | * License version 2, as published by the Free Software Foundation, and | |
8 | * may be copied, distributed, and modified under those terms. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/iopoll.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/of_address.h> | |
23 | #include <linux/of_irq.h> | |
24 | #include <linux/platform_device.h> | |
25 | ||
26 | #include "mtu3.h" | |
27 | ||
28 | /* u2-port0 should be powered on and enabled; */ | |
29 | int ssusb_check_clocks(struct mtu3 *mtu, u32 ex_clks) | |
30 | { | |
31 | void __iomem *ibase = mtu->ippc_base; | |
32 | u32 value, check_val; | |
33 | int ret; | |
34 | ||
35 | check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE | | |
36 | SSUSB_REF_RST_B_STS; | |
37 | ||
38 | ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value, | |
39 | (check_val == (value & check_val)), 100, 20000); | |
40 | if (ret) { | |
41 | dev_err(mtu->dev, "clks of sts1 are not stable!\n"); | |
42 | return ret; | |
43 | } | |
44 | ||
45 | ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value, | |
46 | (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000); | |
47 | if (ret) { | |
48 | dev_err(mtu->dev, "mac2 clock is not stable\n"); | |
49 | return ret; | |
50 | } | |
51 | ||
52 | return 0; | |
53 | } | |
54 | ||
55 | static int ssusb_rscs_init(struct mtu3 *mtu) | |
56 | { | |
57 | int ret = 0; | |
58 | ||
59 | ret = regulator_enable(mtu->vusb33); | |
60 | if (ret) { | |
61 | dev_err(mtu->dev, "failed to enable vusb33\n"); | |
62 | goto vusb33_err; | |
63 | } | |
64 | ||
65 | ret = clk_prepare_enable(mtu->sys_clk); | |
66 | if (ret) { | |
67 | dev_err(mtu->dev, "failed to enable sys_clk\n"); | |
68 | goto clk_err; | |
69 | } | |
70 | ||
71 | ret = phy_init(mtu->phy); | |
72 | if (ret) { | |
73 | dev_err(mtu->dev, "failed to init phy\n"); | |
74 | goto phy_init_err; | |
75 | } | |
76 | ||
77 | ret = phy_power_on(mtu->phy); | |
78 | if (ret) { | |
79 | dev_err(mtu->dev, "failed to power on phy\n"); | |
80 | goto phy_err; | |
81 | } | |
82 | ||
83 | return 0; | |
84 | ||
85 | phy_err: | |
86 | phy_exit(mtu->phy); | |
87 | ||
88 | phy_init_err: | |
89 | clk_disable_unprepare(mtu->sys_clk); | |
90 | ||
91 | clk_err: | |
92 | regulator_disable(mtu->vusb33); | |
93 | ||
94 | vusb33_err: | |
95 | ||
96 | return ret; | |
97 | } | |
98 | ||
99 | static void ssusb_rscs_exit(struct mtu3 *mtu) | |
100 | { | |
101 | clk_disable_unprepare(mtu->sys_clk); | |
102 | regulator_disable(mtu->vusb33); | |
103 | phy_power_off(mtu->phy); | |
104 | phy_exit(mtu->phy); | |
105 | } | |
106 | ||
107 | static void ssusb_ip_sw_reset(struct mtu3 *mtu) | |
108 | { | |
109 | mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); | |
110 | udelay(1); | |
111 | mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); | |
112 | } | |
113 | ||
114 | static int get_ssusb_rscs(struct platform_device *pdev, struct mtu3 *mtu) | |
115 | { | |
116 | struct device_node *node = pdev->dev.of_node; | |
117 | struct device *dev = &pdev->dev; | |
118 | struct resource *res; | |
119 | ||
120 | mtu->phy = devm_of_phy_get_by_index(dev, node, 0); | |
121 | if (IS_ERR(mtu->phy)) { | |
122 | dev_err(dev, "failed to get phy\n"); | |
123 | return PTR_ERR(mtu->phy); | |
124 | } | |
125 | ||
126 | mtu->irq = platform_get_irq(pdev, 0); | |
127 | if (mtu->irq <= 0) { | |
128 | dev_err(dev, "fail to get irq number\n"); | |
129 | return -ENODEV; | |
130 | } | |
131 | dev_info(dev, "irq %d\n", mtu->irq); | |
132 | ||
133 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); | |
134 | mtu->mac_base = devm_ioremap_resource(dev, res); | |
135 | if (IS_ERR(mtu->mac_base)) { | |
136 | dev_err(dev, "error mapping memory for dev mac\n"); | |
137 | return PTR_ERR(mtu->mac_base); | |
138 | } | |
139 | ||
140 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); | |
141 | mtu->ippc_base = devm_ioremap_resource(dev, res); | |
142 | if (IS_ERR(mtu->ippc_base)) { | |
143 | dev_err(dev, "failed to map memory for ippc\n"); | |
144 | return PTR_ERR(mtu->ippc_base); | |
145 | } | |
146 | ||
147 | mtu->vusb33 = devm_regulator_get(&pdev->dev, "vusb33"); | |
148 | if (IS_ERR(mtu->vusb33)) { | |
149 | dev_err(dev, "failed to get vusb33\n"); | |
150 | return PTR_ERR(mtu->vusb33); | |
151 | } | |
152 | ||
153 | mtu->sys_clk = devm_clk_get(dev, "sys_ck"); | |
154 | if (IS_ERR(mtu->sys_clk)) { | |
155 | dev_err(dev, "failed to get sys clock\n"); | |
156 | return PTR_ERR(mtu->sys_clk); | |
157 | } | |
158 | ||
159 | return 0; | |
160 | } | |
161 | ||
162 | static int mtu3_probe(struct platform_device *pdev) | |
163 | { | |
164 | struct device *dev = &pdev->dev; | |
165 | struct mtu3 *mtu; | |
166 | int ret = -ENOMEM; | |
167 | ||
168 | /* all elements are set to ZERO as default value */ | |
169 | mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL); | |
170 | if (!mtu) | |
171 | return -ENOMEM; | |
172 | ||
173 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); | |
174 | if (ret) { | |
175 | dev_err(dev, "No suitable DMA config available\n"); | |
176 | return -ENOTSUPP; | |
177 | } | |
178 | ||
179 | platform_set_drvdata(pdev, mtu); | |
180 | mtu->dev = dev; | |
181 | spin_lock_init(&mtu->lock); | |
182 | ||
183 | ret = get_ssusb_rscs(pdev, mtu); | |
184 | if (ret) | |
185 | return ret; | |
186 | ||
187 | /* enable power domain */ | |
188 | pm_runtime_enable(dev); | |
189 | pm_runtime_get_sync(dev); | |
190 | device_enable_async_suspend(dev); | |
191 | ||
192 | ret = ssusb_rscs_init(mtu); | |
193 | if (ret) | |
194 | goto comm_init_err; | |
195 | ||
196 | ssusb_ip_sw_reset(mtu); | |
197 | ||
198 | ret = ssusb_gadget_init(mtu); | |
199 | if (ret) { | |
200 | dev_err(dev, "failed to initialize gadget\n"); | |
201 | goto comm_exit; | |
202 | } | |
203 | ||
204 | return 0; | |
205 | ||
206 | comm_exit: | |
207 | ssusb_rscs_exit(mtu); | |
208 | ||
209 | comm_init_err: | |
210 | pm_runtime_put_sync(dev); | |
211 | pm_runtime_disable(dev); | |
212 | ||
213 | return ret; | |
214 | } | |
215 | ||
216 | static int mtu3_remove(struct platform_device *pdev) | |
217 | { | |
218 | struct mtu3 *mtu = platform_get_drvdata(pdev); | |
219 | ||
220 | ssusb_gadget_exit(mtu); | |
221 | ssusb_rscs_exit(mtu); | |
222 | pm_runtime_put_sync(&pdev->dev); | |
223 | pm_runtime_disable(&pdev->dev); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | #ifdef CONFIG_OF | |
229 | ||
230 | static const struct of_device_id mtu3_of_match[] = { | |
231 | {.compatible = "mediatek,mt8173-mtu3",}, | |
232 | {}, | |
233 | }; | |
234 | ||
235 | MODULE_DEVICE_TABLE(of, mtu3_of_match); | |
236 | ||
237 | #endif | |
238 | ||
239 | static struct platform_driver mtu3_driver = { | |
240 | .probe = mtu3_probe, | |
241 | .remove = mtu3_remove, | |
242 | .driver = { | |
243 | .name = MTU3_DRIVER_NAME, | |
244 | .of_match_table = of_match_ptr(mtu3_of_match), | |
245 | }, | |
246 | }; | |
247 | module_platform_driver(mtu3_driver); | |
248 | ||
249 | MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); | |
250 | MODULE_LICENSE("GPL v2"); | |
251 | MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver"); |