[linux-2.6-block.git] / drivers / usb / mtu3 / mtu3_plat.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2016 MediaTek Inc.
 *
 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>

#include "mtu3.h"
#include "mtu3_dr.h"

/* u2-port0 should be powered on and enabled; */
int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
{
	void __iomem *ibase = ssusb->ippc_base;
	u32 value, check_val;
	int ret;

	check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
			SSUSB_REF_RST_B_STS;

	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
			(check_val == (value & check_val)), 100, 20000);
	if (ret) {
		dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
		return ret;
	}

	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
			(value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
	if (ret) {
		dev_err(ssusb->dev, "mac2 clock is not stable\n");
		return ret;
	}

	return 0;
}

static int ssusb_phy_init(struct ssusb_mtk *ssusb)
{
	int i;
	int ret;

	for (i = 0; i < ssusb->num_phys; i++) {
		ret = phy_init(ssusb->phys[i]);
		if (ret)
			goto exit_phy;
	}
	return 0;

exit_phy:
	for (; i > 0; i--)
		phy_exit(ssusb->phys[i - 1]);

	return ret;
}

static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
{
	int i;

	for (i = 0; i < ssusb->num_phys; i++)
		phy_exit(ssusb->phys[i]);

	return 0;
}

static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
{
	int i;
	int ret;

	for (i = 0; i < ssusb->num_phys; i++) {
		ret = phy_power_on(ssusb->phys[i]);
		if (ret)
			goto power_off_phy;
	}
	return 0;

power_off_phy:
	for (; i > 0; i--)
		phy_power_off(ssusb->phys[i - 1]);

	return ret;
}

static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
{
	unsigned int i;

	for (i = 0; i < ssusb->num_phys; i++)
		phy_power_off(ssusb->phys[i]);
}

static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
{
	int ret;

	ret = clk_prepare_enable(ssusb->sys_clk);
	if (ret) {
		dev_err(ssusb->dev, "failed to enable sys_clk\n");
		goto sys_clk_err;
	}

	ret = clk_prepare_enable(ssusb->ref_clk);
	if (ret) {
		dev_err(ssusb->dev, "failed to enable ref_clk\n");
		goto ref_clk_err;
	}

	ret = clk_prepare_enable(ssusb->mcu_clk);
	if (ret) {
		dev_err(ssusb->dev, "failed to enable mcu_clk\n");
		goto mcu_clk_err;
	}

	ret = clk_prepare_enable(ssusb->dma_clk);
	if (ret) {
		dev_err(ssusb->dev, "failed to enable dma_clk\n");
		goto dma_clk_err;
	}

	return 0;

dma_clk_err:
	clk_disable_unprepare(ssusb->mcu_clk);
mcu_clk_err:
	clk_disable_unprepare(ssusb->ref_clk);
ref_clk_err:
	clk_disable_unprepare(ssusb->sys_clk);
sys_clk_err:
	return ret;
}

static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
{
	clk_disable_unprepare(ssusb->dma_clk);
	clk_disable_unprepare(ssusb->mcu_clk);
	clk_disable_unprepare(ssusb->ref_clk);
	clk_disable_unprepare(ssusb->sys_clk);
}

static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
{
	int ret = 0;

	ret = regulator_enable(ssusb->vusb33);
	if (ret) {
		dev_err(ssusb->dev, "failed to enable vusb33\n");
		goto vusb33_err;
	}

	ret = ssusb_clks_enable(ssusb);
	if (ret)
		goto clks_err;

	ret = ssusb_phy_init(ssusb);
	if (ret) {
		dev_err(ssusb->dev, "failed to init phy\n");
		goto phy_init_err;
	}

	ret = ssusb_phy_power_on(ssusb);
	if (ret) {
		dev_err(ssusb->dev, "failed to power on phy\n");
		goto phy_err;
	}

	return 0;

phy_err:
	ssusb_phy_exit(ssusb);
phy_init_err:
	ssusb_clks_disable(ssusb);
clks_err:
	regulator_disable(ssusb->vusb33);
vusb33_err:
	return ret;
}

static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
{
	ssusb_clks_disable(ssusb);
	regulator_disable(ssusb->vusb33);
	ssusb_phy_power_off(ssusb);
	ssusb_phy_exit(ssusb);
}

static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
{
	/* reset whole ip (xhci & u3d) */
	mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
	udelay(1);
	mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
}

/* ignore the error if the clock does not exist */
static struct clk *get_optional_clk(struct device *dev, const char *id)
{
	struct clk *opt_clk;

	opt_clk = devm_clk_get(dev, id);
	/* ignore error number except EPROBE_DEFER */
	if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
		opt_clk = NULL;

	return opt_clk;
}

static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
{
	struct device_node *node = pdev->dev.of_node;
	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
	struct device *dev = &pdev->dev;
	struct regulator *vbus;
	struct resource *res;
	int i;
	int ret;

	ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
	if (IS_ERR(ssusb->vusb33)) {
		dev_err(dev, "failed to get vusb33\n");
		return PTR_ERR(ssusb->vusb33);
	}

	ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
	if (IS_ERR(ssusb->sys_clk)) {
		dev_err(dev, "failed to get sys clock\n");
		return PTR_ERR(ssusb->sys_clk);
	}

	ssusb->ref_clk = get_optional_clk(dev, "ref_ck");
	if (IS_ERR(ssusb->ref_clk))
		return PTR_ERR(ssusb->ref_clk);

	ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck");
	if (IS_ERR(ssusb->mcu_clk))
		return PTR_ERR(ssusb->mcu_clk);

	ssusb->dma_clk = get_optional_clk(dev, "dma_ck");
	if (IS_ERR(ssusb->dma_clk))
		return PTR_ERR(ssusb->dma_clk);

	ssusb->num_phys = of_count_phandle_with_args(node,
			"phys", "#phy-cells");
	if (ssusb->num_phys > 0) {
		ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
					sizeof(*ssusb->phys), GFP_KERNEL);
		if (!ssusb->phys)
			return -ENOMEM;
	} else {
		ssusb->num_phys = 0;
	}

	for (i = 0; i < ssusb->num_phys; i++) {
		ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
		if (IS_ERR(ssusb->phys[i])) {
			dev_err(dev, "failed to get phy-%d\n", i);
			return PTR_ERR(ssusb->phys[i]);
		}
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
	ssusb->ippc_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(ssusb->ippc_base))
		return PTR_ERR(ssusb->ippc_base);

	ssusb->dr_mode = usb_get_dr_mode(dev);
	if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
		ssusb->dr_mode = USB_DR_MODE_OTG;

	if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
		return 0;

	/* if host role is supported */
	ret = ssusb_wakeup_of_property_parse(ssusb, node);
	if (ret)
		return ret;

	/* optional property, ignore the error if it does not exist */
	of_property_read_u32(node, "mediatek,u3p-dis-msk",
			     &ssusb->u3p_dis_msk);

	vbus = devm_regulator_get(&pdev->dev, "vbus");
	if (IS_ERR(vbus)) {
		dev_err(dev, "failed to get vbus\n");
		return PTR_ERR(vbus);
	}
	otg_sx->vbus = vbus;

	if (ssusb->dr_mode == USB_DR_MODE_HOST)
		return 0;

	/* if dual-role mode is supported */
	otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
	otg_sx->manual_drd_enabled =
		of_property_read_bool(node, "enable-manual-drd");

	if (of_property_read_bool(node, "extcon")) {
		otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
		if (IS_ERR(otg_sx->edev)) {
			dev_err(ssusb->dev, "couldn't get extcon device\n");
			return -EPROBE_DEFER;
		}
	}

	dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
		ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
		otg_sx->manual_drd_enabled ? "manual" : "auto");

	return 0;
}

static int mtu3_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	struct ssusb_mtk *ssusb;
	int ret = -ENOMEM;

	/* all elements are set to ZERO as default value */
	ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
	if (!ssusb)
		return -ENOMEM;

	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
	if (ret) {
		dev_err(dev, "No suitable DMA config available\n");
		return -ENOTSUPP;
	}

	platform_set_drvdata(pdev, ssusb);
	ssusb->dev = dev;

	ret = get_ssusb_rscs(pdev, ssusb);
	if (ret)
		return ret;

	/* enable power domain */
	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);
	device_enable_async_suspend(dev);

	ret = ssusb_rscs_init(ssusb);
	if (ret)
		goto comm_init_err;

	ssusb_ip_sw_reset(ssusb);

	if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
		ssusb->dr_mode = USB_DR_MODE_HOST;
	else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
		ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;

	/* default as host */
	ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);

	switch (ssusb->dr_mode) {
	case USB_DR_MODE_PERIPHERAL:
		ret = ssusb_gadget_init(ssusb);
		if (ret) {
			dev_err(dev, "failed to initialize gadget\n");
			goto comm_exit;
		}
		break;
	case USB_DR_MODE_HOST:
		ret = ssusb_host_init(ssusb, node);
		if (ret) {
			dev_err(dev, "failed to initialize host\n");
			goto comm_exit;
		}
		break;
	case USB_DR_MODE_OTG:
		ret = ssusb_gadget_init(ssusb);
		if (ret) {
			dev_err(dev, "failed to initialize gadget\n");
			goto comm_exit;
		}

		ret = ssusb_host_init(ssusb, node);
		if (ret) {
			dev_err(dev, "failed to initialize host\n");
			goto gadget_exit;
		}

		ssusb_otg_switch_init(ssusb);
		break;
	default:
		dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
		ret = -EINVAL;
		goto comm_exit;
	}

	return 0;

gadget_exit:
	ssusb_gadget_exit(ssusb);
comm_exit:
	ssusb_rscs_exit(ssusb);
comm_init_err:
	pm_runtime_put_sync(dev);
	pm_runtime_disable(dev);

	return ret;
}

static int mtu3_remove(struct platform_device *pdev)
{
	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);

	switch (ssusb->dr_mode) {
	case USB_DR_MODE_PERIPHERAL:
		ssusb_gadget_exit(ssusb);
		break;
	case USB_DR_MODE_HOST:
		ssusb_host_exit(ssusb);
		break;
	case USB_DR_MODE_OTG:
		ssusb_otg_switch_exit(ssusb);
		ssusb_gadget_exit(ssusb);
		ssusb_host_exit(ssusb);
		break;
	default:
		return -EINVAL;
	}

	ssusb_rscs_exit(ssusb);
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

/*
 * when support dual-role mode, we reject suspend when
 * it works as device mode;
 */
static int __maybe_unused mtu3_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);

	dev_dbg(dev, "%s\n", __func__);

	/* REVISIT: disconnect it for only device mode? */
	if (!ssusb->is_host)
		return 0;

	ssusb_host_disable(ssusb, true);
	ssusb_phy_power_off(ssusb);
	ssusb_clks_disable(ssusb);
	ssusb_wakeup_enable(ssusb);

	return 0;
}

static int __maybe_unused mtu3_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
	int ret;

	dev_dbg(dev, "%s\n", __func__);

	if (!ssusb->is_host)
		return 0;

	ssusb_wakeup_disable(ssusb);
	ret = ssusb_clks_enable(ssusb);
	if (ret)
		goto clks_err;

	ret = ssusb_phy_power_on(ssusb);
	if (ret)
		goto phy_err;

	ssusb_host_enable(ssusb);

	return 0;

phy_err:
	ssusb_clks_disable(ssusb);
clks_err:
	return ret;
}

static const struct dev_pm_ops mtu3_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
};

#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)

#ifdef CONFIG_OF

static const struct of_device_id mtu3_of_match[] = {
	{.compatible = "mediatek,mt8173-mtu3",},
	{.compatible = "mediatek,mtu3",},
	{},
};

MODULE_DEVICE_TABLE(of, mtu3_of_match);

#endif

static struct platform_driver mtu3_driver = {
	.probe = mtu3_probe,
	.remove = mtu3_remove,
	.driver = {
		.name = MTU3_DRIVER_NAME,
		.pm = DEV_PM_OPS,
		.of_match_table = of_match_ptr(mtu3_of_match),
	},
};
module_platform_driver(mtu3_driver);

MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
df2069ac CY	2	/*
	3	* Copyright (C) 2016 MediaTek Inc.
	4	*
	5	* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
	6	*
	7	* This software is licensed under the terms of the GNU General Public
	8	* License version 2, as published by the Free Software Foundation, and
	9	* may be copied, distributed, and modified under those terms.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	*/
	17
	18	#include <linux/clk.h>
	19	#include <linux/dma-mapping.h>
	20	#include <linux/iopoll.h>
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/of_address.h>
	24	#include <linux/of_irq.h>
	25	#include <linux/platform_device.h>
	26
	27	#include "mtu3.h"
b3f4e727	28	#include "mtu3_dr.h"
df2069ac CY	29
df2069ac CY	30	/* u2-port0 should be powered on and enabled; */
b3f4e727	31	int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
df2069ac	32	{
b3f4e727	33	void __iomem *ibase = ssusb->ippc_base;
df2069ac CY	34	u32 value, check_val;
	35	int ret;
	36
	37	check_val = ex_clks \| SSUSB_SYS125_RST_B_STS \| SSUSB_SYSPLL_STABLE \|
	38	SSUSB_REF_RST_B_STS;
	39
	40	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
	41	(check_val == (value & check_val)), 100, 20000);
	42	if (ret) {
b3f4e727	43	dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
df2069ac CY	44	return ret;
	45	}
	46
	47	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
	48	(value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
	49	if (ret) {
b3f4e727	50	dev_err(ssusb->dev, "mac2 clock is not stable\n");
df2069ac CY	51	return ret;
	52	}
	53
	54	return 0;
	55	}
	56
b3f4e727 CY	57	static int ssusb_phy_init(struct ssusb_mtk *ssusb)
	58	{
	59	int i;
	60	int ret;
	61
	62	for (i = 0; i < ssusb->num_phys; i++) {
	63	ret = phy_init(ssusb->phys[i]);
	64	if (ret)
	65	goto exit_phy;
	66	}
	67	return 0;
	68
	69	exit_phy:
	70	for (; i > 0; i--)
	71	phy_exit(ssusb->phys[i - 1]);
	72
	73	return ret;
	74	}
	75
	76	static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
	77	{
	78	int i;
	79
	80	for (i = 0; i < ssusb->num_phys; i++)
	81	phy_exit(ssusb->phys[i]);
	82
	83	return 0;
	84	}
	85
	86	static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
	87	{
	88	int i;
	89	int ret;
	90
	91	for (i = 0; i < ssusb->num_phys; i++) {
	92	ret = phy_power_on(ssusb->phys[i]);
	93	if (ret)
	94	goto power_off_phy;
	95	}
	96	return 0;
	97
	98	power_off_phy:
	99	for (; i > 0; i--)
	100	phy_power_off(ssusb->phys[i - 1]);
	101
	102	return ret;
	103	}
	104
	105	static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
	106	{
	107	unsigned int i;
	108
	109	for (i = 0; i < ssusb->num_phys; i++)
	110	phy_power_off(ssusb->phys[i]);
	111	}
	112
a316da82	113	static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
df2069ac	114	{
a316da82	115	int ret;
df2069ac	116
b3f4e727	117	ret = clk_prepare_enable(ssusb->sys_clk);
df2069ac	118	if (ret) {
b3f4e727	119	dev_err(ssusb->dev, "failed to enable sys_clk\n");
4d70d0c6 CY	120	goto sys_clk_err;
	121	}
	122
	123	ret = clk_prepare_enable(ssusb->ref_clk);
	124	if (ret) {
	125	dev_err(ssusb->dev, "failed to enable ref_clk\n");
	126	goto ref_clk_err;
df2069ac CY	127	}
df2069ac CY	128
a316da82 CY	129	ret = clk_prepare_enable(ssusb->mcu_clk);
	130	if (ret) {
	131	dev_err(ssusb->dev, "failed to enable mcu_clk\n");
	132	goto mcu_clk_err;
	133	}
	134
	135	ret = clk_prepare_enable(ssusb->dma_clk);
	136	if (ret) {
	137	dev_err(ssusb->dev, "failed to enable dma_clk\n");
	138	goto dma_clk_err;
	139	}
	140
	141	return 0;
	142
	143	dma_clk_err:
	144	clk_disable_unprepare(ssusb->mcu_clk);
	145	mcu_clk_err:
	146	clk_disable_unprepare(ssusb->ref_clk);
	147	ref_clk_err:
	148	clk_disable_unprepare(ssusb->sys_clk);
	149	sys_clk_err:
	150	return ret;
	151	}
	152
	153	static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
	154	{
	155	clk_disable_unprepare(ssusb->dma_clk);
	156	clk_disable_unprepare(ssusb->mcu_clk);
	157	clk_disable_unprepare(ssusb->ref_clk);
	158	clk_disable_unprepare(ssusb->sys_clk);
	159	}
	160
	161	static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
	162	{
	163	int ret = 0;
	164
	165	ret = regulator_enable(ssusb->vusb33);
	166	if (ret) {
	167	dev_err(ssusb->dev, "failed to enable vusb33\n");
	168	goto vusb33_err;
	169	}
	170
	171	ret = ssusb_clks_enable(ssusb);
	172	if (ret)
	173	goto clks_err;
	174
b3f4e727	175	ret = ssusb_phy_init(ssusb);
df2069ac	176	if (ret) {
b3f4e727	177	dev_err(ssusb->dev, "failed to init phy\n");
df2069ac CY	178	goto phy_init_err;
	179	}
	180
b3f4e727	181	ret = ssusb_phy_power_on(ssusb);
df2069ac	182	if (ret) {
b3f4e727	183	dev_err(ssusb->dev, "failed to power on phy\n");
df2069ac CY	184	goto phy_err;
	185	}
	186
	187	return 0;
	188
	189	phy_err:
b3f4e727	190	ssusb_phy_exit(ssusb);
df2069ac	191	phy_init_err:
a316da82 CY	192	ssusb_clks_disable(ssusb);
a316da82 CY	193	clks_err:
b3f4e727	194	regulator_disable(ssusb->vusb33);
df2069ac	195	vusb33_err:
df2069ac CY	196	return ret;
	197	}
	198
b3f4e727	199	static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
df2069ac	200	{
a316da82	201	ssusb_clks_disable(ssusb);
b3f4e727 CY	202	regulator_disable(ssusb->vusb33);
	203	ssusb_phy_power_off(ssusb);
	204	ssusb_phy_exit(ssusb);
df2069ac CY	205	}
df2069ac CY	206
b3f4e727	207	static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
df2069ac	208	{
b3f4e727 CY	209	/* reset whole ip (xhci & u3d) */
b3f4e727 CY	210	mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
df2069ac	211	udelay(1);
b3f4e727	212	mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
df2069ac CY	213	}
df2069ac CY	214
a316da82 CY	215	/* ignore the error if the clock does not exist */
	216	static struct clk get_optional_clk(struct device dev, const char *id)
	217	{
	218	struct clk *opt_clk;
	219
	220	opt_clk = devm_clk_get(dev, id);
	221	/* ignore error number except EPROBE_DEFER */
	222	if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
	223	opt_clk = NULL;
	224
	225	return opt_clk;
	226	}
	227
b3f4e727	228	static int get_ssusb_rscs(struct platform_device pdev, struct ssusb_mtk ssusb)
df2069ac CY	229	{
df2069ac CY	230	struct device_node *node = pdev->dev.of_node;
d0ed062a	231	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
df2069ac	232	struct device *dev = &pdev->dev;
d0ed062a	233	struct regulator *vbus;
df2069ac	234	struct resource *res;
b3f4e727 CY	235	int i;
b3f4e727 CY	236	int ret;
df2069ac	237
5cbf2d69 CY	238	ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
	239	if (IS_ERR(ssusb->vusb33)) {
	240	dev_err(dev, "failed to get vusb33\n");
	241	return PTR_ERR(ssusb->vusb33);
	242	}
	243
	244	ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
	245	if (IS_ERR(ssusb->sys_clk)) {
	246	dev_err(dev, "failed to get sys clock\n");
	247	return PTR_ERR(ssusb->sys_clk);
	248	}
	249
a316da82 CY	250	ssusb->ref_clk = get_optional_clk(dev, "ref_ck");
	251	if (IS_ERR(ssusb->ref_clk))
	252	return PTR_ERR(ssusb->ref_clk);
ca12cb7c	253
a316da82 CY	254	ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck");
	255	if (IS_ERR(ssusb->mcu_clk))
	256	return PTR_ERR(ssusb->mcu_clk);
	257
	258	ssusb->dma_clk = get_optional_clk(dev, "dma_ck");
	259	if (IS_ERR(ssusb->dma_clk))
	260	return PTR_ERR(ssusb->dma_clk);
4d70d0c6	261
b3f4e727 CY	262	ssusb->num_phys = of_count_phandle_with_args(node,
	263	"phys", "#phy-cells");
	264	if (ssusb->num_phys > 0) {
	265	ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
	266	sizeof(*ssusb->phys), GFP_KERNEL);
	267	if (!ssusb->phys)
	268	return -ENOMEM;
	269	} else {
	270	ssusb->num_phys = 0;
df2069ac	271	}
df2069ac	272
b3f4e727 CY	273	for (i = 0; i < ssusb->num_phys; i++) {
	274	ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
	275	if (IS_ERR(ssusb->phys[i])) {
	276	dev_err(dev, "failed to get phy-%d\n", i);
	277	return PTR_ERR(ssusb->phys[i]);
	278	}
df2069ac CY	279	}
	280
	281	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
b3f4e727	282	ssusb->ippc_base = devm_ioremap_resource(dev, res);
b7ecfe71	283	if (IS_ERR(ssusb->ippc_base))
b3f4e727	284	return PTR_ERR(ssusb->ippc_base);
df2069ac	285
b3f4e727	286	ssusb->dr_mode = usb_get_dr_mode(dev);
dd9d2f3a CY	287	if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN)
dd9d2f3a CY	288	ssusb->dr_mode = USB_DR_MODE_OTG;
df2069ac	289
b3f4e727 CY	290	if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
	291	return 0;
	292
	293	/* if host role is supported */
	294	ret = ssusb_wakeup_of_property_parse(ssusb, node);
	295	if (ret)
	296	return ret;
	297
076f1a89 CY	298	/* optional property, ignore the error if it does not exist */
	299	of_property_read_u32(node, "mediatek,u3p-dis-msk",
	300	&ssusb->u3p_dis_msk);
	301
d0ed062a CY	302	vbus = devm_regulator_get(&pdev->dev, "vbus");
	303	if (IS_ERR(vbus)) {
	304	dev_err(dev, "failed to get vbus\n");
	305	return PTR_ERR(vbus);
	306	}
	307	otg_sx->vbus = vbus;
	308
6638ec51 CY	309	if (ssusb->dr_mode == USB_DR_MODE_HOST)
	310	return 0;
	311
	312	/* if dual-role mode is supported */
d0ed062a CY	313	otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
	314	otg_sx->manual_drd_enabled =
	315	of_property_read_bool(node, "enable-manual-drd");
	316
	317	if (of_property_read_bool(node, "extcon")) {
	318	otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
	319	if (IS_ERR(otg_sx->edev)) {
	320	dev_err(ssusb->dev, "couldn't get extcon device\n");
	321	return -EPROBE_DEFER;
	322	}
d0ed062a CY	323	}
d0ed062a CY	324
c776f2c3 CY	325	dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
	326	ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
	327	otg_sx->manual_drd_enabled ? "manual" : "auto");
d0ed062a	328
df2069ac CY	329	return 0;
	330	}
	331
	332	static int mtu3_probe(struct platform_device *pdev)
	333	{
b3f4e727	334	struct device_node *node = pdev->dev.of_node;
df2069ac	335	struct device *dev = &pdev->dev;
b3f4e727	336	struct ssusb_mtk *ssusb;
df2069ac CY	337	int ret = -ENOMEM;
	338
	339	/* all elements are set to ZERO as default value */
b3f4e727 CY	340	ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
b3f4e727 CY	341	if (!ssusb)
df2069ac CY	342	return -ENOMEM;
	343
	344	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
	345	if (ret) {
	346	dev_err(dev, "No suitable DMA config available\n");
	347	return -ENOTSUPP;
	348	}
	349
b3f4e727 CY	350	platform_set_drvdata(pdev, ssusb);
b3f4e727 CY	351	ssusb->dev = dev;
df2069ac	352
b3f4e727	353	ret = get_ssusb_rscs(pdev, ssusb);
df2069ac CY	354	if (ret)
	355	return ret;
	356
	357	/* enable power domain */
	358	pm_runtime_enable(dev);
	359	pm_runtime_get_sync(dev);
	360	device_enable_async_suspend(dev);
	361
b3f4e727	362	ret = ssusb_rscs_init(ssusb);
df2069ac CY	363	if (ret)
	364	goto comm_init_err;
	365
b3f4e727 CY	366	ssusb_ip_sw_reset(ssusb);
	367
	368	if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
	369	ssusb->dr_mode = USB_DR_MODE_HOST;
	370	else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
	371	ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
	372
	373	/* default as host */
	374	ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
	375
	376	switch (ssusb->dr_mode) {
	377	case USB_DR_MODE_PERIPHERAL:
	378	ret = ssusb_gadget_init(ssusb);
	379	if (ret) {
	380	dev_err(dev, "failed to initialize gadget\n");
	381	goto comm_exit;
	382	}
	383	break;
	384	case USB_DR_MODE_HOST:
	385	ret = ssusb_host_init(ssusb, node);
	386	if (ret) {
	387	dev_err(dev, "failed to initialize host\n");
	388	goto comm_exit;
	389	}
	390	break;
d0ed062a CY	391	case USB_DR_MODE_OTG:
	392	ret = ssusb_gadget_init(ssusb);
	393	if (ret) {
	394	dev_err(dev, "failed to initialize gadget\n");
	395	goto comm_exit;
	396	}
	397
	398	ret = ssusb_host_init(ssusb, node);
	399	if (ret) {
	400	dev_err(dev, "failed to initialize host\n");
	401	goto gadget_exit;
	402	}
	403
	404	ssusb_otg_switch_init(ssusb);
	405	break;
b3f4e727 CY	406	default:
	407	dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
	408	ret = -EINVAL;
df2069ac CY	409	goto comm_exit;
	410	}
	411
	412	return 0;
	413
d0ed062a CY	414	gadget_exit:
d0ed062a CY	415	ssusb_gadget_exit(ssusb);
df2069ac	416	comm_exit:
b3f4e727	417	ssusb_rscs_exit(ssusb);
df2069ac CY	418	comm_init_err:
	419	pm_runtime_put_sync(dev);
	420	pm_runtime_disable(dev);
	421
	422	return ret;
	423	}
	424
	425	static int mtu3_remove(struct platform_device *pdev)
	426	{
b3f4e727 CY	427	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
	428
	429	switch (ssusb->dr_mode) {
	430	case USB_DR_MODE_PERIPHERAL:
	431	ssusb_gadget_exit(ssusb);
	432	break;
	433	case USB_DR_MODE_HOST:
	434	ssusb_host_exit(ssusb);
	435	break;
d0ed062a CY	436	case USB_DR_MODE_OTG:
	437	ssusb_otg_switch_exit(ssusb);
	438	ssusb_gadget_exit(ssusb);
	439	ssusb_host_exit(ssusb);
	440	break;
b3f4e727 CY	441	default:
	442	return -EINVAL;
	443	}
df2069ac	444
b3f4e727	445	ssusb_rscs_exit(ssusb);
df2069ac CY	446	pm_runtime_put_sync(&pdev->dev);
	447	pm_runtime_disable(&pdev->dev);
	448
	449	return 0;
	450	}
	451
b3f4e727 CY	452	/*
	453	* when support dual-role mode, we reject suspend when
	454	* it works as device mode;
	455	*/
	456	static int __maybe_unused mtu3_suspend(struct device *dev)
	457	{
	458	struct platform_device *pdev = to_platform_device(dev);
	459	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
	460
	461	dev_dbg(dev, "%s\n", __func__);
	462
	463	/* REVISIT: disconnect it for only device mode? */
	464	if (!ssusb->is_host)
	465	return 0;
	466
	467	ssusb_host_disable(ssusb, true);
	468	ssusb_phy_power_off(ssusb);
a316da82	469	ssusb_clks_disable(ssusb);
b3f4e727 CY	470	ssusb_wakeup_enable(ssusb);
	471
	472	return 0;
	473	}
	474
	475	static int __maybe_unused mtu3_resume(struct device *dev)
	476	{
	477	struct platform_device *pdev = to_platform_device(dev);
	478	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
0f4c3f90	479	int ret;
b3f4e727 CY	480
	481	dev_dbg(dev, "%s\n", __func__);
	482
	483	if (!ssusb->is_host)
	484	return 0;
	485
	486	ssusb_wakeup_disable(ssusb);
a316da82	487	ret = ssusb_clks_enable(ssusb);
0f4c3f90	488	if (ret)
a316da82	489	goto clks_err;
0f4c3f90 AY	490
	491	ret = ssusb_phy_power_on(ssusb);
	492	if (ret)
a316da82	493	goto phy_err;
0f4c3f90	494
b3f4e727 CY	495	ssusb_host_enable(ssusb);
	496
	497	return 0;
0f4c3f90	498
a316da82 CY	499	phy_err:
	500	ssusb_clks_disable(ssusb);
	501	clks_err:
0f4c3f90	502	return ret;
b3f4e727 CY	503	}
	504
	505	static const struct dev_pm_ops mtu3_pm_ops = {
	506	SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
	507	};
	508
	509	#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
	510
df2069ac CY	511	#ifdef CONFIG_OF
	512
	513	static const struct of_device_id mtu3_of_match[] = {
	514	{.compatible = "mediatek,mt8173-mtu3",},
dfcdcba9	515	{.compatible = "mediatek,mtu3",},
df2069ac CY	516	{},
	517	};
	518
	519	MODULE_DEVICE_TABLE(of, mtu3_of_match);
	520
	521	#endif
	522
	523	static struct platform_driver mtu3_driver = {
	524	.probe = mtu3_probe,
	525	.remove = mtu3_remove,
	526	.driver = {
	527	.name = MTU3_DRIVER_NAME,
b3f4e727	528	.pm = DEV_PM_OPS,
df2069ac CY	529	.of_match_table = of_match_ptr(mtu3_of_match),
	530	},
	531	};
	532	module_platform_driver(mtu3_driver);
	533
	534	MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
	535	MODULE_LICENSE("GPL v2");
	536	MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");