[linux-2.6-block.git] / drivers / usb / mtu3 / mtu3_plat.c

/*
 * Copyright (C) 2016 MediaTek Inc.
 *
 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>

#include "mtu3.h"
#include "mtu3_dr.h"

/* u2-port0 should be powered on and enabled; */
int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
{
	void __iomem *ibase = ssusb->ippc_base;
	u32 value, check_val;
	int ret;

	check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
			SSUSB_REF_RST_B_STS;

	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
			(check_val == (value & check_val)), 100, 20000);
	if (ret) {
		dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
		return ret;
	}

	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
			(value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
	if (ret) {
		dev_err(ssusb->dev, "mac2 clock is not stable\n");
		return ret;
	}

	return 0;
}

static int ssusb_phy_init(struct ssusb_mtk *ssusb)
{
	int i;
	int ret;

	for (i = 0; i < ssusb->num_phys; i++) {
		ret = phy_init(ssusb->phys[i]);
		if (ret)
			goto exit_phy;
	}
	return 0;

exit_phy:
	for (; i > 0; i--)
		phy_exit(ssusb->phys[i - 1]);

	return ret;
}

static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
{
	int i;

	for (i = 0; i < ssusb->num_phys; i++)
		phy_exit(ssusb->phys[i]);

	return 0;
}

static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
{
	int i;
	int ret;

	for (i = 0; i < ssusb->num_phys; i++) {
		ret = phy_power_on(ssusb->phys[i]);
		if (ret)
			goto power_off_phy;
	}
	return 0;

power_off_phy:
	for (; i > 0; i--)
		phy_power_off(ssusb->phys[i - 1]);

	return ret;
}

static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
{
	unsigned int i;

	for (i = 0; i < ssusb->num_phys; i++)
		phy_power_off(ssusb->phys[i]);
}

static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
{
	int ret;

	ret = clk_prepare_enable(ssusb->sys_clk);
	if (ret) {
		dev_err(ssusb->dev, "failed to enable sys_clk\n");
		goto sys_clk_err;
	}

	ret = clk_prepare_enable(ssusb->ref_clk);
	if (ret) {
		dev_err(ssusb->dev, "failed to enable ref_clk\n");
		goto ref_clk_err;
	}

	ret = clk_prepare_enable(ssusb->mcu_clk);
	if (ret) {
		dev_err(ssusb->dev, "failed to enable mcu_clk\n");
		goto mcu_clk_err;
	}

	ret = clk_prepare_enable(ssusb->dma_clk);
	if (ret) {
		dev_err(ssusb->dev, "failed to enable dma_clk\n");
		goto dma_clk_err;
	}

	return 0;

dma_clk_err:
	clk_disable_unprepare(ssusb->mcu_clk);
mcu_clk_err:
	clk_disable_unprepare(ssusb->ref_clk);
ref_clk_err:
	clk_disable_unprepare(ssusb->sys_clk);
sys_clk_err:
	return ret;
}

static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
{
	clk_disable_unprepare(ssusb->dma_clk);
	clk_disable_unprepare(ssusb->mcu_clk);
	clk_disable_unprepare(ssusb->ref_clk);
	clk_disable_unprepare(ssusb->sys_clk);
}

static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
{
	int ret = 0;

	ret = regulator_enable(ssusb->vusb33);
	if (ret) {
		dev_err(ssusb->dev, "failed to enable vusb33\n");
		goto vusb33_err;
	}

	ret = ssusb_clks_enable(ssusb);
	if (ret)
		goto clks_err;

	ret = ssusb_phy_init(ssusb);
	if (ret) {
		dev_err(ssusb->dev, "failed to init phy\n");
		goto phy_init_err;
	}

	ret = ssusb_phy_power_on(ssusb);
	if (ret) {
		dev_err(ssusb->dev, "failed to power on phy\n");
		goto phy_err;
	}

	return 0;

phy_err:
	ssusb_phy_exit(ssusb);
phy_init_err:
	ssusb_clks_disable(ssusb);
clks_err:
	regulator_disable(ssusb->vusb33);
vusb33_err:
	return ret;
}

static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
{
	ssusb_clks_disable(ssusb);
	regulator_disable(ssusb->vusb33);
	ssusb_phy_power_off(ssusb);
	ssusb_phy_exit(ssusb);
}

static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
{
	/* reset whole ip (xhci & u3d) */
	mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
	udelay(1);
	mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
}

/* ignore the error if the clock does not exist */
static struct clk *get_optional_clk(struct device *dev, const char *id)
{
	struct clk *opt_clk;

	opt_clk = devm_clk_get(dev, id);
	/* ignore error number except EPROBE_DEFER */
	if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
		opt_clk = NULL;

	return opt_clk;
}

static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
{
	struct device_node *node = pdev->dev.of_node;
	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
	struct device *dev = &pdev->dev;
	struct regulator *vbus;
	struct resource *res;
	int i;
	int ret;

	ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
	if (IS_ERR(ssusb->vusb33)) {
		dev_err(dev, "failed to get vusb33\n");
		return PTR_ERR(ssusb->vusb33);
	}

	ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
	if (IS_ERR(ssusb->sys_clk)) {
		dev_err(dev, "failed to get sys clock\n");
		return PTR_ERR(ssusb->sys_clk);
	}

	ssusb->ref_clk = get_optional_clk(dev, "ref_ck");
	if (IS_ERR(ssusb->ref_clk))
		return PTR_ERR(ssusb->ref_clk);

	ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck");
	if (IS_ERR(ssusb->mcu_clk))
		return PTR_ERR(ssusb->mcu_clk);

	ssusb->dma_clk = get_optional_clk(dev, "dma_ck");
	if (IS_ERR(ssusb->dma_clk))
		return PTR_ERR(ssusb->dma_clk);

	ssusb->num_phys = of_count_phandle_with_args(node,
			"phys", "#phy-cells");
	if (ssusb->num_phys > 0) {
		ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
					sizeof(*ssusb->phys), GFP_KERNEL);
		if (!ssusb->phys)
			return -ENOMEM;
	} else {
		ssusb->num_phys = 0;
	}

	for (i = 0; i < ssusb->num_phys; i++) {
		ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
		if (IS_ERR(ssusb->phys[i])) {
			dev_err(dev, "failed to get phy-%d\n", i);
			return PTR_ERR(ssusb->phys[i]);
		}
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
	ssusb->ippc_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(ssusb->ippc_base))
		return PTR_ERR(ssusb->ippc_base);

	ssusb->dr_mode = usb_get_dr_mode(dev);
	if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
		dev_err(dev, "dr_mode is error\n");
		return -EINVAL;
	}

	if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
		return 0;

	/* if host role is supported */
	ret = ssusb_wakeup_of_property_parse(ssusb, node);
	if (ret)
		return ret;

	/* optional property, ignore the error if it does not exist */
	of_property_read_u32(node, "mediatek,u3p-dis-msk",
			     &ssusb->u3p_dis_msk);

	if (ssusb->dr_mode != USB_DR_MODE_OTG)
		return 0;

	/* if dual-role mode is supported */
	vbus = devm_regulator_get(&pdev->dev, "vbus");
	if (IS_ERR(vbus)) {
		dev_err(dev, "failed to get vbus\n");
		return PTR_ERR(vbus);
	}
	otg_sx->vbus = vbus;

	otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
	otg_sx->manual_drd_enabled =
		of_property_read_bool(node, "enable-manual-drd");

	if (of_property_read_bool(node, "extcon")) {
		otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
		if (IS_ERR(otg_sx->edev)) {
			dev_err(ssusb->dev, "couldn't get extcon device\n");
			return -EPROBE_DEFER;
		}
	}

	dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
		ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
		otg_sx->manual_drd_enabled ? "manual" : "auto");

	return 0;
}

static int mtu3_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	struct ssusb_mtk *ssusb;
	int ret = -ENOMEM;

	/* all elements are set to ZERO as default value */
	ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
	if (!ssusb)
		return -ENOMEM;

	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
	if (ret) {
		dev_err(dev, "No suitable DMA config available\n");
		return -ENOTSUPP;
	}

	platform_set_drvdata(pdev, ssusb);
	ssusb->dev = dev;

	ret = get_ssusb_rscs(pdev, ssusb);
	if (ret)
		return ret;

	/* enable power domain */
	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);
	device_enable_async_suspend(dev);

	ret = ssusb_rscs_init(ssusb);
	if (ret)
		goto comm_init_err;

	ssusb_ip_sw_reset(ssusb);

	if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
		ssusb->dr_mode = USB_DR_MODE_HOST;
	else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
		ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;

	/* default as host */
	ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);

	switch (ssusb->dr_mode) {
	case USB_DR_MODE_PERIPHERAL:
		ret = ssusb_gadget_init(ssusb);
		if (ret) {
			dev_err(dev, "failed to initialize gadget\n");
			goto comm_exit;
		}
		break;
	case USB_DR_MODE_HOST:
		ret = ssusb_host_init(ssusb, node);
		if (ret) {
			dev_err(dev, "failed to initialize host\n");
			goto comm_exit;
		}
		break;
	case USB_DR_MODE_OTG:
		ret = ssusb_gadget_init(ssusb);
		if (ret) {
			dev_err(dev, "failed to initialize gadget\n");
			goto comm_exit;
		}

		ret = ssusb_host_init(ssusb, node);
		if (ret) {
			dev_err(dev, "failed to initialize host\n");
			goto gadget_exit;
		}

		ssusb_otg_switch_init(ssusb);
		break;
	default:
		dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
		ret = -EINVAL;
		goto comm_exit;
	}

	return 0;

gadget_exit:
	ssusb_gadget_exit(ssusb);
comm_exit:
	ssusb_rscs_exit(ssusb);
comm_init_err:
	pm_runtime_put_sync(dev);
	pm_runtime_disable(dev);

	return ret;
}

static int mtu3_remove(struct platform_device *pdev)
{
	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);

	switch (ssusb->dr_mode) {
	case USB_DR_MODE_PERIPHERAL:
		ssusb_gadget_exit(ssusb);
		break;
	case USB_DR_MODE_HOST:
		ssusb_host_exit(ssusb);
		break;
	case USB_DR_MODE_OTG:
		ssusb_otg_switch_exit(ssusb);
		ssusb_gadget_exit(ssusb);
		ssusb_host_exit(ssusb);
		break;
	default:
		return -EINVAL;
	}

	ssusb_rscs_exit(ssusb);
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

/*
 * when support dual-role mode, we reject suspend when
 * it works as device mode;
 */
static int __maybe_unused mtu3_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);

	dev_dbg(dev, "%s\n", __func__);

	/* REVISIT: disconnect it for only device mode? */
	if (!ssusb->is_host)
		return 0;

	ssusb_host_disable(ssusb, true);
	ssusb_phy_power_off(ssusb);
	ssusb_clks_disable(ssusb);
	ssusb_wakeup_enable(ssusb);

	return 0;
}

static int __maybe_unused mtu3_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
	int ret;

	dev_dbg(dev, "%s\n", __func__);

	if (!ssusb->is_host)
		return 0;

	ssusb_wakeup_disable(ssusb);
	ret = ssusb_clks_enable(ssusb);
	if (ret)
		goto clks_err;

	ret = ssusb_phy_power_on(ssusb);
	if (ret)
		goto phy_err;

	ssusb_host_enable(ssusb);

	return 0;

phy_err:
	ssusb_clks_disable(ssusb);
clks_err:
	return ret;
}

static const struct dev_pm_ops mtu3_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
};

#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)

#ifdef CONFIG_OF

static const struct of_device_id mtu3_of_match[] = {
	{.compatible = "mediatek,mt8173-mtu3",},
	{.compatible = "mediatek,mtu3",},
	{},
};

MODULE_DEVICE_TABLE(of, mtu3_of_match);

#endif

static struct platform_driver mtu3_driver = {
	.probe = mtu3_probe,
	.remove = mtu3_remove,
	.driver = {
		.name = MTU3_DRIVER_NAME,
		.pm = DEV_PM_OPS,
		.of_match_table = of_match_ptr(mtu3_of_match),
	},
};
module_platform_driver(mtu3_driver);

MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");
Commit	Line	Data
df2069ac CY	1	/*
	2	* Copyright (C) 2016 MediaTek Inc.
	3	*
	4	* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
	5	*
	6	* This software is licensed under the terms of the GNU General Public
	7	* License version 2, as published by the Free Software Foundation, and
	8	* may be copied, distributed, and modified under those terms.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/dma-mapping.h>
	19	#include <linux/iopoll.h>
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_irq.h>
	24	#include <linux/platform_device.h>
	25
	26	#include "mtu3.h"
b3f4e727	27	#include "mtu3_dr.h"
df2069ac CY	28
df2069ac CY	29	/* u2-port0 should be powered on and enabled; */
b3f4e727	30	int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
df2069ac	31	{
b3f4e727	32	void __iomem *ibase = ssusb->ippc_base;
df2069ac CY	33	u32 value, check_val;
	34	int ret;
	35
	36	check_val = ex_clks \| SSUSB_SYS125_RST_B_STS \| SSUSB_SYSPLL_STABLE \|
	37	SSUSB_REF_RST_B_STS;
	38
	39	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
	40	(check_val == (value & check_val)), 100, 20000);
	41	if (ret) {
b3f4e727	42	dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
df2069ac CY	43	return ret;
	44	}
	45
	46	ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
	47	(value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
	48	if (ret) {
b3f4e727	49	dev_err(ssusb->dev, "mac2 clock is not stable\n");
df2069ac CY	50	return ret;
	51	}
	52
	53	return 0;
	54	}
	55
b3f4e727 CY	56	static int ssusb_phy_init(struct ssusb_mtk *ssusb)
	57	{
	58	int i;
	59	int ret;
	60
	61	for (i = 0; i < ssusb->num_phys; i++) {
	62	ret = phy_init(ssusb->phys[i]);
	63	if (ret)
	64	goto exit_phy;
	65	}
	66	return 0;
	67
	68	exit_phy:
	69	for (; i > 0; i--)
	70	phy_exit(ssusb->phys[i - 1]);
	71
	72	return ret;
	73	}
	74
	75	static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
	76	{
	77	int i;
	78
	79	for (i = 0; i < ssusb->num_phys; i++)
	80	phy_exit(ssusb->phys[i]);
	81
	82	return 0;
	83	}
	84
	85	static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
	86	{
	87	int i;
	88	int ret;
	89
	90	for (i = 0; i < ssusb->num_phys; i++) {
	91	ret = phy_power_on(ssusb->phys[i]);
	92	if (ret)
	93	goto power_off_phy;
	94	}
	95	return 0;
	96
	97	power_off_phy:
	98	for (; i > 0; i--)
	99	phy_power_off(ssusb->phys[i - 1]);
	100
	101	return ret;
	102	}
	103
	104	static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
	105	{
	106	unsigned int i;
	107
	108	for (i = 0; i < ssusb->num_phys; i++)
	109	phy_power_off(ssusb->phys[i]);
	110	}
	111
a316da82	112	static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
df2069ac	113	{
a316da82	114	int ret;
df2069ac	115
b3f4e727	116	ret = clk_prepare_enable(ssusb->sys_clk);
df2069ac	117	if (ret) {
b3f4e727	118	dev_err(ssusb->dev, "failed to enable sys_clk\n");
4d70d0c6 CY	119	goto sys_clk_err;
	120	}
	121
	122	ret = clk_prepare_enable(ssusb->ref_clk);
	123	if (ret) {
	124	dev_err(ssusb->dev, "failed to enable ref_clk\n");
	125	goto ref_clk_err;
df2069ac CY	126	}
df2069ac CY	127
a316da82 CY	128	ret = clk_prepare_enable(ssusb->mcu_clk);
	129	if (ret) {
	130	dev_err(ssusb->dev, "failed to enable mcu_clk\n");
	131	goto mcu_clk_err;
	132	}
	133
	134	ret = clk_prepare_enable(ssusb->dma_clk);
	135	if (ret) {
	136	dev_err(ssusb->dev, "failed to enable dma_clk\n");
	137	goto dma_clk_err;
	138	}
	139
	140	return 0;
	141
	142	dma_clk_err:
	143	clk_disable_unprepare(ssusb->mcu_clk);
	144	mcu_clk_err:
	145	clk_disable_unprepare(ssusb->ref_clk);
	146	ref_clk_err:
	147	clk_disable_unprepare(ssusb->sys_clk);
	148	sys_clk_err:
	149	return ret;
	150	}
	151
	152	static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
	153	{
	154	clk_disable_unprepare(ssusb->dma_clk);
	155	clk_disable_unprepare(ssusb->mcu_clk);
	156	clk_disable_unprepare(ssusb->ref_clk);
	157	clk_disable_unprepare(ssusb->sys_clk);
	158	}
	159
	160	static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
	161	{
	162	int ret = 0;
	163
	164	ret = regulator_enable(ssusb->vusb33);
	165	if (ret) {
	166	dev_err(ssusb->dev, "failed to enable vusb33\n");
	167	goto vusb33_err;
	168	}
	169
	170	ret = ssusb_clks_enable(ssusb);
	171	if (ret)
	172	goto clks_err;
	173
b3f4e727	174	ret = ssusb_phy_init(ssusb);
df2069ac	175	if (ret) {
b3f4e727	176	dev_err(ssusb->dev, "failed to init phy\n");
df2069ac CY	177	goto phy_init_err;
	178	}
	179
b3f4e727	180	ret = ssusb_phy_power_on(ssusb);
df2069ac	181	if (ret) {
b3f4e727	182	dev_err(ssusb->dev, "failed to power on phy\n");
df2069ac CY	183	goto phy_err;
	184	}
	185
	186	return 0;
	187
	188	phy_err:
b3f4e727	189	ssusb_phy_exit(ssusb);
df2069ac	190	phy_init_err:
a316da82 CY	191	ssusb_clks_disable(ssusb);
a316da82 CY	192	clks_err:
b3f4e727	193	regulator_disable(ssusb->vusb33);
df2069ac	194	vusb33_err:
df2069ac CY	195	return ret;
	196	}
	197
b3f4e727	198	static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
df2069ac	199	{
a316da82	200	ssusb_clks_disable(ssusb);
b3f4e727 CY	201	regulator_disable(ssusb->vusb33);
	202	ssusb_phy_power_off(ssusb);
	203	ssusb_phy_exit(ssusb);
df2069ac CY	204	}
df2069ac CY	205
b3f4e727	206	static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
df2069ac	207	{
b3f4e727 CY	208	/* reset whole ip (xhci & u3d) */
b3f4e727 CY	209	mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
df2069ac	210	udelay(1);
b3f4e727	211	mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
df2069ac CY	212	}
df2069ac CY	213
a316da82 CY	214	/* ignore the error if the clock does not exist */
	215	static struct clk get_optional_clk(struct device dev, const char *id)
	216	{
	217	struct clk *opt_clk;
	218
	219	opt_clk = devm_clk_get(dev, id);
	220	/* ignore error number except EPROBE_DEFER */
	221	if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
	222	opt_clk = NULL;
	223
	224	return opt_clk;
	225	}
	226
b3f4e727	227	static int get_ssusb_rscs(struct platform_device pdev, struct ssusb_mtk ssusb)
df2069ac CY	228	{
df2069ac CY	229	struct device_node *node = pdev->dev.of_node;
d0ed062a	230	struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
df2069ac	231	struct device *dev = &pdev->dev;
d0ed062a	232	struct regulator *vbus;
df2069ac	233	struct resource *res;
b3f4e727 CY	234	int i;
b3f4e727 CY	235	int ret;
df2069ac	236
5cbf2d69 CY	237	ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
	238	if (IS_ERR(ssusb->vusb33)) {
	239	dev_err(dev, "failed to get vusb33\n");
	240	return PTR_ERR(ssusb->vusb33);
	241	}
	242
	243	ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
	244	if (IS_ERR(ssusb->sys_clk)) {
	245	dev_err(dev, "failed to get sys clock\n");
	246	return PTR_ERR(ssusb->sys_clk);
	247	}
	248
a316da82 CY	249	ssusb->ref_clk = get_optional_clk(dev, "ref_ck");
	250	if (IS_ERR(ssusb->ref_clk))
	251	return PTR_ERR(ssusb->ref_clk);
ca12cb7c	252
a316da82 CY	253	ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck");
	254	if (IS_ERR(ssusb->mcu_clk))
	255	return PTR_ERR(ssusb->mcu_clk);
	256
	257	ssusb->dma_clk = get_optional_clk(dev, "dma_ck");
	258	if (IS_ERR(ssusb->dma_clk))
	259	return PTR_ERR(ssusb->dma_clk);
4d70d0c6	260
b3f4e727 CY	261	ssusb->num_phys = of_count_phandle_with_args(node,
	262	"phys", "#phy-cells");
	263	if (ssusb->num_phys > 0) {
	264	ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
	265	sizeof(*ssusb->phys), GFP_KERNEL);
	266	if (!ssusb->phys)
	267	return -ENOMEM;
	268	} else {
	269	ssusb->num_phys = 0;
df2069ac	270	}
df2069ac	271
b3f4e727 CY	272	for (i = 0; i < ssusb->num_phys; i++) {
	273	ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
	274	if (IS_ERR(ssusb->phys[i])) {
	275	dev_err(dev, "failed to get phy-%d\n", i);
	276	return PTR_ERR(ssusb->phys[i]);
	277	}
df2069ac CY	278	}
	279
	280	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
b3f4e727	281	ssusb->ippc_base = devm_ioremap_resource(dev, res);
b7ecfe71	282	if (IS_ERR(ssusb->ippc_base))
b3f4e727	283	return PTR_ERR(ssusb->ippc_base);
df2069ac	284
b3f4e727 CY	285	ssusb->dr_mode = usb_get_dr_mode(dev);
	286	if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
	287	dev_err(dev, "dr_mode is error\n");
	288	return -EINVAL;
df2069ac CY	289	}
df2069ac CY	290
b3f4e727 CY	291	if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
	292	return 0;
	293
	294	/* if host role is supported */
	295	ret = ssusb_wakeup_of_property_parse(ssusb, node);
	296	if (ret)
	297	return ret;
	298
076f1a89 CY	299	/* optional property, ignore the error if it does not exist */
	300	of_property_read_u32(node, "mediatek,u3p-dis-msk",
	301	&ssusb->u3p_dis_msk);
	302
d0ed062a CY	303	if (ssusb->dr_mode != USB_DR_MODE_OTG)
	304	return 0;
	305
	306	/* if dual-role mode is supported */
	307	vbus = devm_regulator_get(&pdev->dev, "vbus");
	308	if (IS_ERR(vbus)) {
	309	dev_err(dev, "failed to get vbus\n");
	310	return PTR_ERR(vbus);
	311	}
	312	otg_sx->vbus = vbus;
	313
	314	otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
	315	otg_sx->manual_drd_enabled =
	316	of_property_read_bool(node, "enable-manual-drd");
	317
	318	if (of_property_read_bool(node, "extcon")) {
	319	otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
	320	if (IS_ERR(otg_sx->edev)) {
	321	dev_err(ssusb->dev, "couldn't get extcon device\n");
	322	return -EPROBE_DEFER;
	323	}
d0ed062a CY	324	}
d0ed062a CY	325
c776f2c3 CY	326	dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
	327	ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
	328	otg_sx->manual_drd_enabled ? "manual" : "auto");
d0ed062a	329
df2069ac CY	330	return 0;
	331	}
	332
	333	static int mtu3_probe(struct platform_device *pdev)
	334	{
b3f4e727	335	struct device_node *node = pdev->dev.of_node;
df2069ac	336	struct device *dev = &pdev->dev;
b3f4e727	337	struct ssusb_mtk *ssusb;
df2069ac CY	338	int ret = -ENOMEM;
	339
	340	/* all elements are set to ZERO as default value */
b3f4e727 CY	341	ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
b3f4e727 CY	342	if (!ssusb)
df2069ac CY	343	return -ENOMEM;
	344
	345	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
	346	if (ret) {
	347	dev_err(dev, "No suitable DMA config available\n");
	348	return -ENOTSUPP;
	349	}
	350
b3f4e727 CY	351	platform_set_drvdata(pdev, ssusb);
b3f4e727 CY	352	ssusb->dev = dev;
df2069ac	353
b3f4e727	354	ret = get_ssusb_rscs(pdev, ssusb);
df2069ac CY	355	if (ret)
	356	return ret;
	357
	358	/* enable power domain */
	359	pm_runtime_enable(dev);
	360	pm_runtime_get_sync(dev);
	361	device_enable_async_suspend(dev);
	362
b3f4e727	363	ret = ssusb_rscs_init(ssusb);
df2069ac CY	364	if (ret)
	365	goto comm_init_err;
	366
b3f4e727 CY	367	ssusb_ip_sw_reset(ssusb);
	368
	369	if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
	370	ssusb->dr_mode = USB_DR_MODE_HOST;
	371	else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
	372	ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
	373
	374	/* default as host */
	375	ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
	376
	377	switch (ssusb->dr_mode) {
	378	case USB_DR_MODE_PERIPHERAL:
	379	ret = ssusb_gadget_init(ssusb);
	380	if (ret) {
	381	dev_err(dev, "failed to initialize gadget\n");
	382	goto comm_exit;
	383	}
	384	break;
	385	case USB_DR_MODE_HOST:
	386	ret = ssusb_host_init(ssusb, node);
	387	if (ret) {
	388	dev_err(dev, "failed to initialize host\n");
	389	goto comm_exit;
	390	}
	391	break;
d0ed062a CY	392	case USB_DR_MODE_OTG:
	393	ret = ssusb_gadget_init(ssusb);
	394	if (ret) {
	395	dev_err(dev, "failed to initialize gadget\n");
	396	goto comm_exit;
	397	}
	398
	399	ret = ssusb_host_init(ssusb, node);
	400	if (ret) {
	401	dev_err(dev, "failed to initialize host\n");
	402	goto gadget_exit;
	403	}
	404
	405	ssusb_otg_switch_init(ssusb);
	406	break;
b3f4e727 CY	407	default:
	408	dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
	409	ret = -EINVAL;
df2069ac CY	410	goto comm_exit;
	411	}
	412
	413	return 0;
	414
d0ed062a CY	415	gadget_exit:
d0ed062a CY	416	ssusb_gadget_exit(ssusb);
df2069ac	417	comm_exit:
b3f4e727	418	ssusb_rscs_exit(ssusb);
df2069ac CY	419	comm_init_err:
	420	pm_runtime_put_sync(dev);
	421	pm_runtime_disable(dev);
	422
	423	return ret;
	424	}
	425
	426	static int mtu3_remove(struct platform_device *pdev)
	427	{
b3f4e727 CY	428	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
	429
	430	switch (ssusb->dr_mode) {
	431	case USB_DR_MODE_PERIPHERAL:
	432	ssusb_gadget_exit(ssusb);
	433	break;
	434	case USB_DR_MODE_HOST:
	435	ssusb_host_exit(ssusb);
	436	break;
d0ed062a CY	437	case USB_DR_MODE_OTG:
	438	ssusb_otg_switch_exit(ssusb);
	439	ssusb_gadget_exit(ssusb);
	440	ssusb_host_exit(ssusb);
	441	break;
b3f4e727 CY	442	default:
	443	return -EINVAL;
	444	}
df2069ac	445
b3f4e727	446	ssusb_rscs_exit(ssusb);
df2069ac CY	447	pm_runtime_put_sync(&pdev->dev);
	448	pm_runtime_disable(&pdev->dev);
	449
	450	return 0;
	451	}
	452
b3f4e727 CY	453	/*
	454	* when support dual-role mode, we reject suspend when
	455	* it works as device mode;
	456	*/
	457	static int __maybe_unused mtu3_suspend(struct device *dev)
	458	{
	459	struct platform_device *pdev = to_platform_device(dev);
	460	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
	461
	462	dev_dbg(dev, "%s\n", __func__);
	463
	464	/* REVISIT: disconnect it for only device mode? */
	465	if (!ssusb->is_host)
	466	return 0;
	467
	468	ssusb_host_disable(ssusb, true);
	469	ssusb_phy_power_off(ssusb);
a316da82	470	ssusb_clks_disable(ssusb);
b3f4e727 CY	471	ssusb_wakeup_enable(ssusb);
	472
	473	return 0;
	474	}
	475
	476	static int __maybe_unused mtu3_resume(struct device *dev)
	477	{
	478	struct platform_device *pdev = to_platform_device(dev);
	479	struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
0f4c3f90	480	int ret;
b3f4e727 CY	481
	482	dev_dbg(dev, "%s\n", __func__);
	483
	484	if (!ssusb->is_host)
	485	return 0;
	486
	487	ssusb_wakeup_disable(ssusb);
a316da82	488	ret = ssusb_clks_enable(ssusb);
0f4c3f90	489	if (ret)
a316da82	490	goto clks_err;
0f4c3f90 AY	491
	492	ret = ssusb_phy_power_on(ssusb);
	493	if (ret)
a316da82	494	goto phy_err;
0f4c3f90	495
b3f4e727 CY	496	ssusb_host_enable(ssusb);
	497
	498	return 0;
0f4c3f90	499
a316da82 CY	500	phy_err:
	501	ssusb_clks_disable(ssusb);
	502	clks_err:
0f4c3f90	503	return ret;
b3f4e727 CY	504	}
	505
	506	static const struct dev_pm_ops mtu3_pm_ops = {
	507	SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
	508	};
	509
	510	#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
	511
df2069ac CY	512	#ifdef CONFIG_OF
	513
	514	static const struct of_device_id mtu3_of_match[] = {
	515	{.compatible = "mediatek,mt8173-mtu3",},
dfcdcba9	516	{.compatible = "mediatek,mtu3",},
df2069ac CY	517	{},
	518	};
	519
	520	MODULE_DEVICE_TABLE(of, mtu3_of_match);
	521
	522	#endif
	523
	524	static struct platform_driver mtu3_driver = {
	525	.probe = mtu3_probe,
	526	.remove = mtu3_remove,
	527	.driver = {
	528	.name = MTU3_DRIVER_NAME,
b3f4e727	529	.pm = DEV_PM_OPS,
df2069ac CY	530	.of_match_table = of_match_ptr(mtu3_of_match),
	531	},
	532	};
	533	module_platform_driver(mtu3_driver);
	534
	535	MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
	536	MODULE_LICENSE("GPL v2");
	537	MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");