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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
df2069ac CY |
2 | /* |
3 | * mtu3_core.c - hardware access layer and gadget init/exit of | |
4 | * MediaTek usb3 Dual-Role Controller Driver | |
5 | * | |
6 | * Copyright (C) 2016 MediaTek Inc. | |
7 | * | |
8 | * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> | |
df2069ac CY |
9 | */ |
10 | ||
1a46dfea | 11 | #include <linux/dma-mapping.h> |
df2069ac CY |
12 | #include <linux/kernel.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/of_address.h> | |
15 | #include <linux/of_irq.h> | |
16 | #include <linux/platform_device.h> | |
17 | ||
18 | #include "mtu3.h" | |
19 | ||
20 | static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size) | |
21 | { | |
22 | struct mtu3_fifo_info *fifo = mep->fifo; | |
23 | u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT); | |
24 | u32 start_bit; | |
25 | ||
26 | /* ensure that @mep->fifo_seg_size is power of two */ | |
27 | num_bits = roundup_pow_of_two(num_bits); | |
28 | if (num_bits > fifo->limit) | |
29 | return -EINVAL; | |
30 | ||
31 | mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT; | |
32 | num_bits = num_bits * (mep->slot + 1); | |
33 | start_bit = bitmap_find_next_zero_area(fifo->bitmap, | |
34 | fifo->limit, 0, num_bits, 0); | |
35 | if (start_bit >= fifo->limit) | |
36 | return -EOVERFLOW; | |
37 | ||
38 | bitmap_set(fifo->bitmap, start_bit, num_bits); | |
39 | mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT; | |
40 | mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit; | |
41 | ||
42 | dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n", | |
43 | __func__, mep->fifo_seg_size, mep->fifo_size, start_bit); | |
44 | ||
45 | return mep->fifo_addr; | |
46 | } | |
47 | ||
48 | static void ep_fifo_free(struct mtu3_ep *mep) | |
49 | { | |
50 | struct mtu3_fifo_info *fifo = mep->fifo; | |
51 | u32 addr = mep->fifo_addr; | |
52 | u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT; | |
53 | u32 start_bit; | |
54 | ||
55 | if (unlikely(addr < fifo->base || bits > fifo->limit)) | |
56 | return; | |
57 | ||
58 | start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT; | |
59 | bitmap_clear(fifo->bitmap, start_bit, bits); | |
60 | mep->fifo_size = 0; | |
61 | mep->fifo_seg_size = 0; | |
62 | ||
63 | dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n", | |
64 | __func__, mep->fifo_seg_size, mep->fifo_size, start_bit); | |
65 | } | |
66 | ||
a29de31b CY |
67 | /* enable/disable U3D SS function */ |
68 | static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable) | |
69 | { | |
70 | /* If usb3_en==0, LTSSM will go to SS.Disable state */ | |
71 | if (enable) | |
72 | mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); | |
73 | else | |
74 | mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN); | |
75 | ||
76 | dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable); | |
77 | } | |
78 | ||
df2069ac | 79 | /* set/clear U3D HS device soft connect */ |
a29de31b | 80 | static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable) |
df2069ac CY |
81 | { |
82 | if (enable) { | |
83 | mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, | |
84 | SOFT_CONN | SUSPENDM_ENABLE); | |
85 | } else { | |
86 | mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT, | |
87 | SOFT_CONN | SUSPENDM_ENABLE); | |
88 | } | |
89 | dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable); | |
90 | } | |
91 | ||
92 | /* only port0 of U2/U3 supports device mode */ | |
93 | static int mtu3_device_enable(struct mtu3 *mtu) | |
94 | { | |
95 | void __iomem *ibase = mtu->ippc_base; | |
96 | u32 check_clk = 0; | |
97 | ||
98 | mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); | |
a29de31b CY |
99 | |
100 | if (mtu->is_u3_ip) { | |
101 | check_clk = SSUSB_U3_MAC_RST_B_STS; | |
102 | mtu3_clrbits(ibase, SSUSB_U3_CTRL(0), | |
103 | (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN | | |
104 | SSUSB_U3_PORT_HOST_SEL)); | |
105 | } | |
df2069ac CY |
106 | mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), |
107 | (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN | | |
108 | SSUSB_U2_PORT_HOST_SEL)); | |
4da72e6d CY |
109 | |
110 | if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) | |
111 | mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); | |
df2069ac | 112 | |
b3f4e727 | 113 | return ssusb_check_clocks(mtu->ssusb, check_clk); |
df2069ac CY |
114 | } |
115 | ||
116 | static void mtu3_device_disable(struct mtu3 *mtu) | |
117 | { | |
118 | void __iomem *ibase = mtu->ippc_base; | |
119 | ||
a29de31b CY |
120 | if (mtu->is_u3_ip) |
121 | mtu3_setbits(ibase, SSUSB_U3_CTRL(0), | |
122 | (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN)); | |
123 | ||
df2069ac CY |
124 | mtu3_setbits(ibase, SSUSB_U2_CTRL(0), |
125 | SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN); | |
4da72e6d CY |
126 | |
127 | if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) | |
128 | mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); | |
129 | ||
df2069ac CY |
130 | mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); |
131 | } | |
132 | ||
133 | /* reset U3D's device module. */ | |
134 | static void mtu3_device_reset(struct mtu3 *mtu) | |
135 | { | |
136 | void __iomem *ibase = mtu->ippc_base; | |
137 | ||
138 | mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST); | |
139 | udelay(1); | |
140 | mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST); | |
141 | } | |
142 | ||
143 | /* disable all interrupts */ | |
144 | static void mtu3_intr_disable(struct mtu3 *mtu) | |
145 | { | |
146 | void __iomem *mbase = mtu->mac_base; | |
147 | ||
148 | /* Disable level 1 interrupts */ | |
149 | mtu3_writel(mbase, U3D_LV1IECR, ~0x0); | |
df2069ac CY |
150 | /* Disable endpoint interrupts */ |
151 | mtu3_writel(mbase, U3D_EPIECR, ~0x0); | |
152 | } | |
153 | ||
154 | static void mtu3_intr_status_clear(struct mtu3 *mtu) | |
155 | { | |
156 | void __iomem *mbase = mtu->mac_base; | |
157 | ||
158 | /* Clear EP0 and Tx/Rx EPn interrupts status */ | |
159 | mtu3_writel(mbase, U3D_EPISR, ~0x0); | |
df2069ac CY |
160 | /* Clear U2 USB common interrupts status */ |
161 | mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0); | |
a29de31b CY |
162 | /* Clear U3 LTSSM interrupts status */ |
163 | mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0); | |
df2069ac CY |
164 | /* Clear speed change interrupt status */ |
165 | mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0); | |
166 | } | |
167 | ||
168 | /* enable system global interrupt */ | |
169 | static void mtu3_intr_enable(struct mtu3 *mtu) | |
170 | { | |
171 | void __iomem *mbase = mtu->mac_base; | |
172 | u32 value; | |
173 | ||
174 | /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */ | |
a29de31b | 175 | value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR; |
df2069ac CY |
176 | mtu3_writel(mbase, U3D_LV1IESR, value); |
177 | ||
178 | /* Enable U2 common USB interrupts */ | |
ad0c542c | 179 | value = SUSPEND_INTR | RESUME_INTR | RESET_INTR | LPM_RESUME_INTR; |
df2069ac CY |
180 | mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value); |
181 | ||
a29de31b CY |
182 | if (mtu->is_u3_ip) { |
183 | /* Enable U3 LTSSM interrupts */ | |
184 | value = HOT_RST_INTR | WARM_RST_INTR | VBUS_RISE_INTR | | |
185 | VBUS_FALL_INTR | ENTER_U3_INTR | EXIT_U3_INTR; | |
186 | mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value); | |
187 | } | |
188 | ||
df2069ac CY |
189 | /* Enable QMU interrupts. */ |
190 | value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT | | |
191 | RXQ_LENERR_INT | RXQ_ZLPERR_INT; | |
192 | mtu3_writel(mbase, U3D_QIESR1, value); | |
193 | ||
194 | /* Enable speed change interrupt */ | |
195 | mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR); | |
196 | } | |
197 | ||
5fcdd6de CY |
198 | /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */ |
199 | static void mtu3_ep_reset(struct mtu3_ep *mep) | |
200 | { | |
201 | struct mtu3 *mtu = mep->mtu; | |
202 | u32 rst_bit = EP_RST(mep->is_in, mep->epnum); | |
203 | ||
204 | mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit); | |
205 | mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit); | |
206 | } | |
207 | ||
df2069ac CY |
208 | /* set/clear the stall and toggle bits for non-ep0 */ |
209 | void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set) | |
210 | { | |
211 | struct mtu3 *mtu = mep->mtu; | |
212 | void __iomem *mbase = mtu->mac_base; | |
213 | u8 epnum = mep->epnum; | |
214 | u32 csr; | |
215 | ||
216 | if (mep->is_in) { /* TX */ | |
217 | csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS; | |
218 | if (set) | |
219 | csr |= TX_SENDSTALL; | |
220 | else | |
221 | csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL; | |
222 | mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr); | |
223 | } else { /* RX */ | |
224 | csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS; | |
225 | if (set) | |
226 | csr |= RX_SENDSTALL; | |
227 | else | |
228 | csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL; | |
229 | mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr); | |
230 | } | |
231 | ||
232 | if (!set) { | |
5fcdd6de | 233 | mtu3_ep_reset(mep); |
df2069ac CY |
234 | mep->flags &= ~MTU3_EP_STALL; |
235 | } else { | |
236 | mep->flags |= MTU3_EP_STALL; | |
237 | } | |
238 | ||
239 | dev_dbg(mtu->dev, "%s: %s\n", mep->name, | |
240 | set ? "SEND STALL" : "CLEAR STALL, with EP RESET"); | |
241 | } | |
242 | ||
a29de31b CY |
243 | void mtu3_dev_on_off(struct mtu3 *mtu, int is_on) |
244 | { | |
4d79e042 | 245 | if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER) |
a29de31b CY |
246 | mtu3_ss_func_set(mtu, is_on); |
247 | else | |
248 | mtu3_hs_softconn_set(mtu, is_on); | |
249 | ||
250 | dev_info(mtu->dev, "gadget (%s) pullup D%s\n", | |
251 | usb_speed_string(mtu->max_speed), is_on ? "+" : "-"); | |
252 | } | |
253 | ||
df2069ac CY |
254 | void mtu3_start(struct mtu3 *mtu) |
255 | { | |
256 | void __iomem *mbase = mtu->mac_base; | |
257 | ||
258 | dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__, | |
259 | mtu3_readl(mbase, U3D_DEVICE_CONTROL)); | |
260 | ||
261 | mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); | |
262 | ||
a29de31b CY |
263 | /* |
264 | * When disable U2 port, USB2_CSR's register will be reset to | |
265 | * default value after re-enable it again(HS is enabled by default). | |
266 | * So if force mac to work as FS, disable HS function. | |
267 | */ | |
268 | if (mtu->max_speed == USB_SPEED_FULL) | |
269 | mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE); | |
270 | ||
df2069ac CY |
271 | /* Initialize the default interrupts */ |
272 | mtu3_intr_enable(mtu); | |
df2069ac CY |
273 | mtu->is_active = 1; |
274 | ||
275 | if (mtu->softconnect) | |
a29de31b | 276 | mtu3_dev_on_off(mtu, 1); |
df2069ac CY |
277 | } |
278 | ||
279 | void mtu3_stop(struct mtu3 *mtu) | |
280 | { | |
281 | dev_dbg(mtu->dev, "%s\n", __func__); | |
282 | ||
283 | mtu3_intr_disable(mtu); | |
284 | mtu3_intr_status_clear(mtu); | |
285 | ||
286 | if (mtu->softconnect) | |
a29de31b | 287 | mtu3_dev_on_off(mtu, 0); |
df2069ac CY |
288 | |
289 | mtu->is_active = 0; | |
290 | mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); | |
291 | } | |
292 | ||
293 | /* for non-ep0 */ | |
294 | int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep, | |
295 | int interval, int burst, int mult) | |
296 | { | |
297 | void __iomem *mbase = mtu->mac_base; | |
298 | int epnum = mep->epnum; | |
299 | u32 csr0, csr1, csr2; | |
300 | int fifo_sgsz, fifo_addr; | |
301 | int num_pkts; | |
302 | ||
303 | fifo_addr = ep_fifo_alloc(mep, mep->maxp); | |
304 | if (fifo_addr < 0) { | |
305 | dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp); | |
306 | return -ENOMEM; | |
307 | } | |
308 | fifo_sgsz = ilog2(mep->fifo_seg_size); | |
309 | dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz, | |
310 | mep->fifo_seg_size, mep->fifo_size); | |
311 | ||
312 | if (mep->is_in) { | |
313 | csr0 = TX_TXMAXPKTSZ(mep->maxp); | |
314 | csr0 |= TX_DMAREQEN; | |
315 | ||
316 | num_pkts = (burst + 1) * (mult + 1) - 1; | |
317 | csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot); | |
318 | csr1 |= TX_MAX_PKT(num_pkts) | TX_MULT(mult); | |
319 | ||
320 | csr2 = TX_FIFOADDR(fifo_addr >> 4); | |
321 | csr2 |= TX_FIFOSEGSIZE(fifo_sgsz); | |
322 | ||
323 | switch (mep->type) { | |
324 | case USB_ENDPOINT_XFER_BULK: | |
325 | csr1 |= TX_TYPE(TYPE_BULK); | |
326 | break; | |
327 | case USB_ENDPOINT_XFER_ISOC: | |
328 | csr1 |= TX_TYPE(TYPE_ISO); | |
329 | csr2 |= TX_BINTERVAL(interval); | |
330 | break; | |
331 | case USB_ENDPOINT_XFER_INT: | |
332 | csr1 |= TX_TYPE(TYPE_INT); | |
333 | csr2 |= TX_BINTERVAL(interval); | |
334 | break; | |
335 | } | |
336 | ||
337 | /* Enable QMU Done interrupt */ | |
338 | mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum)); | |
339 | ||
340 | mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0); | |
341 | mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1); | |
342 | mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2); | |
343 | ||
344 | dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n", | |
345 | epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)), | |
346 | mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)), | |
347 | mtu3_readl(mbase, MU3D_EP_TXCR2(epnum))); | |
348 | } else { | |
349 | csr0 = RX_RXMAXPKTSZ(mep->maxp); | |
350 | csr0 |= RX_DMAREQEN; | |
351 | ||
352 | num_pkts = (burst + 1) * (mult + 1) - 1; | |
353 | csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot); | |
354 | csr1 |= RX_MAX_PKT(num_pkts) | RX_MULT(mult); | |
355 | ||
356 | csr2 = RX_FIFOADDR(fifo_addr >> 4); | |
357 | csr2 |= RX_FIFOSEGSIZE(fifo_sgsz); | |
358 | ||
359 | switch (mep->type) { | |
360 | case USB_ENDPOINT_XFER_BULK: | |
361 | csr1 |= RX_TYPE(TYPE_BULK); | |
362 | break; | |
363 | case USB_ENDPOINT_XFER_ISOC: | |
364 | csr1 |= RX_TYPE(TYPE_ISO); | |
365 | csr2 |= RX_BINTERVAL(interval); | |
366 | break; | |
367 | case USB_ENDPOINT_XFER_INT: | |
368 | csr1 |= RX_TYPE(TYPE_INT); | |
369 | csr2 |= RX_BINTERVAL(interval); | |
370 | break; | |
371 | } | |
372 | ||
373 | /*Enable QMU Done interrupt */ | |
374 | mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum)); | |
375 | ||
376 | mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0); | |
377 | mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1); | |
378 | mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2); | |
379 | ||
380 | dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n", | |
381 | epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)), | |
382 | mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)), | |
383 | mtu3_readl(mbase, MU3D_EP_RXCR2(epnum))); | |
384 | } | |
385 | ||
386 | dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2); | |
387 | dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n", | |
388 | __func__, mep->name, mep->fifo_addr, mep->fifo_size, | |
389 | fifo_sgsz, mep->fifo_seg_size); | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | /* for non-ep0 */ | |
395 | void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep) | |
396 | { | |
397 | void __iomem *mbase = mtu->mac_base; | |
398 | int epnum = mep->epnum; | |
399 | ||
400 | if (mep->is_in) { | |
401 | mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0); | |
402 | mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0); | |
403 | mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0); | |
404 | mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum)); | |
405 | } else { | |
406 | mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0); | |
407 | mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0); | |
408 | mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0); | |
409 | mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum)); | |
410 | } | |
411 | ||
5fcdd6de | 412 | mtu3_ep_reset(mep); |
df2069ac CY |
413 | ep_fifo_free(mep); |
414 | ||
415 | dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name); | |
416 | } | |
417 | ||
418 | /* | |
a29de31b CY |
419 | * Two scenarios: |
420 | * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs | |
421 | * are separated; | |
422 | * 2. when supports only HS, the fifo is shared for all EPs, and | |
df2069ac CY |
423 | * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate |
424 | * the total fifo size of non-ep0, and ep0's is fixed to 64B, | |
425 | * so the total fifo size is 64B + @EPNTXFFSZ; | |
426 | * Due to the first 64B should be reserved for EP0, non-ep0's fifo | |
427 | * starts from offset 64 and are divided into two equal parts for | |
428 | * TX or RX EPs for simplification. | |
429 | */ | |
430 | static void get_ep_fifo_config(struct mtu3 *mtu) | |
431 | { | |
432 | struct mtu3_fifo_info *tx_fifo; | |
433 | struct mtu3_fifo_info *rx_fifo; | |
434 | u32 fifosize; | |
435 | ||
a29de31b CY |
436 | if (mtu->is_u3_ip) { |
437 | fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ); | |
438 | tx_fifo = &mtu->tx_fifo; | |
439 | tx_fifo->base = 0; | |
440 | tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT; | |
441 | bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); | |
442 | ||
443 | fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ); | |
444 | rx_fifo = &mtu->rx_fifo; | |
445 | rx_fifo->base = 0; | |
446 | rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT; | |
447 | bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); | |
448 | mtu->slot = MTU3_U3_IP_SLOT_DEFAULT; | |
449 | } else { | |
450 | fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ); | |
451 | tx_fifo = &mtu->tx_fifo; | |
452 | tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE; | |
453 | tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1; | |
454 | bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); | |
455 | ||
456 | rx_fifo = &mtu->rx_fifo; | |
457 | rx_fifo->base = | |
458 | tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT; | |
459 | rx_fifo->limit = tx_fifo->limit; | |
460 | bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE); | |
461 | mtu->slot = MTU3_U2_IP_SLOT_DEFAULT; | |
462 | } | |
df2069ac CY |
463 | |
464 | dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n", | |
465 | __func__, tx_fifo->base, tx_fifo->limit, | |
466 | rx_fifo->base, rx_fifo->limit); | |
467 | } | |
468 | ||
469 | void mtu3_ep0_setup(struct mtu3 *mtu) | |
470 | { | |
471 | u32 maxpacket = mtu->g.ep0->maxpacket; | |
472 | u32 csr; | |
473 | ||
474 | dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket); | |
475 | ||
476 | csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR); | |
477 | csr &= ~EP0_MAXPKTSZ_MSK; | |
478 | csr |= EP0_MAXPKTSZ(maxpacket); | |
479 | csr &= EP0_W1C_BITS; | |
480 | mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); | |
481 | ||
482 | /* Enable EP0 interrupt */ | |
483 | mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR); | |
484 | } | |
485 | ||
486 | static int mtu3_mem_alloc(struct mtu3 *mtu) | |
487 | { | |
488 | void __iomem *mbase = mtu->mac_base; | |
489 | struct mtu3_ep *ep_array; | |
490 | int in_ep_num, out_ep_num; | |
220d88ea | 491 | u32 cap_epinfo; |
df2069ac CY |
492 | int ret; |
493 | int i; | |
494 | ||
df2069ac CY |
495 | cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO); |
496 | in_ep_num = CAP_TX_EP_NUM(cap_epinfo); | |
497 | out_ep_num = CAP_RX_EP_NUM(cap_epinfo); | |
498 | ||
df2069ac CY |
499 | dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n", |
500 | mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num, | |
501 | mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num); | |
502 | ||
503 | /* one for ep0, another is reserved */ | |
504 | mtu->num_eps = min(in_ep_num, out_ep_num) + 1; | |
505 | ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL); | |
506 | if (ep_array == NULL) | |
507 | return -ENOMEM; | |
508 | ||
509 | mtu->ep_array = ep_array; | |
510 | mtu->in_eps = ep_array; | |
511 | mtu->out_eps = &ep_array[mtu->num_eps]; | |
512 | /* ep0 uses in_eps[0], out_eps[0] is reserved */ | |
513 | mtu->ep0 = mtu->in_eps; | |
df2069ac CY |
514 | mtu->ep0->mtu = mtu; |
515 | mtu->ep0->epnum = 0; | |
516 | ||
517 | for (i = 1; i < mtu->num_eps; i++) { | |
518 | struct mtu3_ep *mep = mtu->in_eps + i; | |
519 | ||
520 | mep->fifo = &mtu->tx_fifo; | |
521 | mep = mtu->out_eps + i; | |
522 | mep->fifo = &mtu->rx_fifo; | |
523 | } | |
524 | ||
525 | get_ep_fifo_config(mtu); | |
526 | ||
527 | ret = mtu3_qmu_init(mtu); | |
528 | if (ret) | |
529 | kfree(mtu->ep_array); | |
530 | ||
531 | return ret; | |
532 | } | |
533 | ||
534 | static void mtu3_mem_free(struct mtu3 *mtu) | |
535 | { | |
536 | mtu3_qmu_exit(mtu); | |
537 | kfree(mtu->ep_array); | |
538 | } | |
539 | ||
a29de31b CY |
540 | static void mtu3_set_speed(struct mtu3 *mtu) |
541 | { | |
542 | void __iomem *mbase = mtu->mac_base; | |
543 | ||
544 | if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH)) | |
545 | mtu->max_speed = USB_SPEED_HIGH; | |
546 | ||
547 | if (mtu->max_speed == USB_SPEED_FULL) { | |
548 | /* disable U3 SS function */ | |
549 | mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN); | |
550 | /* disable HS function */ | |
551 | mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE); | |
552 | } else if (mtu->max_speed == USB_SPEED_HIGH) { | |
553 | mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN); | |
554 | /* HS/FS detected by HW */ | |
555 | mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE); | |
4d79e042 CY |
556 | } else if (mtu->max_speed == USB_SPEED_SUPER) { |
557 | mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0), | |
558 | SSUSB_U3_PORT_SSP_SPEED); | |
a29de31b | 559 | } |
d0ed062a | 560 | |
a29de31b CY |
561 | dev_info(mtu->dev, "max_speed: %s\n", |
562 | usb_speed_string(mtu->max_speed)); | |
563 | } | |
564 | ||
df2069ac CY |
565 | static void mtu3_regs_init(struct mtu3 *mtu) |
566 | { | |
567 | ||
568 | void __iomem *mbase = mtu->mac_base; | |
569 | ||
570 | /* be sure interrupts are disabled before registration of ISR */ | |
571 | mtu3_intr_disable(mtu); | |
572 | mtu3_intr_status_clear(mtu); | |
573 | ||
a29de31b CY |
574 | if (mtu->is_u3_ip) { |
575 | /* disable LGO_U1/U2 by default */ | |
576 | mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL, | |
577 | SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE | | |
578 | SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE); | |
579 | /* device responses to u3_exit from host automatically */ | |
580 | mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN); | |
c7d4abbc CY |
581 | /* automatically build U2 link when U3 detect fail */ |
582 | mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH); | |
a29de31b CY |
583 | } |
584 | ||
585 | mtu3_set_speed(mtu); | |
df2069ac CY |
586 | |
587 | /* delay about 0.1us from detecting reset to send chirp-K */ | |
588 | mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK); | |
df2069ac CY |
589 | /* U2/U3 detected by HW */ |
590 | mtu3_writel(mbase, U3D_DEVICE_CONF, 0); | |
df2069ac CY |
591 | /* enable QMU 16B checksum */ |
592 | mtu3_setbits(mbase, U3D_QCR0, QMU_CS16B_EN); | |
df2069ac CY |
593 | /* vbus detected by HW */ |
594 | mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON); | |
595 | } | |
596 | ||
597 | static irqreturn_t mtu3_link_isr(struct mtu3 *mtu) | |
598 | { | |
599 | void __iomem *mbase = mtu->mac_base; | |
600 | enum usb_device_speed udev_speed; | |
601 | u32 maxpkt = 64; | |
602 | u32 link; | |
603 | u32 speed; | |
604 | ||
605 | link = mtu3_readl(mbase, U3D_DEV_LINK_INTR); | |
606 | link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE); | |
607 | mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */ | |
608 | dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link); | |
609 | ||
610 | if (!(link & SSUSB_DEV_SPEED_CHG_INTR)) | |
611 | return IRQ_NONE; | |
612 | ||
613 | speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF)); | |
614 | ||
615 | switch (speed) { | |
616 | case MTU3_SPEED_FULL: | |
617 | udev_speed = USB_SPEED_FULL; | |
618 | /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */ | |
619 | mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf) | |
620 | | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa)); | |
621 | mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, | |
622 | LPM_BESL_STALL | LPM_BESLD_STALL); | |
623 | break; | |
624 | case MTU3_SPEED_HIGH: | |
625 | udev_speed = USB_SPEED_HIGH; | |
626 | /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */ | |
627 | mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf) | |
628 | | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa)); | |
629 | mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, | |
630 | LPM_BESL_STALL | LPM_BESLD_STALL); | |
631 | break; | |
a29de31b CY |
632 | case MTU3_SPEED_SUPER: |
633 | udev_speed = USB_SPEED_SUPER; | |
634 | maxpkt = 512; | |
635 | break; | |
4d79e042 CY |
636 | case MTU3_SPEED_SUPER_PLUS: |
637 | udev_speed = USB_SPEED_SUPER_PLUS; | |
638 | maxpkt = 512; | |
639 | break; | |
df2069ac CY |
640 | default: |
641 | udev_speed = USB_SPEED_UNKNOWN; | |
642 | break; | |
643 | } | |
644 | dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed)); | |
645 | ||
646 | mtu->g.speed = udev_speed; | |
647 | mtu->g.ep0->maxpacket = maxpkt; | |
648 | mtu->ep0_state = MU3D_EP0_STATE_SETUP; | |
649 | ||
650 | if (udev_speed == USB_SPEED_UNKNOWN) | |
651 | mtu3_gadget_disconnect(mtu); | |
652 | else | |
653 | mtu3_ep0_setup(mtu); | |
654 | ||
655 | return IRQ_HANDLED; | |
656 | } | |
657 | ||
a29de31b CY |
658 | static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu) |
659 | { | |
660 | void __iomem *mbase = mtu->mac_base; | |
661 | u32 ltssm; | |
662 | ||
663 | ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR); | |
664 | ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE); | |
665 | mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */ | |
666 | dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm); | |
667 | ||
668 | if (ltssm & (HOT_RST_INTR | WARM_RST_INTR)) | |
669 | mtu3_gadget_reset(mtu); | |
670 | ||
4f9f032c | 671 | if (ltssm & VBUS_FALL_INTR) { |
a29de31b | 672 | mtu3_ss_func_set(mtu, false); |
4f9f032c CY |
673 | mtu3_gadget_reset(mtu); |
674 | } | |
a29de31b CY |
675 | |
676 | if (ltssm & VBUS_RISE_INTR) | |
677 | mtu3_ss_func_set(mtu, true); | |
678 | ||
679 | if (ltssm & EXIT_U3_INTR) | |
680 | mtu3_gadget_resume(mtu); | |
681 | ||
682 | if (ltssm & ENTER_U3_INTR) | |
683 | mtu3_gadget_suspend(mtu); | |
684 | ||
685 | return IRQ_HANDLED; | |
686 | } | |
687 | ||
df2069ac CY |
688 | static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu) |
689 | { | |
690 | void __iomem *mbase = mtu->mac_base; | |
691 | u32 u2comm; | |
692 | ||
693 | u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR); | |
694 | u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE); | |
695 | mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */ | |
696 | dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm); | |
697 | ||
698 | if (u2comm & SUSPEND_INTR) | |
699 | mtu3_gadget_suspend(mtu); | |
700 | ||
701 | if (u2comm & RESUME_INTR) | |
702 | mtu3_gadget_resume(mtu); | |
703 | ||
704 | if (u2comm & RESET_INTR) | |
705 | mtu3_gadget_reset(mtu); | |
706 | ||
ad0c542c CY |
707 | if (u2comm & LPM_RESUME_INTR) { |
708 | if (!(mtu3_readl(mbase, U3D_POWER_MANAGEMENT) & LPM_HRWE)) | |
709 | mtu3_setbits(mbase, U3D_USB20_MISC_CONTROL, | |
710 | LPM_U3_ACK_EN); | |
711 | } | |
712 | ||
df2069ac CY |
713 | return IRQ_HANDLED; |
714 | } | |
715 | ||
a8bac371 | 716 | static irqreturn_t mtu3_irq(int irq, void *data) |
df2069ac CY |
717 | { |
718 | struct mtu3 *mtu = (struct mtu3 *)data; | |
719 | unsigned long flags; | |
720 | u32 level1; | |
721 | ||
722 | spin_lock_irqsave(&mtu->lock, flags); | |
723 | ||
724 | /* U3D_LV1ISR is RU */ | |
725 | level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR); | |
726 | level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER); | |
727 | ||
728 | if (level1 & EP_CTRL_INTR) | |
729 | mtu3_link_isr(mtu); | |
730 | ||
731 | if (level1 & MAC2_INTR) | |
732 | mtu3_u2_common_isr(mtu); | |
733 | ||
a29de31b CY |
734 | if (level1 & MAC3_INTR) |
735 | mtu3_u3_ltssm_isr(mtu); | |
736 | ||
df2069ac CY |
737 | if (level1 & BMU_INTR) |
738 | mtu3_ep0_isr(mtu); | |
739 | ||
740 | if (level1 & QMU_INTR) | |
741 | mtu3_qmu_isr(mtu); | |
742 | ||
743 | spin_unlock_irqrestore(&mtu->lock, flags); | |
744 | ||
745 | return IRQ_HANDLED; | |
746 | } | |
747 | ||
748 | static int mtu3_hw_init(struct mtu3 *mtu) | |
749 | { | |
220d88ea | 750 | u32 cap_dev; |
df2069ac CY |
751 | int ret; |
752 | ||
220d88ea CY |
753 | mtu->hw_version = mtu3_readl(mtu->ippc_base, U3D_SSUSB_HW_ID); |
754 | ||
755 | cap_dev = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP); | |
756 | mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(cap_dev); | |
757 | ||
758 | dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version, | |
759 | mtu->is_u3_ip ? "U3" : "U2"); | |
760 | ||
df2069ac CY |
761 | mtu3_device_reset(mtu); |
762 | ||
763 | ret = mtu3_device_enable(mtu); | |
764 | if (ret) { | |
765 | dev_err(mtu->dev, "device enable failed %d\n", ret); | |
766 | return ret; | |
767 | } | |
768 | ||
769 | ret = mtu3_mem_alloc(mtu); | |
770 | if (ret) | |
771 | return -ENOMEM; | |
772 | ||
773 | mtu3_regs_init(mtu); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | static void mtu3_hw_exit(struct mtu3 *mtu) | |
779 | { | |
780 | mtu3_device_disable(mtu); | |
781 | mtu3_mem_free(mtu); | |
782 | } | |
783 | ||
1a46dfea CY |
784 | /** |
785 | * we set 32-bit DMA mask by default, here check whether the controller | |
786 | * supports 36-bit DMA or not, if it does, set 36-bit DMA mask. | |
787 | */ | |
788 | static int mtu3_set_dma_mask(struct mtu3 *mtu) | |
789 | { | |
790 | struct device *dev = mtu->dev; | |
791 | bool is_36bit = false; | |
792 | int ret = 0; | |
793 | u32 value; | |
794 | ||
795 | value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL); | |
796 | if (value & DMA_ADDR_36BIT) { | |
797 | is_36bit = true; | |
798 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); | |
799 | /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */ | |
800 | if (ret) { | |
801 | is_36bit = false; | |
802 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); | |
803 | } | |
804 | } | |
805 | dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32"); | |
806 | ||
807 | return ret; | |
808 | } | |
df2069ac | 809 | |
b3f4e727 | 810 | int ssusb_gadget_init(struct ssusb_mtk *ssusb) |
df2069ac | 811 | { |
b3f4e727 CY |
812 | struct device *dev = ssusb->dev; |
813 | struct platform_device *pdev = to_platform_device(dev); | |
814 | struct mtu3 *mtu = NULL; | |
815 | struct resource *res; | |
816 | int ret = -ENOMEM; | |
817 | ||
818 | mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL); | |
819 | if (mtu == NULL) | |
820 | return -ENOMEM; | |
821 | ||
822 | mtu->irq = platform_get_irq(pdev, 0); | |
c162ff0a | 823 | if (mtu->irq < 0) { |
b3f4e727 | 824 | dev_err(dev, "fail to get irq number\n"); |
c162ff0a | 825 | return mtu->irq; |
b3f4e727 CY |
826 | } |
827 | dev_info(dev, "irq %d\n", mtu->irq); | |
df2069ac | 828 | |
b3f4e727 CY |
829 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); |
830 | mtu->mac_base = devm_ioremap_resource(dev, res); | |
831 | if (IS_ERR(mtu->mac_base)) { | |
832 | dev_err(dev, "error mapping memory for dev mac\n"); | |
833 | return PTR_ERR(mtu->mac_base); | |
834 | } | |
835 | ||
836 | spin_lock_init(&mtu->lock); | |
837 | mtu->dev = dev; | |
838 | mtu->ippc_base = ssusb->ippc_base; | |
839 | ssusb->mac_base = mtu->mac_base; | |
840 | ssusb->u3d = mtu; | |
841 | mtu->ssusb = ssusb; | |
a29de31b CY |
842 | mtu->max_speed = usb_get_maximum_speed(dev); |
843 | ||
844 | /* check the max_speed parameter */ | |
845 | switch (mtu->max_speed) { | |
846 | case USB_SPEED_FULL: | |
847 | case USB_SPEED_HIGH: | |
848 | case USB_SPEED_SUPER: | |
4d79e042 | 849 | case USB_SPEED_SUPER_PLUS: |
a29de31b CY |
850 | break; |
851 | default: | |
852 | dev_err(dev, "invalid max_speed: %s\n", | |
853 | usb_speed_string(mtu->max_speed)); | |
854 | /* fall through */ | |
855 | case USB_SPEED_UNKNOWN: | |
4d79e042 CY |
856 | /* default as SSP */ |
857 | mtu->max_speed = USB_SPEED_SUPER_PLUS; | |
a29de31b CY |
858 | break; |
859 | } | |
860 | ||
861 | dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n", | |
862 | mtu->mac_base, mtu->ippc_base); | |
863 | ||
df2069ac CY |
864 | ret = mtu3_hw_init(mtu); |
865 | if (ret) { | |
866 | dev_err(dev, "mtu3 hw init failed:%d\n", ret); | |
867 | return ret; | |
868 | } | |
869 | ||
1a46dfea CY |
870 | ret = mtu3_set_dma_mask(mtu); |
871 | if (ret) { | |
872 | dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret); | |
873 | goto dma_mask_err; | |
874 | } | |
875 | ||
df2069ac CY |
876 | ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu); |
877 | if (ret) { | |
878 | dev_err(dev, "request irq %d failed!\n", mtu->irq); | |
879 | goto irq_err; | |
880 | } | |
881 | ||
882 | device_init_wakeup(dev, true); | |
883 | ||
884 | ret = mtu3_gadget_setup(mtu); | |
885 | if (ret) { | |
886 | dev_err(dev, "mtu3 gadget init failed:%d\n", ret); | |
887 | goto gadget_err; | |
888 | } | |
889 | ||
d0ed062a CY |
890 | /* init as host mode, power down device IP for power saving */ |
891 | if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) | |
892 | mtu3_stop(mtu); | |
893 | ||
df2069ac CY |
894 | dev_dbg(dev, " %s() done...\n", __func__); |
895 | ||
896 | return 0; | |
897 | ||
898 | gadget_err: | |
899 | device_init_wakeup(dev, false); | |
900 | ||
1a46dfea | 901 | dma_mask_err: |
df2069ac CY |
902 | irq_err: |
903 | mtu3_hw_exit(mtu); | |
b3f4e727 | 904 | ssusb->u3d = NULL; |
df2069ac CY |
905 | dev_err(dev, " %s() fail...\n", __func__); |
906 | ||
907 | return ret; | |
908 | } | |
909 | ||
b3f4e727 | 910 | void ssusb_gadget_exit(struct ssusb_mtk *ssusb) |
df2069ac | 911 | { |
b3f4e727 CY |
912 | struct mtu3 *mtu = ssusb->u3d; |
913 | ||
df2069ac | 914 | mtu3_gadget_cleanup(mtu); |
b3f4e727 | 915 | device_init_wakeup(ssusb->dev, false); |
df2069ac CY |
916 | mtu3_hw_exit(mtu); |
917 | } |