Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
db11e47d SS |
2 | /* |
3 | * Driver for the NXP ISP1760 chip | |
4 | * | |
5 | * However, the code might contain some bugs. What doesn't work for sure is: | |
6 | * - ISO | |
7 | * - OTG | |
8 | e The interrupt line is configured as active low, level. | |
9 | * | |
10 | * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> | |
11 | * | |
71a9f9d2 AB |
12 | * (c) 2011 Arvid Brodin <arvid.brodin@enea.com> |
13 | * | |
60d789f3 RMS |
14 | * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org> |
15 | * | |
db11e47d | 16 | */ |
7eb42c6e | 17 | #include <linux/gpio/consumer.h> |
db11e47d SS |
18 | #include <linux/module.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/usb.h> | |
27729aad | 23 | #include <linux/usb/hcd.h> |
db11e47d SS |
24 | #include <linux/debugfs.h> |
25 | #include <linux/uaccess.h> | |
26 | #include <linux/io.h> | |
08305b45 | 27 | #include <linux/iopoll.h> |
db8516f6 | 28 | #include <linux/mm.h> |
6d50c60e | 29 | #include <linux/timer.h> |
db11e47d | 30 | #include <asm/unaligned.h> |
db8516f6 | 31 | #include <asm/cacheflush.h> |
db11e47d | 32 | |
5171446a | 33 | #include "isp1760-core.h" |
db11e47d | 34 | #include "isp1760-hcd.h" |
e19c99e7 | 35 | #include "isp1760-regs.h" |
db11e47d SS |
36 | |
37 | static struct kmem_cache *qtd_cachep; | |
38 | static struct kmem_cache *qh_cachep; | |
71a9f9d2 | 39 | static struct kmem_cache *urb_listitem_cachep; |
db11e47d | 40 | |
f0bdbb0e LP |
41 | typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, |
42 | struct isp1760_qtd *qtd); | |
db11e47d SS |
43 | |
44 | static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) | |
45 | { | |
cdd36e87 | 46 | return *(struct isp1760_hcd **)hcd->hcd_priv; |
db11e47d | 47 | } |
db11e47d | 48 | |
60d789f3 RMS |
49 | #define dw_to_le32(x) (cpu_to_le32((__force u32)x)) |
50 | #define le32_to_dw(x) ((__force __dw)(le32_to_cpu(x))) | |
51 | ||
e19c99e7 LP |
52 | /* urb state*/ |
53 | #define DELETE_URB (0x0008) | |
54 | #define NO_TRANSFER_ACTIVE (0xffffffff) | |
55 | ||
56 | /* Philips Proprietary Transfer Descriptor (PTD) */ | |
57 | typedef __u32 __bitwise __dw; | |
58 | struct ptd { | |
59 | __dw dw0; | |
60 | __dw dw1; | |
61 | __dw dw2; | |
62 | __dw dw3; | |
63 | __dw dw4; | |
64 | __dw dw5; | |
65 | __dw dw6; | |
66 | __dw dw7; | |
67 | }; | |
60d789f3 RMS |
68 | |
69 | struct ptd_le32 { | |
70 | __le32 dw0; | |
71 | __le32 dw1; | |
72 | __le32 dw2; | |
73 | __le32 dw3; | |
74 | __le32 dw4; | |
75 | __le32 dw5; | |
76 | __le32 dw6; | |
77 | __le32 dw7; | |
78 | }; | |
79 | ||
e19c99e7 LP |
80 | #define PTD_OFFSET 0x0400 |
81 | #define ISO_PTD_OFFSET 0x0400 | |
82 | #define INT_PTD_OFFSET 0x0800 | |
83 | #define ATL_PTD_OFFSET 0x0c00 | |
84 | #define PAYLOAD_OFFSET 0x1000 | |
85 | ||
1da9e1c0 RMS |
86 | #define ISP_BANK_0 0x00 |
87 | #define ISP_BANK_1 0x01 | |
88 | #define ISP_BANK_2 0x02 | |
89 | #define ISP_BANK_3 0x03 | |
90 | ||
abfabc8a RMS |
91 | #define TO_DW(x) ((__force __dw)x) |
92 | #define TO_U32(x) ((__force u32)x) | |
93 | ||
94 | /* ATL */ | |
95 | /* DW0 */ | |
96 | #define DW0_VALID_BIT TO_DW(1) | |
97 | #define FROM_DW0_VALID(x) (TO_U32(x) & 0x01) | |
98 | #define TO_DW0_LENGTH(x) TO_DW((((u32)x) << 3)) | |
99 | #define TO_DW0_MAXPACKET(x) TO_DW((((u32)x) << 18)) | |
100 | #define TO_DW0_MULTI(x) TO_DW((((u32)x) << 29)) | |
101 | #define TO_DW0_ENDPOINT(x) TO_DW((((u32)x) << 31)) | |
e19c99e7 | 102 | /* DW1 */ |
abfabc8a RMS |
103 | #define TO_DW1_DEVICE_ADDR(x) TO_DW((((u32)x) << 3)) |
104 | #define TO_DW1_PID_TOKEN(x) TO_DW((((u32)x) << 10)) | |
105 | #define DW1_TRANS_BULK TO_DW(((u32)2 << 12)) | |
106 | #define DW1_TRANS_INT TO_DW(((u32)3 << 12)) | |
107 | #define DW1_TRANS_SPLIT TO_DW(((u32)1 << 14)) | |
108 | #define DW1_SE_USB_LOSPEED TO_DW(((u32)2 << 16)) | |
109 | #define TO_DW1_PORT_NUM(x) TO_DW((((u32)x) << 18)) | |
110 | #define TO_DW1_HUB_NUM(x) TO_DW((((u32)x) << 25)) | |
e19c99e7 | 111 | /* DW2 */ |
abfabc8a RMS |
112 | #define TO_DW2_DATA_START_ADDR(x) TO_DW((((u32)x) << 8)) |
113 | #define TO_DW2_RL(x) TO_DW(((x) << 25)) | |
114 | #define FROM_DW2_RL(x) ((TO_U32(x) >> 25) & 0xf) | |
e19c99e7 | 115 | /* DW3 */ |
60d789f3 | 116 | #define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x3fff) |
abfabc8a RMS |
117 | #define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x07ff) |
118 | #define TO_DW3_NAKCOUNT(x) TO_DW(((x) << 19)) | |
119 | #define FROM_DW3_NAKCOUNT(x) ((TO_U32(x) >> 19) & 0xf) | |
120 | #define TO_DW3_CERR(x) TO_DW(((x) << 23)) | |
121 | #define FROM_DW3_CERR(x) ((TO_U32(x) >> 23) & 0x3) | |
122 | #define TO_DW3_DATA_TOGGLE(x) TO_DW(((x) << 25)) | |
123 | #define FROM_DW3_DATA_TOGGLE(x) ((TO_U32(x) >> 25) & 0x1) | |
124 | #define TO_DW3_PING(x) TO_DW(((x) << 26)) | |
125 | #define FROM_DW3_PING(x) ((TO_U32(x) >> 26) & 0x1) | |
126 | #define DW3_ERROR_BIT TO_DW((1 << 28)) | |
127 | #define DW3_BABBLE_BIT TO_DW((1 << 29)) | |
128 | #define DW3_HALT_BIT TO_DW((1 << 30)) | |
129 | #define DW3_ACTIVE_BIT TO_DW((1 << 31)) | |
130 | #define FROM_DW3_ACTIVE(x) ((TO_U32(x) >> 31) & 0x01) | |
e19c99e7 LP |
131 | |
132 | #define INT_UNDERRUN (1 << 2) | |
133 | #define INT_BABBLE (1 << 1) | |
134 | #define INT_EXACT (1 << 0) | |
135 | ||
136 | #define SETUP_PID (2) | |
137 | #define IN_PID (1) | |
138 | #define OUT_PID (0) | |
139 | ||
140 | /* Errata 1 */ | |
141 | #define RL_COUNTER (0) | |
142 | #define NAK_COUNTER (0) | |
60d789f3 | 143 | #define ERR_COUNTER (3) |
db11e47d SS |
144 | |
145 | struct isp1760_qtd { | |
db11e47d | 146 | u8 packet_type; |
db11e47d | 147 | void *data_buffer; |
a041d8e4 AB |
148 | u32 payload_addr; |
149 | ||
db11e47d SS |
150 | /* the rest is HCD-private */ |
151 | struct list_head qtd_list; | |
152 | struct urb *urb; | |
153 | size_t length; | |
71a9f9d2 AB |
154 | size_t actual_length; |
155 | ||
156 | /* QTD_ENQUEUED: waiting for transfer (inactive) */ | |
157 | /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */ | |
158 | /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only | |
159 | interrupt handler may touch this qtd! */ | |
160 | /* QTD_XFER_COMPLETE: payload has been transferred successfully */ | |
161 | /* QTD_RETIRE: transfer error/abort qtd */ | |
162 | #define QTD_ENQUEUED 0 | |
163 | #define QTD_PAYLOAD_ALLOC 1 | |
164 | #define QTD_XFER_STARTED 2 | |
165 | #define QTD_XFER_COMPLETE 3 | |
166 | #define QTD_RETIRE 4 | |
db11e47d | 167 | u32 status; |
db11e47d SS |
168 | }; |
169 | ||
71a9f9d2 | 170 | /* Queue head, one for each active endpoint */ |
db11e47d | 171 | struct isp1760_qh { |
71a9f9d2 | 172 | struct list_head qh_list; |
db11e47d | 173 | struct list_head qtd_list; |
db11e47d SS |
174 | u32 toggle; |
175 | u32 ping; | |
71a9f9d2 | 176 | int slot; |
74ad6029 | 177 | int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ |
71a9f9d2 AB |
178 | }; |
179 | ||
180 | struct urb_listitem { | |
181 | struct list_head urb_list; | |
182 | struct urb *urb; | |
db11e47d SS |
183 | }; |
184 | ||
36815a4a | 185 | static const u32 isp176x_hc_portsc1_fields[] = { |
60d789f3 RMS |
186 | [PORT_OWNER] = BIT(13), |
187 | [PORT_POWER] = BIT(12), | |
188 | [PORT_LSTATUS] = BIT(10), | |
189 | [PORT_RESET] = BIT(8), | |
190 | [PORT_SUSPEND] = BIT(7), | |
191 | [PORT_RESUME] = BIT(6), | |
192 | [PORT_PE] = BIT(2), | |
193 | [PORT_CSC] = BIT(1), | |
194 | [PORT_CONNECT] = BIT(0), | |
195 | }; | |
196 | ||
bedc0c31 | 197 | /* |
1da9e1c0 | 198 | * Access functions for isp176x registers regmap fields |
bedc0c31 | 199 | */ |
1da9e1c0 RMS |
200 | static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field) |
201 | { | |
202 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
203 | ||
204 | return isp1760_field_read(priv->fields, field); | |
205 | } | |
206 | ||
60d789f3 | 207 | /* |
36815a4a | 208 | * We need, in isp176x, to write directly the values to the portsc1 |
60d789f3 RMS |
209 | * register so it will make the other values to trigger. |
210 | */ | |
211 | static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field, | |
212 | u32 val) | |
213 | { | |
36815a4a RMS |
214 | u32 bit = isp176x_hc_portsc1_fields[field]; |
215 | u16 portsc1_reg = priv->is_isp1763 ? ISP1763_HC_PORTSC1 : | |
216 | ISP176x_HC_PORTSC1; | |
217 | u32 port_status = readl(priv->base + portsc1_reg); | |
60d789f3 RMS |
218 | |
219 | if (val) | |
36815a4a | 220 | writel(port_status | bit, priv->base + portsc1_reg); |
60d789f3 | 221 | else |
36815a4a | 222 | writel(port_status & ~bit, priv->base + portsc1_reg); |
60d789f3 RMS |
223 | } |
224 | ||
1da9e1c0 RMS |
225 | static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val) |
226 | { | |
227 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
228 | ||
36815a4a | 229 | if (unlikely((field >= PORT_OWNER && field <= PORT_CONNECT))) |
60d789f3 RMS |
230 | return isp1760_hcd_portsc1_set_clear(priv, field, val); |
231 | ||
1da9e1c0 RMS |
232 | isp1760_field_write(priv->fields, field, val); |
233 | } | |
234 | ||
235 | static void isp1760_hcd_set(struct usb_hcd *hcd, u32 field) | |
236 | { | |
237 | isp1760_hcd_write(hcd, field, 0xFFFFFFFF); | |
238 | } | |
239 | ||
240 | static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field) | |
241 | { | |
242 | isp1760_hcd_write(hcd, field, 0); | |
243 | } | |
244 | ||
60d789f3 RMS |
245 | static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field, |
246 | u32 timeout_us) | |
247 | { | |
248 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
249 | u32 val; | |
250 | ||
251 | isp1760_hcd_set(hcd, field); | |
252 | ||
253 | return regmap_field_read_poll_timeout(priv->fields[field], val, | |
41f67318 | 254 | val, 0, timeout_us); |
60d789f3 RMS |
255 | } |
256 | ||
257 | static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field, | |
258 | u32 timeout_us) | |
1da9e1c0 RMS |
259 | { |
260 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
60d789f3 | 261 | u32 val; |
1da9e1c0 RMS |
262 | |
263 | isp1760_hcd_set(hcd, field); | |
264 | ||
60d789f3 | 265 | return regmap_field_read_poll_timeout(priv->fields[field], val, |
41f67318 | 266 | !val, 0, timeout_us); |
1da9e1c0 RMS |
267 | } |
268 | ||
60d789f3 RMS |
269 | static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field, |
270 | u32 timeout_us) | |
db11e47d | 271 | { |
1da9e1c0 | 272 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
60d789f3 | 273 | u32 val; |
1da9e1c0 RMS |
274 | |
275 | isp1760_hcd_clear(hcd, field); | |
276 | ||
60d789f3 | 277 | return regmap_field_read_poll_timeout(priv->fields[field], val, |
41f67318 | 278 | !val, 0, timeout_us); |
db11e47d SS |
279 | } |
280 | ||
1da9e1c0 | 281 | static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field) |
db11e47d | 282 | { |
1da9e1c0 | 283 | return !!isp1760_hcd_read(hcd, field); |
db11e47d SS |
284 | } |
285 | ||
60d789f3 RMS |
286 | static bool isp1760_hcd_ppc_is_set(struct usb_hcd *hcd) |
287 | { | |
288 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
289 | ||
290 | if (priv->is_isp1763) | |
291 | return true; | |
292 | ||
293 | return isp1760_hcd_is_set(hcd, HCS_PPC); | |
294 | } | |
295 | ||
296 | static u32 isp1760_hcd_n_ports(struct usb_hcd *hcd) | |
297 | { | |
298 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
299 | ||
300 | if (priv->is_isp1763) | |
301 | return 1; | |
302 | ||
303 | return isp1760_hcd_read(hcd, HCS_N_PORTS); | |
304 | } | |
305 | ||
db11e47d | 306 | /* |
bedc0c31 AB |
307 | * Access functions for isp176x memory (offset >= 0x0400). |
308 | * | |
309 | * bank_reads8() reads memory locations prefetched by an earlier write to | |
310 | * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- | |
60d789f3 | 311 | * bank optimizations, you should use the more generic mem_read() below. |
bedc0c31 AB |
312 | * |
313 | * For access to ptd memory, use the specialized ptd_read() and ptd_write() | |
314 | * below. | |
315 | * | |
316 | * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() | |
db11e47d SS |
317 | * doesn't quite work because some people have to enforce 32-bit access |
318 | */ | |
bedc0c31 AB |
319 | static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, |
320 | __u32 *dst, u32 bytes) | |
db11e47d | 321 | { |
bedc0c31 | 322 | __u32 __iomem *src; |
db11e47d | 323 | u32 val; |
bedc0c31 AB |
324 | __u8 *src_byteptr; |
325 | __u8 *dst_byteptr; | |
db11e47d | 326 | |
bedc0c31 | 327 | src = src_base + (bank_addr | src_offset); |
db11e47d | 328 | |
bedc0c31 AB |
329 | if (src_offset < PAYLOAD_OFFSET) { |
330 | while (bytes >= 4) { | |
03e28d52 | 331 | *dst = readl_relaxed(src); |
bedc0c31 AB |
332 | bytes -= 4; |
333 | src++; | |
334 | dst++; | |
335 | } | |
336 | } else { | |
337 | while (bytes >= 4) { | |
338 | *dst = __raw_readl(src); | |
339 | bytes -= 4; | |
340 | src++; | |
341 | dst++; | |
342 | } | |
db11e47d SS |
343 | } |
344 | ||
bedc0c31 | 345 | if (!bytes) |
db11e47d SS |
346 | return; |
347 | ||
348 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully | |
349 | * allocated. | |
350 | */ | |
bedc0c31 | 351 | if (src_offset < PAYLOAD_OFFSET) |
03e28d52 | 352 | val = readl_relaxed(src); |
bedc0c31 AB |
353 | else |
354 | val = __raw_readl(src); | |
355 | ||
356 | dst_byteptr = (void *) dst; | |
357 | src_byteptr = (void *) &val; | |
358 | while (bytes > 0) { | |
359 | *dst_byteptr = *src_byteptr; | |
360 | dst_byteptr++; | |
361 | src_byteptr++; | |
362 | bytes--; | |
db11e47d SS |
363 | } |
364 | } | |
365 | ||
60d789f3 RMS |
366 | static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst, |
367 | u32 bytes) | |
db11e47d | 368 | { |
60d789f3 RMS |
369 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
370 | ||
36815a4a | 371 | isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset); |
60d789f3 | 372 | ndelay(100); |
1da9e1c0 | 373 | |
60d789f3 RMS |
374 | bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes); |
375 | } | |
1da9e1c0 | 376 | |
60d789f3 RMS |
377 | /* |
378 | * ISP1763 does not have the banks direct host controller memory access, | |
379 | * needs to use the HC_DATA register. Add data read/write according to this, | |
380 | * and also adjust 16bit access. | |
381 | */ | |
382 | static void isp1763_mem_read(struct usb_hcd *hcd, u16 srcaddr, | |
383 | u16 *dstptr, u32 bytes) | |
384 | { | |
385 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
386 | ||
387 | /* Write the starting device address to the hcd memory register */ | |
388 | isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, srcaddr); | |
389 | ndelay(100); /* Delay between consecutive access */ | |
390 | ||
391 | /* As long there are at least 16-bit to read ... */ | |
392 | while (bytes >= 2) { | |
393 | *dstptr = __raw_readw(priv->base + ISP1763_HC_DATA); | |
394 | bytes -= 2; | |
395 | dstptr++; | |
396 | } | |
397 | ||
398 | /* If there are no more bytes to read, return */ | |
399 | if (bytes <= 0) | |
400 | return; | |
401 | ||
402 | *((u8 *)dstptr) = (u8)(readw(priv->base + ISP1763_HC_DATA) & 0xFF); | |
403 | } | |
404 | ||
405 | static void mem_read(struct usb_hcd *hcd, u32 src_offset, __u32 *dst, | |
406 | u32 bytes) | |
407 | { | |
408 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
409 | ||
410 | if (!priv->is_isp1763) | |
411 | return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes); | |
412 | ||
413 | isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes); | |
bedc0c31 AB |
414 | } |
415 | ||
60d789f3 RMS |
416 | static void isp1760_mem_write(void __iomem *dst_base, u32 dst_offset, |
417 | __u32 const *src, u32 bytes) | |
bedc0c31 AB |
418 | { |
419 | __u32 __iomem *dst; | |
420 | ||
421 | dst = dst_base + dst_offset; | |
422 | ||
423 | if (dst_offset < PAYLOAD_OFFSET) { | |
424 | while (bytes >= 4) { | |
03e28d52 | 425 | writel_relaxed(*src, dst); |
bedc0c31 AB |
426 | bytes -= 4; |
427 | src++; | |
428 | dst++; | |
429 | } | |
430 | } else { | |
431 | while (bytes >= 4) { | |
432 | __raw_writel(*src, dst); | |
433 | bytes -= 4; | |
434 | src++; | |
435 | dst++; | |
436 | } | |
db11e47d SS |
437 | } |
438 | ||
bedc0c31 | 439 | if (!bytes) |
db11e47d | 440 | return; |
bedc0c31 AB |
441 | /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the |
442 | * extra bytes should not be read by the HW. | |
db11e47d SS |
443 | */ |
444 | ||
bedc0c31 | 445 | if (dst_offset < PAYLOAD_OFFSET) |
03e28d52 | 446 | writel_relaxed(*src, dst); |
bedc0c31 AB |
447 | else |
448 | __raw_writel(*src, dst); | |
db11e47d SS |
449 | } |
450 | ||
60d789f3 RMS |
451 | static void isp1763_mem_write(struct usb_hcd *hcd, u16 dstaddr, u16 *src, |
452 | u32 bytes) | |
453 | { | |
454 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
455 | ||
456 | /* Write the starting device address to the hcd memory register */ | |
457 | isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, dstaddr); | |
458 | ndelay(100); /* Delay between consecutive access */ | |
459 | ||
460 | while (bytes >= 2) { | |
461 | /* Get and write the data; then adjust the data ptr and len */ | |
462 | __raw_writew(*src, priv->base + ISP1763_HC_DATA); | |
463 | bytes -= 2; | |
464 | src++; | |
465 | } | |
466 | ||
467 | /* If there are no more bytes to process, return */ | |
468 | if (bytes <= 0) | |
469 | return; | |
470 | ||
471 | /* | |
472 | * The only way to get here is if there is a single byte left, | |
473 | * get it and write it to the data reg; | |
474 | */ | |
475 | writew(*((u8 *)src), priv->base + ISP1763_HC_DATA); | |
476 | } | |
477 | ||
478 | static void mem_write(struct usb_hcd *hcd, u32 dst_offset, __u32 *src, | |
479 | u32 bytes) | |
480 | { | |
481 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
482 | ||
483 | if (!priv->is_isp1763) | |
484 | return isp1760_mem_write(priv->base, dst_offset, src, bytes); | |
485 | ||
486 | isp1763_mem_write(hcd, dst_offset, (u16 *)src, bytes); | |
487 | } | |
488 | ||
bedc0c31 AB |
489 | /* |
490 | * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, | |
491 | * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. | |
492 | */ | |
60d789f3 RMS |
493 | static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
494 | struct ptd *ptd) | |
bedc0c31 | 495 | { |
60d789f3 RMS |
496 | u16 src_offset = ptd_offset + slot * sizeof(*ptd); |
497 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
498 | ||
36815a4a | 499 | isp1760_reg_write(priv->regs, ISP176x_HC_MEMORY, src_offset); |
bedc0c31 | 500 | ndelay(90); |
60d789f3 RMS |
501 | |
502 | bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd, | |
503 | sizeof(*ptd)); | |
504 | } | |
505 | ||
506 | static void isp1763_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, | |
507 | struct ptd *ptd) | |
508 | { | |
509 | u16 src_offset = ptd_offset + slot * sizeof(*ptd); | |
510 | struct ptd_le32 le32_ptd; | |
511 | ||
512 | isp1763_mem_read(hcd, src_offset, (u16 *)&le32_ptd, sizeof(le32_ptd)); | |
513 | /* Normalize the data obtained */ | |
514 | ptd->dw0 = le32_to_dw(le32_ptd.dw0); | |
515 | ptd->dw1 = le32_to_dw(le32_ptd.dw1); | |
516 | ptd->dw2 = le32_to_dw(le32_ptd.dw2); | |
517 | ptd->dw3 = le32_to_dw(le32_ptd.dw3); | |
518 | ptd->dw4 = le32_to_dw(le32_ptd.dw4); | |
519 | ptd->dw5 = le32_to_dw(le32_ptd.dw5); | |
520 | ptd->dw6 = le32_to_dw(le32_ptd.dw6); | |
521 | ptd->dw7 = le32_to_dw(le32_ptd.dw7); | |
522 | } | |
523 | ||
524 | static void ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, | |
525 | struct ptd *ptd) | |
526 | { | |
527 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
528 | ||
529 | if (!priv->is_isp1763) | |
530 | return isp1760_ptd_read(hcd, ptd_offset, slot, ptd); | |
531 | ||
532 | isp1763_ptd_read(hcd, ptd_offset, slot, ptd); | |
533 | } | |
534 | ||
535 | static void isp1763_ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, | |
536 | struct ptd *cpu_ptd) | |
537 | { | |
538 | u16 dst_offset = ptd_offset + slot * sizeof(*cpu_ptd); | |
539 | struct ptd_le32 ptd; | |
540 | ||
541 | ptd.dw0 = dw_to_le32(cpu_ptd->dw0); | |
542 | ptd.dw1 = dw_to_le32(cpu_ptd->dw1); | |
543 | ptd.dw2 = dw_to_le32(cpu_ptd->dw2); | |
544 | ptd.dw3 = dw_to_le32(cpu_ptd->dw3); | |
545 | ptd.dw4 = dw_to_le32(cpu_ptd->dw4); | |
546 | ptd.dw5 = dw_to_le32(cpu_ptd->dw5); | |
547 | ptd.dw6 = dw_to_le32(cpu_ptd->dw6); | |
548 | ptd.dw7 = dw_to_le32(cpu_ptd->dw7); | |
549 | ||
550 | isp1763_mem_write(hcd, dst_offset, (u16 *)&ptd.dw0, | |
551 | 8 * sizeof(ptd.dw0)); | |
bedc0c31 AB |
552 | } |
553 | ||
60d789f3 RMS |
554 | static void isp1760_ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, |
555 | struct ptd *ptd) | |
bedc0c31 | 556 | { |
60d789f3 RMS |
557 | u32 dst_offset = ptd_offset + slot * sizeof(*ptd); |
558 | ||
559 | /* | |
560 | * Make sure dw0 gets written last (after other dw's and after payload) | |
561 | * since it contains the enable bit | |
562 | */ | |
563 | isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0), | |
564 | (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1)); | |
bedc0c31 | 565 | wmb(); |
60d789f3 RMS |
566 | isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0, |
567 | sizeof(ptd->dw0)); | |
bedc0c31 AB |
568 | } |
569 | ||
60d789f3 RMS |
570 | static void ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, |
571 | struct ptd *ptd) | |
572 | { | |
573 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
574 | ||
575 | if (!priv->is_isp1763) | |
576 | return isp1760_ptd_write(priv->base, ptd_offset, slot, ptd); | |
577 | ||
578 | isp1763_ptd_write(hcd, ptd_offset, slot, ptd); | |
579 | } | |
bedc0c31 | 580 | |
db11e47d SS |
581 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ |
582 | static void init_memory(struct isp1760_hcd *priv) | |
583 | { | |
a74f639c RMS |
584 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
585 | int i, j, curr; | |
a041d8e4 | 586 | u32 payload_addr; |
db11e47d | 587 | |
a041d8e4 | 588 | payload_addr = PAYLOAD_OFFSET; |
db11e47d | 589 | |
f757f929 RMS |
590 | for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++, curr += j) { |
591 | for (j = 0; j < mem->blocks[i]; j++) { | |
a74f639c RMS |
592 | priv->memory_pool[curr + j].start = payload_addr; |
593 | priv->memory_pool[curr + j].size = mem->blocks_size[i]; | |
594 | priv->memory_pool[curr + j].free = 1; | |
595 | payload_addr += priv->memory_pool[curr + j].size; | |
596 | } | |
db11e47d SS |
597 | } |
598 | ||
a74f639c RMS |
599 | WARN_ON(payload_addr - priv->memory_pool[0].start > |
600 | mem->payload_area_size); | |
db11e47d SS |
601 | } |
602 | ||
6bda21bc | 603 | static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
db11e47d | 604 | { |
6bda21bc | 605 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
a74f639c | 606 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
db11e47d SS |
607 | int i; |
608 | ||
34537731 | 609 | WARN_ON(qtd->payload_addr); |
a041d8e4 AB |
610 | |
611 | if (!qtd->length) | |
612 | return; | |
db11e47d | 613 | |
a74f639c | 614 | for (i = 0; i < mem->payload_blocks; i++) { |
a041d8e4 | 615 | if (priv->memory_pool[i].size >= qtd->length && |
db11e47d | 616 | priv->memory_pool[i].free) { |
db11e47d | 617 | priv->memory_pool[i].free = 0; |
a041d8e4 AB |
618 | qtd->payload_addr = priv->memory_pool[i].start; |
619 | return; | |
db11e47d SS |
620 | } |
621 | } | |
db11e47d SS |
622 | } |
623 | ||
6bda21bc | 624 | static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
db11e47d | 625 | { |
6bda21bc | 626 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
a74f639c | 627 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
db11e47d SS |
628 | int i; |
629 | ||
a041d8e4 | 630 | if (!qtd->payload_addr) |
db11e47d SS |
631 | return; |
632 | ||
a74f639c | 633 | for (i = 0; i < mem->payload_blocks; i++) { |
a041d8e4 | 634 | if (priv->memory_pool[i].start == qtd->payload_addr) { |
34537731 | 635 | WARN_ON(priv->memory_pool[i].free); |
db11e47d | 636 | priv->memory_pool[i].free = 1; |
a041d8e4 AB |
637 | qtd->payload_addr = 0; |
638 | return; | |
db11e47d SS |
639 | } |
640 | } | |
641 | ||
6bda21bc AB |
642 | dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", |
643 | __func__, qtd->payload_addr); | |
71a9f9d2 AB |
644 | WARN_ON(1); |
645 | qtd->payload_addr = 0; | |
db11e47d SS |
646 | } |
647 | ||
db11e47d | 648 | /* reset a non-running (STS_HALT == 1) controller */ |
6bda21bc | 649 | static int ehci_reset(struct usb_hcd *hcd) |
db11e47d | 650 | { |
6bda21bc AB |
651 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
652 | ||
db11e47d SS |
653 | hcd->state = HC_STATE_HALT; |
654 | priv->next_statechange = jiffies; | |
992510f3 | 655 | |
60d789f3 | 656 | return isp1760_hcd_set_and_wait_swap(hcd, CMD_RESET, 250 * 1000); |
db11e47d SS |
657 | } |
658 | ||
71a9f9d2 | 659 | static struct isp1760_qh *qh_alloc(gfp_t flags) |
db11e47d SS |
660 | { |
661 | struct isp1760_qh *qh; | |
662 | ||
663 | qh = kmem_cache_zalloc(qh_cachep, flags); | |
664 | if (!qh) | |
71a9f9d2 | 665 | return NULL; |
db11e47d | 666 | |
71a9f9d2 | 667 | INIT_LIST_HEAD(&qh->qh_list); |
db11e47d | 668 | INIT_LIST_HEAD(&qh->qtd_list); |
71a9f9d2 AB |
669 | qh->slot = -1; |
670 | ||
db11e47d SS |
671 | return qh; |
672 | } | |
673 | ||
71a9f9d2 AB |
674 | static void qh_free(struct isp1760_qh *qh) |
675 | { | |
676 | WARN_ON(!list_empty(&qh->qtd_list)); | |
677 | WARN_ON(qh->slot > -1); | |
678 | kmem_cache_free(qh_cachep, qh); | |
679 | } | |
db11e47d SS |
680 | |
681 | /* one-time init, only for memory state */ | |
682 | static int priv_init(struct usb_hcd *hcd) | |
683 | { | |
1da9e1c0 RMS |
684 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
685 | u32 isoc_cache; | |
686 | u32 isoc_thres; | |
e08f6a27 | 687 | int i; |
db11e47d SS |
688 | |
689 | spin_lock_init(&priv->lock); | |
690 | ||
e08f6a27 AB |
691 | for (i = 0; i < QH_END; i++) |
692 | INIT_LIST_HEAD(&priv->qh_list[i]); | |
71a9f9d2 | 693 | |
db11e47d SS |
694 | /* |
695 | * hw default: 1K periodic list heads, one per frame. | |
696 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
697 | */ | |
698 | priv->periodic_size = DEFAULT_I_TDPS; | |
699 | ||
60d789f3 RMS |
700 | if (priv->is_isp1763) { |
701 | priv->i_thresh = 2; | |
702 | return 0; | |
703 | } | |
704 | ||
db11e47d | 705 | /* controllers may cache some of the periodic schedule ... */ |
1da9e1c0 RMS |
706 | isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE); |
707 | isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES); | |
708 | ||
db11e47d | 709 | /* full frame cache */ |
1da9e1c0 | 710 | if (isoc_cache) |
db11e47d SS |
711 | priv->i_thresh = 8; |
712 | else /* N microframes cached */ | |
1da9e1c0 | 713 | priv->i_thresh = 2 + isoc_thres; |
db11e47d SS |
714 | |
715 | return 0; | |
716 | } | |
717 | ||
718 | static int isp1760_hc_setup(struct usb_hcd *hcd) | |
719 | { | |
720 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
60d789f3 | 721 | u32 atx_reset; |
db11e47d | 722 | int result; |
1da9e1c0 | 723 | u32 scratch; |
60d789f3 | 724 | u32 pattern; |
1da9e1c0 | 725 | |
60d789f3 RMS |
726 | if (priv->is_isp1763) |
727 | pattern = 0xcafe; | |
728 | else | |
729 | pattern = 0xdeadcafe; | |
730 | ||
731 | isp1760_hcd_write(hcd, HC_SCRATCH, pattern); | |
3faefc88 | 732 | |
8472896f RMS |
733 | /* |
734 | * we do not care about the read value here we just want to | |
735 | * change bus pattern. | |
736 | */ | |
737 | isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); | |
60d789f3 RMS |
738 | scratch = isp1760_hcd_read(hcd, HC_SCRATCH); |
739 | if (scratch != pattern) { | |
8472896f RMS |
740 | dev_err(hcd->self.controller, "Scratch test failed. 0x%08x\n", |
741 | scratch); | |
db11e47d SS |
742 | return -ENODEV; |
743 | } | |
744 | ||
5171446a LP |
745 | /* |
746 | * The RESET_HC bit in the SW_RESET register is supposed to reset the | |
747 | * host controller without touching the CPU interface registers, but at | |
748 | * least on the ISP1761 it seems to behave as the RESET_ALL bit and | |
749 | * reset the whole device. We thus can't use it here, so let's reset | |
750 | * the host controller through the EHCI USB Command register. The device | |
751 | * has been reset in core code anyway, so this shouldn't matter. | |
752 | */ | |
60d789f3 RMS |
753 | isp1760_hcd_clear(hcd, ISO_BUF_FILL); |
754 | isp1760_hcd_clear(hcd, INT_BUF_FILL); | |
755 | isp1760_hcd_clear(hcd, ATL_BUF_FILL); | |
756 | ||
757 | isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); | |
758 | isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); | |
759 | isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); | |
db11e47d | 760 | |
6bda21bc | 761 | result = ehci_reset(hcd); |
db11e47d SS |
762 | if (result) |
763 | return result; | |
764 | ||
765 | /* Step 11 passed */ | |
766 | ||
db11e47d | 767 | /* ATL reset */ |
60d789f3 RMS |
768 | if (priv->is_isp1763) |
769 | atx_reset = SW_RESET_RESET_ATX; | |
770 | else | |
771 | atx_reset = ALL_ATX_RESET; | |
772 | ||
773 | isp1760_hcd_set(hcd, atx_reset); | |
db11e47d | 774 | mdelay(10); |
60d789f3 | 775 | isp1760_hcd_clear(hcd, atx_reset); |
db11e47d | 776 | |
60d789f3 RMS |
777 | if (priv->is_isp1763) { |
778 | isp1760_hcd_set(hcd, HW_OTG_DISABLE); | |
779 | isp1760_hcd_set(hcd, HW_SW_SEL_HC_DC_CLEAR); | |
780 | isp1760_hcd_set(hcd, HW_HC_2_DIS_CLEAR); | |
781 | mdelay(10); | |
782 | ||
783 | isp1760_hcd_set(hcd, HW_INTF_LOCK); | |
784 | } | |
785 | ||
786 | isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); | |
787 | isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); | |
db11e47d SS |
788 | |
789 | return priv_init(hcd); | |
790 | } | |
791 | ||
db11e47d SS |
792 | static u32 base_to_chip(u32 base) |
793 | { | |
794 | return ((base - 0x400) >> 3); | |
795 | } | |
796 | ||
7adc14b1 AB |
797 | static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) |
798 | { | |
799 | struct urb *urb; | |
800 | ||
801 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) | |
802 | return 1; | |
803 | ||
804 | urb = qtd->urb; | |
805 | qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); | |
806 | return (qtd->urb != urb); | |
807 | } | |
808 | ||
71a9f9d2 AB |
809 | /* magic numbers that can affect system performance */ |
810 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
811 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
812 | #define EHCI_TUNE_RL_TT 0 | |
813 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
814 | #define EHCI_TUNE_MULT_TT 1 | |
815 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
816 | ||
817 | static void create_ptd_atl(struct isp1760_qh *qh, | |
a041d8e4 | 818 | struct isp1760_qtd *qtd, struct ptd *ptd) |
db11e47d | 819 | { |
db11e47d SS |
820 | u32 maxpacket; |
821 | u32 multi; | |
db11e47d SS |
822 | u32 rl = RL_COUNTER; |
823 | u32 nak = NAK_COUNTER; | |
824 | ||
bedc0c31 AB |
825 | memset(ptd, 0, sizeof(*ptd)); |
826 | ||
db11e47d | 827 | /* according to 3.6.2, max packet len can not be > 0x400 */ |
dcd2e49b | 828 | maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe); |
db11e47d SS |
829 | multi = 1 + ((maxpacket >> 11) & 0x3); |
830 | maxpacket &= 0x7ff; | |
831 | ||
832 | /* DW0 */ | |
71a9f9d2 AB |
833 | ptd->dw0 = DW0_VALID_BIT; |
834 | ptd->dw0 |= TO_DW0_LENGTH(qtd->length); | |
835 | ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); | |
836 | ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); | |
db11e47d SS |
837 | |
838 | /* DW1 */ | |
abfabc8a | 839 | ptd->dw1 = TO_DW((usb_pipeendpoint(qtd->urb->pipe) >> 1)); |
71a9f9d2 AB |
840 | ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); |
841 | ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); | |
db11e47d | 842 | |
a041d8e4 | 843 | if (usb_pipebulk(qtd->urb->pipe)) |
71a9f9d2 | 844 | ptd->dw1 |= DW1_TRANS_BULK; |
a041d8e4 | 845 | else if (usb_pipeint(qtd->urb->pipe)) |
71a9f9d2 | 846 | ptd->dw1 |= DW1_TRANS_INT; |
db11e47d | 847 | |
a041d8e4 | 848 | if (qtd->urb->dev->speed != USB_SPEED_HIGH) { |
db11e47d SS |
849 | /* split transaction */ |
850 | ||
71a9f9d2 | 851 | ptd->dw1 |= DW1_TRANS_SPLIT; |
a041d8e4 | 852 | if (qtd->urb->dev->speed == USB_SPEED_LOW) |
71a9f9d2 | 853 | ptd->dw1 |= DW1_SE_USB_LOSPEED; |
db11e47d | 854 | |
71a9f9d2 AB |
855 | ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport); |
856 | ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum); | |
db11e47d SS |
857 | |
858 | /* SE bit for Split INT transfers */ | |
a041d8e4 AB |
859 | if (usb_pipeint(qtd->urb->pipe) && |
860 | (qtd->urb->dev->speed == USB_SPEED_LOW)) | |
abfabc8a | 861 | ptd->dw1 |= DW1_SE_USB_LOSPEED; |
db11e47d | 862 | |
db11e47d SS |
863 | rl = 0; |
864 | nak = 0; | |
865 | } else { | |
71a9f9d2 | 866 | ptd->dw0 |= TO_DW0_MULTI(multi); |
a041d8e4 AB |
867 | if (usb_pipecontrol(qtd->urb->pipe) || |
868 | usb_pipebulk(qtd->urb->pipe)) | |
71a9f9d2 | 869 | ptd->dw3 |= TO_DW3_PING(qh->ping); |
db11e47d SS |
870 | } |
871 | /* DW2 */ | |
bedc0c31 | 872 | ptd->dw2 = 0; |
71a9f9d2 AB |
873 | ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); |
874 | ptd->dw2 |= TO_DW2_RL(rl); | |
db11e47d SS |
875 | |
876 | /* DW3 */ | |
71a9f9d2 AB |
877 | ptd->dw3 |= TO_DW3_NAKCOUNT(nak); |
878 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); | |
7adc14b1 AB |
879 | if (usb_pipecontrol(qtd->urb->pipe)) { |
880 | if (qtd->data_buffer == qtd->urb->setup_packet) | |
71a9f9d2 | 881 | ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); |
7adc14b1 | 882 | else if (last_qtd_of_urb(qtd, qh)) |
71a9f9d2 | 883 | ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); |
7adc14b1 | 884 | } |
db11e47d | 885 | |
71a9f9d2 | 886 | ptd->dw3 |= DW3_ACTIVE_BIT; |
db11e47d | 887 | /* Cerr */ |
71a9f9d2 | 888 | ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); |
db11e47d SS |
889 | } |
890 | ||
6bda21bc | 891 | static void transform_add_int(struct isp1760_qh *qh, |
a041d8e4 | 892 | struct isp1760_qtd *qtd, struct ptd *ptd) |
db11e47d | 893 | { |
65f1b525 | 894 | u32 usof; |
db11e47d SS |
895 | u32 period; |
896 | ||
65f1b525 AB |
897 | /* |
898 | * Most of this is guessing. ISP1761 datasheet is quite unclear, and | |
899 | * the algorithm from the original Philips driver code, which was | |
900 | * pretty much used in this driver before as well, is quite horrendous | |
901 | * and, i believe, incorrect. The code below follows the datasheet and | |
902 | * USB2.0 spec as far as I can tell, and plug/unplug seems to be much | |
903 | * more reliable this way (fingers crossed...). | |
904 | */ | |
db11e47d | 905 | |
65f1b525 AB |
906 | if (qtd->urb->dev->speed == USB_SPEED_HIGH) { |
907 | /* urb->interval is in units of microframes (1/8 ms) */ | |
908 | period = qtd->urb->interval >> 3; | |
909 | ||
910 | if (qtd->urb->interval > 4) | |
911 | usof = 0x01; /* One bit set => | |
912 | interval 1 ms * uFrame-match */ | |
913 | else if (qtd->urb->interval > 2) | |
914 | usof = 0x22; /* Two bits set => interval 1/2 ms */ | |
915 | else if (qtd->urb->interval > 1) | |
916 | usof = 0x55; /* Four bits set => interval 1/4 ms */ | |
db11e47d | 917 | else |
65f1b525 | 918 | usof = 0xff; /* All bits set => interval 1/8 ms */ |
db11e47d | 919 | } else { |
65f1b525 AB |
920 | /* urb->interval is in units of frames (1 ms) */ |
921 | period = qtd->urb->interval; | |
922 | usof = 0x0f; /* Execute Start Split on any of the | |
923 | four first uFrames */ | |
924 | ||
925 | /* | |
926 | * First 8 bits in dw5 is uSCS and "specifies which uSOF the | |
927 | * complete split needs to be sent. Valid only for IN." Also, | |
928 | * "All bits can be set to one for every transfer." (p 82, | |
929 | * ISP1761 data sheet.) 0x1c is from Philips driver. Where did | |
930 | * that number come from? 0xff seems to work fine... | |
931 | */ | |
932 | /* ptd->dw5 = 0x1c; */ | |
abfabc8a | 933 | ptd->dw5 = TO_DW(0xff); /* Execute Complete Split on any uFrame */ |
db11e47d SS |
934 | } |
935 | ||
65f1b525 AB |
936 | period = period >> 1;/* Ensure equal or shorter period than requested */ |
937 | period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ | |
938 | ||
abfabc8a RMS |
939 | ptd->dw2 |= TO_DW(period); |
940 | ptd->dw4 = TO_DW(usof); | |
db11e47d SS |
941 | } |
942 | ||
71a9f9d2 | 943 | static void create_ptd_int(struct isp1760_qh *qh, |
a041d8e4 | 944 | struct isp1760_qtd *qtd, struct ptd *ptd) |
db11e47d | 945 | { |
71a9f9d2 | 946 | create_ptd_atl(qh, qtd, ptd); |
6bda21bc | 947 | transform_add_int(qh, qtd, ptd); |
db11e47d SS |
948 | } |
949 | ||
6bda21bc | 950 | static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) |
db11e47d SS |
951 | __releases(priv->lock) |
952 | __acquires(priv->lock) | |
953 | { | |
6bda21bc AB |
954 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
955 | ||
db11e47d | 956 | if (!urb->unlinked) { |
6bda21bc AB |
957 | if (urb->status == -EINPROGRESS) |
958 | urb->status = 0; | |
db11e47d SS |
959 | } |
960 | ||
db8516f6 CM |
961 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { |
962 | void *ptr; | |
963 | for (ptr = urb->transfer_buffer; | |
964 | ptr < urb->transfer_buffer + urb->transfer_buffer_length; | |
965 | ptr += PAGE_SIZE) | |
966 | flush_dcache_page(virt_to_page(ptr)); | |
967 | } | |
968 | ||
db11e47d | 969 | /* complete() can reenter this HCD */ |
6bda21bc | 970 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
db11e47d | 971 | spin_unlock(&priv->lock); |
6bda21bc | 972 | usb_hcd_giveback_urb(hcd, urb, urb->status); |
db11e47d SS |
973 | spin_lock(&priv->lock); |
974 | } | |
975 | ||
34537731 AB |
976 | static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, |
977 | u8 packet_type) | |
db11e47d | 978 | { |
34537731 AB |
979 | struct isp1760_qtd *qtd; |
980 | ||
981 | qtd = kmem_cache_zalloc(qtd_cachep, flags); | |
982 | if (!qtd) | |
983 | return NULL; | |
984 | ||
985 | INIT_LIST_HEAD(&qtd->qtd_list); | |
986 | qtd->urb = urb; | |
987 | qtd->packet_type = packet_type; | |
71a9f9d2 AB |
988 | qtd->status = QTD_ENQUEUED; |
989 | qtd->actual_length = 0; | |
34537731 AB |
990 | |
991 | return qtd; | |
992 | } | |
993 | ||
994 | static void qtd_free(struct isp1760_qtd *qtd) | |
995 | { | |
996 | WARN_ON(qtd->payload_addr); | |
db11e47d SS |
997 | kmem_cache_free(qtd_cachep, qtd); |
998 | } | |
999 | ||
71a9f9d2 | 1000 | static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, |
ea0b1fab LP |
1001 | struct isp1760_slotinfo *slots, |
1002 | struct isp1760_qtd *qtd, struct isp1760_qh *qh, | |
1003 | struct ptd *ptd) | |
db11e47d | 1004 | { |
71a9f9d2 | 1005 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
60d789f3 | 1006 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
d05b6ec0 AB |
1007 | int skip_map; |
1008 | ||
60d789f3 | 1009 | WARN_ON((slot < 0) || (slot > mem->slot_num - 1)); |
71a9f9d2 AB |
1010 | WARN_ON(qtd->length && !qtd->payload_addr); |
1011 | WARN_ON(slots[slot].qtd); | |
1012 | WARN_ON(slots[slot].qh); | |
1013 | WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); | |
1014 | ||
60d789f3 RMS |
1015 | if (priv->is_isp1763) |
1016 | ndelay(100); | |
1017 | ||
d05b6ec0 AB |
1018 | /* Make sure done map has not triggered from some unlinked transfer */ |
1019 | if (ptd_offset == ATL_PTD_OFFSET) { | |
60d789f3 RMS |
1020 | skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); |
1021 | isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, | |
1022 | skip_map | (1 << slot)); | |
1023 | priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); | |
6477acc0 AB |
1024 | priv->atl_done_map &= ~(1 << slot); |
1025 | } else { | |
60d789f3 RMS |
1026 | skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); |
1027 | isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, | |
1028 | skip_map | (1 << slot)); | |
1029 | priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); | |
6477acc0 AB |
1030 | priv->int_done_map &= ~(1 << slot); |
1031 | } | |
d05b6ec0 | 1032 | |
60d789f3 | 1033 | skip_map &= ~(1 << slot); |
6477acc0 AB |
1034 | qh->slot = slot; |
1035 | qtd->status = QTD_XFER_STARTED; | |
1036 | slots[slot].timestamp = jiffies; | |
1037 | slots[slot].qtd = qtd; | |
1038 | slots[slot].qh = qh; | |
60d789f3 | 1039 | ptd_write(hcd, ptd_offset, slot, ptd); |
6477acc0 | 1040 | |
60d789f3 RMS |
1041 | if (ptd_offset == ATL_PTD_OFFSET) |
1042 | isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); | |
1043 | else | |
1044 | isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); | |
db11e47d SS |
1045 | } |
1046 | ||
71a9f9d2 | 1047 | static int is_short_bulk(struct isp1760_qtd *qtd) |
db11e47d | 1048 | { |
71a9f9d2 AB |
1049 | return (usb_pipebulk(qtd->urb->pipe) && |
1050 | (qtd->actual_length < qtd->length)); | |
db11e47d SS |
1051 | } |
1052 | ||
71a9f9d2 AB |
1053 | static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, |
1054 | struct list_head *urb_list) | |
db11e47d | 1055 | { |
71a9f9d2 AB |
1056 | struct isp1760_qtd *qtd, *qtd_next; |
1057 | struct urb_listitem *urb_listitem; | |
1da9e1c0 | 1058 | int last_qtd; |
db11e47d | 1059 | |
71a9f9d2 AB |
1060 | list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { |
1061 | if (qtd->status < QTD_XFER_COMPLETE) | |
1062 | break; | |
db11e47d | 1063 | |
38679b72 | 1064 | last_qtd = last_qtd_of_urb(qtd, qh); |
71a9f9d2 AB |
1065 | |
1066 | if ((!last_qtd) && (qtd->status == QTD_RETIRE)) | |
1067 | qtd_next->status = QTD_RETIRE; | |
1068 | ||
1069 | if (qtd->status == QTD_XFER_COMPLETE) { | |
1070 | if (qtd->actual_length) { | |
1071 | switch (qtd->packet_type) { | |
1072 | case IN_PID: | |
60d789f3 RMS |
1073 | mem_read(hcd, qtd->payload_addr, |
1074 | qtd->data_buffer, | |
1075 | qtd->actual_length); | |
0d9b6d49 | 1076 | fallthrough; |
71a9f9d2 AB |
1077 | case OUT_PID: |
1078 | qtd->urb->actual_length += | |
1079 | qtd->actual_length; | |
0d9b6d49 | 1080 | fallthrough; |
71a9f9d2 AB |
1081 | case SETUP_PID: |
1082 | break; | |
1083 | } | |
1084 | } | |
db11e47d | 1085 | |
71a9f9d2 AB |
1086 | if (is_short_bulk(qtd)) { |
1087 | if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1088 | qtd->urb->status = -EREMOTEIO; | |
1089 | if (!last_qtd) | |
1090 | qtd_next->status = QTD_RETIRE; | |
1091 | } | |
1092 | } | |
db11e47d | 1093 | |
71a9f9d2 AB |
1094 | if (qtd->payload_addr) |
1095 | free_mem(hcd, qtd); | |
db11e47d | 1096 | |
71a9f9d2 AB |
1097 | if (last_qtd) { |
1098 | if ((qtd->status == QTD_RETIRE) && | |
1099 | (qtd->urb->status == -EINPROGRESS)) | |
1100 | qtd->urb->status = -EPIPE; | |
1101 | /* Defer calling of urb_done() since it releases lock */ | |
1102 | urb_listitem = kmem_cache_zalloc(urb_listitem_cachep, | |
1103 | GFP_ATOMIC); | |
1104 | if (unlikely(!urb_listitem)) | |
38679b72 | 1105 | break; /* Try again on next call */ |
71a9f9d2 AB |
1106 | urb_listitem->urb = qtd->urb; |
1107 | list_add_tail(&urb_listitem->urb_list, urb_list); | |
1108 | } | |
847ed3e8 | 1109 | |
71a9f9d2 AB |
1110 | list_del(&qtd->qtd_list); |
1111 | qtd_free(qtd); | |
1112 | } | |
1113 | } | |
3f02a957 | 1114 | |
71a9f9d2 AB |
1115 | #define ENQUEUE_DEPTH 2 |
1116 | static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) | |
1117 | { | |
1118 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
60d789f3 RMS |
1119 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
1120 | int slot_num = mem->slot_num; | |
71a9f9d2 | 1121 | int ptd_offset; |
ea0b1fab | 1122 | struct isp1760_slotinfo *slots; |
71a9f9d2 AB |
1123 | int curr_slot, free_slot; |
1124 | int n; | |
1125 | struct ptd ptd; | |
1126 | struct isp1760_qtd *qtd; | |
db11e47d | 1127 | |
71a9f9d2 AB |
1128 | if (unlikely(list_empty(&qh->qtd_list))) { |
1129 | WARN_ON(1); | |
1130 | return; | |
1131 | } | |
db11e47d | 1132 | |
74ad6029 AB |
1133 | /* Make sure this endpoint's TT buffer is clean before queueing ptds */ |
1134 | if (qh->tt_buffer_dirty) | |
1135 | return; | |
1136 | ||
71a9f9d2 AB |
1137 | if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, |
1138 | qtd_list)->urb->pipe)) { | |
1139 | ptd_offset = INT_PTD_OFFSET; | |
1140 | slots = priv->int_slots; | |
1141 | } else { | |
1142 | ptd_offset = ATL_PTD_OFFSET; | |
1143 | slots = priv->atl_slots; | |
1144 | } | |
db11e47d | 1145 | |
71a9f9d2 | 1146 | free_slot = -1; |
60d789f3 | 1147 | for (curr_slot = 0; curr_slot < slot_num; curr_slot++) { |
71a9f9d2 AB |
1148 | if ((free_slot == -1) && (slots[curr_slot].qtd == NULL)) |
1149 | free_slot = curr_slot; | |
1150 | if (slots[curr_slot].qh == qh) | |
1151 | break; | |
1152 | } | |
db11e47d | 1153 | |
71a9f9d2 AB |
1154 | n = 0; |
1155 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { | |
1156 | if (qtd->status == QTD_ENQUEUED) { | |
1157 | WARN_ON(qtd->payload_addr); | |
1158 | alloc_mem(hcd, qtd); | |
1159 | if ((qtd->length) && (!qtd->payload_addr)) | |
1160 | break; | |
db11e47d | 1161 | |
60d789f3 RMS |
1162 | if (qtd->length && (qtd->packet_type == SETUP_PID || |
1163 | qtd->packet_type == OUT_PID)) { | |
1164 | mem_write(hcd, qtd->payload_addr, | |
1165 | qtd->data_buffer, qtd->length); | |
71a9f9d2 | 1166 | } |
db11e47d | 1167 | |
71a9f9d2 | 1168 | qtd->status = QTD_PAYLOAD_ALLOC; |
db11e47d SS |
1169 | } |
1170 | ||
71a9f9d2 AB |
1171 | if (qtd->status == QTD_PAYLOAD_ALLOC) { |
1172 | /* | |
1173 | if ((curr_slot > 31) && (free_slot == -1)) | |
1174 | dev_dbg(hcd->self.controller, "%s: No slot " | |
1175 | "available for transfer\n", __func__); | |
1176 | */ | |
1177 | /* Start xfer for this endpoint if not already done */ | |
60d789f3 | 1178 | if ((curr_slot > slot_num - 1) && (free_slot > -1)) { |
71a9f9d2 AB |
1179 | if (usb_pipeint(qtd->urb->pipe)) |
1180 | create_ptd_int(qh, qtd, &ptd); | |
1181 | else | |
1182 | create_ptd_atl(qh, qtd, &ptd); | |
1183 | ||
1184 | start_bus_transfer(hcd, ptd_offset, free_slot, | |
1185 | slots, qtd, qh, &ptd); | |
1186 | curr_slot = free_slot; | |
1187 | } | |
db11e47d | 1188 | |
71a9f9d2 AB |
1189 | n++; |
1190 | if (n >= ENQUEUE_DEPTH) | |
1191 | break; | |
1192 | } | |
1193 | } | |
1194 | } | |
db11e47d | 1195 | |
de9c6307 | 1196 | static void schedule_ptds(struct usb_hcd *hcd) |
71a9f9d2 AB |
1197 | { |
1198 | struct isp1760_hcd *priv; | |
1199 | struct isp1760_qh *qh, *qh_next; | |
1200 | struct list_head *ep_queue; | |
71a9f9d2 AB |
1201 | LIST_HEAD(urb_list); |
1202 | struct urb_listitem *urb_listitem, *urb_listitem_next; | |
e08f6a27 | 1203 | int i; |
71a9f9d2 AB |
1204 | |
1205 | if (!hcd) { | |
1206 | WARN_ON(1); | |
1207 | return; | |
1208 | } | |
db11e47d | 1209 | |
71a9f9d2 | 1210 | priv = hcd_to_priv(hcd); |
db11e47d | 1211 | |
71a9f9d2 AB |
1212 | /* |
1213 | * check finished/retired xfers, transfer payloads, call urb_done() | |
1214 | */ | |
e08f6a27 AB |
1215 | for (i = 0; i < QH_END; i++) { |
1216 | ep_queue = &priv->qh_list[i]; | |
71a9f9d2 | 1217 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) { |
71a9f9d2 | 1218 | collect_qtds(hcd, qh, &urb_list); |
c64391f2 | 1219 | if (list_empty(&qh->qtd_list)) |
71a9f9d2 | 1220 | list_del(&qh->qh_list); |
db11e47d | 1221 | } |
71a9f9d2 | 1222 | } |
db11e47d | 1223 | |
71a9f9d2 AB |
1224 | list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, |
1225 | urb_list) { | |
1226 | isp1760_urb_done(hcd, urb_listitem->urb); | |
1227 | kmem_cache_free(urb_listitem_cachep, urb_listitem); | |
1228 | } | |
db11e47d | 1229 | |
71a9f9d2 AB |
1230 | /* |
1231 | * Schedule packets for transfer. | |
1232 | * | |
1233 | * According to USB2.0 specification: | |
1234 | * | |
1235 | * 1st prio: interrupt xfers, up to 80 % of bandwidth | |
1236 | * 2nd prio: control xfers | |
1237 | * 3rd prio: bulk xfers | |
1238 | * | |
1239 | * ... but let's use a simpler scheme here (mostly because ISP1761 doc | |
1240 | * is very unclear on how to prioritize traffic): | |
1241 | * | |
1242 | * 1) Enqueue any queued control transfers, as long as payload chip mem | |
1243 | * and PTD ATL slots are available. | |
1244 | * 2) Enqueue any queued INT transfers, as long as payload chip mem | |
1245 | * and PTD INT slots are available. | |
1246 | * 3) Enqueue any queued bulk transfers, as long as payload chip mem | |
1247 | * and PTD ATL slots are available. | |
1248 | * | |
1249 | * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between | |
1250 | * conservation of chip mem and performance. | |
1251 | * | |
1252 | * I'm sure this scheme could be improved upon! | |
1253 | */ | |
e08f6a27 AB |
1254 | for (i = 0; i < QH_END; i++) { |
1255 | ep_queue = &priv->qh_list[i]; | |
71a9f9d2 AB |
1256 | list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) |
1257 | enqueue_qtds(hcd, qh); | |
71a9f9d2 AB |
1258 | } |
1259 | } | |
db11e47d | 1260 | |
71a9f9d2 AB |
1261 | #define PTD_STATE_QTD_DONE 1 |
1262 | #define PTD_STATE_QTD_RELOAD 2 | |
1263 | #define PTD_STATE_URB_RETIRE 3 | |
db11e47d | 1264 | |
71a9f9d2 AB |
1265 | static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
1266 | struct urb *urb) | |
1267 | { | |
abfabc8a | 1268 | u32 dw4; |
71a9f9d2 | 1269 | int i; |
db11e47d | 1270 | |
abfabc8a | 1271 | dw4 = TO_U32(ptd->dw4); |
71a9f9d2 | 1272 | dw4 >>= 8; |
db11e47d | 1273 | |
71a9f9d2 AB |
1274 | /* FIXME: ISP1761 datasheet does not say what to do with these. Do we |
1275 | need to handle these errors? Is it done in hardware? */ | |
db11e47d | 1276 | |
71a9f9d2 | 1277 | if (ptd->dw3 & DW3_HALT_BIT) { |
db11e47d | 1278 | |
71a9f9d2 | 1279 | urb->status = -EPROTO; /* Default unknown error */ |
db11e47d | 1280 | |
71a9f9d2 AB |
1281 | for (i = 0; i < 8; i++) { |
1282 | switch (dw4 & 0x7) { | |
1283 | case INT_UNDERRUN: | |
1284 | dev_dbg(hcd->self.controller, "%s: underrun " | |
1285 | "during uFrame %d\n", | |
1286 | __func__, i); | |
1287 | urb->status = -ECOMM; /* Could not write data */ | |
1288 | break; | |
1289 | case INT_EXACT: | |
1290 | dev_dbg(hcd->self.controller, "%s: transaction " | |
1291 | "error during uFrame %d\n", | |
1292 | __func__, i); | |
1293 | urb->status = -EPROTO; /* timeout, bad CRC, PID | |
1294 | error etc. */ | |
1295 | break; | |
1296 | case INT_BABBLE: | |
1297 | dev_dbg(hcd->self.controller, "%s: babble " | |
1298 | "error during uFrame %d\n", | |
1299 | __func__, i); | |
1300 | urb->status = -EOVERFLOW; | |
1301 | break; | |
1302 | } | |
1303 | dw4 >>= 3; | |
1304 | } | |
db11e47d | 1305 | |
71a9f9d2 AB |
1306 | return PTD_STATE_URB_RETIRE; |
1307 | } | |
db11e47d | 1308 | |
71a9f9d2 AB |
1309 | return PTD_STATE_QTD_DONE; |
1310 | } | |
db11e47d | 1311 | |
71a9f9d2 AB |
1312 | static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, |
1313 | struct urb *urb) | |
1314 | { | |
1315 | WARN_ON(!ptd); | |
1316 | if (ptd->dw3 & DW3_HALT_BIT) { | |
1317 | if (ptd->dw3 & DW3_BABBLE_BIT) | |
1318 | urb->status = -EOVERFLOW; | |
1319 | else if (FROM_DW3_CERR(ptd->dw3)) | |
1320 | urb->status = -EPIPE; /* Stall */ | |
71a9f9d2 AB |
1321 | else |
1322 | urb->status = -EPROTO; /* Unknown */ | |
1323 | /* | |
1324 | dev_dbg(hcd->self.controller, "%s: ptd error:\n" | |
1325 | " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" | |
1326 | " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", | |
1327 | __func__, | |
1328 | ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, | |
1329 | ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); | |
1330 | */ | |
1331 | return PTD_STATE_URB_RETIRE; | |
1332 | } | |
db11e47d | 1333 | |
71a9f9d2 AB |
1334 | if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) { |
1335 | /* Transfer Error, *but* active and no HALT -> reload */ | |
1336 | dev_dbg(hcd->self.controller, "PID error; reloading ptd\n"); | |
1337 | return PTD_STATE_QTD_RELOAD; | |
1338 | } | |
db11e47d | 1339 | |
71a9f9d2 AB |
1340 | if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) { |
1341 | /* | |
1342 | * NAKs are handled in HW by the chip. Usually if the | |
1343 | * device is not able to send data fast enough. | |
1344 | * This happens mostly on slower hardware. | |
1345 | */ | |
1346 | return PTD_STATE_QTD_RELOAD; | |
db11e47d | 1347 | } |
71a9f9d2 AB |
1348 | |
1349 | return PTD_STATE_QTD_DONE; | |
db11e47d SS |
1350 | } |
1351 | ||
6d50c60e | 1352 | static void handle_done_ptds(struct usb_hcd *hcd) |
db11e47d | 1353 | { |
bedc0c31 | 1354 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d | 1355 | struct ptd ptd; |
db11e47d | 1356 | struct isp1760_qh *qh; |
71a9f9d2 AB |
1357 | int slot; |
1358 | int state; | |
ea0b1fab | 1359 | struct isp1760_slotinfo *slots; |
71a9f9d2 AB |
1360 | u32 ptd_offset; |
1361 | struct isp1760_qtd *qtd; | |
1362 | int modified; | |
6d50c60e | 1363 | int skip_map; |
71a9f9d2 | 1364 | |
60d789f3 | 1365 | skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); |
6d50c60e | 1366 | priv->int_done_map &= ~skip_map; |
60d789f3 | 1367 | skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); |
6d50c60e | 1368 | priv->atl_done_map &= ~skip_map; |
71a9f9d2 | 1369 | |
6d50c60e | 1370 | modified = priv->int_done_map || priv->atl_done_map; |
d05b6ec0 AB |
1371 | |
1372 | while (priv->int_done_map || priv->atl_done_map) { | |
1373 | if (priv->int_done_map) { | |
71a9f9d2 | 1374 | /* INT ptd */ |
d05b6ec0 AB |
1375 | slot = __ffs(priv->int_done_map); |
1376 | priv->int_done_map &= ~(1 << slot); | |
71a9f9d2 | 1377 | slots = priv->int_slots; |
d05b6ec0 AB |
1378 | /* This should not trigger, and could be removed if |
1379 | noone have any problems with it triggering: */ | |
1380 | if (!slots[slot].qh) { | |
1381 | WARN_ON(1); | |
71a9f9d2 | 1382 | continue; |
d05b6ec0 | 1383 | } |
71a9f9d2 | 1384 | ptd_offset = INT_PTD_OFFSET; |
60d789f3 | 1385 | ptd_read(hcd, INT_PTD_OFFSET, slot, &ptd); |
71a9f9d2 AB |
1386 | state = check_int_transfer(hcd, &ptd, |
1387 | slots[slot].qtd->urb); | |
db11e47d | 1388 | } else { |
71a9f9d2 | 1389 | /* ATL ptd */ |
d05b6ec0 AB |
1390 | slot = __ffs(priv->atl_done_map); |
1391 | priv->atl_done_map &= ~(1 << slot); | |
71a9f9d2 | 1392 | slots = priv->atl_slots; |
d05b6ec0 AB |
1393 | /* This should not trigger, and could be removed if |
1394 | noone have any problems with it triggering: */ | |
1395 | if (!slots[slot].qh) { | |
1396 | WARN_ON(1); | |
71a9f9d2 | 1397 | continue; |
d05b6ec0 | 1398 | } |
71a9f9d2 | 1399 | ptd_offset = ATL_PTD_OFFSET; |
60d789f3 | 1400 | ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd); |
71a9f9d2 AB |
1401 | state = check_atl_transfer(hcd, &ptd, |
1402 | slots[slot].qtd->urb); | |
db11e47d SS |
1403 | } |
1404 | ||
71a9f9d2 AB |
1405 | qtd = slots[slot].qtd; |
1406 | slots[slot].qtd = NULL; | |
1407 | qh = slots[slot].qh; | |
1408 | slots[slot].qh = NULL; | |
71a9f9d2 AB |
1409 | qh->slot = -1; |
1410 | ||
1411 | WARN_ON(qtd->status != QTD_XFER_STARTED); | |
1412 | ||
1413 | switch (state) { | |
1414 | case PTD_STATE_QTD_DONE: | |
1415 | if ((usb_pipeint(qtd->urb->pipe)) && | |
1416 | (qtd->urb->dev->speed != USB_SPEED_HIGH)) | |
1417 | qtd->actual_length = | |
1418 | FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); | |
1419 | else | |
1420 | qtd->actual_length = | |
1421 | FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); | |
db11e47d | 1422 | |
71a9f9d2 AB |
1423 | qtd->status = QTD_XFER_COMPLETE; |
1424 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || | |
1da9e1c0 | 1425 | is_short_bulk(qtd)) |
71a9f9d2 AB |
1426 | qtd = NULL; |
1427 | else | |
1428 | qtd = list_entry(qtd->qtd_list.next, | |
1429 | typeof(*qtd), qtd_list); | |
db11e47d | 1430 | |
71a9f9d2 AB |
1431 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); |
1432 | qh->ping = FROM_DW3_PING(ptd.dw3); | |
1433 | break; | |
db11e47d | 1434 | |
71a9f9d2 AB |
1435 | case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ |
1436 | qtd->status = QTD_PAYLOAD_ALLOC; | |
1437 | ptd.dw0 |= DW0_VALID_BIT; | |
1438 | /* RL counter = ERR counter */ | |
1439 | ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); | |
1440 | ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); | |
1441 | ptd.dw3 &= ~TO_DW3_CERR(3); | |
1442 | ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); | |
1443 | qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); | |
1444 | qh->ping = FROM_DW3_PING(ptd.dw3); | |
1445 | break; | |
db11e47d | 1446 | |
71a9f9d2 AB |
1447 | case PTD_STATE_URB_RETIRE: |
1448 | qtd->status = QTD_RETIRE; | |
74ad6029 AB |
1449 | if ((qtd->urb->dev->speed != USB_SPEED_HIGH) && |
1450 | (qtd->urb->status != -EPIPE) && | |
1451 | (qtd->urb->status != -EREMOTEIO)) { | |
1452 | qh->tt_buffer_dirty = 1; | |
1453 | if (usb_hub_clear_tt_buffer(qtd->urb)) | |
1454 | /* Clear failed; let's hope things work | |
1455 | anyway */ | |
1456 | qh->tt_buffer_dirty = 0; | |
1457 | } | |
71a9f9d2 AB |
1458 | qtd = NULL; |
1459 | qh->toggle = 0; | |
1460 | qh->ping = 0; | |
1461 | break; | |
db11e47d | 1462 | |
71a9f9d2 AB |
1463 | default: |
1464 | WARN_ON(1); | |
1465 | continue; | |
1466 | } | |
db11e47d | 1467 | |
71a9f9d2 AB |
1468 | if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) { |
1469 | if (slots == priv->int_slots) { | |
1470 | if (state == PTD_STATE_QTD_RELOAD) | |
1471 | dev_err(hcd->self.controller, | |
1472 | "%s: PTD_STATE_QTD_RELOAD on " | |
1473 | "interrupt packet\n", __func__); | |
1474 | if (state != PTD_STATE_QTD_RELOAD) | |
1475 | create_ptd_int(qh, qtd, &ptd); | |
1476 | } else { | |
1477 | if (state != PTD_STATE_QTD_RELOAD) | |
1478 | create_ptd_atl(qh, qtd, &ptd); | |
1479 | } | |
db11e47d | 1480 | |
71a9f9d2 AB |
1481 | start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, |
1482 | qh, &ptd); | |
1483 | } | |
1484 | } | |
db11e47d | 1485 | |
71a9f9d2 AB |
1486 | if (modified) |
1487 | schedule_ptds(hcd); | |
6d50c60e | 1488 | } |
db11e47d | 1489 | |
6d50c60e AB |
1490 | static irqreturn_t isp1760_irq(struct usb_hcd *hcd) |
1491 | { | |
1492 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
6d50c60e | 1493 | irqreturn_t irqret = IRQ_NONE; |
60d789f3 RMS |
1494 | u32 int_reg; |
1495 | u32 imask; | |
db11e47d | 1496 | |
6d50c60e AB |
1497 | spin_lock(&priv->lock); |
1498 | ||
1499 | if (!(hcd->state & HC_STATE_RUNNING)) | |
1500 | goto leave; | |
1501 | ||
60d789f3 | 1502 | imask = isp1760_hcd_read(hcd, HC_INTERRUPT); |
6d50c60e AB |
1503 | if (unlikely(!imask)) |
1504 | goto leave; | |
6d50c60e | 1505 | |
60d789f3 RMS |
1506 | int_reg = priv->is_isp1763 ? ISP1763_HC_INTERRUPT : |
1507 | ISP176x_HC_INTERRUPT; | |
1508 | isp1760_reg_write(priv->regs, int_reg, imask); | |
1509 | ||
1510 | priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); | |
1511 | priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); | |
6d50c60e AB |
1512 | |
1513 | handle_done_ptds(hcd); | |
db11e47d | 1514 | |
71a9f9d2 | 1515 | irqret = IRQ_HANDLED; |
60d789f3 | 1516 | |
71a9f9d2 AB |
1517 | leave: |
1518 | spin_unlock(&priv->lock); | |
db11e47d | 1519 | |
71a9f9d2 | 1520 | return irqret; |
db11e47d SS |
1521 | } |
1522 | ||
6d50c60e AB |
1523 | /* |
1524 | * Workaround for problem described in chip errata 2: | |
1525 | * | |
1526 | * Sometimes interrupts are not generated when ATL (not INT?) completion occurs. | |
1527 | * One solution suggested in the errata is to use SOF interrupts _instead_of_ | |
1528 | * ATL done interrupts (the "instead of" might be important since it seems | |
1529 | * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget" | |
1530 | * to set the PTD's done bit in addition to not generating an interrupt!). | |
1531 | * | |
1532 | * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their | |
1533 | * done bit is not being set. This is bad - it blocks the endpoint until reboot. | |
1534 | * | |
1535 | * If we use SOF interrupts only, we get latency between ptd completion and the | |
1536 | * actual handling. This is very noticeable in testusb runs which takes several | |
1537 | * minutes longer without ATL interrupts. | |
1538 | * | |
1539 | * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it | |
1540 | * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the | |
1541 | * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered | |
1542 | * completed and its done map bit is set. | |
1543 | * | |
1544 | * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen | |
1545 | * not to cause too much lag when this HW bug occurs, while still hopefully | |
1546 | * ensuring that the check does not falsely trigger. | |
1547 | */ | |
6477acc0 | 1548 | #define SLOT_TIMEOUT 300 |
6d50c60e AB |
1549 | #define SLOT_CHECK_PERIOD 200 |
1550 | static struct timer_list errata2_timer; | |
7e33da59 | 1551 | static struct usb_hcd *errata2_timer_hcd; |
6d50c60e | 1552 | |
7e33da59 | 1553 | static void errata2_function(struct timer_list *unused) |
6d50c60e | 1554 | { |
7e33da59 | 1555 | struct usb_hcd *hcd = errata2_timer_hcd; |
6d50c60e | 1556 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
60d789f3 | 1557 | const struct isp1760_memory_layout *mem = priv->memory_layout; |
6d50c60e AB |
1558 | int slot; |
1559 | struct ptd ptd; | |
1560 | unsigned long spinflags; | |
1561 | ||
1562 | spin_lock_irqsave(&priv->lock, spinflags); | |
1563 | ||
60d789f3 | 1564 | for (slot = 0; slot < mem->slot_num; slot++) |
6477acc0 AB |
1565 | if (priv->atl_slots[slot].qh && time_after(jiffies, |
1566 | priv->atl_slots[slot].timestamp + | |
4d3db7d7 | 1567 | msecs_to_jiffies(SLOT_TIMEOUT))) { |
60d789f3 | 1568 | ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd); |
6d50c60e AB |
1569 | if (!FROM_DW0_VALID(ptd.dw0) && |
1570 | !FROM_DW3_ACTIVE(ptd.dw3)) | |
1571 | priv->atl_done_map |= 1 << slot; | |
1572 | } | |
1573 | ||
6477acc0 AB |
1574 | if (priv->atl_done_map) |
1575 | handle_done_ptds(hcd); | |
6d50c60e AB |
1576 | |
1577 | spin_unlock_irqrestore(&priv->lock, spinflags); | |
1578 | ||
4d3db7d7 | 1579 | errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD); |
6d50c60e AB |
1580 | add_timer(&errata2_timer); |
1581 | } | |
1582 | ||
60d789f3 RMS |
1583 | static int isp1763_run(struct usb_hcd *hcd) |
1584 | { | |
1585 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1586 | int retval; | |
1587 | u32 chipid_h; | |
1588 | u32 chipid_l; | |
1589 | u32 chip_rev; | |
1590 | u32 ptd_atl_int; | |
1591 | u32 ptd_iso; | |
1592 | ||
1593 | hcd->uses_new_polling = 1; | |
1594 | hcd->state = HC_STATE_RUNNING; | |
1595 | ||
1596 | chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); | |
1597 | chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); | |
1598 | chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); | |
1599 | dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n", | |
1600 | chipid_h, chipid_l, chip_rev); | |
1601 | ||
1602 | isp1760_hcd_clear(hcd, ISO_BUF_FILL); | |
1603 | isp1760_hcd_clear(hcd, INT_BUF_FILL); | |
1604 | isp1760_hcd_clear(hcd, ATL_BUF_FILL); | |
1605 | ||
1606 | isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); | |
1607 | isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); | |
1608 | isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); | |
1609 | ndelay(100); | |
1610 | isp1760_hcd_clear(hcd, HC_ATL_PTD_DONEMAP); | |
1611 | isp1760_hcd_clear(hcd, HC_INT_PTD_DONEMAP); | |
1612 | isp1760_hcd_clear(hcd, HC_ISO_PTD_DONEMAP); | |
1613 | ||
1614 | isp1760_hcd_set(hcd, HW_OTG_DISABLE); | |
1615 | isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(7)); | |
1616 | isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(15)); | |
1617 | mdelay(10); | |
1618 | ||
1619 | isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); | |
1620 | isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); | |
1621 | ||
1622 | isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); | |
1623 | ||
1624 | isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); | |
1625 | isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); | |
1626 | isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); | |
1627 | ||
1628 | isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); | |
1629 | isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); | |
1630 | isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); | |
1631 | ||
1632 | ptd_atl_int = 0x8000; | |
1633 | ptd_iso = 0x0001; | |
1634 | ||
1635 | isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); | |
1636 | isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); | |
1637 | isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); | |
1638 | ||
1639 | isp1760_hcd_set(hcd, ATL_BUF_FILL); | |
1640 | isp1760_hcd_set(hcd, INT_BUF_FILL); | |
1641 | ||
1642 | isp1760_hcd_clear(hcd, CMD_LRESET); | |
1643 | isp1760_hcd_clear(hcd, CMD_RESET); | |
1644 | ||
1645 | retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); | |
1646 | if (retval) | |
1647 | return retval; | |
1648 | ||
1649 | down_write(&ehci_cf_port_reset_rwsem); | |
1650 | retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); | |
1651 | up_write(&ehci_cf_port_reset_rwsem); | |
60d789f3 RMS |
1652 | if (retval) |
1653 | return retval; | |
1654 | ||
1655 | return 0; | |
1656 | } | |
1657 | ||
0ba7905e AB |
1658 | static int isp1760_run(struct usb_hcd *hcd) |
1659 | { | |
1da9e1c0 | 1660 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
0ba7905e | 1661 | int retval; |
60d789f3 RMS |
1662 | u32 chipid_h; |
1663 | u32 chipid_l; | |
1664 | u32 chip_rev; | |
1665 | u32 ptd_atl_int; | |
1666 | u32 ptd_iso; | |
1667 | ||
1668 | /* | |
1669 | * ISP1763 have some differences in the setup and order to enable | |
1670 | * the ports, disable otg, setup buffers, and ATL, INT, ISO status. | |
1671 | * So, just handle it a separate sequence. | |
1672 | */ | |
1673 | if (priv->is_isp1763) | |
1674 | return isp1763_run(hcd); | |
0ba7905e AB |
1675 | |
1676 | hcd->uses_new_polling = 1; | |
1677 | ||
1678 | hcd->state = HC_STATE_RUNNING; | |
1679 | ||
1680 | /* Set PTD interrupt AND & OR maps */ | |
60d789f3 RMS |
1681 | isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); |
1682 | isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); | |
1683 | isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); | |
1684 | ||
1685 | isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); | |
1686 | isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); | |
1687 | isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); | |
1688 | ||
0ba7905e AB |
1689 | /* step 23 passed */ |
1690 | ||
1da9e1c0 | 1691 | isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); |
0ba7905e | 1692 | |
1da9e1c0 RMS |
1693 | isp1760_hcd_clear(hcd, CMD_LRESET); |
1694 | isp1760_hcd_clear(hcd, CMD_RESET); | |
0ba7905e | 1695 | |
60d789f3 | 1696 | retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); |
0ba7905e AB |
1697 | if (retval) |
1698 | return retval; | |
1699 | ||
1700 | /* | |
1701 | * XXX | |
1702 | * Spec says to write FLAG_CF as last config action, priv code grabs | |
1703 | * the semaphore while doing so. | |
1704 | */ | |
1705 | down_write(&ehci_cf_port_reset_rwsem); | |
0ba7905e | 1706 | |
60d789f3 | 1707 | retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); |
0ba7905e AB |
1708 | up_write(&ehci_cf_port_reset_rwsem); |
1709 | if (retval) | |
1710 | return retval; | |
1711 | ||
7e33da59 KC |
1712 | errata2_timer_hcd = hcd; |
1713 | timer_setup(&errata2_timer, errata2_function, 0); | |
4d3db7d7 | 1714 | errata2_timer.expires = jiffies + msecs_to_jiffies(SLOT_CHECK_PERIOD); |
6d50c60e AB |
1715 | add_timer(&errata2_timer); |
1716 | ||
60d789f3 RMS |
1717 | chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); |
1718 | chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); | |
1719 | chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); | |
1720 | dev_info(hcd->self.controller, "USB ISP %02x%02x HW rev. %d started\n", | |
1721 | chipid_h, chipid_l, chip_rev); | |
0ba7905e AB |
1722 | |
1723 | /* PTD Register Init Part 2, Step 28 */ | |
1724 | ||
1725 | /* Setup registers controlling PTD checking */ | |
60d789f3 RMS |
1726 | ptd_atl_int = 0x80000000; |
1727 | ptd_iso = 0x00000001; | |
1728 | ||
1729 | isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); | |
1730 | isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); | |
1731 | isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); | |
1732 | ||
1733 | isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); | |
1734 | isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); | |
1735 | isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); | |
1da9e1c0 RMS |
1736 | |
1737 | isp1760_hcd_set(hcd, ATL_BUF_FILL); | |
1738 | isp1760_hcd_set(hcd, INT_BUF_FILL); | |
0ba7905e AB |
1739 | |
1740 | /* GRR this is run-once init(), being done every time the HC starts. | |
1741 | * So long as they're part of class devices, we can't do it init() | |
1742 | * since the class device isn't created that early. | |
1743 | */ | |
1744 | return 0; | |
1745 | } | |
1746 | ||
34537731 | 1747 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) |
db11e47d | 1748 | { |
34537731 | 1749 | qtd->data_buffer = databuffer; |
db11e47d | 1750 | |
34537731 | 1751 | qtd->length = len; |
db11e47d | 1752 | |
34537731 | 1753 | return qtd->length; |
db11e47d SS |
1754 | } |
1755 | ||
34537731 | 1756 | static void qtd_list_free(struct list_head *qtd_list) |
db11e47d | 1757 | { |
34537731 | 1758 | struct isp1760_qtd *qtd, *qtd_next; |
db11e47d | 1759 | |
34537731 | 1760 | list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { |
db11e47d | 1761 | list_del(&qtd->qtd_list); |
34537731 | 1762 | qtd_free(qtd); |
db11e47d SS |
1763 | } |
1764 | } | |
1765 | ||
db11e47d | 1766 | /* |
34537731 AB |
1767 | * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. |
1768 | * Also calculate the PID type (SETUP/IN/OUT) for each packet. | |
db11e47d | 1769 | */ |
34537731 | 1770 | static void packetize_urb(struct usb_hcd *hcd, |
db11e47d SS |
1771 | struct urb *urb, struct list_head *head, gfp_t flags) |
1772 | { | |
a74f639c RMS |
1773 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1774 | const struct isp1760_memory_layout *mem = priv->memory_layout; | |
fd436aee | 1775 | struct isp1760_qtd *qtd; |
db11e47d | 1776 | void *buf; |
34537731 AB |
1777 | int len, maxpacketsize; |
1778 | u8 packet_type; | |
db11e47d SS |
1779 | |
1780 | /* | |
1781 | * URBs map to sequences of QTDs: one logical transaction | |
1782 | */ | |
db11e47d | 1783 | |
34537731 AB |
1784 | if (!urb->transfer_buffer && urb->transfer_buffer_length) { |
1785 | /* XXX This looks like usb storage / SCSI bug */ | |
1786 | dev_err(hcd->self.controller, | |
1787 | "buf is null, dma is %08lx len is %d\n", | |
1788 | (long unsigned)urb->transfer_dma, | |
1789 | urb->transfer_buffer_length); | |
1790 | WARN_ON(1); | |
1791 | } | |
db11e47d | 1792 | |
34537731 AB |
1793 | if (usb_pipein(urb->pipe)) |
1794 | packet_type = IN_PID; | |
1795 | else | |
1796 | packet_type = OUT_PID; | |
db11e47d | 1797 | |
db11e47d | 1798 | if (usb_pipecontrol(urb->pipe)) { |
34537731 | 1799 | qtd = qtd_alloc(flags, urb, SETUP_PID); |
db11e47d SS |
1800 | if (!qtd) |
1801 | goto cleanup; | |
34537731 | 1802 | qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); |
db11e47d SS |
1803 | list_add_tail(&qtd->qtd_list, head); |
1804 | ||
1805 | /* for zero length DATA stages, STATUS is always IN */ | |
34537731 AB |
1806 | if (urb->transfer_buffer_length == 0) |
1807 | packet_type = IN_PID; | |
db11e47d SS |
1808 | } |
1809 | ||
dcd2e49b | 1810 | maxpacketsize = usb_maxpacket(urb->dev, urb->pipe); |
db11e47d SS |
1811 | |
1812 | /* | |
1813 | * buffer gets wrapped in one or more qtds; | |
1814 | * last one may be "short" (including zero len) | |
1815 | * and may serve as a control status ack | |
1816 | */ | |
34537731 AB |
1817 | buf = urb->transfer_buffer; |
1818 | len = urb->transfer_buffer_length; | |
1819 | ||
db11e47d SS |
1820 | for (;;) { |
1821 | int this_qtd_len; | |
1822 | ||
34537731 AB |
1823 | qtd = qtd_alloc(flags, urb, packet_type); |
1824 | if (!qtd) | |
1825 | goto cleanup; | |
a74f639c RMS |
1826 | |
1827 | if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1]) | |
cbfa3eff RMS |
1828 | this_qtd_len = mem->blocks_size[ISP176x_BLOCK_NUM - 1]; |
1829 | else | |
1830 | this_qtd_len = len; | |
a74f639c | 1831 | |
cbfa3eff | 1832 | this_qtd_len = qtd_fill(qtd, buf, this_qtd_len); |
34537731 | 1833 | list_add_tail(&qtd->qtd_list, head); |
db11e47d | 1834 | |
db11e47d SS |
1835 | len -= this_qtd_len; |
1836 | buf += this_qtd_len; | |
1837 | ||
db11e47d SS |
1838 | if (len <= 0) |
1839 | break; | |
db11e47d SS |
1840 | } |
1841 | ||
1842 | /* | |
1843 | * control requests may need a terminating data "status" ack; | |
1844 | * bulk ones may need a terminating short packet (zero length). | |
1845 | */ | |
1846 | if (urb->transfer_buffer_length != 0) { | |
1847 | int one_more = 0; | |
1848 | ||
1849 | if (usb_pipecontrol(urb->pipe)) { | |
1850 | one_more = 1; | |
34537731 AB |
1851 | if (packet_type == IN_PID) |
1852 | packet_type = OUT_PID; | |
1853 | else | |
1854 | packet_type = IN_PID; | |
8e58b771 | 1855 | } else if (usb_pipebulk(urb->pipe) && maxpacketsize |
db11e47d | 1856 | && (urb->transfer_flags & URB_ZERO_PACKET) |
34537731 AB |
1857 | && !(urb->transfer_buffer_length % |
1858 | maxpacketsize)) { | |
db11e47d SS |
1859 | one_more = 1; |
1860 | } | |
1861 | if (one_more) { | |
34537731 | 1862 | qtd = qtd_alloc(flags, urb, packet_type); |
db11e47d SS |
1863 | if (!qtd) |
1864 | goto cleanup; | |
db11e47d SS |
1865 | |
1866 | /* never any data in such packets */ | |
34537731 AB |
1867 | qtd_fill(qtd, NULL, 0); |
1868 | list_add_tail(&qtd->qtd_list, head); | |
db11e47d SS |
1869 | } |
1870 | } | |
1871 | ||
34537731 | 1872 | return; |
db11e47d SS |
1873 | |
1874 | cleanup: | |
34537731 AB |
1875 | qtd_list_free(head); |
1876 | } | |
1877 | ||
db11e47d SS |
1878 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, |
1879 | gfp_t mem_flags) | |
1880 | { | |
71a9f9d2 AB |
1881 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
1882 | struct list_head *ep_queue; | |
1883 | struct isp1760_qh *qh, *qhit; | |
1884 | unsigned long spinflags; | |
1885 | LIST_HEAD(new_qtds); | |
1886 | int retval; | |
1887 | int qh_in_queue; | |
db11e47d SS |
1888 | |
1889 | switch (usb_pipetype(urb->pipe)) { | |
1890 | case PIPE_CONTROL: | |
e08f6a27 | 1891 | ep_queue = &priv->qh_list[QH_CONTROL]; |
71a9f9d2 | 1892 | break; |
db11e47d | 1893 | case PIPE_BULK: |
e08f6a27 | 1894 | ep_queue = &priv->qh_list[QH_BULK]; |
db11e47d | 1895 | break; |
db11e47d | 1896 | case PIPE_INTERRUPT: |
71a9f9d2 AB |
1897 | if (urb->interval < 0) |
1898 | return -EINVAL; | |
1899 | /* FIXME: Check bandwidth */ | |
e08f6a27 | 1900 | ep_queue = &priv->qh_list[QH_INTERRUPT]; |
db11e47d | 1901 | break; |
db11e47d | 1902 | case PIPE_ISOCHRONOUS: |
71a9f9d2 AB |
1903 | dev_err(hcd->self.controller, "%s: isochronous USB packets " |
1904 | "not yet supported\n", | |
1905 | __func__); | |
1906 | return -EPIPE; | |
db11e47d | 1907 | default: |
71a9f9d2 AB |
1908 | dev_err(hcd->self.controller, "%s: unknown pipe type\n", |
1909 | __func__); | |
db11e47d SS |
1910 | return -EPIPE; |
1911 | } | |
1912 | ||
71a9f9d2 AB |
1913 | if (usb_pipein(urb->pipe)) |
1914 | urb->actual_length = 0; | |
db11e47d | 1915 | |
71a9f9d2 AB |
1916 | packetize_urb(hcd, urb, &new_qtds, mem_flags); |
1917 | if (list_empty(&new_qtds)) | |
1918 | return -ENOMEM; | |
db11e47d | 1919 | |
71a9f9d2 | 1920 | spin_lock_irqsave(&priv->lock, spinflags); |
db11e47d | 1921 | |
71a9f9d2 AB |
1922 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { |
1923 | retval = -ESHUTDOWN; | |
8788fa03 | 1924 | qtd_list_free(&new_qtds); |
71a9f9d2 | 1925 | goto out; |
db11e47d | 1926 | } |
71a9f9d2 | 1927 | retval = usb_hcd_link_urb_to_ep(hcd, urb); |
8788fa03 MG |
1928 | if (retval) { |
1929 | qtd_list_free(&new_qtds); | |
71a9f9d2 | 1930 | goto out; |
8788fa03 | 1931 | } |
db11e47d | 1932 | |
71a9f9d2 AB |
1933 | qh = urb->ep->hcpriv; |
1934 | if (qh) { | |
1935 | qh_in_queue = 0; | |
1936 | list_for_each_entry(qhit, ep_queue, qh_list) { | |
1937 | if (qhit == qh) { | |
1938 | qh_in_queue = 1; | |
0afb20e0 | 1939 | break; |
71a9f9d2 AB |
1940 | } |
1941 | } | |
1942 | if (!qh_in_queue) | |
1943 | list_add_tail(&qh->qh_list, ep_queue); | |
1944 | } else { | |
1945 | qh = qh_alloc(GFP_ATOMIC); | |
1946 | if (!qh) { | |
1947 | retval = -ENOMEM; | |
38679b72 | 1948 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
8788fa03 | 1949 | qtd_list_free(&new_qtds); |
71a9f9d2 | 1950 | goto out; |
db11e47d | 1951 | } |
71a9f9d2 AB |
1952 | list_add_tail(&qh->qh_list, ep_queue); |
1953 | urb->ep->hcpriv = qh; | |
db11e47d SS |
1954 | } |
1955 | ||
71a9f9d2 AB |
1956 | list_splice_tail(&new_qtds, &qh->qtd_list); |
1957 | schedule_ptds(hcd); | |
1958 | ||
1959 | out: | |
1960 | spin_unlock_irqrestore(&priv->lock, spinflags); | |
1961 | return retval; | |
db11e47d SS |
1962 | } |
1963 | ||
d05b6ec0 AB |
1964 | static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, |
1965 | struct isp1760_qh *qh) | |
1966 | { | |
1967 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1968 | int skip_map; | |
1969 | ||
1970 | WARN_ON(qh->slot == -1); | |
1971 | ||
1972 | /* We need to forcefully reclaim the slot since some transfers never | |
1973 | return, e.g. interrupt transfers and NAKed bulk transfers. */ | |
8b1ab60c | 1974 | if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { |
7d1d3882 RMS |
1975 | if (qh->slot != -1) { |
1976 | skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); | |
1977 | skip_map |= (1 << qh->slot); | |
1978 | isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); | |
1979 | ndelay(100); | |
1980 | } | |
d05b6ec0 AB |
1981 | priv->atl_slots[qh->slot].qh = NULL; |
1982 | priv->atl_slots[qh->slot].qtd = NULL; | |
1983 | } else { | |
7d1d3882 RMS |
1984 | if (qh->slot != -1) { |
1985 | skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); | |
1986 | skip_map |= (1 << qh->slot); | |
1987 | isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); | |
1988 | } | |
d05b6ec0 AB |
1989 | priv->int_slots[qh->slot].qh = NULL; |
1990 | priv->int_slots[qh->slot].qtd = NULL; | |
1991 | } | |
1992 | ||
1993 | qh->slot = -1; | |
d05b6ec0 AB |
1994 | } |
1995 | ||
74ad6029 AB |
1996 | /* |
1997 | * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing | |
1998 | * any active transfer belonging to the urb in the process. | |
1999 | */ | |
2000 | static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, | |
2001 | struct isp1760_qtd *qtd) | |
2002 | { | |
2003 | struct urb *urb; | |
2004 | int urb_was_running; | |
2005 | ||
2006 | urb = qtd->urb; | |
2007 | urb_was_running = 0; | |
2008 | list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { | |
2009 | if (qtd->urb != urb) | |
2010 | break; | |
2011 | ||
2012 | if (qtd->status >= QTD_XFER_STARTED) | |
2013 | urb_was_running = 1; | |
2014 | if (last_qtd_of_urb(qtd, qh) && | |
2015 | (qtd->status >= QTD_XFER_COMPLETE)) | |
2016 | urb_was_running = 0; | |
2017 | ||
2018 | if (qtd->status == QTD_XFER_STARTED) | |
2019 | kill_transfer(hcd, urb, qh); | |
2020 | qtd->status = QTD_RETIRE; | |
2021 | } | |
2022 | ||
2023 | if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) { | |
2024 | qh->tt_buffer_dirty = 1; | |
2025 | if (usb_hub_clear_tt_buffer(urb)) | |
2026 | /* Clear failed; let's hope things work anyway */ | |
2027 | qh->tt_buffer_dirty = 0; | |
2028 | } | |
2029 | } | |
2030 | ||
71a9f9d2 AB |
2031 | static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, |
2032 | int status) | |
db11e47d | 2033 | { |
6bda21bc | 2034 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
d05b6ec0 | 2035 | unsigned long spinflags; |
71a9f9d2 AB |
2036 | struct isp1760_qh *qh; |
2037 | struct isp1760_qtd *qtd; | |
71a9f9d2 | 2038 | int retval = 0; |
db11e47d | 2039 | |
71a9f9d2 | 2040 | spin_lock_irqsave(&priv->lock, spinflags); |
17d3e145 AB |
2041 | retval = usb_hcd_check_unlink_urb(hcd, urb, status); |
2042 | if (retval) | |
2043 | goto out; | |
db11e47d | 2044 | |
71a9f9d2 AB |
2045 | qh = urb->ep->hcpriv; |
2046 | if (!qh) { | |
2047 | retval = -EINVAL; | |
2048 | goto out; | |
2049 | } | |
db11e47d | 2050 | |
d05b6ec0 AB |
2051 | list_for_each_entry(qtd, &qh->qtd_list, qtd_list) |
2052 | if (qtd->urb == urb) { | |
74ad6029 | 2053 | dequeue_urb_from_qtd(hcd, qh, qtd); |
8cb22680 | 2054 | list_move(&qtd->qtd_list, &qh->qtd_list); |
74ad6029 | 2055 | break; |
d05b6ec0 | 2056 | } |
db11e47d | 2057 | |
71a9f9d2 AB |
2058 | urb->status = status; |
2059 | schedule_ptds(hcd); | |
db11e47d | 2060 | |
71a9f9d2 AB |
2061 | out: |
2062 | spin_unlock_irqrestore(&priv->lock, spinflags); | |
71a9f9d2 | 2063 | return retval; |
db11e47d SS |
2064 | } |
2065 | ||
079cdb09 AB |
2066 | static void isp1760_endpoint_disable(struct usb_hcd *hcd, |
2067 | struct usb_host_endpoint *ep) | |
2068 | { | |
2069 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
d05b6ec0 | 2070 | unsigned long spinflags; |
c64391f2 AB |
2071 | struct isp1760_qh *qh, *qh_iter; |
2072 | int i; | |
079cdb09 AB |
2073 | |
2074 | spin_lock_irqsave(&priv->lock, spinflags); | |
d05b6ec0 | 2075 | |
079cdb09 AB |
2076 | qh = ep->hcpriv; |
2077 | if (!qh) | |
2078 | goto out; | |
2079 | ||
c64391f2 | 2080 | WARN_ON(!list_empty(&qh->qtd_list)); |
d05b6ec0 | 2081 | |
c64391f2 AB |
2082 | for (i = 0; i < QH_END; i++) |
2083 | list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list) | |
2084 | if (qh_iter == qh) { | |
2085 | list_del(&qh_iter->qh_list); | |
2086 | i = QH_END; | |
2087 | break; | |
2088 | } | |
2089 | qh_free(qh); | |
079cdb09 | 2090 | ep->hcpriv = NULL; |
079cdb09 | 2091 | |
d05b6ec0 AB |
2092 | schedule_ptds(hcd); |
2093 | ||
079cdb09 AB |
2094 | out: |
2095 | spin_unlock_irqrestore(&priv->lock, spinflags); | |
2096 | } | |
2097 | ||
db11e47d SS |
2098 | static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) |
2099 | { | |
2100 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1da9e1c0 | 2101 | u32 status = 0; |
db11e47d SS |
2102 | int retval = 1; |
2103 | unsigned long flags; | |
2104 | ||
464ed18e | 2105 | /* if !PM, root hub timers won't get shut down ... */ |
db11e47d SS |
2106 | if (!HC_IS_RUNNING(hcd->state)) |
2107 | return 0; | |
2108 | ||
2109 | /* init status to no-changes */ | |
2110 | buf[0] = 0; | |
db11e47d SS |
2111 | |
2112 | spin_lock_irqsave(&priv->lock, flags); | |
db11e47d | 2113 | |
1da9e1c0 RMS |
2114 | if (isp1760_hcd_is_set(hcd, PORT_OWNER) && |
2115 | isp1760_hcd_is_set(hcd, PORT_CSC)) { | |
2116 | isp1760_hcd_clear(hcd, PORT_CSC); | |
2117 | goto done; | |
db11e47d SS |
2118 | } |
2119 | ||
2120 | /* | |
2121 | * Return status information even for ports with OWNER set. | |
37ebb549 | 2122 | * Otherwise hub_wq wouldn't see the disconnect event when a |
db11e47d SS |
2123 | * high-speed device is switched over to the companion |
2124 | * controller by the user. | |
2125 | */ | |
1da9e1c0 RMS |
2126 | if (isp1760_hcd_is_set(hcd, PORT_CSC) || |
2127 | (isp1760_hcd_is_set(hcd, PORT_RESUME) && | |
2128 | time_after_eq(jiffies, priv->reset_done))) { | |
db11e47d SS |
2129 | buf [0] |= 1 << (0 + 1); |
2130 | status = STS_PCD; | |
2131 | } | |
2132 | /* FIXME autosuspend idle root hubs */ | |
2133 | done: | |
2134 | spin_unlock_irqrestore(&priv->lock, flags); | |
2135 | return status ? retval : 0; | |
2136 | } | |
2137 | ||
2138 | static void isp1760_hub_descriptor(struct isp1760_hcd *priv, | |
2139 | struct usb_hub_descriptor *desc) | |
2140 | { | |
1da9e1c0 | 2141 | int ports; |
db11e47d SS |
2142 | u16 temp; |
2143 | ||
60d789f3 | 2144 | ports = isp1760_hcd_n_ports(priv->hcd); |
1da9e1c0 | 2145 | |
1cf6563b | 2146 | desc->bDescriptorType = USB_DT_HUB; |
db11e47d SS |
2147 | /* priv 1.0, 2.3.9 says 20ms max */ |
2148 | desc->bPwrOn2PwrGood = 10; | |
2149 | desc->bHubContrCurrent = 0; | |
2150 | ||
2151 | desc->bNbrPorts = ports; | |
2152 | temp = 1 + (ports / 8); | |
2153 | desc->bDescLength = 7 + 2 * temp; | |
2154 | ||
da13051c | 2155 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
dbe79bbe JY |
2156 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
2157 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); | |
db11e47d SS |
2158 | |
2159 | /* per-port overcurrent reporting */ | |
cc581c12 | 2160 | temp = HUB_CHAR_INDV_PORT_OCPM; |
60d789f3 | 2161 | if (isp1760_hcd_ppc_is_set(priv->hcd)) |
db11e47d | 2162 | /* per-port power control */ |
cc581c12 | 2163 | temp |= HUB_CHAR_INDV_PORT_LPSM; |
db11e47d SS |
2164 | else |
2165 | /* no power switching */ | |
cc581c12 | 2166 | temp |= HUB_CHAR_NO_LPSM; |
db11e47d SS |
2167 | desc->wHubCharacteristics = cpu_to_le16(temp); |
2168 | } | |
2169 | ||
2170 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) | |
2171 | ||
1da9e1c0 | 2172 | static void check_reset_complete(struct usb_hcd *hcd, int index) |
db11e47d | 2173 | { |
1da9e1c0 RMS |
2174 | if (!(isp1760_hcd_is_set(hcd, PORT_CONNECT))) |
2175 | return; | |
db11e47d SS |
2176 | |
2177 | /* if reset finished and it's still not enabled -- handoff */ | |
1da9e1c0 | 2178 | if (!isp1760_hcd_is_set(hcd, PORT_PE)) { |
71a9f9d2 | 2179 | dev_info(hcd->self.controller, |
1da9e1c0 | 2180 | "port %d full speed --> companion\n", index + 1); |
db11e47d | 2181 | |
1da9e1c0 | 2182 | isp1760_hcd_set(hcd, PORT_OWNER); |
db11e47d | 2183 | |
1da9e1c0 RMS |
2184 | isp1760_hcd_clear(hcd, PORT_CSC); |
2185 | } else { | |
71a9f9d2 | 2186 | dev_info(hcd->self.controller, "port %d high speed\n", |
1da9e1c0 RMS |
2187 | index + 1); |
2188 | } | |
db11e47d | 2189 | |
1da9e1c0 | 2190 | return; |
db11e47d SS |
2191 | } |
2192 | ||
2193 | static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |
2194 | u16 wValue, u16 wIndex, char *buf, u16 wLength) | |
2195 | { | |
2196 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1da9e1c0 | 2197 | u32 status; |
db11e47d SS |
2198 | unsigned long flags; |
2199 | int retval = 0; | |
1da9e1c0 RMS |
2200 | int ports; |
2201 | ||
60d789f3 | 2202 | ports = isp1760_hcd_n_ports(hcd); |
db11e47d SS |
2203 | |
2204 | /* | |
2205 | * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. | |
2206 | * HCS_INDICATOR may say we can change LEDs to off/amber/green. | |
2207 | * (track current state ourselves) ... blink for diagnostics, | |
2208 | * power, "this is the one", etc. EHCI spec supports this. | |
2209 | */ | |
2210 | ||
2211 | spin_lock_irqsave(&priv->lock, flags); | |
2212 | switch (typeReq) { | |
2213 | case ClearHubFeature: | |
2214 | switch (wValue) { | |
2215 | case C_HUB_LOCAL_POWER: | |
2216 | case C_HUB_OVER_CURRENT: | |
2217 | /* no hub-wide feature/status flags */ | |
2218 | break; | |
2219 | default: | |
2220 | goto error; | |
2221 | } | |
2222 | break; | |
2223 | case ClearPortFeature: | |
2224 | if (!wIndex || wIndex > ports) | |
2225 | goto error; | |
2226 | wIndex--; | |
db11e47d SS |
2227 | |
2228 | /* | |
2229 | * Even if OWNER is set, so the port is owned by the | |
37ebb549 | 2230 | * companion controller, hub_wq needs to be able to clear |
db11e47d | 2231 | * the port-change status bits (especially |
749da5f8 | 2232 | * USB_PORT_STAT_C_CONNECTION). |
db11e47d SS |
2233 | */ |
2234 | ||
2235 | switch (wValue) { | |
2236 | case USB_PORT_FEAT_ENABLE: | |
1da9e1c0 | 2237 | isp1760_hcd_clear(hcd, PORT_PE); |
db11e47d SS |
2238 | break; |
2239 | case USB_PORT_FEAT_C_ENABLE: | |
2240 | /* XXX error? */ | |
2241 | break; | |
2242 | case USB_PORT_FEAT_SUSPEND: | |
1da9e1c0 | 2243 | if (isp1760_hcd_is_set(hcd, PORT_RESET)) |
db11e47d SS |
2244 | goto error; |
2245 | ||
1da9e1c0 RMS |
2246 | if (isp1760_hcd_is_set(hcd, PORT_SUSPEND)) { |
2247 | if (!isp1760_hcd_is_set(hcd, PORT_PE)) | |
db11e47d SS |
2248 | goto error; |
2249 | /* resume signaling for 20 msec */ | |
1da9e1c0 RMS |
2250 | isp1760_hcd_clear(hcd, PORT_CSC); |
2251 | isp1760_hcd_set(hcd, PORT_RESUME); | |
2252 | ||
db11e47d | 2253 | priv->reset_done = jiffies + |
59c9904c | 2254 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
db11e47d SS |
2255 | } |
2256 | break; | |
2257 | case USB_PORT_FEAT_C_SUSPEND: | |
2258 | /* we auto-clear this feature */ | |
2259 | break; | |
2260 | case USB_PORT_FEAT_POWER: | |
60d789f3 | 2261 | if (isp1760_hcd_ppc_is_set(hcd)) |
1da9e1c0 | 2262 | isp1760_hcd_clear(hcd, PORT_POWER); |
db11e47d SS |
2263 | break; |
2264 | case USB_PORT_FEAT_C_CONNECTION: | |
1da9e1c0 | 2265 | isp1760_hcd_set(hcd, PORT_CSC); |
db11e47d SS |
2266 | break; |
2267 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
2268 | /* XXX error ?*/ | |
2269 | break; | |
2270 | case USB_PORT_FEAT_C_RESET: | |
2271 | /* GetPortStatus clears reset */ | |
2272 | break; | |
2273 | default: | |
2274 | goto error; | |
2275 | } | |
60d789f3 | 2276 | isp1760_hcd_read(hcd, CMD_RUN); |
db11e47d SS |
2277 | break; |
2278 | case GetHubDescriptor: | |
2279 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) | |
2280 | buf); | |
2281 | break; | |
2282 | case GetHubStatus: | |
2283 | /* no hub-wide feature/status flags */ | |
2284 | memset(buf, 0, 4); | |
2285 | break; | |
2286 | case GetPortStatus: | |
2287 | if (!wIndex || wIndex > ports) | |
2288 | goto error; | |
2289 | wIndex--; | |
2290 | status = 0; | |
db11e47d SS |
2291 | |
2292 | /* wPortChange bits */ | |
1da9e1c0 | 2293 | if (isp1760_hcd_is_set(hcd, PORT_CSC)) |
749da5f8 | 2294 | status |= USB_PORT_STAT_C_CONNECTION << 16; |
db11e47d | 2295 | |
db11e47d | 2296 | /* whoever resumes must GetPortStatus to complete it!! */ |
1da9e1c0 | 2297 | if (isp1760_hcd_is_set(hcd, PORT_RESUME)) { |
6bda21bc | 2298 | dev_err(hcd->self.controller, "Port resume should be skipped.\n"); |
db11e47d SS |
2299 | |
2300 | /* Remote Wakeup received? */ | |
2301 | if (!priv->reset_done) { | |
2302 | /* resume signaling for 20 msec */ | |
2303 | priv->reset_done = jiffies | |
2304 | + msecs_to_jiffies(20); | |
2305 | /* check the port again */ | |
6bda21bc | 2306 | mod_timer(&hcd->rh_timer, priv->reset_done); |
db11e47d SS |
2307 | } |
2308 | ||
2309 | /* resume completed? */ | |
2310 | else if (time_after_eq(jiffies, | |
2311 | priv->reset_done)) { | |
749da5f8 | 2312 | status |= USB_PORT_STAT_C_SUSPEND << 16; |
db11e47d SS |
2313 | priv->reset_done = 0; |
2314 | ||
2315 | /* stop resume signaling */ | |
1da9e1c0 RMS |
2316 | isp1760_hcd_clear(hcd, PORT_CSC); |
2317 | ||
60d789f3 | 2318 | retval = isp1760_hcd_clear_and_wait(hcd, |
1da9e1c0 | 2319 | PORT_RESUME, 2000); |
db11e47d | 2320 | if (retval != 0) { |
6bda21bc | 2321 | dev_err(hcd->self.controller, |
db11e47d SS |
2322 | "port %d resume error %d\n", |
2323 | wIndex + 1, retval); | |
2324 | goto error; | |
2325 | } | |
db11e47d SS |
2326 | } |
2327 | } | |
2328 | ||
2329 | /* whoever resets must GetPortStatus to complete it!! */ | |
1da9e1c0 RMS |
2330 | if (isp1760_hcd_is_set(hcd, PORT_RESET) && |
2331 | time_after_eq(jiffies, priv->reset_done)) { | |
749da5f8 | 2332 | status |= USB_PORT_STAT_C_RESET << 16; |
db11e47d SS |
2333 | priv->reset_done = 0; |
2334 | ||
2335 | /* force reset to complete */ | |
db11e47d SS |
2336 | /* REVISIT: some hardware needs 550+ usec to clear |
2337 | * this bit; seems too long to spin routinely... | |
2338 | */ | |
60d789f3 RMS |
2339 | retval = isp1760_hcd_clear_and_wait(hcd, PORT_RESET, |
2340 | 750); | |
db11e47d | 2341 | if (retval != 0) { |
6bda21bc | 2342 | dev_err(hcd->self.controller, "port %d reset error %d\n", |
60d789f3 | 2343 | wIndex + 1, retval); |
db11e47d SS |
2344 | goto error; |
2345 | } | |
2346 | ||
2347 | /* see what we found out */ | |
1da9e1c0 | 2348 | check_reset_complete(hcd, wIndex); |
db11e47d SS |
2349 | } |
2350 | /* | |
37ebb549 | 2351 | * Even if OWNER is set, there's no harm letting hub_wq |
db11e47d SS |
2352 | * see the wPortStatus values (they should all be 0 except |
2353 | * for PORT_POWER anyway). | |
2354 | */ | |
2355 | ||
1da9e1c0 | 2356 | if (isp1760_hcd_is_set(hcd, PORT_OWNER)) |
6bda21bc | 2357 | dev_err(hcd->self.controller, "PORT_OWNER is set\n"); |
db11e47d | 2358 | |
1da9e1c0 | 2359 | if (isp1760_hcd_is_set(hcd, PORT_CONNECT)) { |
749da5f8 | 2360 | status |= USB_PORT_STAT_CONNECTION; |
db11e47d | 2361 | /* status may be from integrated TT */ |
6bda21bc | 2362 | status |= USB_PORT_STAT_HIGH_SPEED; |
db11e47d | 2363 | } |
1da9e1c0 | 2364 | if (isp1760_hcd_is_set(hcd, PORT_PE)) |
749da5f8 | 2365 | status |= USB_PORT_STAT_ENABLE; |
1da9e1c0 RMS |
2366 | if (isp1760_hcd_is_set(hcd, PORT_SUSPEND) && |
2367 | isp1760_hcd_is_set(hcd, PORT_RESUME)) | |
749da5f8 | 2368 | status |= USB_PORT_STAT_SUSPEND; |
1da9e1c0 | 2369 | if (isp1760_hcd_is_set(hcd, PORT_RESET)) |
749da5f8 | 2370 | status |= USB_PORT_STAT_RESET; |
1da9e1c0 | 2371 | if (isp1760_hcd_is_set(hcd, PORT_POWER)) |
749da5f8 | 2372 | status |= USB_PORT_STAT_POWER; |
db11e47d SS |
2373 | |
2374 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); | |
2375 | break; | |
2376 | case SetHubFeature: | |
2377 | switch (wValue) { | |
2378 | case C_HUB_LOCAL_POWER: | |
2379 | case C_HUB_OVER_CURRENT: | |
2380 | /* no hub-wide feature/status flags */ | |
2381 | break; | |
2382 | default: | |
2383 | goto error; | |
2384 | } | |
2385 | break; | |
2386 | case SetPortFeature: | |
db11e47d SS |
2387 | wIndex &= 0xff; |
2388 | if (!wIndex || wIndex > ports) | |
2389 | goto error; | |
2390 | wIndex--; | |
60d789f3 | 2391 | |
1da9e1c0 | 2392 | if (isp1760_hcd_is_set(hcd, PORT_OWNER)) |
db11e47d SS |
2393 | break; |
2394 | ||
db11e47d SS |
2395 | switch (wValue) { |
2396 | case USB_PORT_FEAT_ENABLE: | |
1da9e1c0 | 2397 | isp1760_hcd_set(hcd, PORT_PE); |
db11e47d SS |
2398 | break; |
2399 | ||
2400 | case USB_PORT_FEAT_SUSPEND: | |
1da9e1c0 RMS |
2401 | if (!isp1760_hcd_is_set(hcd, PORT_PE) || |
2402 | isp1760_hcd_is_set(hcd, PORT_RESET)) | |
db11e47d SS |
2403 | goto error; |
2404 | ||
1da9e1c0 | 2405 | isp1760_hcd_set(hcd, PORT_SUSPEND); |
db11e47d SS |
2406 | break; |
2407 | case USB_PORT_FEAT_POWER: | |
60d789f3 | 2408 | if (isp1760_hcd_ppc_is_set(hcd)) |
1da9e1c0 | 2409 | isp1760_hcd_set(hcd, PORT_POWER); |
db11e47d SS |
2410 | break; |
2411 | case USB_PORT_FEAT_RESET: | |
1da9e1c0 | 2412 | if (isp1760_hcd_is_set(hcd, PORT_RESUME)) |
db11e47d SS |
2413 | goto error; |
2414 | /* line status bits may report this as low speed, | |
2415 | * which can be fine if this root hub has a | |
2416 | * transaction translator built in. | |
2417 | */ | |
1da9e1c0 RMS |
2418 | if ((isp1760_hcd_is_set(hcd, PORT_CONNECT) && |
2419 | !isp1760_hcd_is_set(hcd, PORT_PE)) && | |
2420 | (isp1760_hcd_read(hcd, PORT_LSTATUS) == 1)) { | |
2421 | isp1760_hcd_set(hcd, PORT_OWNER); | |
db11e47d | 2422 | } else { |
1da9e1c0 RMS |
2423 | isp1760_hcd_set(hcd, PORT_RESET); |
2424 | isp1760_hcd_clear(hcd, PORT_PE); | |
db11e47d SS |
2425 | |
2426 | /* | |
2427 | * caller must wait, then call GetPortStatus | |
2428 | * usb 2.0 spec says 50 ms resets on root | |
2429 | */ | |
2430 | priv->reset_done = jiffies + | |
2431 | msecs_to_jiffies(50); | |
2432 | } | |
db11e47d SS |
2433 | break; |
2434 | default: | |
2435 | goto error; | |
2436 | } | |
db11e47d SS |
2437 | break; |
2438 | ||
2439 | default: | |
2440 | error: | |
2441 | /* "stall" on error */ | |
2442 | retval = -EPIPE; | |
2443 | } | |
2444 | spin_unlock_irqrestore(&priv->lock, flags); | |
2445 | return retval; | |
2446 | } | |
2447 | ||
db11e47d SS |
2448 | static int isp1760_get_frame(struct usb_hcd *hcd) |
2449 | { | |
2450 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
2451 | u32 fr; | |
2452 | ||
1da9e1c0 | 2453 | fr = isp1760_hcd_read(hcd, HC_FRINDEX); |
db11e47d SS |
2454 | return (fr >> 3) % priv->periodic_size; |
2455 | } | |
2456 | ||
2457 | static void isp1760_stop(struct usb_hcd *hcd) | |
2458 | { | |
2459 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
2460 | ||
6d50c60e AB |
2461 | del_timer(&errata2_timer); |
2462 | ||
db11e47d SS |
2463 | isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, |
2464 | NULL, 0); | |
de0611b2 | 2465 | msleep(20); |
db11e47d SS |
2466 | |
2467 | spin_lock_irq(&priv->lock); | |
6bda21bc | 2468 | ehci_reset(hcd); |
db11e47d | 2469 | /* Disable IRQ */ |
1da9e1c0 | 2470 | isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN); |
db11e47d SS |
2471 | spin_unlock_irq(&priv->lock); |
2472 | ||
1da9e1c0 | 2473 | isp1760_hcd_clear(hcd, FLAG_CF); |
db11e47d SS |
2474 | } |
2475 | ||
2476 | static void isp1760_shutdown(struct usb_hcd *hcd) | |
2477 | { | |
db11e47d | 2478 | isp1760_stop(hcd); |
db11e47d | 2479 | |
1da9e1c0 RMS |
2480 | isp1760_hcd_clear(hcd, HW_GLOBAL_INTR_EN); |
2481 | ||
2482 | isp1760_hcd_clear(hcd, CMD_RUN); | |
db11e47d SS |
2483 | } |
2484 | ||
74ad6029 AB |
2485 | static void isp1760_clear_tt_buffer_complete(struct usb_hcd *hcd, |
2486 | struct usb_host_endpoint *ep) | |
2487 | { | |
2488 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
2489 | struct isp1760_qh *qh = ep->hcpriv; | |
2490 | unsigned long spinflags; | |
2491 | ||
2492 | if (!qh) | |
2493 | return; | |
2494 | ||
2495 | spin_lock_irqsave(&priv->lock, spinflags); | |
2496 | qh->tt_buffer_dirty = 0; | |
2497 | schedule_ptds(hcd); | |
2498 | spin_unlock_irqrestore(&priv->lock, spinflags); | |
2499 | } | |
2500 | ||
2501 | ||
db11e47d SS |
2502 | static const struct hc_driver isp1760_hc_driver = { |
2503 | .description = "isp1760-hcd", | |
2504 | .product_desc = "NXP ISP1760 USB Host Controller", | |
cdd36e87 | 2505 | .hcd_priv_size = sizeof(struct isp1760_hcd *), |
db11e47d SS |
2506 | .irq = isp1760_irq, |
2507 | .flags = HCD_MEMORY | HCD_USB2, | |
2508 | .reset = isp1760_hc_setup, | |
2509 | .start = isp1760_run, | |
2510 | .stop = isp1760_stop, | |
2511 | .shutdown = isp1760_shutdown, | |
2512 | .urb_enqueue = isp1760_urb_enqueue, | |
2513 | .urb_dequeue = isp1760_urb_dequeue, | |
2514 | .endpoint_disable = isp1760_endpoint_disable, | |
2515 | .get_frame_number = isp1760_get_frame, | |
2516 | .hub_status_data = isp1760_hub_status_data, | |
2517 | .hub_control = isp1760_hub_control, | |
74ad6029 | 2518 | .clear_tt_buffer_complete = isp1760_clear_tt_buffer_complete, |
db11e47d SS |
2519 | }; |
2520 | ||
5a6356ac | 2521 | int __init isp1760_init_kmem_once(void) |
db11e47d | 2522 | { |
94011ec2 | 2523 | urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem", |
71a9f9d2 AB |
2524 | sizeof(struct urb_listitem), 0, SLAB_TEMPORARY | |
2525 | SLAB_MEM_SPREAD, NULL); | |
2526 | ||
2527 | if (!urb_listitem_cachep) | |
2528 | return -ENOMEM; | |
2529 | ||
db11e47d SS |
2530 | qtd_cachep = kmem_cache_create("isp1760_qtd", |
2531 | sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | | |
2532 | SLAB_MEM_SPREAD, NULL); | |
2533 | ||
2534 | if (!qtd_cachep) | |
cbbdb3fe | 2535 | goto destroy_urb_listitem; |
db11e47d SS |
2536 | |
2537 | qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), | |
2538 | 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); | |
2539 | ||
cbbdb3fe RMS |
2540 | if (!qh_cachep) |
2541 | goto destroy_qtd; | |
db11e47d SS |
2542 | |
2543 | return 0; | |
cbbdb3fe RMS |
2544 | |
2545 | destroy_qtd: | |
2546 | kmem_cache_destroy(qtd_cachep); | |
2547 | ||
2548 | destroy_urb_listitem: | |
2549 | kmem_cache_destroy(urb_listitem_cachep); | |
2550 | ||
2551 | return -ENOMEM; | |
db11e47d SS |
2552 | } |
2553 | ||
5a6356ac | 2554 | void isp1760_deinit_kmem_cache(void) |
db11e47d SS |
2555 | { |
2556 | kmem_cache_destroy(qtd_cachep); | |
2557 | kmem_cache_destroy(qh_cachep); | |
71a9f9d2 | 2558 | kmem_cache_destroy(urb_listitem_cachep); |
db11e47d SS |
2559 | } |
2560 | ||
1da9e1c0 RMS |
2561 | int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, |
2562 | int irq, unsigned long irqflags, | |
5171446a | 2563 | struct device *dev) |
db11e47d | 2564 | { |
a74f639c | 2565 | const struct isp1760_memory_layout *mem_layout = priv->memory_layout; |
db11e47d | 2566 | struct usb_hcd *hcd; |
db11e47d SS |
2567 | int ret; |
2568 | ||
0031a06e | 2569 | hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); |
db11e47d | 2570 | if (!hcd) |
f0bdbb0e | 2571 | return -ENOMEM; |
db11e47d | 2572 | |
cdd36e87 LP |
2573 | *(struct isp1760_hcd **)hcd->hcd_priv = priv; |
2574 | ||
4b1a577d | 2575 | priv->hcd = hcd; |
db11e47d | 2576 | |
60d789f3 | 2577 | priv->atl_slots = kcalloc(mem_layout->slot_num, |
a74f639c RMS |
2578 | sizeof(struct isp1760_slotinfo), GFP_KERNEL); |
2579 | if (!priv->atl_slots) { | |
2580 | ret = -ENOMEM; | |
60d789f3 | 2581 | goto put_hcd; |
a74f639c RMS |
2582 | } |
2583 | ||
60d789f3 | 2584 | priv->int_slots = kcalloc(mem_layout->slot_num, |
a74f639c RMS |
2585 | sizeof(struct isp1760_slotinfo), GFP_KERNEL); |
2586 | if (!priv->int_slots) { | |
2587 | ret = -ENOMEM; | |
2588 | goto free_atl_slots; | |
2589 | } | |
2590 | ||
db11e47d | 2591 | init_memory(priv); |
db11e47d | 2592 | |
db11e47d | 2593 | hcd->irq = irq; |
4942e00e LP |
2594 | hcd->rsrc_start = mem->start; |
2595 | hcd->rsrc_len = resource_size(mem); | |
db11e47d | 2596 | |
074f9dd5 AS |
2597 | /* This driver doesn't support wakeup requests */ |
2598 | hcd->cant_recv_wakeups = 1; | |
2599 | ||
e6942d63 NC |
2600 | ret = usb_add_hcd(hcd, irq, irqflags); |
2601 | if (ret) | |
a74f639c | 2602 | goto free_int_slots; |
e6942d63 | 2603 | |
3c9740a1 | 2604 | device_wakeup_enable(hcd->self.controller); |
e6942d63 | 2605 | |
f0bdbb0e | 2606 | return 0; |
db11e47d | 2607 | |
a74f639c RMS |
2608 | free_int_slots: |
2609 | kfree(priv->int_slots); | |
2610 | free_atl_slots: | |
2611 | kfree(priv->atl_slots); | |
a74f639c | 2612 | put_hcd: |
30573751 | 2613 | usb_put_hcd(hcd); |
30573751 | 2614 | return ret; |
db11e47d | 2615 | } |
db11e47d | 2616 | |
4b1a577d | 2617 | void isp1760_hcd_unregister(struct isp1760_hcd *priv) |
10c73f09 | 2618 | { |
d21daf1e LP |
2619 | if (!priv->hcd) |
2620 | return; | |
db11e47d | 2621 | |
4b1a577d LP |
2622 | usb_remove_hcd(priv->hcd); |
2623 | usb_put_hcd(priv->hcd); | |
a74f639c RMS |
2624 | kfree(priv->atl_slots); |
2625 | kfree(priv->int_slots); | |
db11e47d | 2626 | } |