Commit | Line | Data |
---|---|---|
66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
43b86af8 | 23 | #include <linux/pci.h> |
66d4eadd | 24 | #include <linux/irq.h> |
8df75f42 | 25 | #include <linux/log2.h> |
66d4eadd | 26 | #include <linux/module.h> |
b0567b3f | 27 | #include <linux/moduleparam.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
71c731a2 | 29 | #include <linux/dmi.h> |
008eb957 | 30 | #include <linux/dma-mapping.h> |
66d4eadd SS |
31 | |
32 | #include "xhci.h" | |
84a99f6f | 33 | #include "xhci-trace.h" |
0cbd4b34 | 34 | #include "xhci-mtk.h" |
66d4eadd SS |
35 | |
36 | #define DRIVER_AUTHOR "Sarah Sharp" | |
37 | #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" | |
38 | ||
a1377e53 LB |
39 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
40 | ||
b0567b3f SS |
41 | /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */ |
42 | static int link_quirk; | |
43 | module_param(link_quirk, int, S_IRUGO | S_IWUSR); | |
44 | MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); | |
45 | ||
4e6a1ee7 TI |
46 | static unsigned int quirks; |
47 | module_param(quirks, uint, S_IRUGO); | |
48 | MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default"); | |
49 | ||
66d4eadd SS |
50 | /* TODO: copied from ehci-hcd.c - can this be refactored? */ |
51 | /* | |
2611bd18 | 52 | * xhci_handshake - spin reading hc until handshake completes or fails |
66d4eadd SS |
53 | * @ptr: address of hc register to be read |
54 | * @mask: bits to look at in result of read | |
55 | * @done: value of those bits when handshake succeeds | |
56 | * @usec: timeout in microseconds | |
57 | * | |
58 | * Returns negative errno, or zero on success | |
59 | * | |
60 | * Success happens when the "mask" bits have the specified value (hardware | |
61 | * handshake done). There are two failure modes: "usec" have passed (major | |
62 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
63 | */ | |
dc0b177c | 64 | int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec) |
66d4eadd SS |
65 | { |
66 | u32 result; | |
67 | ||
68 | do { | |
b0ba9720 | 69 | result = readl(ptr); |
66d4eadd SS |
70 | if (result == ~(u32)0) /* card removed */ |
71 | return -ENODEV; | |
72 | result &= mask; | |
73 | if (result == done) | |
74 | return 0; | |
75 | udelay(1); | |
76 | usec--; | |
77 | } while (usec > 0); | |
78 | return -ETIMEDOUT; | |
79 | } | |
80 | ||
81 | /* | |
4f0f0bae | 82 | * Disable interrupts and begin the xHCI halting process. |
66d4eadd | 83 | */ |
4f0f0bae | 84 | void xhci_quiesce(struct xhci_hcd *xhci) |
66d4eadd SS |
85 | { |
86 | u32 halted; | |
87 | u32 cmd; | |
88 | u32 mask; | |
89 | ||
66d4eadd | 90 | mask = ~(XHCI_IRQS); |
b0ba9720 | 91 | halted = readl(&xhci->op_regs->status) & STS_HALT; |
66d4eadd SS |
92 | if (!halted) |
93 | mask &= ~CMD_RUN; | |
94 | ||
b0ba9720 | 95 | cmd = readl(&xhci->op_regs->command); |
66d4eadd | 96 | cmd &= mask; |
204b7793 | 97 | writel(cmd, &xhci->op_regs->command); |
4f0f0bae SS |
98 | } |
99 | ||
100 | /* | |
101 | * Force HC into halt state. | |
102 | * | |
103 | * Disable any IRQs and clear the run/stop bit. | |
104 | * HC will complete any current and actively pipelined transactions, and | |
bdfca502 | 105 | * should halt within 16 ms of the run/stop bit being cleared. |
4f0f0bae | 106 | * Read HC Halted bit in the status register to see when the HC is finished. |
4f0f0bae SS |
107 | */ |
108 | int xhci_halt(struct xhci_hcd *xhci) | |
109 | { | |
c6cc27c7 | 110 | int ret; |
d195fcff | 111 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC"); |
4f0f0bae | 112 | xhci_quiesce(xhci); |
66d4eadd | 113 | |
dc0b177c | 114 | ret = xhci_handshake(&xhci->op_regs->status, |
66d4eadd | 115 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); |
99154fd3 MN |
116 | if (ret) { |
117 | xhci_warn(xhci, "Host halt failed, %d\n", ret); | |
118 | return ret; | |
119 | } | |
120 | xhci->xhc_state |= XHCI_STATE_HALTED; | |
121 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
c6cc27c7 | 122 | return ret; |
66d4eadd SS |
123 | } |
124 | ||
ed07453f SS |
125 | /* |
126 | * Set the run bit and wait for the host to be running. | |
127 | */ | |
8212a49d | 128 | static int xhci_start(struct xhci_hcd *xhci) |
ed07453f SS |
129 | { |
130 | u32 temp; | |
131 | int ret; | |
132 | ||
b0ba9720 | 133 | temp = readl(&xhci->op_regs->command); |
ed07453f | 134 | temp |= (CMD_RUN); |
d195fcff | 135 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", |
ed07453f | 136 | temp); |
204b7793 | 137 | writel(temp, &xhci->op_regs->command); |
ed07453f SS |
138 | |
139 | /* | |
140 | * Wait for the HCHalted Status bit to be 0 to indicate the host is | |
141 | * running. | |
142 | */ | |
dc0b177c | 143 | ret = xhci_handshake(&xhci->op_regs->status, |
ed07453f SS |
144 | STS_HALT, 0, XHCI_MAX_HALT_USEC); |
145 | if (ret == -ETIMEDOUT) | |
146 | xhci_err(xhci, "Host took too long to start, " | |
147 | "waited %u microseconds.\n", | |
148 | XHCI_MAX_HALT_USEC); | |
c6cc27c7 | 149 | if (!ret) |
98d74f9c MN |
150 | /* clear state flags. Including dying, halted or removing */ |
151 | xhci->xhc_state = 0; | |
e5bfeab0 | 152 | |
ed07453f SS |
153 | return ret; |
154 | } | |
155 | ||
66d4eadd | 156 | /* |
ac04e6ff | 157 | * Reset a halted HC. |
66d4eadd SS |
158 | * |
159 | * This resets pipelines, timers, counters, state machines, etc. | |
160 | * Transactions will be terminated immediately, and operational registers | |
161 | * will be set to their defaults. | |
162 | */ | |
163 | int xhci_reset(struct xhci_hcd *xhci) | |
164 | { | |
165 | u32 command; | |
166 | u32 state; | |
f370b996 | 167 | int ret, i; |
66d4eadd | 168 | |
b0ba9720 | 169 | state = readl(&xhci->op_regs->status); |
c11ae038 MN |
170 | |
171 | if (state == ~(u32)0) { | |
172 | xhci_warn(xhci, "Host not accessible, reset failed.\n"); | |
173 | return -ENODEV; | |
174 | } | |
175 | ||
d3512f63 SS |
176 | if ((state & STS_HALT) == 0) { |
177 | xhci_warn(xhci, "Host controller not halted, aborting reset.\n"); | |
178 | return 0; | |
179 | } | |
66d4eadd | 180 | |
d195fcff | 181 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); |
b0ba9720 | 182 | command = readl(&xhci->op_regs->command); |
66d4eadd | 183 | command |= CMD_RESET; |
204b7793 | 184 | writel(command, &xhci->op_regs->command); |
66d4eadd | 185 | |
a5964396 RM |
186 | /* Existing Intel xHCI controllers require a delay of 1 mS, |
187 | * after setting the CMD_RESET bit, and before accessing any | |
188 | * HC registers. This allows the HC to complete the | |
189 | * reset operation and be ready for HC register access. | |
190 | * Without this delay, the subsequent HC register access, | |
191 | * may result in a system hang very rarely. | |
192 | */ | |
193 | if (xhci->quirks & XHCI_INTEL_HOST) | |
194 | udelay(1000); | |
195 | ||
dc0b177c | 196 | ret = xhci_handshake(&xhci->op_regs->command, |
22ceac19 | 197 | CMD_RESET, 0, 10 * 1000 * 1000); |
2d62f3ee SS |
198 | if (ret) |
199 | return ret; | |
200 | ||
d195fcff XR |
201 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
202 | "Wait for controller to be ready for doorbell rings"); | |
2d62f3ee SS |
203 | /* |
204 | * xHCI cannot write to any doorbells or operational registers other | |
205 | * than status until the "Controller Not Ready" flag is cleared. | |
206 | */ | |
dc0b177c | 207 | ret = xhci_handshake(&xhci->op_regs->status, |
22ceac19 | 208 | STS_CNR, 0, 10 * 1000 * 1000); |
f370b996 | 209 | |
98871e94 | 210 | for (i = 0; i < 2; i++) { |
f370b996 AX |
211 | xhci->bus_state[i].port_c_suspend = 0; |
212 | xhci->bus_state[i].suspended_ports = 0; | |
213 | xhci->bus_state[i].resuming_ports = 0; | |
214 | } | |
215 | ||
216 | return ret; | |
66d4eadd SS |
217 | } |
218 | ||
2c93e790 | 219 | #ifdef CONFIG_USB_PCI |
421aa841 | 220 | static int xhci_free_msi(struct xhci_hcd *xhci) |
43b86af8 DN |
221 | { |
222 | int i; | |
43b86af8 | 223 | |
421aa841 SAS |
224 | if (!xhci->msix_entries) |
225 | return -EINVAL; | |
43b86af8 | 226 | |
421aa841 SAS |
227 | for (i = 0; i < xhci->msix_count; i++) |
228 | if (xhci->msix_entries[i].vector) | |
229 | free_irq(xhci->msix_entries[i].vector, | |
230 | xhci_to_hcd(xhci)); | |
231 | return 0; | |
43b86af8 DN |
232 | } |
233 | ||
234 | /* | |
235 | * Set up MSI | |
236 | */ | |
237 | static int xhci_setup_msi(struct xhci_hcd *xhci) | |
66d4eadd SS |
238 | { |
239 | int ret; | |
4c39d4b9 AB |
240 | /* |
241 | * TODO:Check with MSI Soc for sysdev | |
242 | */ | |
43b86af8 DN |
243 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
244 | ||
245 | ret = pci_enable_msi(pdev); | |
246 | if (ret) { | |
d195fcff XR |
247 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
248 | "failed to allocate MSI entry"); | |
43b86af8 DN |
249 | return ret; |
250 | } | |
251 | ||
851ec164 | 252 | ret = request_irq(pdev->irq, xhci_msi_irq, |
43b86af8 DN |
253 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
254 | if (ret) { | |
d195fcff XR |
255 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
256 | "disable MSI interrupt"); | |
43b86af8 DN |
257 | pci_disable_msi(pdev); |
258 | } | |
259 | ||
260 | return ret; | |
261 | } | |
262 | ||
421aa841 SAS |
263 | /* |
264 | * Free IRQs | |
265 | * free all IRQs request | |
266 | */ | |
267 | static void xhci_free_irq(struct xhci_hcd *xhci) | |
268 | { | |
4c39d4b9 | 269 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.sysdev); |
421aa841 SAS |
270 | int ret; |
271 | ||
272 | /* return if using legacy interrupt */ | |
cd70469d | 273 | if (xhci_to_hcd(xhci)->irq > 0) |
421aa841 SAS |
274 | return; |
275 | ||
276 | ret = xhci_free_msi(xhci); | |
277 | if (!ret) | |
278 | return; | |
cd70469d | 279 | if (pdev->irq > 0) |
421aa841 SAS |
280 | free_irq(pdev->irq, xhci_to_hcd(xhci)); |
281 | ||
282 | return; | |
283 | } | |
284 | ||
43b86af8 DN |
285 | /* |
286 | * Set up MSI-X | |
287 | */ | |
288 | static int xhci_setup_msix(struct xhci_hcd *xhci) | |
289 | { | |
290 | int i, ret = 0; | |
0029227f AX |
291 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
292 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 293 | |
43b86af8 DN |
294 | /* |
295 | * calculate number of msi-x vectors supported. | |
296 | * - HCS_MAX_INTRS: the max number of interrupts the host can handle, | |
297 | * with max number of interrupters based on the xhci HCSPARAMS1. | |
298 | * - num_online_cpus: maximum msi-x vectors per CPUs core. | |
299 | * Add additional 1 vector to ensure always available interrupt. | |
300 | */ | |
301 | xhci->msix_count = min(num_online_cpus() + 1, | |
302 | HCS_MAX_INTRS(xhci->hcs_params1)); | |
303 | ||
304 | xhci->msix_entries = | |
305 | kmalloc((sizeof(struct msix_entry))*xhci->msix_count, | |
86871975 | 306 | GFP_KERNEL); |
f4c46f11 | 307 | if (!xhci->msix_entries) |
66d4eadd | 308 | return -ENOMEM; |
43b86af8 DN |
309 | |
310 | for (i = 0; i < xhci->msix_count; i++) { | |
311 | xhci->msix_entries[i].entry = i; | |
312 | xhci->msix_entries[i].vector = 0; | |
313 | } | |
66d4eadd | 314 | |
a62445ae | 315 | ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count); |
66d4eadd | 316 | if (ret) { |
d195fcff XR |
317 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
318 | "Failed to enable MSI-X"); | |
66d4eadd SS |
319 | goto free_entries; |
320 | } | |
321 | ||
43b86af8 DN |
322 | for (i = 0; i < xhci->msix_count; i++) { |
323 | ret = request_irq(xhci->msix_entries[i].vector, | |
851ec164 | 324 | xhci_msi_irq, |
43b86af8 DN |
325 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
326 | if (ret) | |
327 | goto disable_msix; | |
66d4eadd | 328 | } |
43b86af8 | 329 | |
0029227f | 330 | hcd->msix_enabled = 1; |
43b86af8 | 331 | return ret; |
66d4eadd SS |
332 | |
333 | disable_msix: | |
d195fcff | 334 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); |
43b86af8 | 335 | xhci_free_irq(xhci); |
66d4eadd SS |
336 | pci_disable_msix(pdev); |
337 | free_entries: | |
338 | kfree(xhci->msix_entries); | |
339 | xhci->msix_entries = NULL; | |
340 | return ret; | |
341 | } | |
342 | ||
66d4eadd SS |
343 | /* Free any IRQs and disable MSI-X */ |
344 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |
345 | { | |
0029227f AX |
346 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
347 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 348 | |
9005355a JP |
349 | if (xhci->quirks & XHCI_PLAT) |
350 | return; | |
351 | ||
43b86af8 DN |
352 | xhci_free_irq(xhci); |
353 | ||
354 | if (xhci->msix_entries) { | |
355 | pci_disable_msix(pdev); | |
356 | kfree(xhci->msix_entries); | |
357 | xhci->msix_entries = NULL; | |
358 | } else { | |
359 | pci_disable_msi(pdev); | |
360 | } | |
361 | ||
0029227f | 362 | hcd->msix_enabled = 0; |
43b86af8 | 363 | return; |
66d4eadd | 364 | } |
66d4eadd | 365 | |
d5c82feb | 366 | static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 SAS |
367 | { |
368 | int i; | |
369 | ||
370 | if (xhci->msix_entries) { | |
371 | for (i = 0; i < xhci->msix_count; i++) | |
372 | synchronize_irq(xhci->msix_entries[i].vector); | |
373 | } | |
374 | } | |
375 | ||
376 | static int xhci_try_enable_msi(struct usb_hcd *hcd) | |
377 | { | |
378 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
52fb6125 | 379 | struct pci_dev *pdev; |
421aa841 SAS |
380 | int ret; |
381 | ||
52fb6125 SS |
382 | /* The xhci platform device has set up IRQs through usb_add_hcd. */ |
383 | if (xhci->quirks & XHCI_PLAT) | |
384 | return 0; | |
385 | ||
386 | pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
421aa841 SAS |
387 | /* |
388 | * Some Fresco Logic host controllers advertise MSI, but fail to | |
389 | * generate interrupts. Don't even try to enable MSI. | |
390 | */ | |
391 | if (xhci->quirks & XHCI_BROKEN_MSI) | |
00eed9c8 | 392 | goto legacy_irq; |
421aa841 SAS |
393 | |
394 | /* unregister the legacy interrupt */ | |
395 | if (hcd->irq) | |
396 | free_irq(hcd->irq, hcd); | |
cd70469d | 397 | hcd->irq = 0; |
421aa841 SAS |
398 | |
399 | ret = xhci_setup_msix(xhci); | |
400 | if (ret) | |
401 | /* fall back to msi*/ | |
402 | ret = xhci_setup_msi(xhci); | |
403 | ||
404 | if (!ret) | |
cd70469d | 405 | /* hcd->irq is 0, we have MSI */ |
421aa841 SAS |
406 | return 0; |
407 | ||
68d07f64 SS |
408 | if (!pdev->irq) { |
409 | xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); | |
410 | return -EINVAL; | |
411 | } | |
412 | ||
00eed9c8 | 413 | legacy_irq: |
79699437 AH |
414 | if (!strlen(hcd->irq_descr)) |
415 | snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", | |
416 | hcd->driver->description, hcd->self.busnum); | |
417 | ||
421aa841 SAS |
418 | /* fall back to legacy interrupt*/ |
419 | ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, | |
420 | hcd->irq_descr, hcd); | |
421 | if (ret) { | |
422 | xhci_err(xhci, "request interrupt %d failed\n", | |
423 | pdev->irq); | |
424 | return ret; | |
425 | } | |
426 | hcd->irq = pdev->irq; | |
427 | return 0; | |
428 | } | |
429 | ||
430 | #else | |
431 | ||
01bb59eb | 432 | static inline int xhci_try_enable_msi(struct usb_hcd *hcd) |
421aa841 SAS |
433 | { |
434 | return 0; | |
435 | } | |
436 | ||
01bb59eb | 437 | static inline void xhci_cleanup_msix(struct xhci_hcd *xhci) |
421aa841 SAS |
438 | { |
439 | } | |
440 | ||
01bb59eb | 441 | static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 SAS |
442 | { |
443 | } | |
444 | ||
445 | #endif | |
446 | ||
71c731a2 AC |
447 | static void compliance_mode_recovery(unsigned long arg) |
448 | { | |
449 | struct xhci_hcd *xhci; | |
450 | struct usb_hcd *hcd; | |
451 | u32 temp; | |
452 | int i; | |
453 | ||
454 | xhci = (struct xhci_hcd *)arg; | |
455 | ||
456 | for (i = 0; i < xhci->num_usb3_ports; i++) { | |
b0ba9720 | 457 | temp = readl(xhci->usb3_ports[i]); |
71c731a2 AC |
458 | if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) { |
459 | /* | |
460 | * Compliance Mode Detected. Letting USB Core | |
461 | * handle the Warm Reset | |
462 | */ | |
4bdfe4c3 XR |
463 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
464 | "Compliance mode detected->port %d", | |
71c731a2 | 465 | i + 1); |
4bdfe4c3 XR |
466 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
467 | "Attempting compliance mode recovery"); | |
71c731a2 AC |
468 | hcd = xhci->shared_hcd; |
469 | ||
470 | if (hcd->state == HC_STATE_SUSPENDED) | |
471 | usb_hcd_resume_root_hub(hcd); | |
472 | ||
473 | usb_hcd_poll_rh_status(hcd); | |
474 | } | |
475 | } | |
476 | ||
477 | if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1)) | |
478 | mod_timer(&xhci->comp_mode_recovery_timer, | |
479 | jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS)); | |
480 | } | |
481 | ||
482 | /* | |
483 | * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver | |
484 | * that causes ports behind that hardware to enter compliance mode sometimes. | |
485 | * The quirk creates a timer that polls every 2 seconds the link state of | |
486 | * each host controller's port and recovers it by issuing a Warm reset | |
487 | * if Compliance mode is detected, otherwise the port will become "dead" (no | |
488 | * device connections or disconnections will be detected anymore). Becasue no | |
489 | * status event is generated when entering compliance mode (per xhci spec), | |
490 | * this quirk is needed on systems that have the failing hardware installed. | |
491 | */ | |
492 | static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci) | |
493 | { | |
494 | xhci->port_status_u0 = 0; | |
fc8abe02 JL |
495 | setup_timer(&xhci->comp_mode_recovery_timer, |
496 | compliance_mode_recovery, (unsigned long)xhci); | |
71c731a2 AC |
497 | xhci->comp_mode_recovery_timer.expires = jiffies + |
498 | msecs_to_jiffies(COMP_MODE_RCVRY_MSECS); | |
499 | ||
71c731a2 | 500 | add_timer(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
501 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
502 | "Compliance mode recovery timer initialized"); | |
71c731a2 AC |
503 | } |
504 | ||
505 | /* | |
506 | * This function identifies the systems that have installed the SN65LVPE502CP | |
507 | * USB3.0 re-driver and that need the Compliance Mode Quirk. | |
508 | * Systems: | |
509 | * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820 | |
510 | */ | |
e1cd9727 | 511 | static bool xhci_compliance_mode_recovery_timer_quirk_check(void) |
71c731a2 AC |
512 | { |
513 | const char *dmi_product_name, *dmi_sys_vendor; | |
514 | ||
515 | dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); | |
516 | dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR); | |
457a73d3 VG |
517 | if (!dmi_product_name || !dmi_sys_vendor) |
518 | return false; | |
71c731a2 AC |
519 | |
520 | if (!(strstr(dmi_sys_vendor, "Hewlett-Packard"))) | |
521 | return false; | |
522 | ||
523 | if (strstr(dmi_product_name, "Z420") || | |
524 | strstr(dmi_product_name, "Z620") || | |
47080974 | 525 | strstr(dmi_product_name, "Z820") || |
b0e4e606 | 526 | strstr(dmi_product_name, "Z1 Workstation")) |
71c731a2 AC |
527 | return true; |
528 | ||
529 | return false; | |
530 | } | |
531 | ||
532 | static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci) | |
533 | { | |
534 | return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1)); | |
535 | } | |
536 | ||
537 | ||
66d4eadd SS |
538 | /* |
539 | * Initialize memory for HCD and xHC (one-time init). | |
540 | * | |
541 | * Program the PAGESIZE register, initialize the device context array, create | |
542 | * device contexts (?), set up a command ring segment (or two?), create event | |
543 | * ring (one for now). | |
544 | */ | |
545 | int xhci_init(struct usb_hcd *hcd) | |
546 | { | |
547 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
548 | int retval = 0; | |
549 | ||
d195fcff | 550 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init"); |
66d4eadd | 551 | spin_lock_init(&xhci->lock); |
d7826599 | 552 | if (xhci->hci_version == 0x95 && link_quirk) { |
4bdfe4c3 XR |
553 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
554 | "QUIRK: Not clearing Link TRB chain bits."); | |
b0567b3f SS |
555 | xhci->quirks |= XHCI_LINK_TRB_QUIRK; |
556 | } else { | |
d195fcff XR |
557 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
558 | "xHCI doesn't need link TRB QUIRK"); | |
b0567b3f | 559 | } |
66d4eadd | 560 | retval = xhci_mem_init(xhci, GFP_KERNEL); |
d195fcff | 561 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init"); |
66d4eadd | 562 | |
71c731a2 | 563 | /* Initializing Compliance Mode Recovery Data If Needed */ |
c3897aa5 | 564 | if (xhci_compliance_mode_recovery_timer_quirk_check()) { |
71c731a2 AC |
565 | xhci->quirks |= XHCI_COMP_MODE_QUIRK; |
566 | compliance_mode_recovery_timer_init(xhci); | |
567 | } | |
568 | ||
66d4eadd SS |
569 | return retval; |
570 | } | |
571 | ||
7f84eef0 SS |
572 | /*-------------------------------------------------------------------------*/ |
573 | ||
7f84eef0 | 574 | |
f6ff0ac8 SS |
575 | static int xhci_run_finished(struct xhci_hcd *xhci) |
576 | { | |
577 | if (xhci_start(xhci)) { | |
578 | xhci_halt(xhci); | |
579 | return -ENODEV; | |
580 | } | |
581 | xhci->shared_hcd->state = HC_STATE_RUNNING; | |
c181bc5b | 582 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; |
f6ff0ac8 SS |
583 | |
584 | if (xhci->quirks & XHCI_NEC_HOST) | |
585 | xhci_ring_cmd_db(xhci); | |
586 | ||
d195fcff XR |
587 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
588 | "Finished xhci_run for USB3 roothub"); | |
f6ff0ac8 SS |
589 | return 0; |
590 | } | |
591 | ||
66d4eadd SS |
592 | /* |
593 | * Start the HC after it was halted. | |
594 | * | |
595 | * This function is called by the USB core when the HC driver is added. | |
596 | * Its opposite is xhci_stop(). | |
597 | * | |
598 | * xhci_init() must be called once before this function can be called. | |
599 | * Reset the HC, enable device slot contexts, program DCBAAP, and | |
600 | * set command ring pointer and event ring pointer. | |
601 | * | |
602 | * Setup MSI-X vectors and enable interrupts. | |
603 | */ | |
604 | int xhci_run(struct usb_hcd *hcd) | |
605 | { | |
606 | u32 temp; | |
8e595a5d | 607 | u64 temp_64; |
3fd1ec58 | 608 | int ret; |
66d4eadd | 609 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
66d4eadd | 610 | |
f6ff0ac8 SS |
611 | /* Start the xHCI host controller running only after the USB 2.0 roothub |
612 | * is setup. | |
613 | */ | |
66d4eadd | 614 | |
0f2a7930 | 615 | hcd->uses_new_polling = 1; |
f6ff0ac8 SS |
616 | if (!usb_hcd_is_primary_hcd(hcd)) |
617 | return xhci_run_finished(xhci); | |
0f2a7930 | 618 | |
d195fcff | 619 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run"); |
43b86af8 | 620 | |
3fd1ec58 | 621 | ret = xhci_try_enable_msi(hcd); |
43b86af8 | 622 | if (ret) |
3fd1ec58 | 623 | return ret; |
66d4eadd | 624 | |
66e49d87 SS |
625 | xhci_dbg(xhci, "Command ring memory map follows:\n"); |
626 | xhci_debug_ring(xhci, xhci->cmd_ring); | |
627 | xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); | |
628 | xhci_dbg_cmd_ptrs(xhci); | |
629 | ||
630 | xhci_dbg(xhci, "ERST memory map follows:\n"); | |
631 | xhci_dbg_erst(xhci, &xhci->erst); | |
632 | xhci_dbg(xhci, "Event ring:\n"); | |
633 | xhci_debug_ring(xhci, xhci->event_ring); | |
634 | xhci_dbg_ring_ptrs(xhci, xhci->event_ring); | |
f7b2e403 | 635 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
66e49d87 | 636 | temp_64 &= ~ERST_PTR_MASK; |
d195fcff XR |
637 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
638 | "ERST deq = 64'h%0lx", (long unsigned int) temp_64); | |
66e49d87 | 639 | |
d195fcff XR |
640 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
641 | "// Set the interrupt modulation register"); | |
b0ba9720 | 642 | temp = readl(&xhci->ir_set->irq_control); |
a4d88302 | 643 | temp &= ~ER_IRQ_INTERVAL_MASK; |
0cbd4b34 CY |
644 | /* |
645 | * the increment interval is 8 times as much as that defined | |
646 | * in xHCI spec on MTK's controller | |
647 | */ | |
648 | temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160); | |
204b7793 | 649 | writel(temp, &xhci->ir_set->irq_control); |
66d4eadd SS |
650 | |
651 | /* Set the HCD state before we enable the irqs */ | |
b0ba9720 | 652 | temp = readl(&xhci->op_regs->command); |
66d4eadd | 653 | temp |= (CMD_EIE); |
d195fcff XR |
654 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
655 | "// Enable interrupts, cmd = 0x%x.", temp); | |
204b7793 | 656 | writel(temp, &xhci->op_regs->command); |
66d4eadd | 657 | |
b0ba9720 | 658 | temp = readl(&xhci->ir_set->irq_pending); |
d195fcff XR |
659 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
660 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", | |
700e2052 | 661 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); |
204b7793 | 662 | writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 663 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 664 | |
ddba5cd0 MN |
665 | if (xhci->quirks & XHCI_NEC_HOST) { |
666 | struct xhci_command *command; | |
667 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); | |
668 | if (!command) | |
669 | return -ENOMEM; | |
670 | xhci_queue_vendor_command(xhci, command, 0, 0, 0, | |
0238634d | 671 | TRB_TYPE(TRB_NEC_GET_FW)); |
ddba5cd0 | 672 | } |
d195fcff XR |
673 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
674 | "Finished xhci_run for USB2 roothub"); | |
f6ff0ac8 SS |
675 | return 0; |
676 | } | |
436e8c7d | 677 | EXPORT_SYMBOL_GPL(xhci_run); |
ed07453f | 678 | |
66d4eadd SS |
679 | /* |
680 | * Stop xHCI driver. | |
681 | * | |
682 | * This function is called by the USB core when the HC driver is removed. | |
683 | * Its opposite is xhci_run(). | |
684 | * | |
685 | * Disable device contexts, disable IRQs, and quiesce the HC. | |
686 | * Reset the HC, finish any completed transactions, and cleanup memory. | |
687 | */ | |
688 | void xhci_stop(struct usb_hcd *hcd) | |
689 | { | |
690 | u32 temp; | |
691 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
692 | ||
8c24d6d7 | 693 | mutex_lock(&xhci->mutex); |
8c24d6d7 | 694 | |
27a41a83 GKB |
695 | if (!(xhci->xhc_state & XHCI_STATE_HALTED)) { |
696 | spin_lock_irq(&xhci->lock); | |
697 | ||
698 | xhci->xhc_state |= XHCI_STATE_HALTED; | |
699 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
700 | xhci_halt(xhci); | |
701 | xhci_reset(xhci); | |
27a41a83 GKB |
702 | spin_unlock_irq(&xhci->lock); |
703 | } | |
704 | ||
705 | if (!usb_hcd_is_primary_hcd(hcd)) { | |
706 | mutex_unlock(&xhci->mutex); | |
707 | return; | |
708 | } | |
66d4eadd | 709 | |
40a9fb17 ZR |
710 | xhci_cleanup_msix(xhci); |
711 | ||
71c731a2 AC |
712 | /* Deleting Compliance Mode Recovery Timer */ |
713 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
58b1d799 | 714 | (!(xhci_all_ports_seen_u0(xhci)))) { |
71c731a2 | 715 | del_timer_sync(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
716 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
717 | "%s: compliance mode recovery timer deleted", | |
58b1d799 TC |
718 | __func__); |
719 | } | |
71c731a2 | 720 | |
c41136b0 AX |
721 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
722 | usb_amd_dev_put(); | |
723 | ||
d195fcff XR |
724 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
725 | "// Disabling event ring interrupts"); | |
b0ba9720 | 726 | temp = readl(&xhci->op_regs->status); |
d1001ab4 | 727 | writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 728 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 729 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 730 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 731 | |
d195fcff | 732 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); |
66d4eadd | 733 | xhci_mem_cleanup(xhci); |
d195fcff XR |
734 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
735 | "xhci_stop completed - status = %x", | |
b0ba9720 | 736 | readl(&xhci->op_regs->status)); |
85ac90f8 | 737 | mutex_unlock(&xhci->mutex); |
66d4eadd SS |
738 | } |
739 | ||
740 | /* | |
741 | * Shutdown HC (not bus-specific) | |
742 | * | |
743 | * This is called when the machine is rebooting or halting. We assume that the | |
744 | * machine will be powered off, and the HC's internal state will be reset. | |
745 | * Don't bother to free memory. | |
f6ff0ac8 SS |
746 | * |
747 | * This will only ever be called with the main usb_hcd (the USB3 roothub). | |
66d4eadd SS |
748 | */ |
749 | void xhci_shutdown(struct usb_hcd *hcd) | |
750 | { | |
751 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
752 | ||
052c7f9f | 753 | if (xhci->quirks & XHCI_SPURIOUS_REBOOT) |
4c39d4b9 | 754 | usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev)); |
e95829f4 | 755 | |
66d4eadd SS |
756 | spin_lock_irq(&xhci->lock); |
757 | xhci_halt(xhci); | |
638298dc TI |
758 | /* Workaround for spurious wakeups at shutdown with HSW */ |
759 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
760 | xhci_reset(xhci); | |
43b86af8 | 761 | spin_unlock_irq(&xhci->lock); |
66d4eadd | 762 | |
40a9fb17 ZR |
763 | xhci_cleanup_msix(xhci); |
764 | ||
d195fcff XR |
765 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
766 | "xhci_shutdown completed - status = %x", | |
b0ba9720 | 767 | readl(&xhci->op_regs->status)); |
638298dc TI |
768 | |
769 | /* Yet another workaround for spurious wakeups at shutdown with HSW */ | |
770 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
4c39d4b9 | 771 | pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot); |
66d4eadd SS |
772 | } |
773 | ||
b5b5c3ac | 774 | #ifdef CONFIG_PM |
5535b1d5 AX |
775 | static void xhci_save_registers(struct xhci_hcd *xhci) |
776 | { | |
b0ba9720 XR |
777 | xhci->s3.command = readl(&xhci->op_regs->command); |
778 | xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification); | |
f7b2e403 | 779 | xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
b0ba9720 XR |
780 | xhci->s3.config_reg = readl(&xhci->op_regs->config_reg); |
781 | xhci->s3.erst_size = readl(&xhci->ir_set->erst_size); | |
f7b2e403 SS |
782 | xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
783 | xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
b0ba9720 XR |
784 | xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending); |
785 | xhci->s3.irq_control = readl(&xhci->ir_set->irq_control); | |
5535b1d5 AX |
786 | } |
787 | ||
788 | static void xhci_restore_registers(struct xhci_hcd *xhci) | |
789 | { | |
204b7793 XR |
790 | writel(xhci->s3.command, &xhci->op_regs->command); |
791 | writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification); | |
477632df | 792 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); |
204b7793 XR |
793 | writel(xhci->s3.config_reg, &xhci->op_regs->config_reg); |
794 | writel(xhci->s3.erst_size, &xhci->ir_set->erst_size); | |
477632df SS |
795 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); |
796 | xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); | |
204b7793 XR |
797 | writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending); |
798 | writel(xhci->s3.irq_control, &xhci->ir_set->irq_control); | |
5535b1d5 AX |
799 | } |
800 | ||
89821320 SS |
801 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) |
802 | { | |
803 | u64 val_64; | |
804 | ||
805 | /* step 2: initialize command ring buffer */ | |
f7b2e403 | 806 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
89821320 SS |
807 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
808 | (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | |
809 | xhci->cmd_ring->dequeue) & | |
810 | (u64) ~CMD_RING_RSVD_BITS) | | |
811 | xhci->cmd_ring->cycle_state; | |
d195fcff XR |
812 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
813 | "// Setting command ring address to 0x%llx", | |
89821320 | 814 | (long unsigned long) val_64); |
477632df | 815 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); |
89821320 SS |
816 | } |
817 | ||
818 | /* | |
819 | * The whole command ring must be cleared to zero when we suspend the host. | |
820 | * | |
821 | * The host doesn't save the command ring pointer in the suspend well, so we | |
822 | * need to re-program it on resume. Unfortunately, the pointer must be 64-byte | |
823 | * aligned, because of the reserved bits in the command ring dequeue pointer | |
824 | * register. Therefore, we can't just set the dequeue pointer back in the | |
825 | * middle of the ring (TRBs are 16-byte aligned). | |
826 | */ | |
827 | static void xhci_clear_command_ring(struct xhci_hcd *xhci) | |
828 | { | |
829 | struct xhci_ring *ring; | |
830 | struct xhci_segment *seg; | |
831 | ||
832 | ring = xhci->cmd_ring; | |
833 | seg = ring->deq_seg; | |
834 | do { | |
158886cd AX |
835 | memset(seg->trbs, 0, |
836 | sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1)); | |
837 | seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= | |
838 | cpu_to_le32(~TRB_CYCLE); | |
89821320 SS |
839 | seg = seg->next; |
840 | } while (seg != ring->deq_seg); | |
841 | ||
842 | /* Reset the software enqueue and dequeue pointers */ | |
843 | ring->deq_seg = ring->first_seg; | |
844 | ring->dequeue = ring->first_seg->trbs; | |
845 | ring->enq_seg = ring->deq_seg; | |
846 | ring->enqueue = ring->dequeue; | |
847 | ||
b008df60 | 848 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; |
89821320 SS |
849 | /* |
850 | * Ring is now zeroed, so the HW should look for change of ownership | |
851 | * when the cycle bit is set to 1. | |
852 | */ | |
853 | ring->cycle_state = 1; | |
854 | ||
855 | /* | |
856 | * Reset the hardware dequeue pointer. | |
857 | * Yes, this will need to be re-written after resume, but we're paranoid | |
858 | * and want to make sure the hardware doesn't access bogus memory | |
859 | * because, say, the BIOS or an SMI started the host without changing | |
860 | * the command ring pointers. | |
861 | */ | |
862 | xhci_set_cmd_ring_deq(xhci); | |
863 | } | |
864 | ||
a1377e53 LB |
865 | static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci) |
866 | { | |
867 | int port_index; | |
868 | __le32 __iomem **port_array; | |
869 | unsigned long flags; | |
870 | u32 t1, t2; | |
871 | ||
872 | spin_lock_irqsave(&xhci->lock, flags); | |
873 | ||
8a1115ff | 874 | /* disable usb3 ports Wake bits */ |
a1377e53 LB |
875 | port_index = xhci->num_usb3_ports; |
876 | port_array = xhci->usb3_ports; | |
877 | while (port_index--) { | |
878 | t1 = readl(port_array[port_index]); | |
879 | t1 = xhci_port_state_to_neutral(t1); | |
880 | t2 = t1 & ~PORT_WAKE_BITS; | |
881 | if (t1 != t2) | |
882 | writel(t2, port_array[port_index]); | |
883 | } | |
884 | ||
8a1115ff | 885 | /* disable usb2 ports Wake bits */ |
a1377e53 LB |
886 | port_index = xhci->num_usb2_ports; |
887 | port_array = xhci->usb2_ports; | |
888 | while (port_index--) { | |
889 | t1 = readl(port_array[port_index]); | |
890 | t1 = xhci_port_state_to_neutral(t1); | |
891 | t2 = t1 & ~PORT_WAKE_BITS; | |
892 | if (t1 != t2) | |
893 | writel(t2, port_array[port_index]); | |
894 | } | |
895 | ||
896 | spin_unlock_irqrestore(&xhci->lock, flags); | |
897 | } | |
898 | ||
5535b1d5 AX |
899 | /* |
900 | * Stop HC (not bus-specific) | |
901 | * | |
902 | * This is called when the machine transition into S3/S4 mode. | |
903 | * | |
904 | */ | |
a1377e53 | 905 | int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) |
5535b1d5 AX |
906 | { |
907 | int rc = 0; | |
455f5892 | 908 | unsigned int delay = XHCI_MAX_HALT_USEC; |
5535b1d5 AX |
909 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
910 | u32 command; | |
911 | ||
9fa733f2 RQ |
912 | if (!hcd->state) |
913 | return 0; | |
914 | ||
77b84767 FB |
915 | if (hcd->state != HC_STATE_SUSPENDED || |
916 | xhci->shared_hcd->state != HC_STATE_SUSPENDED) | |
917 | return -EINVAL; | |
918 | ||
a1377e53 LB |
919 | /* Clear root port wake on bits if wakeup not allowed. */ |
920 | if (!do_wakeup) | |
921 | xhci_disable_port_wake_on_bits(xhci); | |
922 | ||
c52804a4 SS |
923 | /* Don't poll the roothubs on bus suspend. */ |
924 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
925 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
926 | del_timer_sync(&hcd->rh_timer); | |
14e61a1b AC |
927 | clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); |
928 | del_timer_sync(&xhci->shared_hcd->rh_timer); | |
c52804a4 | 929 | |
5535b1d5 AX |
930 | spin_lock_irq(&xhci->lock); |
931 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
b3209379 | 932 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); |
5535b1d5 AX |
933 | /* step 1: stop endpoint */ |
934 | /* skipped assuming that port suspend has done */ | |
935 | ||
936 | /* step 2: clear Run/Stop bit */ | |
b0ba9720 | 937 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 938 | command &= ~CMD_RUN; |
204b7793 | 939 | writel(command, &xhci->op_regs->command); |
455f5892 ON |
940 | |
941 | /* Some chips from Fresco Logic need an extraordinary delay */ | |
942 | delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; | |
943 | ||
dc0b177c | 944 | if (xhci_handshake(&xhci->op_regs->status, |
455f5892 | 945 | STS_HALT, STS_HALT, delay)) { |
5535b1d5 AX |
946 | xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n"); |
947 | spin_unlock_irq(&xhci->lock); | |
948 | return -ETIMEDOUT; | |
949 | } | |
89821320 | 950 | xhci_clear_command_ring(xhci); |
5535b1d5 AX |
951 | |
952 | /* step 3: save registers */ | |
953 | xhci_save_registers(xhci); | |
954 | ||
955 | /* step 4: set CSS flag */ | |
b0ba9720 | 956 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 957 | command |= CMD_CSS; |
204b7793 | 958 | writel(command, &xhci->op_regs->command); |
dc0b177c | 959 | if (xhci_handshake(&xhci->op_regs->status, |
2611bd18 | 960 | STS_SAVE, 0, 10 * 1000)) { |
622eb783 | 961 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); |
5535b1d5 AX |
962 | spin_unlock_irq(&xhci->lock); |
963 | return -ETIMEDOUT; | |
964 | } | |
5535b1d5 AX |
965 | spin_unlock_irq(&xhci->lock); |
966 | ||
71c731a2 AC |
967 | /* |
968 | * Deleting Compliance Mode Recovery Timer because the xHCI Host | |
969 | * is about to be suspended. | |
970 | */ | |
971 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
972 | (!(xhci_all_ports_seen_u0(xhci)))) { | |
973 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
974 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
975 | "%s: compliance mode recovery timer deleted", | |
58b1d799 | 976 | __func__); |
71c731a2 AC |
977 | } |
978 | ||
0029227f AX |
979 | /* step 5: remove core well power */ |
980 | /* synchronize irq when using MSI-X */ | |
421aa841 | 981 | xhci_msix_sync_irqs(xhci); |
0029227f | 982 | |
5535b1d5 AX |
983 | return rc; |
984 | } | |
436e8c7d | 985 | EXPORT_SYMBOL_GPL(xhci_suspend); |
5535b1d5 AX |
986 | |
987 | /* | |
988 | * start xHC (not bus-specific) | |
989 | * | |
990 | * This is called when the machine transition from S3/S4 mode. | |
991 | * | |
992 | */ | |
993 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |
994 | { | |
d6236f6d | 995 | u32 command, temp = 0, status; |
5535b1d5 | 996 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
65b22f93 | 997 | struct usb_hcd *secondary_hcd; |
f69e3120 | 998 | int retval = 0; |
77df9e0b | 999 | bool comp_timer_running = false; |
5535b1d5 | 1000 | |
9fa733f2 RQ |
1001 | if (!hcd->state) |
1002 | return 0; | |
1003 | ||
f6ff0ac8 | 1004 | /* Wait a bit if either of the roothubs need to settle from the |
25985edc | 1005 | * transition into bus suspend. |
20b67cf5 | 1006 | */ |
f6ff0ac8 SS |
1007 | if (time_before(jiffies, xhci->bus_state[0].next_statechange) || |
1008 | time_before(jiffies, | |
1009 | xhci->bus_state[1].next_statechange)) | |
5535b1d5 AX |
1010 | msleep(100); |
1011 | ||
f69e3120 AS |
1012 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
1013 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); | |
1014 | ||
5535b1d5 | 1015 | spin_lock_irq(&xhci->lock); |
c877b3b2 ML |
1016 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
1017 | hibernated = true; | |
5535b1d5 AX |
1018 | |
1019 | if (!hibernated) { | |
1020 | /* step 1: restore register */ | |
1021 | xhci_restore_registers(xhci); | |
1022 | /* step 2: initialize command ring buffer */ | |
89821320 | 1023 | xhci_set_cmd_ring_deq(xhci); |
5535b1d5 AX |
1024 | /* step 3: restore state and start state*/ |
1025 | /* step 3: set CRS flag */ | |
b0ba9720 | 1026 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1027 | command |= CMD_CRS; |
204b7793 | 1028 | writel(command, &xhci->op_regs->command); |
dc0b177c | 1029 | if (xhci_handshake(&xhci->op_regs->status, |
622eb783 AX |
1030 | STS_RESTORE, 0, 10 * 1000)) { |
1031 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); | |
5535b1d5 AX |
1032 | spin_unlock_irq(&xhci->lock); |
1033 | return -ETIMEDOUT; | |
1034 | } | |
b0ba9720 | 1035 | temp = readl(&xhci->op_regs->status); |
5535b1d5 AX |
1036 | } |
1037 | ||
1038 | /* If restore operation fails, re-initialize the HC during resume */ | |
1039 | if ((temp & STS_SRE) || hibernated) { | |
77df9e0b TC |
1040 | |
1041 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
1042 | !(xhci_all_ports_seen_u0(xhci))) { | |
1043 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
1044 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1045 | "Compliance Mode Recovery Timer deleted!"); | |
77df9e0b TC |
1046 | } |
1047 | ||
fedd383e SS |
1048 | /* Let the USB core know _both_ roothubs lost power. */ |
1049 | usb_root_hub_lost_power(xhci->main_hcd->self.root_hub); | |
1050 | usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub); | |
5535b1d5 AX |
1051 | |
1052 | xhci_dbg(xhci, "Stop HCD\n"); | |
1053 | xhci_halt(xhci); | |
1054 | xhci_reset(xhci); | |
5535b1d5 | 1055 | spin_unlock_irq(&xhci->lock); |
0029227f | 1056 | xhci_cleanup_msix(xhci); |
5535b1d5 | 1057 | |
5535b1d5 | 1058 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
b0ba9720 | 1059 | temp = readl(&xhci->op_regs->status); |
d1001ab4 | 1060 | writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 1061 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 1062 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 1063 | xhci_print_ir_set(xhci, 0); |
5535b1d5 AX |
1064 | |
1065 | xhci_dbg(xhci, "cleaning up memory\n"); | |
1066 | xhci_mem_cleanup(xhci); | |
1067 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", | |
b0ba9720 | 1068 | readl(&xhci->op_regs->status)); |
5535b1d5 | 1069 | |
65b22f93 SS |
1070 | /* USB core calls the PCI reinit and start functions twice: |
1071 | * first with the primary HCD, and then with the secondary HCD. | |
1072 | * If we don't do the same, the host will never be started. | |
1073 | */ | |
1074 | if (!usb_hcd_is_primary_hcd(hcd)) | |
1075 | secondary_hcd = hcd; | |
1076 | else | |
1077 | secondary_hcd = xhci->shared_hcd; | |
1078 | ||
1079 | xhci_dbg(xhci, "Initialize the xhci_hcd\n"); | |
1080 | retval = xhci_init(hcd->primary_hcd); | |
5535b1d5 AX |
1081 | if (retval) |
1082 | return retval; | |
77df9e0b TC |
1083 | comp_timer_running = true; |
1084 | ||
65b22f93 SS |
1085 | xhci_dbg(xhci, "Start the primary HCD\n"); |
1086 | retval = xhci_run(hcd->primary_hcd); | |
b3209379 | 1087 | if (!retval) { |
f69e3120 AS |
1088 | xhci_dbg(xhci, "Start the secondary HCD\n"); |
1089 | retval = xhci_run(secondary_hcd); | |
b3209379 | 1090 | } |
5535b1d5 | 1091 | hcd->state = HC_STATE_SUSPENDED; |
b3209379 | 1092 | xhci->shared_hcd->state = HC_STATE_SUSPENDED; |
f69e3120 | 1093 | goto done; |
5535b1d5 AX |
1094 | } |
1095 | ||
5535b1d5 | 1096 | /* step 4: set Run/Stop bit */ |
b0ba9720 | 1097 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1098 | command |= CMD_RUN; |
204b7793 | 1099 | writel(command, &xhci->op_regs->command); |
dc0b177c | 1100 | xhci_handshake(&xhci->op_regs->status, STS_HALT, |
5535b1d5 AX |
1101 | 0, 250 * 1000); |
1102 | ||
1103 | /* step 5: walk topology and initialize portsc, | |
1104 | * portpmsc and portli | |
1105 | */ | |
1106 | /* this is done in bus_resume */ | |
1107 | ||
1108 | /* step 6: restart each of the previously | |
1109 | * Running endpoints by ringing their doorbells | |
1110 | */ | |
1111 | ||
5535b1d5 | 1112 | spin_unlock_irq(&xhci->lock); |
f69e3120 AS |
1113 | |
1114 | done: | |
1115 | if (retval == 0) { | |
d6236f6d WY |
1116 | /* Resume root hubs only when have pending events. */ |
1117 | status = readl(&xhci->op_regs->status); | |
1118 | if (status & STS_EINT) { | |
d6236f6d | 1119 | usb_hcd_resume_root_hub(xhci->shared_hcd); |
671ffdff | 1120 | usb_hcd_resume_root_hub(hcd); |
d6236f6d | 1121 | } |
f69e3120 | 1122 | } |
71c731a2 AC |
1123 | |
1124 | /* | |
1125 | * If system is subject to the Quirk, Compliance Mode Timer needs to | |
1126 | * be re-initialized Always after a system resume. Ports are subject | |
1127 | * to suffer the Compliance Mode issue again. It doesn't matter if | |
1128 | * ports have entered previously to U0 before system's suspension. | |
1129 | */ | |
77df9e0b | 1130 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running) |
71c731a2 AC |
1131 | compliance_mode_recovery_timer_init(xhci); |
1132 | ||
c52804a4 SS |
1133 | /* Re-enable port polling. */ |
1134 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
14e61a1b AC |
1135 | set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); |
1136 | usb_hcd_poll_rh_status(xhci->shared_hcd); | |
671ffdff MN |
1137 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
1138 | usb_hcd_poll_rh_status(hcd); | |
c52804a4 | 1139 | |
f69e3120 | 1140 | return retval; |
5535b1d5 | 1141 | } |
436e8c7d | 1142 | EXPORT_SYMBOL_GPL(xhci_resume); |
b5b5c3ac SS |
1143 | #endif /* CONFIG_PM */ |
1144 | ||
7f84eef0 SS |
1145 | /*-------------------------------------------------------------------------*/ |
1146 | ||
d0e96f5a SS |
1147 | /** |
1148 | * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and | |
1149 | * HCDs. Find the index for an endpoint given its descriptor. Use the return | |
1150 | * value to right shift 1 for the bitmask. | |
1151 | * | |
1152 | * Index = (epnum * 2) + direction - 1, | |
1153 | * where direction = 0 for OUT, 1 for IN. | |
1154 | * For control endpoints, the IN index is used (OUT index is unused), so | |
1155 | * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) | |
1156 | */ | |
1157 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc) | |
1158 | { | |
1159 | unsigned int index; | |
1160 | if (usb_endpoint_xfer_control(desc)) | |
1161 | index = (unsigned int) (usb_endpoint_num(desc)*2); | |
1162 | else | |
1163 | index = (unsigned int) (usb_endpoint_num(desc)*2) + | |
1164 | (usb_endpoint_dir_in(desc) ? 1 : 0) - 1; | |
1165 | return index; | |
1166 | } | |
1167 | ||
01c5f447 JW |
1168 | /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint |
1169 | * address from the XHCI endpoint index. | |
1170 | */ | |
1171 | unsigned int xhci_get_endpoint_address(unsigned int ep_index) | |
1172 | { | |
1173 | unsigned int number = DIV_ROUND_UP(ep_index, 2); | |
1174 | unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN; | |
1175 | return direction | number; | |
1176 | } | |
1177 | ||
f94e0186 SS |
1178 | /* Find the flag for this endpoint (for use in the control context). Use the |
1179 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1180 | * bit 1, etc. | |
1181 | */ | |
1182 | unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc) | |
1183 | { | |
1184 | return 1 << (xhci_get_endpoint_index(desc) + 1); | |
1185 | } | |
1186 | ||
ac9d8fe7 SS |
1187 | /* Find the flag for this endpoint (for use in the control context). Use the |
1188 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1189 | * bit 1, etc. | |
1190 | */ | |
1191 | unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index) | |
1192 | { | |
1193 | return 1 << (ep_index + 1); | |
1194 | } | |
1195 | ||
f94e0186 SS |
1196 | /* Compute the last valid endpoint context index. Basically, this is the |
1197 | * endpoint index plus one. For slot contexts with more than valid endpoint, | |
1198 | * we find the most significant bit set in the added contexts flags. | |
1199 | * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000 | |
1200 | * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one. | |
1201 | */ | |
ac9d8fe7 | 1202 | unsigned int xhci_last_valid_endpoint(u32 added_ctxs) |
f94e0186 SS |
1203 | { |
1204 | return fls(added_ctxs) - 1; | |
1205 | } | |
1206 | ||
d0e96f5a SS |
1207 | /* Returns 1 if the arguments are OK; |
1208 | * returns 0 this is a root hub; returns -EINVAL for NULL pointers. | |
1209 | */ | |
8212a49d | 1210 | static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, |
64927730 AX |
1211 | struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev, |
1212 | const char *func) { | |
1213 | struct xhci_hcd *xhci; | |
1214 | struct xhci_virt_device *virt_dev; | |
1215 | ||
d0e96f5a | 1216 | if (!hcd || (check_ep && !ep) || !udev) { |
5c1127d3 | 1217 | pr_debug("xHCI %s called with invalid args\n", func); |
d0e96f5a SS |
1218 | return -EINVAL; |
1219 | } | |
1220 | if (!udev->parent) { | |
5c1127d3 | 1221 | pr_debug("xHCI %s called for root hub\n", func); |
d0e96f5a SS |
1222 | return 0; |
1223 | } | |
64927730 | 1224 | |
7bd89b40 | 1225 | xhci = hcd_to_xhci(hcd); |
64927730 | 1226 | if (check_virt_dev) { |
73ddc247 | 1227 | if (!udev->slot_id || !xhci->devs[udev->slot_id]) { |
5c1127d3 XR |
1228 | xhci_dbg(xhci, "xHCI %s called with unaddressed device\n", |
1229 | func); | |
64927730 AX |
1230 | return -EINVAL; |
1231 | } | |
1232 | ||
1233 | virt_dev = xhci->devs[udev->slot_id]; | |
1234 | if (virt_dev->udev != udev) { | |
5c1127d3 | 1235 | xhci_dbg(xhci, "xHCI %s called with udev and " |
64927730 AX |
1236 | "virt_dev does not match\n", func); |
1237 | return -EINVAL; | |
1238 | } | |
d0e96f5a | 1239 | } |
64927730 | 1240 | |
203a8661 SS |
1241 | if (xhci->xhc_state & XHCI_STATE_HALTED) |
1242 | return -ENODEV; | |
1243 | ||
d0e96f5a SS |
1244 | return 1; |
1245 | } | |
1246 | ||
2d3f1fac | 1247 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, |
913a8a34 SS |
1248 | struct usb_device *udev, struct xhci_command *command, |
1249 | bool ctx_change, bool must_succeed); | |
2d3f1fac SS |
1250 | |
1251 | /* | |
1252 | * Full speed devices may have a max packet size greater than 8 bytes, but the | |
1253 | * USB core doesn't know that until it reads the first 8 bytes of the | |
1254 | * descriptor. If the usb_device's max packet size changes after that point, | |
1255 | * we need to issue an evaluate context command and wait on it. | |
1256 | */ | |
1257 | static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, | |
1258 | unsigned int ep_index, struct urb *urb) | |
1259 | { | |
2d3f1fac SS |
1260 | struct xhci_container_ctx *out_ctx; |
1261 | struct xhci_input_control_ctx *ctrl_ctx; | |
1262 | struct xhci_ep_ctx *ep_ctx; | |
ddba5cd0 | 1263 | struct xhci_command *command; |
2d3f1fac SS |
1264 | int max_packet_size; |
1265 | int hw_max_packet_size; | |
1266 | int ret = 0; | |
1267 | ||
1268 | out_ctx = xhci->devs[slot_id]->out_ctx; | |
1269 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); | |
28ccd296 | 1270 | hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); |
29cc8897 | 1271 | max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc); |
2d3f1fac | 1272 | if (hw_max_packet_size != max_packet_size) { |
3a7fa5be XR |
1273 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1274 | "Max Packet Size for ep 0 changed."); | |
1275 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, | |
1276 | "Max packet size in usb_device = %d", | |
2d3f1fac | 1277 | max_packet_size); |
3a7fa5be XR |
1278 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1279 | "Max packet size in xHCI HW = %d", | |
2d3f1fac | 1280 | hw_max_packet_size); |
3a7fa5be XR |
1281 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1282 | "Issuing evaluate context command."); | |
2d3f1fac | 1283 | |
92f8e767 SS |
1284 | /* Set up the input context flags for the command */ |
1285 | /* FIXME: This won't work if a non-default control endpoint | |
1286 | * changes max packet sizes. | |
1287 | */ | |
ddba5cd0 MN |
1288 | |
1289 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); | |
1290 | if (!command) | |
1291 | return -ENOMEM; | |
1292 | ||
1293 | command->in_ctx = xhci->devs[slot_id]->in_ctx; | |
4daf9df5 | 1294 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
1295 | if (!ctrl_ctx) { |
1296 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1297 | __func__); | |
ddba5cd0 MN |
1298 | ret = -ENOMEM; |
1299 | goto command_cleanup; | |
92f8e767 | 1300 | } |
2d3f1fac | 1301 | /* Set up the modified control endpoint 0 */ |
913a8a34 SS |
1302 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
1303 | xhci->devs[slot_id]->out_ctx, ep_index); | |
92f8e767 | 1304 | |
ddba5cd0 | 1305 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); |
28ccd296 ME |
1306 | ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK); |
1307 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); | |
2d3f1fac | 1308 | |
28ccd296 | 1309 | ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); |
2d3f1fac SS |
1310 | ctrl_ctx->drop_flags = 0; |
1311 | ||
1312 | xhci_dbg(xhci, "Slot %d input context\n", slot_id); | |
ddba5cd0 | 1313 | xhci_dbg_ctx(xhci, command->in_ctx, ep_index); |
2d3f1fac SS |
1314 | xhci_dbg(xhci, "Slot %d output context\n", slot_id); |
1315 | xhci_dbg_ctx(xhci, out_ctx, ep_index); | |
1316 | ||
ddba5cd0 | 1317 | ret = xhci_configure_endpoint(xhci, urb->dev, command, |
913a8a34 | 1318 | true, false); |
2d3f1fac SS |
1319 | |
1320 | /* Clean up the input context for later use by bandwidth | |
1321 | * functions. | |
1322 | */ | |
28ccd296 | 1323 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); |
ddba5cd0 MN |
1324 | command_cleanup: |
1325 | kfree(command->completion); | |
1326 | kfree(command); | |
2d3f1fac SS |
1327 | } |
1328 | return ret; | |
1329 | } | |
1330 | ||
d0e96f5a SS |
1331 | /* |
1332 | * non-error returns are a promise to giveback() the urb later | |
1333 | * we drop ownership so next owner (or urb unlink) can get it | |
1334 | */ | |
1335 | int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) | |
1336 | { | |
1337 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
1338 | unsigned long flags; | |
1339 | int ret = 0; | |
6969408d | 1340 | unsigned int slot_id, ep_index, ep_state; |
8e51adcc | 1341 | struct urb_priv *urb_priv; |
7e64b037 | 1342 | int num_tds; |
2d3f1fac | 1343 | |
64927730 AX |
1344 | if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, |
1345 | true, true, __func__) <= 0) | |
d0e96f5a SS |
1346 | return -EINVAL; |
1347 | ||
1348 | slot_id = urb->dev->slot_id; | |
1349 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
d0e96f5a | 1350 | |
541c7d43 | 1351 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
d0e96f5a SS |
1352 | if (!in_interrupt()) |
1353 | xhci_dbg(xhci, "urb submitted during PCI suspend\n"); | |
6969408d | 1354 | return -ESHUTDOWN; |
d0e96f5a | 1355 | } |
8e51adcc AX |
1356 | |
1357 | if (usb_endpoint_xfer_isoc(&urb->ep->desc)) | |
e6f7caa3 | 1358 | num_tds = urb->number_of_packets; |
4758dcd1 RA |
1359 | else if (usb_endpoint_is_bulk_out(&urb->ep->desc) && |
1360 | urb->transfer_buffer_length > 0 && | |
1361 | urb->transfer_flags & URB_ZERO_PACKET && | |
1362 | !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc))) | |
e6f7caa3 | 1363 | num_tds = 2; |
8e51adcc | 1364 | else |
e6f7caa3 | 1365 | num_tds = 1; |
8e51adcc AX |
1366 | |
1367 | urb_priv = kzalloc(sizeof(struct urb_priv) + | |
7e64b037 | 1368 | num_tds * sizeof(struct xhci_td), mem_flags); |
8e51adcc AX |
1369 | if (!urb_priv) |
1370 | return -ENOMEM; | |
1371 | ||
9ef7fbbb MN |
1372 | urb_priv->num_tds = num_tds; |
1373 | urb_priv->num_tds_done = 0; | |
8e51adcc AX |
1374 | urb->hcpriv = urb_priv; |
1375 | ||
5abdc2e6 FB |
1376 | trace_xhci_urb_enqueue(urb); |
1377 | ||
2d3f1fac SS |
1378 | if (usb_endpoint_xfer_control(&urb->ep->desc)) { |
1379 | /* Check to see if the max packet size for the default control | |
1380 | * endpoint changed during FS device enumeration | |
1381 | */ | |
1382 | if (urb->dev->speed == USB_SPEED_FULL) { | |
1383 | ret = xhci_check_maxpacket(xhci, slot_id, | |
1384 | ep_index, urb); | |
d13565c1 | 1385 | if (ret < 0) { |
4daf9df5 | 1386 | xhci_urb_free_priv(urb_priv); |
d13565c1 | 1387 | urb->hcpriv = NULL; |
2d3f1fac | 1388 | return ret; |
d13565c1 | 1389 | } |
2d3f1fac | 1390 | } |
6969408d | 1391 | } |
2d3f1fac | 1392 | |
6969408d MN |
1393 | spin_lock_irqsave(&xhci->lock, flags); |
1394 | ||
1395 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
1396 | xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n", | |
1397 | urb->ep->desc.bEndpointAddress, urb); | |
1398 | ret = -ESHUTDOWN; | |
1399 | goto free_priv; | |
1400 | } | |
1401 | ||
1402 | switch (usb_endpoint_type(&urb->ep->desc)) { | |
1403 | ||
1404 | case USB_ENDPOINT_XFER_CONTROL: | |
b11069f5 | 1405 | ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb, |
6969408d MN |
1406 | slot_id, ep_index); |
1407 | break; | |
1408 | case USB_ENDPOINT_XFER_BULK: | |
1409 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
1410 | if (ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) { | |
1411 | xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n", | |
1412 | ep_state); | |
8df75f42 | 1413 | ret = -EINVAL; |
6969408d | 1414 | break; |
8df75f42 | 1415 | } |
6969408d MN |
1416 | ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, |
1417 | slot_id, ep_index); | |
1418 | break; | |
1419 | ||
1420 | ||
1421 | case USB_ENDPOINT_XFER_INT: | |
624defa1 SS |
1422 | ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb, |
1423 | slot_id, ep_index); | |
6969408d MN |
1424 | break; |
1425 | ||
1426 | case USB_ENDPOINT_XFER_ISOC: | |
787f4e5a AX |
1427 | ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb, |
1428 | slot_id, ep_index); | |
2d3f1fac | 1429 | } |
6969408d MN |
1430 | |
1431 | if (ret) { | |
d13565c1 | 1432 | free_priv: |
6969408d MN |
1433 | xhci_urb_free_priv(urb_priv); |
1434 | urb->hcpriv = NULL; | |
1435 | } | |
6f5165cf | 1436 | spin_unlock_irqrestore(&xhci->lock, flags); |
d13565c1 | 1437 | return ret; |
d0e96f5a SS |
1438 | } |
1439 | ||
ae636747 SS |
1440 | /* |
1441 | * Remove the URB's TD from the endpoint ring. This may cause the HC to stop | |
1442 | * USB transfers, potentially stopping in the middle of a TRB buffer. The HC | |
1443 | * should pick up where it left off in the TD, unless a Set Transfer Ring | |
1444 | * Dequeue Pointer is issued. | |
1445 | * | |
1446 | * The TRBs that make up the buffers for the canceled URB will be "removed" from | |
1447 | * the ring. Since the ring is a contiguous structure, they can't be physically | |
1448 | * removed. Instead, there are two options: | |
1449 | * | |
1450 | * 1) If the HC is in the middle of processing the URB to be canceled, we | |
1451 | * simply move the ring's dequeue pointer past those TRBs using the Set | |
1452 | * Transfer Ring Dequeue Pointer command. This will be the common case, | |
1453 | * when drivers timeout on the last submitted URB and attempt to cancel. | |
1454 | * | |
1455 | * 2) If the HC is in the middle of a different TD, we turn the TRBs into a | |
1456 | * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The | |
1457 | * HC will need to invalidate the any TRBs it has cached after the stop | |
1458 | * endpoint command, as noted in the xHCI 0.95 errata. | |
1459 | * | |
1460 | * 3) The TD may have completed by the time the Stop Endpoint Command | |
1461 | * completes, so software needs to handle that case too. | |
1462 | * | |
1463 | * This function should protect against the TD enqueueing code ringing the | |
1464 | * doorbell while this code is waiting for a Stop Endpoint command to complete. | |
1465 | * It also needs to account for multiple cancellations on happening at the same | |
1466 | * time for the same endpoint. | |
1467 | * | |
1468 | * Note that this function can be called in any context, or so says | |
1469 | * usb_hcd_unlink_urb() | |
d0e96f5a SS |
1470 | */ |
1471 | int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | |
1472 | { | |
ae636747 | 1473 | unsigned long flags; |
8e51adcc | 1474 | int ret, i; |
e34b2fbf | 1475 | u32 temp; |
ae636747 | 1476 | struct xhci_hcd *xhci; |
8e51adcc | 1477 | struct urb_priv *urb_priv; |
ae636747 SS |
1478 | struct xhci_td *td; |
1479 | unsigned int ep_index; | |
1480 | struct xhci_ring *ep_ring; | |
63a0d9ab | 1481 | struct xhci_virt_ep *ep; |
ddba5cd0 | 1482 | struct xhci_command *command; |
d3519b9d | 1483 | struct xhci_virt_device *vdev; |
ae636747 SS |
1484 | |
1485 | xhci = hcd_to_xhci(hcd); | |
1486 | spin_lock_irqsave(&xhci->lock, flags); | |
5abdc2e6 FB |
1487 | |
1488 | trace_xhci_urb_dequeue(urb); | |
1489 | ||
ae636747 SS |
1490 | /* Make sure the URB hasn't completed or been unlinked already */ |
1491 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); | |
d3519b9d | 1492 | if (ret) |
ae636747 | 1493 | goto done; |
d3519b9d MN |
1494 | |
1495 | /* give back URB now if we can't queue it for cancel */ | |
1496 | vdev = xhci->devs[urb->dev->slot_id]; | |
1497 | urb_priv = urb->hcpriv; | |
1498 | if (!vdev || !urb_priv) | |
1499 | goto err_giveback; | |
1500 | ||
1501 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
1502 | ep = &vdev->eps[ep_index]; | |
1503 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); | |
1504 | if (!ep || !ep_ring) | |
1505 | goto err_giveback; | |
1506 | ||
b0ba9720 | 1507 | temp = readl(&xhci->op_regs->status); |
c6cc27c7 | 1508 | if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) { |
aa50b290 XR |
1509 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1510 | "HW died, freeing TD."); | |
9ef7fbbb | 1511 | for (i = urb_priv->num_tds_done; |
d3519b9d | 1512 | i < urb_priv->num_tds; |
5c821711 | 1513 | i++) { |
7e64b037 | 1514 | td = &urb_priv->td[i]; |
585df1d9 SS |
1515 | if (!list_empty(&td->td_list)) |
1516 | list_del_init(&td->td_list); | |
1517 | if (!list_empty(&td->cancelled_td_list)) | |
1518 | list_del_init(&td->cancelled_td_list); | |
1519 | } | |
d3519b9d | 1520 | goto err_giveback; |
e34b2fbf | 1521 | } |
ae636747 | 1522 | |
9ef7fbbb MN |
1523 | i = urb_priv->num_tds_done; |
1524 | if (i < urb_priv->num_tds) | |
aa50b290 XR |
1525 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1526 | "Cancel URB %p, dev %s, ep 0x%x, " | |
1527 | "starting at offset 0x%llx", | |
79688acf SS |
1528 | urb, urb->dev->devpath, |
1529 | urb->ep->desc.bEndpointAddress, | |
1530 | (unsigned long long) xhci_trb_virt_to_dma( | |
7e64b037 MN |
1531 | urb_priv->td[i].start_seg, |
1532 | urb_priv->td[i].first_trb)); | |
79688acf | 1533 | |
9ef7fbbb | 1534 | for (; i < urb_priv->num_tds; i++) { |
7e64b037 | 1535 | td = &urb_priv->td[i]; |
8e51adcc AX |
1536 | list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); |
1537 | } | |
1538 | ||
ae636747 SS |
1539 | /* Queue a stop endpoint command, but only if this is |
1540 | * the first cancellation to be handled. | |
1541 | */ | |
9983a5fc | 1542 | if (!(ep->ep_state & EP_STOP_CMD_PENDING)) { |
ddba5cd0 | 1543 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); |
a0ee619f HG |
1544 | if (!command) { |
1545 | ret = -ENOMEM; | |
1546 | goto done; | |
1547 | } | |
9983a5fc | 1548 | ep->ep_state |= EP_STOP_CMD_PENDING; |
6f5165cf SS |
1549 | ep->stop_cmd_timer.expires = jiffies + |
1550 | XHCI_STOP_EP_CMD_TIMEOUT * HZ; | |
1551 | add_timer(&ep->stop_cmd_timer); | |
ddba5cd0 MN |
1552 | xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id, |
1553 | ep_index, 0); | |
23e3be11 | 1554 | xhci_ring_cmd_db(xhci); |
ae636747 SS |
1555 | } |
1556 | done: | |
1557 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1558 | return ret; | |
d3519b9d MN |
1559 | |
1560 | err_giveback: | |
1561 | if (urb_priv) | |
1562 | xhci_urb_free_priv(urb_priv); | |
1563 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
1564 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1565 | usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN); | |
1566 | return ret; | |
d0e96f5a SS |
1567 | } |
1568 | ||
f94e0186 SS |
1569 | /* Drop an endpoint from a new bandwidth configuration for this device. |
1570 | * Only one call to this function is allowed per endpoint before | |
1571 | * check_bandwidth() or reset_bandwidth() must be called. | |
1572 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1573 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1574 | * different endpoint descriptor in usb_host_endpoint. | |
1575 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1576 | * not allowed. | |
f88ba78d SS |
1577 | * |
1578 | * The USB core will not allow URBs to be queued to an endpoint that is being | |
1579 | * disabled, so there's no need for mutual exclusion to protect | |
1580 | * the xhci->devs[slot_id] structure. | |
f94e0186 SS |
1581 | */ |
1582 | int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |
1583 | struct usb_host_endpoint *ep) | |
1584 | { | |
f94e0186 | 1585 | struct xhci_hcd *xhci; |
d115b048 JY |
1586 | struct xhci_container_ctx *in_ctx, *out_ctx; |
1587 | struct xhci_input_control_ctx *ctrl_ctx; | |
f94e0186 SS |
1588 | unsigned int ep_index; |
1589 | struct xhci_ep_ctx *ep_ctx; | |
1590 | u32 drop_flag; | |
d6759133 | 1591 | u32 new_add_flags, new_drop_flags; |
f94e0186 SS |
1592 | int ret; |
1593 | ||
64927730 | 1594 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
f94e0186 SS |
1595 | if (ret <= 0) |
1596 | return ret; | |
1597 | xhci = hcd_to_xhci(hcd); | |
fe6c6c13 SS |
1598 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1599 | return -ENODEV; | |
f94e0186 | 1600 | |
fe6c6c13 | 1601 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
1602 | drop_flag = xhci_get_endpoint_flag(&ep->desc); |
1603 | if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { | |
1604 | xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", | |
1605 | __func__, drop_flag); | |
1606 | return 0; | |
1607 | } | |
1608 | ||
f94e0186 | 1609 | in_ctx = xhci->devs[udev->slot_id]->in_ctx; |
d115b048 | 1610 | out_ctx = xhci->devs[udev->slot_id]->out_ctx; |
4daf9df5 | 1611 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
1612 | if (!ctrl_ctx) { |
1613 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1614 | __func__); | |
1615 | return 0; | |
1616 | } | |
1617 | ||
f94e0186 | 1618 | ep_index = xhci_get_endpoint_index(&ep->desc); |
d115b048 | 1619 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
f94e0186 SS |
1620 | /* If the HC already knows the endpoint is disabled, |
1621 | * or the HCD has noted it is disabled, ignore this request | |
1622 | */ | |
5071e6b2 | 1623 | if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) || |
28ccd296 ME |
1624 | le32_to_cpu(ctrl_ctx->drop_flags) & |
1625 | xhci_get_endpoint_flag(&ep->desc)) { | |
a6134136 HG |
1626 | /* Do not warn when called after a usb_device_reset */ |
1627 | if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL) | |
1628 | xhci_warn(xhci, "xHCI %s called with disabled ep %p\n", | |
1629 | __func__, ep); | |
f94e0186 SS |
1630 | return 0; |
1631 | } | |
1632 | ||
28ccd296 ME |
1633 | ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag); |
1634 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
f94e0186 | 1635 | |
28ccd296 ME |
1636 | ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag); |
1637 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 | 1638 | |
f94e0186 SS |
1639 | xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); |
1640 | ||
0cbd4b34 CY |
1641 | if (xhci->quirks & XHCI_MTK_HOST) |
1642 | xhci_mtk_drop_ep_quirk(hcd, udev, ep); | |
1643 | ||
d6759133 | 1644 | xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", |
f94e0186 SS |
1645 | (unsigned int) ep->desc.bEndpointAddress, |
1646 | udev->slot_id, | |
1647 | (unsigned int) new_drop_flags, | |
d6759133 | 1648 | (unsigned int) new_add_flags); |
f94e0186 SS |
1649 | return 0; |
1650 | } | |
1651 | ||
1652 | /* Add an endpoint to a new possible bandwidth configuration for this device. | |
1653 | * Only one call to this function is allowed per endpoint before | |
1654 | * check_bandwidth() or reset_bandwidth() must be called. | |
1655 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1656 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1657 | * different endpoint descriptor in usb_host_endpoint. | |
1658 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1659 | * not allowed. | |
f88ba78d SS |
1660 | * |
1661 | * The USB core will not allow URBs to be queued to an endpoint until the | |
1662 | * configuration or alt setting is installed in the device, so there's no need | |
1663 | * for mutual exclusion to protect the xhci->devs[slot_id] structure. | |
f94e0186 SS |
1664 | */ |
1665 | int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |
1666 | struct usb_host_endpoint *ep) | |
1667 | { | |
f94e0186 | 1668 | struct xhci_hcd *xhci; |
92c9691b | 1669 | struct xhci_container_ctx *in_ctx; |
f94e0186 | 1670 | unsigned int ep_index; |
d115b048 | 1671 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1672 | u32 added_ctxs; |
d6759133 | 1673 | u32 new_add_flags, new_drop_flags; |
fa75ac37 | 1674 | struct xhci_virt_device *virt_dev; |
f94e0186 SS |
1675 | int ret = 0; |
1676 | ||
64927730 | 1677 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
a1587d97 SS |
1678 | if (ret <= 0) { |
1679 | /* So we won't queue a reset ep command for a root hub */ | |
1680 | ep->hcpriv = NULL; | |
f94e0186 | 1681 | return ret; |
a1587d97 | 1682 | } |
f94e0186 | 1683 | xhci = hcd_to_xhci(hcd); |
fe6c6c13 SS |
1684 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1685 | return -ENODEV; | |
f94e0186 SS |
1686 | |
1687 | added_ctxs = xhci_get_endpoint_flag(&ep->desc); | |
f94e0186 SS |
1688 | if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) { |
1689 | /* FIXME when we have to issue an evaluate endpoint command to | |
1690 | * deal with ep0 max packet size changing once we get the | |
1691 | * descriptors | |
1692 | */ | |
1693 | xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n", | |
1694 | __func__, added_ctxs); | |
1695 | return 0; | |
1696 | } | |
1697 | ||
fa75ac37 SS |
1698 | virt_dev = xhci->devs[udev->slot_id]; |
1699 | in_ctx = virt_dev->in_ctx; | |
4daf9df5 | 1700 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
1701 | if (!ctrl_ctx) { |
1702 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1703 | __func__); | |
1704 | return 0; | |
1705 | } | |
fa75ac37 | 1706 | |
92f8e767 | 1707 | ep_index = xhci_get_endpoint_index(&ep->desc); |
fa75ac37 SS |
1708 | /* If this endpoint is already in use, and the upper layers are trying |
1709 | * to add it again without dropping it, reject the addition. | |
1710 | */ | |
1711 | if (virt_dev->eps[ep_index].ring && | |
92c9691b | 1712 | !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) { |
fa75ac37 SS |
1713 | xhci_warn(xhci, "Trying to add endpoint 0x%x " |
1714 | "without dropping it.\n", | |
1715 | (unsigned int) ep->desc.bEndpointAddress); | |
1716 | return -EINVAL; | |
1717 | } | |
1718 | ||
f94e0186 SS |
1719 | /* If the HCD has already noted the endpoint is enabled, |
1720 | * ignore this request. | |
1721 | */ | |
92c9691b | 1722 | if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) { |
700e2052 GKH |
1723 | xhci_warn(xhci, "xHCI %s called with enabled ep %p\n", |
1724 | __func__, ep); | |
f94e0186 SS |
1725 | return 0; |
1726 | } | |
1727 | ||
f88ba78d SS |
1728 | /* |
1729 | * Configuration and alternate setting changes must be done in | |
1730 | * process context, not interrupt context (or so documenation | |
1731 | * for usb_set_interface() and usb_set_configuration() claim). | |
1732 | */ | |
fa75ac37 | 1733 | if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) { |
f94e0186 SS |
1734 | dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n", |
1735 | __func__, ep->desc.bEndpointAddress); | |
f94e0186 SS |
1736 | return -ENOMEM; |
1737 | } | |
1738 | ||
0cbd4b34 CY |
1739 | if (xhci->quirks & XHCI_MTK_HOST) { |
1740 | ret = xhci_mtk_add_ep_quirk(hcd, udev, ep); | |
1741 | if (ret < 0) { | |
1742 | xhci_free_or_cache_endpoint_ring(xhci, | |
1743 | virt_dev, ep_index); | |
1744 | return ret; | |
1745 | } | |
1746 | } | |
1747 | ||
28ccd296 ME |
1748 | ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs); |
1749 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 SS |
1750 | |
1751 | /* If xhci_endpoint_disable() was called for this endpoint, but the | |
1752 | * xHC hasn't been notified yet through the check_bandwidth() call, | |
1753 | * this re-adds a new state for the endpoint from the new endpoint | |
1754 | * descriptors. We must drop and re-add this endpoint, so we leave the | |
1755 | * drop flags alone. | |
1756 | */ | |
28ccd296 | 1757 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); |
f94e0186 | 1758 | |
a1587d97 SS |
1759 | /* Store the usb_device pointer for later use */ |
1760 | ep->hcpriv = udev; | |
1761 | ||
d6759133 | 1762 | xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", |
f94e0186 SS |
1763 | (unsigned int) ep->desc.bEndpointAddress, |
1764 | udev->slot_id, | |
1765 | (unsigned int) new_drop_flags, | |
d6759133 | 1766 | (unsigned int) new_add_flags); |
f94e0186 SS |
1767 | return 0; |
1768 | } | |
1769 | ||
d115b048 | 1770 | static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev) |
f94e0186 | 1771 | { |
d115b048 | 1772 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1773 | struct xhci_ep_ctx *ep_ctx; |
d115b048 | 1774 | struct xhci_slot_ctx *slot_ctx; |
f94e0186 SS |
1775 | int i; |
1776 | ||
4daf9df5 | 1777 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
92f8e767 SS |
1778 | if (!ctrl_ctx) { |
1779 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1780 | __func__); | |
1781 | return; | |
1782 | } | |
1783 | ||
f94e0186 SS |
1784 | /* When a device's add flag and drop flag are zero, any subsequent |
1785 | * configure endpoint command will leave that endpoint's state | |
1786 | * untouched. Make sure we don't leave any old state in the input | |
1787 | * endpoint contexts. | |
1788 | */ | |
d115b048 JY |
1789 | ctrl_ctx->drop_flags = 0; |
1790 | ctrl_ctx->add_flags = 0; | |
1791 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); | |
28ccd296 | 1792 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); |
f94e0186 | 1793 | /* Endpoint 0 is always valid */ |
28ccd296 | 1794 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); |
98871e94 | 1795 | for (i = 1; i < 31; i++) { |
d115b048 | 1796 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i); |
f94e0186 SS |
1797 | ep_ctx->ep_info = 0; |
1798 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1799 | ep_ctx->deq = 0; |
f94e0186 SS |
1800 | ep_ctx->tx_info = 0; |
1801 | } | |
1802 | } | |
1803 | ||
f2217e8e | 1804 | static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, |
00161f7d | 1805 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1806 | { |
1807 | int ret; | |
1808 | ||
913a8a34 | 1809 | switch (*cmd_status) { |
0b7c105a FB |
1810 | case COMP_COMMAND_ABORTED: |
1811 | case COMP_STOPPED: | |
c311e391 MN |
1812 | xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n"); |
1813 | ret = -ETIME; | |
1814 | break; | |
0b7c105a | 1815 | case COMP_RESOURCE_ERROR: |
288c0f44 ON |
1816 | dev_warn(&udev->dev, |
1817 | "Not enough host controller resources for new device state.\n"); | |
f2217e8e SS |
1818 | ret = -ENOMEM; |
1819 | /* FIXME: can we allocate more resources for the HC? */ | |
1820 | break; | |
0b7c105a FB |
1821 | case COMP_BANDWIDTH_ERROR: |
1822 | case COMP_SECONDARY_BANDWIDTH_ERROR: | |
288c0f44 ON |
1823 | dev_warn(&udev->dev, |
1824 | "Not enough bandwidth for new device state.\n"); | |
f2217e8e SS |
1825 | ret = -ENOSPC; |
1826 | /* FIXME: can we go back to the old state? */ | |
1827 | break; | |
0b7c105a | 1828 | case COMP_TRB_ERROR: |
f2217e8e SS |
1829 | /* the HCD set up something wrong */ |
1830 | dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, " | |
1831 | "add flag = 1, " | |
1832 | "and endpoint is not disabled.\n"); | |
1833 | ret = -EINVAL; | |
1834 | break; | |
0b7c105a | 1835 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
288c0f44 ON |
1836 | dev_warn(&udev->dev, |
1837 | "ERROR: Incompatible device for endpoint configure command.\n"); | |
f6ba6fe2 AH |
1838 | ret = -ENODEV; |
1839 | break; | |
f2217e8e | 1840 | case COMP_SUCCESS: |
3a7fa5be XR |
1841 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1842 | "Successful Endpoint Configure command"); | |
f2217e8e SS |
1843 | ret = 0; |
1844 | break; | |
1845 | default: | |
288c0f44 ON |
1846 | xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n", |
1847 | *cmd_status); | |
f2217e8e SS |
1848 | ret = -EINVAL; |
1849 | break; | |
1850 | } | |
1851 | return ret; | |
1852 | } | |
1853 | ||
1854 | static int xhci_evaluate_context_result(struct xhci_hcd *xhci, | |
00161f7d | 1855 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1856 | { |
1857 | int ret; | |
913a8a34 | 1858 | struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id]; |
f2217e8e | 1859 | |
913a8a34 | 1860 | switch (*cmd_status) { |
0b7c105a FB |
1861 | case COMP_COMMAND_ABORTED: |
1862 | case COMP_STOPPED: | |
c311e391 MN |
1863 | xhci_warn(xhci, "Timeout while waiting for evaluate context command\n"); |
1864 | ret = -ETIME; | |
1865 | break; | |
0b7c105a | 1866 | case COMP_PARAMETER_ERROR: |
288c0f44 ON |
1867 | dev_warn(&udev->dev, |
1868 | "WARN: xHCI driver setup invalid evaluate context command.\n"); | |
f2217e8e SS |
1869 | ret = -EINVAL; |
1870 | break; | |
0b7c105a | 1871 | case COMP_SLOT_NOT_ENABLED_ERROR: |
288c0f44 ON |
1872 | dev_warn(&udev->dev, |
1873 | "WARN: slot not enabled for evaluate context command.\n"); | |
b8031342 SS |
1874 | ret = -EINVAL; |
1875 | break; | |
0b7c105a | 1876 | case COMP_CONTEXT_STATE_ERROR: |
288c0f44 ON |
1877 | dev_warn(&udev->dev, |
1878 | "WARN: invalid context state for evaluate context command.\n"); | |
f2217e8e SS |
1879 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1); |
1880 | ret = -EINVAL; | |
1881 | break; | |
0b7c105a | 1882 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
288c0f44 ON |
1883 | dev_warn(&udev->dev, |
1884 | "ERROR: Incompatible device for evaluate context command.\n"); | |
f6ba6fe2 AH |
1885 | ret = -ENODEV; |
1886 | break; | |
0b7c105a | 1887 | case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: |
1bb73a88 AH |
1888 | /* Max Exit Latency too large error */ |
1889 | dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n"); | |
1890 | ret = -EINVAL; | |
1891 | break; | |
f2217e8e | 1892 | case COMP_SUCCESS: |
3a7fa5be XR |
1893 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1894 | "Successful evaluate context command"); | |
f2217e8e SS |
1895 | ret = 0; |
1896 | break; | |
1897 | default: | |
288c0f44 ON |
1898 | xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n", |
1899 | *cmd_status); | |
f2217e8e SS |
1900 | ret = -EINVAL; |
1901 | break; | |
1902 | } | |
1903 | return ret; | |
1904 | } | |
1905 | ||
2cf95c18 | 1906 | static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci, |
92f8e767 | 1907 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1908 | { |
2cf95c18 SS |
1909 | u32 valid_add_flags; |
1910 | u32 valid_drop_flags; | |
1911 | ||
2cf95c18 SS |
1912 | /* Ignore the slot flag (bit 0), and the default control endpoint flag |
1913 | * (bit 1). The default control endpoint is added during the Address | |
1914 | * Device command and is never removed until the slot is disabled. | |
1915 | */ | |
ef73400c XR |
1916 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1917 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
1918 | |
1919 | /* Use hweight32 to count the number of ones in the add flags, or | |
1920 | * number of endpoints added. Don't count endpoints that are changed | |
1921 | * (both added and dropped). | |
1922 | */ | |
1923 | return hweight32(valid_add_flags) - | |
1924 | hweight32(valid_add_flags & valid_drop_flags); | |
1925 | } | |
1926 | ||
1927 | static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci, | |
92f8e767 | 1928 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1929 | { |
2cf95c18 SS |
1930 | u32 valid_add_flags; |
1931 | u32 valid_drop_flags; | |
1932 | ||
78d1ff02 XR |
1933 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1934 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
1935 | |
1936 | return hweight32(valid_drop_flags) - | |
1937 | hweight32(valid_add_flags & valid_drop_flags); | |
1938 | } | |
1939 | ||
1940 | /* | |
1941 | * We need to reserve the new number of endpoints before the configure endpoint | |
1942 | * command completes. We can't subtract the dropped endpoints from the number | |
1943 | * of active endpoints until the command completes because we can oversubscribe | |
1944 | * the host in this case: | |
1945 | * | |
1946 | * - the first configure endpoint command drops more endpoints than it adds | |
1947 | * - a second configure endpoint command that adds more endpoints is queued | |
1948 | * - the first configure endpoint command fails, so the config is unchanged | |
1949 | * - the second command may succeed, even though there isn't enough resources | |
1950 | * | |
1951 | * Must be called with xhci->lock held. | |
1952 | */ | |
1953 | static int xhci_reserve_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1954 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1955 | { |
1956 | u32 added_eps; | |
1957 | ||
92f8e767 | 1958 | added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1959 | if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) { |
4bdfe4c3 XR |
1960 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1961 | "Not enough ep ctxs: " | |
1962 | "%u active, need to add %u, limit is %u.", | |
2cf95c18 SS |
1963 | xhci->num_active_eps, added_eps, |
1964 | xhci->limit_active_eps); | |
1965 | return -ENOMEM; | |
1966 | } | |
1967 | xhci->num_active_eps += added_eps; | |
4bdfe4c3 XR |
1968 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1969 | "Adding %u ep ctxs, %u now active.", added_eps, | |
2cf95c18 SS |
1970 | xhci->num_active_eps); |
1971 | return 0; | |
1972 | } | |
1973 | ||
1974 | /* | |
1975 | * The configure endpoint was failed by the xHC for some other reason, so we | |
1976 | * need to revert the resources that failed configuration would have used. | |
1977 | * | |
1978 | * Must be called with xhci->lock held. | |
1979 | */ | |
1980 | static void xhci_free_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1981 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1982 | { |
1983 | u32 num_failed_eps; | |
1984 | ||
92f8e767 | 1985 | num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1986 | xhci->num_active_eps -= num_failed_eps; |
4bdfe4c3 XR |
1987 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1988 | "Removing %u failed ep ctxs, %u now active.", | |
2cf95c18 SS |
1989 | num_failed_eps, |
1990 | xhci->num_active_eps); | |
1991 | } | |
1992 | ||
1993 | /* | |
1994 | * Now that the command has completed, clean up the active endpoint count by | |
1995 | * subtracting out the endpoints that were dropped (but not changed). | |
1996 | * | |
1997 | * Must be called with xhci->lock held. | |
1998 | */ | |
1999 | static void xhci_finish_resource_reservation(struct xhci_hcd *xhci, | |
92f8e767 | 2000 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
2001 | { |
2002 | u32 num_dropped_eps; | |
2003 | ||
92f8e767 | 2004 | num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx); |
2cf95c18 SS |
2005 | xhci->num_active_eps -= num_dropped_eps; |
2006 | if (num_dropped_eps) | |
4bdfe4c3 XR |
2007 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2008 | "Removing %u dropped ep ctxs, %u now active.", | |
2cf95c18 SS |
2009 | num_dropped_eps, |
2010 | xhci->num_active_eps); | |
2011 | } | |
2012 | ||
ed384bd3 | 2013 | static unsigned int xhci_get_block_size(struct usb_device *udev) |
c29eea62 SS |
2014 | { |
2015 | switch (udev->speed) { | |
2016 | case USB_SPEED_LOW: | |
2017 | case USB_SPEED_FULL: | |
2018 | return FS_BLOCK; | |
2019 | case USB_SPEED_HIGH: | |
2020 | return HS_BLOCK; | |
2021 | case USB_SPEED_SUPER: | |
0caf6b33 | 2022 | case USB_SPEED_SUPER_PLUS: |
c29eea62 SS |
2023 | return SS_BLOCK; |
2024 | case USB_SPEED_UNKNOWN: | |
2025 | case USB_SPEED_WIRELESS: | |
2026 | default: | |
2027 | /* Should never happen */ | |
2028 | return 1; | |
2029 | } | |
2030 | } | |
2031 | ||
ed384bd3 FB |
2032 | static unsigned int |
2033 | xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw) | |
c29eea62 SS |
2034 | { |
2035 | if (interval_bw->overhead[LS_OVERHEAD_TYPE]) | |
2036 | return LS_OVERHEAD; | |
2037 | if (interval_bw->overhead[FS_OVERHEAD_TYPE]) | |
2038 | return FS_OVERHEAD; | |
2039 | return HS_OVERHEAD; | |
2040 | } | |
2041 | ||
2042 | /* If we are changing a LS/FS device under a HS hub, | |
2043 | * make sure (if we are activating a new TT) that the HS bus has enough | |
2044 | * bandwidth for this new TT. | |
2045 | */ | |
2046 | static int xhci_check_tt_bw_table(struct xhci_hcd *xhci, | |
2047 | struct xhci_virt_device *virt_dev, | |
2048 | int old_active_eps) | |
2049 | { | |
2050 | struct xhci_interval_bw_table *bw_table; | |
2051 | struct xhci_tt_bw_info *tt_info; | |
2052 | ||
2053 | /* Find the bandwidth table for the root port this TT is attached to. */ | |
2054 | bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table; | |
2055 | tt_info = virt_dev->tt_info; | |
2056 | /* If this TT already had active endpoints, the bandwidth for this TT | |
2057 | * has already been added. Removing all periodic endpoints (and thus | |
2058 | * making the TT enactive) will only decrease the bandwidth used. | |
2059 | */ | |
2060 | if (old_active_eps) | |
2061 | return 0; | |
2062 | if (old_active_eps == 0 && tt_info->active_eps != 0) { | |
2063 | if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT) | |
2064 | return -ENOMEM; | |
2065 | return 0; | |
2066 | } | |
2067 | /* Not sure why we would have no new active endpoints... | |
2068 | * | |
2069 | * Maybe because of an Evaluate Context change for a hub update or a | |
2070 | * control endpoint 0 max packet size change? | |
2071 | * FIXME: skip the bandwidth calculation in that case. | |
2072 | */ | |
2073 | return 0; | |
2074 | } | |
2075 | ||
2b698999 SS |
2076 | static int xhci_check_ss_bw(struct xhci_hcd *xhci, |
2077 | struct xhci_virt_device *virt_dev) | |
2078 | { | |
2079 | unsigned int bw_reserved; | |
2080 | ||
2081 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100); | |
2082 | if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved)) | |
2083 | return -ENOMEM; | |
2084 | ||
2085 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100); | |
2086 | if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved)) | |
2087 | return -ENOMEM; | |
2088 | ||
2089 | return 0; | |
2090 | } | |
2091 | ||
c29eea62 SS |
2092 | /* |
2093 | * This algorithm is a very conservative estimate of the worst-case scheduling | |
2094 | * scenario for any one interval. The hardware dynamically schedules the | |
2095 | * packets, so we can't tell which microframe could be the limiting factor in | |
2096 | * the bandwidth scheduling. This only takes into account periodic endpoints. | |
2097 | * | |
2098 | * Obviously, we can't solve an NP complete problem to find the minimum worst | |
2099 | * case scenario. Instead, we come up with an estimate that is no less than | |
2100 | * the worst case bandwidth used for any one microframe, but may be an | |
2101 | * over-estimate. | |
2102 | * | |
2103 | * We walk the requirements for each endpoint by interval, starting with the | |
2104 | * smallest interval, and place packets in the schedule where there is only one | |
2105 | * possible way to schedule packets for that interval. In order to simplify | |
2106 | * this algorithm, we record the largest max packet size for each interval, and | |
2107 | * assume all packets will be that size. | |
2108 | * | |
2109 | * For interval 0, we obviously must schedule all packets for each interval. | |
2110 | * The bandwidth for interval 0 is just the amount of data to be transmitted | |
2111 | * (the sum of all max ESIT payload sizes, plus any overhead per packet times | |
2112 | * the number of packets). | |
2113 | * | |
2114 | * For interval 1, we have two possible microframes to schedule those packets | |
2115 | * in. For this algorithm, if we can schedule the same number of packets for | |
2116 | * each possible scheduling opportunity (each microframe), we will do so. The | |
2117 | * remaining number of packets will be saved to be transmitted in the gaps in | |
2118 | * the next interval's scheduling sequence. | |
2119 | * | |
2120 | * As we move those remaining packets to be scheduled with interval 2 packets, | |
2121 | * we have to double the number of remaining packets to transmit. This is | |
2122 | * because the intervals are actually powers of 2, and we would be transmitting | |
2123 | * the previous interval's packets twice in this interval. We also have to be | |
2124 | * sure that when we look at the largest max packet size for this interval, we | |
2125 | * also look at the largest max packet size for the remaining packets and take | |
2126 | * the greater of the two. | |
2127 | * | |
2128 | * The algorithm continues to evenly distribute packets in each scheduling | |
2129 | * opportunity, and push the remaining packets out, until we get to the last | |
2130 | * interval. Then those packets and their associated overhead are just added | |
2131 | * to the bandwidth used. | |
2e27980e SS |
2132 | */ |
2133 | static int xhci_check_bw_table(struct xhci_hcd *xhci, | |
2134 | struct xhci_virt_device *virt_dev, | |
2135 | int old_active_eps) | |
2136 | { | |
c29eea62 SS |
2137 | unsigned int bw_reserved; |
2138 | unsigned int max_bandwidth; | |
2139 | unsigned int bw_used; | |
2140 | unsigned int block_size; | |
2141 | struct xhci_interval_bw_table *bw_table; | |
2142 | unsigned int packet_size = 0; | |
2143 | unsigned int overhead = 0; | |
2144 | unsigned int packets_transmitted = 0; | |
2145 | unsigned int packets_remaining = 0; | |
2146 | unsigned int i; | |
2147 | ||
0caf6b33 | 2148 | if (virt_dev->udev->speed >= USB_SPEED_SUPER) |
2b698999 SS |
2149 | return xhci_check_ss_bw(xhci, virt_dev); |
2150 | ||
c29eea62 SS |
2151 | if (virt_dev->udev->speed == USB_SPEED_HIGH) { |
2152 | max_bandwidth = HS_BW_LIMIT; | |
2153 | /* Convert percent of bus BW reserved to blocks reserved */ | |
2154 | bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100); | |
2155 | } else { | |
2156 | max_bandwidth = FS_BW_LIMIT; | |
2157 | bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100); | |
2158 | } | |
2159 | ||
2160 | bw_table = virt_dev->bw_table; | |
2161 | /* We need to translate the max packet size and max ESIT payloads into | |
2162 | * the units the hardware uses. | |
2163 | */ | |
2164 | block_size = xhci_get_block_size(virt_dev->udev); | |
2165 | ||
2166 | /* If we are manipulating a LS/FS device under a HS hub, double check | |
2167 | * that the HS bus has enough bandwidth if we are activing a new TT. | |
2168 | */ | |
2169 | if (virt_dev->tt_info) { | |
4bdfe4c3 XR |
2170 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2171 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2172 | virt_dev->real_port); |
2173 | if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) { | |
2174 | xhci_warn(xhci, "Not enough bandwidth on HS bus for " | |
2175 | "newly activated TT.\n"); | |
2176 | return -ENOMEM; | |
2177 | } | |
4bdfe4c3 XR |
2178 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2179 | "Recalculating BW for TT slot %u port %u", | |
c29eea62 SS |
2180 | virt_dev->tt_info->slot_id, |
2181 | virt_dev->tt_info->ttport); | |
2182 | } else { | |
4bdfe4c3 XR |
2183 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2184 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2185 | virt_dev->real_port); |
2186 | } | |
2187 | ||
2188 | /* Add in how much bandwidth will be used for interval zero, or the | |
2189 | * rounded max ESIT payload + number of packets * largest overhead. | |
2190 | */ | |
2191 | bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) + | |
2192 | bw_table->interval_bw[0].num_packets * | |
2193 | xhci_get_largest_overhead(&bw_table->interval_bw[0]); | |
2194 | ||
2195 | for (i = 1; i < XHCI_MAX_INTERVAL; i++) { | |
2196 | unsigned int bw_added; | |
2197 | unsigned int largest_mps; | |
2198 | unsigned int interval_overhead; | |
2199 | ||
2200 | /* | |
2201 | * How many packets could we transmit in this interval? | |
2202 | * If packets didn't fit in the previous interval, we will need | |
2203 | * to transmit that many packets twice within this interval. | |
2204 | */ | |
2205 | packets_remaining = 2 * packets_remaining + | |
2206 | bw_table->interval_bw[i].num_packets; | |
2207 | ||
2208 | /* Find the largest max packet size of this or the previous | |
2209 | * interval. | |
2210 | */ | |
2211 | if (list_empty(&bw_table->interval_bw[i].endpoints)) | |
2212 | largest_mps = 0; | |
2213 | else { | |
2214 | struct xhci_virt_ep *virt_ep; | |
2215 | struct list_head *ep_entry; | |
2216 | ||
2217 | ep_entry = bw_table->interval_bw[i].endpoints.next; | |
2218 | virt_ep = list_entry(ep_entry, | |
2219 | struct xhci_virt_ep, bw_endpoint_list); | |
2220 | /* Convert to blocks, rounding up */ | |
2221 | largest_mps = DIV_ROUND_UP( | |
2222 | virt_ep->bw_info.max_packet_size, | |
2223 | block_size); | |
2224 | } | |
2225 | if (largest_mps > packet_size) | |
2226 | packet_size = largest_mps; | |
2227 | ||
2228 | /* Use the larger overhead of this or the previous interval. */ | |
2229 | interval_overhead = xhci_get_largest_overhead( | |
2230 | &bw_table->interval_bw[i]); | |
2231 | if (interval_overhead > overhead) | |
2232 | overhead = interval_overhead; | |
2233 | ||
2234 | /* How many packets can we evenly distribute across | |
2235 | * (1 << (i + 1)) possible scheduling opportunities? | |
2236 | */ | |
2237 | packets_transmitted = packets_remaining >> (i + 1); | |
2238 | ||
2239 | /* Add in the bandwidth used for those scheduled packets */ | |
2240 | bw_added = packets_transmitted * (overhead + packet_size); | |
2241 | ||
2242 | /* How many packets do we have remaining to transmit? */ | |
2243 | packets_remaining = packets_remaining % (1 << (i + 1)); | |
2244 | ||
2245 | /* What largest max packet size should those packets have? */ | |
2246 | /* If we've transmitted all packets, don't carry over the | |
2247 | * largest packet size. | |
2248 | */ | |
2249 | if (packets_remaining == 0) { | |
2250 | packet_size = 0; | |
2251 | overhead = 0; | |
2252 | } else if (packets_transmitted > 0) { | |
2253 | /* Otherwise if we do have remaining packets, and we've | |
2254 | * scheduled some packets in this interval, take the | |
2255 | * largest max packet size from endpoints with this | |
2256 | * interval. | |
2257 | */ | |
2258 | packet_size = largest_mps; | |
2259 | overhead = interval_overhead; | |
2260 | } | |
2261 | /* Otherwise carry over packet_size and overhead from the last | |
2262 | * time we had a remainder. | |
2263 | */ | |
2264 | bw_used += bw_added; | |
2265 | if (bw_used > max_bandwidth) { | |
2266 | xhci_warn(xhci, "Not enough bandwidth. " | |
2267 | "Proposed: %u, Max: %u\n", | |
2268 | bw_used, max_bandwidth); | |
2269 | return -ENOMEM; | |
2270 | } | |
2271 | } | |
2272 | /* | |
2273 | * Ok, we know we have some packets left over after even-handedly | |
2274 | * scheduling interval 15. We don't know which microframes they will | |
2275 | * fit into, so we over-schedule and say they will be scheduled every | |
2276 | * microframe. | |
2277 | */ | |
2278 | if (packets_remaining > 0) | |
2279 | bw_used += overhead + packet_size; | |
2280 | ||
2281 | if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) { | |
2282 | unsigned int port_index = virt_dev->real_port - 1; | |
2283 | ||
2284 | /* OK, we're manipulating a HS device attached to a | |
2285 | * root port bandwidth domain. Include the number of active TTs | |
2286 | * in the bandwidth used. | |
2287 | */ | |
2288 | bw_used += TT_HS_OVERHEAD * | |
2289 | xhci->rh_bw[port_index].num_active_tts; | |
2290 | } | |
2291 | ||
4bdfe4c3 XR |
2292 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2293 | "Final bandwidth: %u, Limit: %u, Reserved: %u, " | |
2294 | "Available: %u " "percent", | |
c29eea62 SS |
2295 | bw_used, max_bandwidth, bw_reserved, |
2296 | (max_bandwidth - bw_used - bw_reserved) * 100 / | |
2297 | max_bandwidth); | |
2298 | ||
2299 | bw_used += bw_reserved; | |
2300 | if (bw_used > max_bandwidth) { | |
2301 | xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n", | |
2302 | bw_used, max_bandwidth); | |
2303 | return -ENOMEM; | |
2304 | } | |
2305 | ||
2306 | bw_table->bw_used = bw_used; | |
2e27980e SS |
2307 | return 0; |
2308 | } | |
2309 | ||
2310 | static bool xhci_is_async_ep(unsigned int ep_type) | |
2311 | { | |
2312 | return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
2313 | ep_type != ISOC_IN_EP && | |
2314 | ep_type != INT_IN_EP); | |
2315 | } | |
2316 | ||
2b698999 SS |
2317 | static bool xhci_is_sync_in_ep(unsigned int ep_type) |
2318 | { | |
392a07ae | 2319 | return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP); |
2b698999 SS |
2320 | } |
2321 | ||
2322 | static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw) | |
2323 | { | |
2324 | unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK); | |
2325 | ||
2326 | if (ep_bw->ep_interval == 0) | |
2327 | return SS_OVERHEAD_BURST + | |
2328 | (ep_bw->mult * ep_bw->num_packets * | |
2329 | (SS_OVERHEAD + mps)); | |
2330 | return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets * | |
2331 | (SS_OVERHEAD + mps + SS_OVERHEAD_BURST), | |
2332 | 1 << ep_bw->ep_interval); | |
2333 | ||
2334 | } | |
2335 | ||
2e27980e SS |
2336 | void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, |
2337 | struct xhci_bw_info *ep_bw, | |
2338 | struct xhci_interval_bw_table *bw_table, | |
2339 | struct usb_device *udev, | |
2340 | struct xhci_virt_ep *virt_ep, | |
2341 | struct xhci_tt_bw_info *tt_info) | |
2342 | { | |
2343 | struct xhci_interval_bw *interval_bw; | |
2344 | int normalized_interval; | |
2345 | ||
2b698999 | 2346 | if (xhci_is_async_ep(ep_bw->type)) |
2e27980e SS |
2347 | return; |
2348 | ||
0caf6b33 | 2349 | if (udev->speed >= USB_SPEED_SUPER) { |
2b698999 SS |
2350 | if (xhci_is_sync_in_ep(ep_bw->type)) |
2351 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in -= | |
2352 | xhci_get_ss_bw_consumed(ep_bw); | |
2353 | else | |
2354 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out -= | |
2355 | xhci_get_ss_bw_consumed(ep_bw); | |
2356 | return; | |
2357 | } | |
2358 | ||
2359 | /* SuperSpeed endpoints never get added to intervals in the table, so | |
2360 | * this check is only valid for HS/FS/LS devices. | |
2361 | */ | |
2362 | if (list_empty(&virt_ep->bw_endpoint_list)) | |
2363 | return; | |
2e27980e SS |
2364 | /* For LS/FS devices, we need to translate the interval expressed in |
2365 | * microframes to frames. | |
2366 | */ | |
2367 | if (udev->speed == USB_SPEED_HIGH) | |
2368 | normalized_interval = ep_bw->ep_interval; | |
2369 | else | |
2370 | normalized_interval = ep_bw->ep_interval - 3; | |
2371 | ||
2372 | if (normalized_interval == 0) | |
2373 | bw_table->interval0_esit_payload -= ep_bw->max_esit_payload; | |
2374 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2375 | interval_bw->num_packets -= ep_bw->num_packets; | |
2376 | switch (udev->speed) { | |
2377 | case USB_SPEED_LOW: | |
2378 | interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1; | |
2379 | break; | |
2380 | case USB_SPEED_FULL: | |
2381 | interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1; | |
2382 | break; | |
2383 | case USB_SPEED_HIGH: | |
2384 | interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1; | |
2385 | break; | |
2386 | case USB_SPEED_SUPER: | |
0caf6b33 | 2387 | case USB_SPEED_SUPER_PLUS: |
2e27980e SS |
2388 | case USB_SPEED_UNKNOWN: |
2389 | case USB_SPEED_WIRELESS: | |
2390 | /* Should never happen because only LS/FS/HS endpoints will get | |
2391 | * added to the endpoint list. | |
2392 | */ | |
2393 | return; | |
2394 | } | |
2395 | if (tt_info) | |
2396 | tt_info->active_eps -= 1; | |
2397 | list_del_init(&virt_ep->bw_endpoint_list); | |
2398 | } | |
2399 | ||
2400 | static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci, | |
2401 | struct xhci_bw_info *ep_bw, | |
2402 | struct xhci_interval_bw_table *bw_table, | |
2403 | struct usb_device *udev, | |
2404 | struct xhci_virt_ep *virt_ep, | |
2405 | struct xhci_tt_bw_info *tt_info) | |
2406 | { | |
2407 | struct xhci_interval_bw *interval_bw; | |
2408 | struct xhci_virt_ep *smaller_ep; | |
2409 | int normalized_interval; | |
2410 | ||
2411 | if (xhci_is_async_ep(ep_bw->type)) | |
2412 | return; | |
2413 | ||
2b698999 SS |
2414 | if (udev->speed == USB_SPEED_SUPER) { |
2415 | if (xhci_is_sync_in_ep(ep_bw->type)) | |
2416 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in += | |
2417 | xhci_get_ss_bw_consumed(ep_bw); | |
2418 | else | |
2419 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out += | |
2420 | xhci_get_ss_bw_consumed(ep_bw); | |
2421 | return; | |
2422 | } | |
2423 | ||
2e27980e SS |
2424 | /* For LS/FS devices, we need to translate the interval expressed in |
2425 | * microframes to frames. | |
2426 | */ | |
2427 | if (udev->speed == USB_SPEED_HIGH) | |
2428 | normalized_interval = ep_bw->ep_interval; | |
2429 | else | |
2430 | normalized_interval = ep_bw->ep_interval - 3; | |
2431 | ||
2432 | if (normalized_interval == 0) | |
2433 | bw_table->interval0_esit_payload += ep_bw->max_esit_payload; | |
2434 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2435 | interval_bw->num_packets += ep_bw->num_packets; | |
2436 | switch (udev->speed) { | |
2437 | case USB_SPEED_LOW: | |
2438 | interval_bw->overhead[LS_OVERHEAD_TYPE] += 1; | |
2439 | break; | |
2440 | case USB_SPEED_FULL: | |
2441 | interval_bw->overhead[FS_OVERHEAD_TYPE] += 1; | |
2442 | break; | |
2443 | case USB_SPEED_HIGH: | |
2444 | interval_bw->overhead[HS_OVERHEAD_TYPE] += 1; | |
2445 | break; | |
2446 | case USB_SPEED_SUPER: | |
0caf6b33 | 2447 | case USB_SPEED_SUPER_PLUS: |
2e27980e SS |
2448 | case USB_SPEED_UNKNOWN: |
2449 | case USB_SPEED_WIRELESS: | |
2450 | /* Should never happen because only LS/FS/HS endpoints will get | |
2451 | * added to the endpoint list. | |
2452 | */ | |
2453 | return; | |
2454 | } | |
2455 | ||
2456 | if (tt_info) | |
2457 | tt_info->active_eps += 1; | |
2458 | /* Insert the endpoint into the list, largest max packet size first. */ | |
2459 | list_for_each_entry(smaller_ep, &interval_bw->endpoints, | |
2460 | bw_endpoint_list) { | |
2461 | if (ep_bw->max_packet_size >= | |
2462 | smaller_ep->bw_info.max_packet_size) { | |
2463 | /* Add the new ep before the smaller endpoint */ | |
2464 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2465 | &smaller_ep->bw_endpoint_list); | |
2466 | return; | |
2467 | } | |
2468 | } | |
2469 | /* Add the new endpoint at the end of the list. */ | |
2470 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2471 | &interval_bw->endpoints); | |
2472 | } | |
2473 | ||
2474 | void xhci_update_tt_active_eps(struct xhci_hcd *xhci, | |
2475 | struct xhci_virt_device *virt_dev, | |
2476 | int old_active_eps) | |
2477 | { | |
2478 | struct xhci_root_port_bw_info *rh_bw_info; | |
2479 | if (!virt_dev->tt_info) | |
2480 | return; | |
2481 | ||
2482 | rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1]; | |
2483 | if (old_active_eps == 0 && | |
2484 | virt_dev->tt_info->active_eps != 0) { | |
2485 | rh_bw_info->num_active_tts += 1; | |
c29eea62 | 2486 | rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD; |
2e27980e SS |
2487 | } else if (old_active_eps != 0 && |
2488 | virt_dev->tt_info->active_eps == 0) { | |
2489 | rh_bw_info->num_active_tts -= 1; | |
c29eea62 | 2490 | rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD; |
2e27980e SS |
2491 | } |
2492 | } | |
2493 | ||
2494 | static int xhci_reserve_bandwidth(struct xhci_hcd *xhci, | |
2495 | struct xhci_virt_device *virt_dev, | |
2496 | struct xhci_container_ctx *in_ctx) | |
2497 | { | |
2498 | struct xhci_bw_info ep_bw_info[31]; | |
2499 | int i; | |
2500 | struct xhci_input_control_ctx *ctrl_ctx; | |
2501 | int old_active_eps = 0; | |
2502 | ||
2e27980e SS |
2503 | if (virt_dev->tt_info) |
2504 | old_active_eps = virt_dev->tt_info->active_eps; | |
2505 | ||
4daf9df5 | 2506 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
2507 | if (!ctrl_ctx) { |
2508 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2509 | __func__); | |
2510 | return -ENOMEM; | |
2511 | } | |
2e27980e SS |
2512 | |
2513 | for (i = 0; i < 31; i++) { | |
2514 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2515 | continue; | |
2516 | ||
2517 | /* Make a copy of the BW info in case we need to revert this */ | |
2518 | memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info, | |
2519 | sizeof(ep_bw_info[i])); | |
2520 | /* Drop the endpoint from the interval table if the endpoint is | |
2521 | * being dropped or changed. | |
2522 | */ | |
2523 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2524 | xhci_drop_ep_from_interval_table(xhci, | |
2525 | &virt_dev->eps[i].bw_info, | |
2526 | virt_dev->bw_table, | |
2527 | virt_dev->udev, | |
2528 | &virt_dev->eps[i], | |
2529 | virt_dev->tt_info); | |
2530 | } | |
2531 | /* Overwrite the information stored in the endpoints' bw_info */ | |
2532 | xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev); | |
2533 | for (i = 0; i < 31; i++) { | |
2534 | /* Add any changed or added endpoints to the interval table */ | |
2535 | if (EP_IS_ADDED(ctrl_ctx, i)) | |
2536 | xhci_add_ep_to_interval_table(xhci, | |
2537 | &virt_dev->eps[i].bw_info, | |
2538 | virt_dev->bw_table, | |
2539 | virt_dev->udev, | |
2540 | &virt_dev->eps[i], | |
2541 | virt_dev->tt_info); | |
2542 | } | |
2543 | ||
2544 | if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) { | |
2545 | /* Ok, this fits in the bandwidth we have. | |
2546 | * Update the number of active TTs. | |
2547 | */ | |
2548 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
2549 | return 0; | |
2550 | } | |
2551 | ||
2552 | /* We don't have enough bandwidth for this, revert the stored info. */ | |
2553 | for (i = 0; i < 31; i++) { | |
2554 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2555 | continue; | |
2556 | ||
2557 | /* Drop the new copies of any added or changed endpoints from | |
2558 | * the interval table. | |
2559 | */ | |
2560 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
2561 | xhci_drop_ep_from_interval_table(xhci, | |
2562 | &virt_dev->eps[i].bw_info, | |
2563 | virt_dev->bw_table, | |
2564 | virt_dev->udev, | |
2565 | &virt_dev->eps[i], | |
2566 | virt_dev->tt_info); | |
2567 | } | |
2568 | /* Revert the endpoint back to its old information */ | |
2569 | memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i], | |
2570 | sizeof(ep_bw_info[i])); | |
2571 | /* Add any changed or dropped endpoints back into the table */ | |
2572 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2573 | xhci_add_ep_to_interval_table(xhci, | |
2574 | &virt_dev->eps[i].bw_info, | |
2575 | virt_dev->bw_table, | |
2576 | virt_dev->udev, | |
2577 | &virt_dev->eps[i], | |
2578 | virt_dev->tt_info); | |
2579 | } | |
2580 | return -ENOMEM; | |
2581 | } | |
2582 | ||
2583 | ||
f2217e8e SS |
2584 | /* Issue a configure endpoint command or evaluate context command |
2585 | * and wait for it to finish. | |
2586 | */ | |
2587 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |
913a8a34 SS |
2588 | struct usb_device *udev, |
2589 | struct xhci_command *command, | |
2590 | bool ctx_change, bool must_succeed) | |
f2217e8e SS |
2591 | { |
2592 | int ret; | |
f2217e8e | 2593 | unsigned long flags; |
92f8e767 | 2594 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 2595 | struct xhci_virt_device *virt_dev; |
ddba5cd0 MN |
2596 | |
2597 | if (!command) | |
2598 | return -EINVAL; | |
f2217e8e SS |
2599 | |
2600 | spin_lock_irqsave(&xhci->lock, flags); | |
913a8a34 | 2601 | virt_dev = xhci->devs[udev->slot_id]; |
750645f8 | 2602 | |
4daf9df5 | 2603 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 | 2604 | if (!ctrl_ctx) { |
1f21569c | 2605 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
2606 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
2607 | __func__); | |
2608 | return -ENOMEM; | |
2609 | } | |
2cf95c18 | 2610 | |
750645f8 | 2611 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && |
92f8e767 | 2612 | xhci_reserve_host_resources(xhci, ctrl_ctx)) { |
750645f8 SS |
2613 | spin_unlock_irqrestore(&xhci->lock, flags); |
2614 | xhci_warn(xhci, "Not enough host resources, " | |
2615 | "active endpoint contexts = %u\n", | |
2616 | xhci->num_active_eps); | |
2617 | return -ENOMEM; | |
2618 | } | |
2e27980e | 2619 | if ((xhci->quirks & XHCI_SW_BW_CHECKING) && |
ddba5cd0 | 2620 | xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) { |
2e27980e | 2621 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2622 | xhci_free_host_resources(xhci, ctrl_ctx); |
2e27980e SS |
2623 | spin_unlock_irqrestore(&xhci->lock, flags); |
2624 | xhci_warn(xhci, "Not enough bandwidth\n"); | |
2625 | return -ENOMEM; | |
2626 | } | |
750645f8 | 2627 | |
f2217e8e | 2628 | if (!ctx_change) |
ddba5cd0 MN |
2629 | ret = xhci_queue_configure_endpoint(xhci, command, |
2630 | command->in_ctx->dma, | |
913a8a34 | 2631 | udev->slot_id, must_succeed); |
f2217e8e | 2632 | else |
ddba5cd0 MN |
2633 | ret = xhci_queue_evaluate_context(xhci, command, |
2634 | command->in_ctx->dma, | |
4b266541 | 2635 | udev->slot_id, must_succeed); |
f2217e8e | 2636 | if (ret < 0) { |
2cf95c18 | 2637 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2638 | xhci_free_host_resources(xhci, ctrl_ctx); |
f2217e8e | 2639 | spin_unlock_irqrestore(&xhci->lock, flags); |
3a7fa5be XR |
2640 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
2641 | "FIXME allocate a new ring segment"); | |
f2217e8e SS |
2642 | return -ENOMEM; |
2643 | } | |
2644 | xhci_ring_cmd_db(xhci); | |
2645 | spin_unlock_irqrestore(&xhci->lock, flags); | |
2646 | ||
2647 | /* Wait for the configure endpoint command to complete */ | |
c311e391 | 2648 | wait_for_completion(command->completion); |
f2217e8e SS |
2649 | |
2650 | if (!ctx_change) | |
ddba5cd0 MN |
2651 | ret = xhci_configure_endpoint_result(xhci, udev, |
2652 | &command->status); | |
2cf95c18 | 2653 | else |
ddba5cd0 MN |
2654 | ret = xhci_evaluate_context_result(xhci, udev, |
2655 | &command->status); | |
2cf95c18 SS |
2656 | |
2657 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
2658 | spin_lock_irqsave(&xhci->lock, flags); | |
2659 | /* If the command failed, remove the reserved resources. | |
2660 | * Otherwise, clean up the estimate to include dropped eps. | |
2661 | */ | |
2662 | if (ret) | |
92f8e767 | 2663 | xhci_free_host_resources(xhci, ctrl_ctx); |
2cf95c18 | 2664 | else |
92f8e767 | 2665 | xhci_finish_resource_reservation(xhci, ctrl_ctx); |
2cf95c18 SS |
2666 | spin_unlock_irqrestore(&xhci->lock, flags); |
2667 | } | |
2668 | return ret; | |
f2217e8e SS |
2669 | } |
2670 | ||
df613834 HG |
2671 | static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci, |
2672 | struct xhci_virt_device *vdev, int i) | |
2673 | { | |
2674 | struct xhci_virt_ep *ep = &vdev->eps[i]; | |
2675 | ||
2676 | if (ep->ep_state & EP_HAS_STREAMS) { | |
2677 | xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n", | |
2678 | xhci_get_endpoint_address(i)); | |
2679 | xhci_free_stream_info(xhci, ep->stream_info); | |
2680 | ep->stream_info = NULL; | |
2681 | ep->ep_state &= ~EP_HAS_STREAMS; | |
2682 | } | |
2683 | } | |
2684 | ||
f88ba78d SS |
2685 | /* Called after one or more calls to xhci_add_endpoint() or |
2686 | * xhci_drop_endpoint(). If this call fails, the USB core is expected | |
2687 | * to call xhci_reset_bandwidth(). | |
2688 | * | |
2689 | * Since we are in the middle of changing either configuration or | |
2690 | * installing a new alt setting, the USB core won't allow URBs to be | |
2691 | * enqueued for any endpoint on the old config or interface. Nothing | |
2692 | * else should be touching the xhci->devs[slot_id] structure, so we | |
2693 | * don't need to take the xhci->lock for manipulating that. | |
2694 | */ | |
f94e0186 SS |
2695 | int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) |
2696 | { | |
2697 | int i; | |
2698 | int ret = 0; | |
f94e0186 SS |
2699 | struct xhci_hcd *xhci; |
2700 | struct xhci_virt_device *virt_dev; | |
d115b048 JY |
2701 | struct xhci_input_control_ctx *ctrl_ctx; |
2702 | struct xhci_slot_ctx *slot_ctx; | |
ddba5cd0 | 2703 | struct xhci_command *command; |
f94e0186 | 2704 | |
64927730 | 2705 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2706 | if (ret <= 0) |
2707 | return ret; | |
2708 | xhci = hcd_to_xhci(hcd); | |
98d74f9c MN |
2709 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
2710 | (xhci->xhc_state & XHCI_STATE_REMOVING)) | |
fe6c6c13 | 2711 | return -ENODEV; |
f94e0186 | 2712 | |
700e2052 | 2713 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2714 | virt_dev = xhci->devs[udev->slot_id]; |
2715 | ||
ddba5cd0 MN |
2716 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); |
2717 | if (!command) | |
2718 | return -ENOMEM; | |
2719 | ||
2720 | command->in_ctx = virt_dev->in_ctx; | |
2721 | ||
f94e0186 | 2722 | /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */ |
4daf9df5 | 2723 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
2724 | if (!ctrl_ctx) { |
2725 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2726 | __func__); | |
ddba5cd0 MN |
2727 | ret = -ENOMEM; |
2728 | goto command_cleanup; | |
92f8e767 | 2729 | } |
28ccd296 ME |
2730 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
2731 | ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG); | |
2732 | ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG)); | |
2dc37539 SS |
2733 | |
2734 | /* Don't issue the command if there's no endpoints to update. */ | |
2735 | if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) && | |
ddba5cd0 MN |
2736 | ctrl_ctx->drop_flags == 0) { |
2737 | ret = 0; | |
2738 | goto command_cleanup; | |
2739 | } | |
d6759133 | 2740 | /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */ |
d115b048 | 2741 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
d6759133 JW |
2742 | for (i = 31; i >= 1; i--) { |
2743 | __le32 le32 = cpu_to_le32(BIT(i)); | |
2744 | ||
2745 | if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32)) | |
2746 | || (ctrl_ctx->add_flags & le32) || i == 1) { | |
2747 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
2748 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i)); | |
2749 | break; | |
2750 | } | |
2751 | } | |
2752 | xhci_dbg(xhci, "New Input Control Context:\n"); | |
d115b048 | 2753 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, |
28ccd296 | 2754 | LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); |
f94e0186 | 2755 | |
ddba5cd0 | 2756 | ret = xhci_configure_endpoint(xhci, udev, command, |
913a8a34 | 2757 | false, false); |
ddba5cd0 | 2758 | if (ret) |
f94e0186 | 2759 | /* Callee should call reset_bandwidth() */ |
ddba5cd0 | 2760 | goto command_cleanup; |
f94e0186 SS |
2761 | |
2762 | xhci_dbg(xhci, "Output context after successful config ep cmd:\n"); | |
d115b048 | 2763 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, |
28ccd296 | 2764 | LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); |
f94e0186 | 2765 | |
834cb0fc | 2766 | /* Free any rings that were dropped, but not changed. */ |
98871e94 | 2767 | for (i = 1; i < 31; i++) { |
4819fef5 | 2768 | if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) && |
df613834 | 2769 | !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) { |
834cb0fc | 2770 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); |
df613834 HG |
2771 | xhci_check_bw_drop_ep_streams(xhci, virt_dev, i); |
2772 | } | |
834cb0fc | 2773 | } |
d115b048 | 2774 | xhci_zero_in_ctx(xhci, virt_dev); |
834cb0fc SS |
2775 | /* |
2776 | * Install any rings for completely new endpoints or changed endpoints, | |
2777 | * and free or cache any old rings from changed endpoints. | |
2778 | */ | |
98871e94 | 2779 | for (i = 1; i < 31; i++) { |
74f9fe21 SS |
2780 | if (!virt_dev->eps[i].new_ring) |
2781 | continue; | |
2782 | /* Only cache or free the old ring if it exists. | |
2783 | * It may not if this is the first add of an endpoint. | |
2784 | */ | |
2785 | if (virt_dev->eps[i].ring) { | |
412566bd | 2786 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); |
f94e0186 | 2787 | } |
df613834 | 2788 | xhci_check_bw_drop_ep_streams(xhci, virt_dev, i); |
74f9fe21 SS |
2789 | virt_dev->eps[i].ring = virt_dev->eps[i].new_ring; |
2790 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 | 2791 | } |
ddba5cd0 MN |
2792 | command_cleanup: |
2793 | kfree(command->completion); | |
2794 | kfree(command); | |
f94e0186 | 2795 | |
f94e0186 SS |
2796 | return ret; |
2797 | } | |
2798 | ||
2799 | void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) | |
2800 | { | |
f94e0186 SS |
2801 | struct xhci_hcd *xhci; |
2802 | struct xhci_virt_device *virt_dev; | |
2803 | int i, ret; | |
2804 | ||
64927730 | 2805 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2806 | if (ret <= 0) |
2807 | return; | |
2808 | xhci = hcd_to_xhci(hcd); | |
2809 | ||
700e2052 | 2810 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2811 | virt_dev = xhci->devs[udev->slot_id]; |
2812 | /* Free any rings allocated for added endpoints */ | |
98871e94 | 2813 | for (i = 0; i < 31; i++) { |
63a0d9ab SS |
2814 | if (virt_dev->eps[i].new_ring) { |
2815 | xhci_ring_free(xhci, virt_dev->eps[i].new_ring); | |
2816 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 SS |
2817 | } |
2818 | } | |
d115b048 | 2819 | xhci_zero_in_ctx(xhci, virt_dev); |
f94e0186 SS |
2820 | } |
2821 | ||
5270b951 | 2822 | static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci, |
913a8a34 SS |
2823 | struct xhci_container_ctx *in_ctx, |
2824 | struct xhci_container_ctx *out_ctx, | |
92f8e767 | 2825 | struct xhci_input_control_ctx *ctrl_ctx, |
913a8a34 | 2826 | u32 add_flags, u32 drop_flags) |
5270b951 | 2827 | { |
28ccd296 ME |
2828 | ctrl_ctx->add_flags = cpu_to_le32(add_flags); |
2829 | ctrl_ctx->drop_flags = cpu_to_le32(drop_flags); | |
913a8a34 | 2830 | xhci_slot_copy(xhci, in_ctx, out_ctx); |
28ccd296 | 2831 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
5270b951 | 2832 | |
913a8a34 SS |
2833 | xhci_dbg(xhci, "Input Context:\n"); |
2834 | xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags)); | |
5270b951 SS |
2835 | } |
2836 | ||
8212a49d | 2837 | static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, |
ac9d8fe7 SS |
2838 | unsigned int slot_id, unsigned int ep_index, |
2839 | struct xhci_dequeue_state *deq_state) | |
2840 | { | |
92f8e767 | 2841 | struct xhci_input_control_ctx *ctrl_ctx; |
ac9d8fe7 | 2842 | struct xhci_container_ctx *in_ctx; |
ac9d8fe7 SS |
2843 | struct xhci_ep_ctx *ep_ctx; |
2844 | u32 added_ctxs; | |
2845 | dma_addr_t addr; | |
2846 | ||
92f8e767 | 2847 | in_ctx = xhci->devs[slot_id]->in_ctx; |
4daf9df5 | 2848 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
2849 | if (!ctrl_ctx) { |
2850 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2851 | __func__); | |
2852 | return; | |
2853 | } | |
2854 | ||
913a8a34 SS |
2855 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
2856 | xhci->devs[slot_id]->out_ctx, ep_index); | |
ac9d8fe7 SS |
2857 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); |
2858 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
2859 | deq_state->new_deq_ptr); | |
2860 | if (addr == 0) { | |
2861 | xhci_warn(xhci, "WARN Cannot submit config ep after " | |
2862 | "reset ep command\n"); | |
2863 | xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n", | |
2864 | deq_state->new_deq_seg, | |
2865 | deq_state->new_deq_ptr); | |
2866 | return; | |
2867 | } | |
28ccd296 | 2868 | ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state); |
ac9d8fe7 | 2869 | |
ac9d8fe7 | 2870 | added_ctxs = xhci_get_endpoint_flag_from_index(ep_index); |
913a8a34 | 2871 | xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx, |
92f8e767 SS |
2872 | xhci->devs[slot_id]->out_ctx, ctrl_ctx, |
2873 | added_ctxs, added_ctxs); | |
ac9d8fe7 SS |
2874 | } |
2875 | ||
82d1009f | 2876 | void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, |
d97b4f8d | 2877 | unsigned int ep_index, struct xhci_td *td) |
82d1009f SS |
2878 | { |
2879 | struct xhci_dequeue_state deq_state; | |
63a0d9ab | 2880 | struct xhci_virt_ep *ep; |
d97b4f8d | 2881 | struct usb_device *udev = td->urb->dev; |
82d1009f | 2882 | |
a0254324 XR |
2883 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2884 | "Cleaning up stalled endpoint ring"); | |
63a0d9ab | 2885 | ep = &xhci->devs[udev->slot_id]->eps[ep_index]; |
82d1009f SS |
2886 | /* We need to move the HW's dequeue pointer past this TD, |
2887 | * or it will attempt to resend it on the next doorbell ring. | |
2888 | */ | |
2889 | xhci_find_new_dequeue_state(xhci, udev->slot_id, | |
d97b4f8d | 2890 | ep_index, ep->stopped_stream, td, &deq_state); |
82d1009f | 2891 | |
365038d8 MN |
2892 | if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg) |
2893 | return; | |
2894 | ||
ac9d8fe7 SS |
2895 | /* HW with the reset endpoint quirk will use the saved dequeue state to |
2896 | * issue a configure endpoint command later. | |
2897 | */ | |
2898 | if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) { | |
a0254324 XR |
2899 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2900 | "Queueing new dequeue state"); | |
1e3452e3 | 2901 | xhci_queue_new_dequeue_state(xhci, udev->slot_id, |
e9df17eb | 2902 | ep_index, ep->stopped_stream, &deq_state); |
ac9d8fe7 SS |
2903 | } else { |
2904 | /* Better hope no one uses the input context between now and the | |
2905 | * reset endpoint completion! | |
e9df17eb SS |
2906 | * XXX: No idea how this hardware will react when stream rings |
2907 | * are enabled. | |
ac9d8fe7 | 2908 | */ |
4bdfe4c3 XR |
2909 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2910 | "Setting up input context for " | |
2911 | "configure endpoint command"); | |
ac9d8fe7 SS |
2912 | xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id, |
2913 | ep_index, &deq_state); | |
2914 | } | |
82d1009f SS |
2915 | } |
2916 | ||
d0167ad2 | 2917 | /* Called when clearing halted device. The core should have sent the control |
8e71a322 | 2918 | * message to clear the device halt condition. The host side of the halt should |
d0167ad2 MN |
2919 | * already be cleared with a reset endpoint command issued when the STALL tx |
2920 | * event was received. | |
2921 | * | |
2922 | * Context: in_interrupt | |
a1587d97 | 2923 | */ |
8e71a322 | 2924 | |
a1587d97 SS |
2925 | void xhci_endpoint_reset(struct usb_hcd *hcd, |
2926 | struct usb_host_endpoint *ep) | |
2927 | { | |
2928 | struct xhci_hcd *xhci; | |
a1587d97 SS |
2929 | |
2930 | xhci = hcd_to_xhci(hcd); | |
ddba5cd0 | 2931 | |
c92bcfa7 | 2932 | /* |
d0167ad2 | 2933 | * We might need to implement the config ep cmd in xhci 4.8.1 note: |
8e71a322 MN |
2934 | * The Reset Endpoint Command may only be issued to endpoints in the |
2935 | * Halted state. If software wishes reset the Data Toggle or Sequence | |
2936 | * Number of an endpoint that isn't in the Halted state, then software | |
2937 | * may issue a Configure Endpoint Command with the Drop and Add bits set | |
2938 | * for the target endpoint. that is in the Stopped state. | |
c92bcfa7 | 2939 | */ |
a1587d97 | 2940 | |
d0167ad2 MN |
2941 | /* For now just print debug to follow the situation */ |
2942 | xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n", | |
2943 | ep->desc.bEndpointAddress); | |
a1587d97 SS |
2944 | } |
2945 | ||
8df75f42 SS |
2946 | static int xhci_check_streams_endpoint(struct xhci_hcd *xhci, |
2947 | struct usb_device *udev, struct usb_host_endpoint *ep, | |
2948 | unsigned int slot_id) | |
2949 | { | |
2950 | int ret; | |
2951 | unsigned int ep_index; | |
2952 | unsigned int ep_state; | |
2953 | ||
2954 | if (!ep) | |
2955 | return -EINVAL; | |
64927730 | 2956 | ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__); |
8df75f42 SS |
2957 | if (ret <= 0) |
2958 | return -EINVAL; | |
a3901538 | 2959 | if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) { |
8df75f42 SS |
2960 | xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion" |
2961 | " descriptor for ep 0x%x does not support streams\n", | |
2962 | ep->desc.bEndpointAddress); | |
2963 | return -EINVAL; | |
2964 | } | |
2965 | ||
2966 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
2967 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
2968 | if (ep_state & EP_HAS_STREAMS || | |
2969 | ep_state & EP_GETTING_STREAMS) { | |
2970 | xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x " | |
2971 | "already has streams set up.\n", | |
2972 | ep->desc.bEndpointAddress); | |
2973 | xhci_warn(xhci, "Send email to xHCI maintainer and ask for " | |
2974 | "dynamic stream context array reallocation.\n"); | |
2975 | return -EINVAL; | |
2976 | } | |
2977 | if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) { | |
2978 | xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk " | |
2979 | "endpoint 0x%x; URBs are pending.\n", | |
2980 | ep->desc.bEndpointAddress); | |
2981 | return -EINVAL; | |
2982 | } | |
2983 | return 0; | |
2984 | } | |
2985 | ||
2986 | static void xhci_calculate_streams_entries(struct xhci_hcd *xhci, | |
2987 | unsigned int *num_streams, unsigned int *num_stream_ctxs) | |
2988 | { | |
2989 | unsigned int max_streams; | |
2990 | ||
2991 | /* The stream context array size must be a power of two */ | |
2992 | *num_stream_ctxs = roundup_pow_of_two(*num_streams); | |
2993 | /* | |
2994 | * Find out how many primary stream array entries the host controller | |
2995 | * supports. Later we may use secondary stream arrays (similar to 2nd | |
2996 | * level page entries), but that's an optional feature for xHCI host | |
2997 | * controllers. xHCs must support at least 4 stream IDs. | |
2998 | */ | |
2999 | max_streams = HCC_MAX_PSA(xhci->hcc_params); | |
3000 | if (*num_stream_ctxs > max_streams) { | |
3001 | xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n", | |
3002 | max_streams); | |
3003 | *num_stream_ctxs = max_streams; | |
3004 | *num_streams = max_streams; | |
3005 | } | |
3006 | } | |
3007 | ||
3008 | /* Returns an error code if one of the endpoint already has streams. | |
3009 | * This does not change any data structures, it only checks and gathers | |
3010 | * information. | |
3011 | */ | |
3012 | static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci, | |
3013 | struct usb_device *udev, | |
3014 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3015 | unsigned int *num_streams, u32 *changed_ep_bitmask) | |
3016 | { | |
8df75f42 SS |
3017 | unsigned int max_streams; |
3018 | unsigned int endpoint_flag; | |
3019 | int i; | |
3020 | int ret; | |
3021 | ||
3022 | for (i = 0; i < num_eps; i++) { | |
3023 | ret = xhci_check_streams_endpoint(xhci, udev, | |
3024 | eps[i], udev->slot_id); | |
3025 | if (ret < 0) | |
3026 | return ret; | |
3027 | ||
18b7ede5 | 3028 | max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp); |
8df75f42 SS |
3029 | if (max_streams < (*num_streams - 1)) { |
3030 | xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n", | |
3031 | eps[i]->desc.bEndpointAddress, | |
3032 | max_streams); | |
3033 | *num_streams = max_streams+1; | |
3034 | } | |
3035 | ||
3036 | endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc); | |
3037 | if (*changed_ep_bitmask & endpoint_flag) | |
3038 | return -EINVAL; | |
3039 | *changed_ep_bitmask |= endpoint_flag; | |
3040 | } | |
3041 | return 0; | |
3042 | } | |
3043 | ||
3044 | static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci, | |
3045 | struct usb_device *udev, | |
3046 | struct usb_host_endpoint **eps, unsigned int num_eps) | |
3047 | { | |
3048 | u32 changed_ep_bitmask = 0; | |
3049 | unsigned int slot_id; | |
3050 | unsigned int ep_index; | |
3051 | unsigned int ep_state; | |
3052 | int i; | |
3053 | ||
3054 | slot_id = udev->slot_id; | |
3055 | if (!xhci->devs[slot_id]) | |
3056 | return 0; | |
3057 | ||
3058 | for (i = 0; i < num_eps; i++) { | |
3059 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3060 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
3061 | /* Are streams already being freed for the endpoint? */ | |
3062 | if (ep_state & EP_GETTING_NO_STREAMS) { | |
3063 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3064 | "endpoint 0x%x, " |
3065 | "streams are being disabled already\n", | |
8df75f42 SS |
3066 | eps[i]->desc.bEndpointAddress); |
3067 | return 0; | |
3068 | } | |
3069 | /* Are there actually any streams to free? */ | |
3070 | if (!(ep_state & EP_HAS_STREAMS) && | |
3071 | !(ep_state & EP_GETTING_STREAMS)) { | |
3072 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3073 | "endpoint 0x%x, " |
3074 | "streams are already disabled!\n", | |
8df75f42 SS |
3075 | eps[i]->desc.bEndpointAddress); |
3076 | xhci_warn(xhci, "WARN xhci_free_streams() called " | |
3077 | "with non-streams endpoint\n"); | |
3078 | return 0; | |
3079 | } | |
3080 | changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc); | |
3081 | } | |
3082 | return changed_ep_bitmask; | |
3083 | } | |
3084 | ||
3085 | /* | |
c2a298d9 | 3086 | * The USB device drivers use this function (through the HCD interface in USB |
8df75f42 SS |
3087 | * core) to prepare a set of bulk endpoints to use streams. Streams are used to |
3088 | * coordinate mass storage command queueing across multiple endpoints (basically | |
3089 | * a stream ID == a task ID). | |
3090 | * | |
3091 | * Setting up streams involves allocating the same size stream context array | |
3092 | * for each endpoint and issuing a configure endpoint command for all endpoints. | |
3093 | * | |
3094 | * Don't allow the call to succeed if one endpoint only supports one stream | |
3095 | * (which means it doesn't support streams at all). | |
3096 | * | |
3097 | * Drivers may get less stream IDs than they asked for, if the host controller | |
3098 | * hardware or endpoints claim they can't support the number of requested | |
3099 | * stream IDs. | |
3100 | */ | |
3101 | int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, | |
3102 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3103 | unsigned int num_streams, gfp_t mem_flags) | |
3104 | { | |
3105 | int i, ret; | |
3106 | struct xhci_hcd *xhci; | |
3107 | struct xhci_virt_device *vdev; | |
3108 | struct xhci_command *config_cmd; | |
92f8e767 | 3109 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3110 | unsigned int ep_index; |
3111 | unsigned int num_stream_ctxs; | |
f9c589e1 | 3112 | unsigned int max_packet; |
8df75f42 SS |
3113 | unsigned long flags; |
3114 | u32 changed_ep_bitmask = 0; | |
3115 | ||
3116 | if (!eps) | |
3117 | return -EINVAL; | |
3118 | ||
3119 | /* Add one to the number of streams requested to account for | |
3120 | * stream 0 that is reserved for xHCI usage. | |
3121 | */ | |
3122 | num_streams += 1; | |
3123 | xhci = hcd_to_xhci(hcd); | |
3124 | xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n", | |
3125 | num_streams); | |
3126 | ||
f7920884 | 3127 | /* MaxPSASize value 0 (2 streams) means streams are not supported */ |
8f873c1f HG |
3128 | if ((xhci->quirks & XHCI_BROKEN_STREAMS) || |
3129 | HCC_MAX_PSA(xhci->hcc_params) < 4) { | |
f7920884 HG |
3130 | xhci_dbg(xhci, "xHCI controller does not support streams.\n"); |
3131 | return -ENOSYS; | |
3132 | } | |
3133 | ||
8df75f42 SS |
3134 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); |
3135 | if (!config_cmd) { | |
3136 | xhci_dbg(xhci, "Could not allocate xHCI command structure.\n"); | |
3137 | return -ENOMEM; | |
3138 | } | |
4daf9df5 | 3139 | ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx); |
92f8e767 SS |
3140 | if (!ctrl_ctx) { |
3141 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3142 | __func__); | |
3143 | xhci_free_command(xhci, config_cmd); | |
3144 | return -ENOMEM; | |
3145 | } | |
8df75f42 SS |
3146 | |
3147 | /* Check to make sure all endpoints are not already configured for | |
3148 | * streams. While we're at it, find the maximum number of streams that | |
3149 | * all the endpoints will support and check for duplicate endpoints. | |
3150 | */ | |
3151 | spin_lock_irqsave(&xhci->lock, flags); | |
3152 | ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps, | |
3153 | num_eps, &num_streams, &changed_ep_bitmask); | |
3154 | if (ret < 0) { | |
3155 | xhci_free_command(xhci, config_cmd); | |
3156 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3157 | return ret; | |
3158 | } | |
3159 | if (num_streams <= 1) { | |
3160 | xhci_warn(xhci, "WARN: endpoints can't handle " | |
3161 | "more than one stream.\n"); | |
3162 | xhci_free_command(xhci, config_cmd); | |
3163 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3164 | return -EINVAL; | |
3165 | } | |
3166 | vdev = xhci->devs[udev->slot_id]; | |
25985edc | 3167 | /* Mark each endpoint as being in transition, so |
8df75f42 SS |
3168 | * xhci_urb_enqueue() will reject all URBs. |
3169 | */ | |
3170 | for (i = 0; i < num_eps; i++) { | |
3171 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3172 | vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS; | |
3173 | } | |
3174 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3175 | ||
3176 | /* Setup internal data structures and allocate HW data structures for | |
3177 | * streams (but don't install the HW structures in the input context | |
3178 | * until we're sure all memory allocation succeeded). | |
3179 | */ | |
3180 | xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs); | |
3181 | xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n", | |
3182 | num_stream_ctxs, num_streams); | |
3183 | ||
3184 | for (i = 0; i < num_eps; i++) { | |
3185 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
734d3ddd | 3186 | max_packet = usb_endpoint_maxp(&eps[i]->desc); |
8df75f42 SS |
3187 | vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci, |
3188 | num_stream_ctxs, | |
f9c589e1 MN |
3189 | num_streams, |
3190 | max_packet, mem_flags); | |
8df75f42 SS |
3191 | if (!vdev->eps[ep_index].stream_info) |
3192 | goto cleanup; | |
3193 | /* Set maxPstreams in endpoint context and update deq ptr to | |
3194 | * point to stream context array. FIXME | |
3195 | */ | |
3196 | } | |
3197 | ||
3198 | /* Set up the input context for a configure endpoint command. */ | |
3199 | for (i = 0; i < num_eps; i++) { | |
3200 | struct xhci_ep_ctx *ep_ctx; | |
3201 | ||
3202 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3203 | ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index); | |
3204 | ||
3205 | xhci_endpoint_copy(xhci, config_cmd->in_ctx, | |
3206 | vdev->out_ctx, ep_index); | |
3207 | xhci_setup_streams_ep_input_ctx(xhci, ep_ctx, | |
3208 | vdev->eps[ep_index].stream_info); | |
3209 | } | |
3210 | /* Tell the HW to drop its old copy of the endpoint context info | |
3211 | * and add the updated copy from the input context. | |
3212 | */ | |
3213 | xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx, | |
92f8e767 SS |
3214 | vdev->out_ctx, ctrl_ctx, |
3215 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3216 | |
3217 | /* Issue and wait for the configure endpoint command */ | |
3218 | ret = xhci_configure_endpoint(xhci, udev, config_cmd, | |
3219 | false, false); | |
3220 | ||
3221 | /* xHC rejected the configure endpoint command for some reason, so we | |
3222 | * leave the old ring intact and free our internal streams data | |
3223 | * structure. | |
3224 | */ | |
3225 | if (ret < 0) | |
3226 | goto cleanup; | |
3227 | ||
3228 | spin_lock_irqsave(&xhci->lock, flags); | |
3229 | for (i = 0; i < num_eps; i++) { | |
3230 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3231 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3232 | xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n", | |
3233 | udev->slot_id, ep_index); | |
3234 | vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS; | |
3235 | } | |
3236 | xhci_free_command(xhci, config_cmd); | |
3237 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3238 | ||
3239 | /* Subtract 1 for stream 0, which drivers can't use */ | |
3240 | return num_streams - 1; | |
3241 | ||
3242 | cleanup: | |
3243 | /* If it didn't work, free the streams! */ | |
3244 | for (i = 0; i < num_eps; i++) { | |
3245 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3246 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3247 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3248 | /* FIXME Unset maxPstreams in endpoint context and |
3249 | * update deq ptr to point to normal string ring. | |
3250 | */ | |
3251 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3252 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3253 | xhci_endpoint_zero(xhci, vdev, eps[i]); | |
3254 | } | |
3255 | xhci_free_command(xhci, config_cmd); | |
3256 | return -ENOMEM; | |
3257 | } | |
3258 | ||
3259 | /* Transition the endpoint from using streams to being a "normal" endpoint | |
3260 | * without streams. | |
3261 | * | |
3262 | * Modify the endpoint context state, submit a configure endpoint command, | |
3263 | * and free all endpoint rings for streams if that completes successfully. | |
3264 | */ | |
3265 | int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, | |
3266 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3267 | gfp_t mem_flags) | |
3268 | { | |
3269 | int i, ret; | |
3270 | struct xhci_hcd *xhci; | |
3271 | struct xhci_virt_device *vdev; | |
3272 | struct xhci_command *command; | |
92f8e767 | 3273 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3274 | unsigned int ep_index; |
3275 | unsigned long flags; | |
3276 | u32 changed_ep_bitmask; | |
3277 | ||
3278 | xhci = hcd_to_xhci(hcd); | |
3279 | vdev = xhci->devs[udev->slot_id]; | |
3280 | ||
3281 | /* Set up a configure endpoint command to remove the streams rings */ | |
3282 | spin_lock_irqsave(&xhci->lock, flags); | |
3283 | changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci, | |
3284 | udev, eps, num_eps); | |
3285 | if (changed_ep_bitmask == 0) { | |
3286 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3287 | return -EINVAL; | |
3288 | } | |
3289 | ||
3290 | /* Use the xhci_command structure from the first endpoint. We may have | |
3291 | * allocated too many, but the driver may call xhci_free_streams() for | |
3292 | * each endpoint it grouped into one call to xhci_alloc_streams(). | |
3293 | */ | |
3294 | ep_index = xhci_get_endpoint_index(&eps[0]->desc); | |
3295 | command = vdev->eps[ep_index].stream_info->free_streams_command; | |
4daf9df5 | 3296 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 | 3297 | if (!ctrl_ctx) { |
1f21569c | 3298 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
3299 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
3300 | __func__); | |
3301 | return -EINVAL; | |
3302 | } | |
3303 | ||
8df75f42 SS |
3304 | for (i = 0; i < num_eps; i++) { |
3305 | struct xhci_ep_ctx *ep_ctx; | |
3306 | ||
3307 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3308 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); | |
3309 | xhci->devs[udev->slot_id]->eps[ep_index].ep_state |= | |
3310 | EP_GETTING_NO_STREAMS; | |
3311 | ||
3312 | xhci_endpoint_copy(xhci, command->in_ctx, | |
3313 | vdev->out_ctx, ep_index); | |
4daf9df5 | 3314 | xhci_setup_no_streams_ep_input_ctx(ep_ctx, |
8df75f42 SS |
3315 | &vdev->eps[ep_index]); |
3316 | } | |
3317 | xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx, | |
92f8e767 SS |
3318 | vdev->out_ctx, ctrl_ctx, |
3319 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3320 | spin_unlock_irqrestore(&xhci->lock, flags); |
3321 | ||
3322 | /* Issue and wait for the configure endpoint command, | |
3323 | * which must succeed. | |
3324 | */ | |
3325 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3326 | false, true); | |
3327 | ||
3328 | /* xHC rejected the configure endpoint command for some reason, so we | |
3329 | * leave the streams rings intact. | |
3330 | */ | |
3331 | if (ret < 0) | |
3332 | return ret; | |
3333 | ||
3334 | spin_lock_irqsave(&xhci->lock, flags); | |
3335 | for (i = 0; i < num_eps; i++) { | |
3336 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3337 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3338 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3339 | /* FIXME Unset maxPstreams in endpoint context and |
3340 | * update deq ptr to point to normal string ring. | |
3341 | */ | |
3342 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS; | |
3343 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3344 | } | |
3345 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3346 | ||
3347 | return 0; | |
3348 | } | |
3349 | ||
2cf95c18 SS |
3350 | /* |
3351 | * Deletes endpoint resources for endpoints that were active before a Reset | |
3352 | * Device command, or a Disable Slot command. The Reset Device command leaves | |
3353 | * the control endpoint intact, whereas the Disable Slot command deletes it. | |
3354 | * | |
3355 | * Must be called with xhci->lock held. | |
3356 | */ | |
3357 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, | |
3358 | struct xhci_virt_device *virt_dev, bool drop_control_ep) | |
3359 | { | |
3360 | int i; | |
3361 | unsigned int num_dropped_eps = 0; | |
3362 | unsigned int drop_flags = 0; | |
3363 | ||
3364 | for (i = (drop_control_ep ? 0 : 1); i < 31; i++) { | |
3365 | if (virt_dev->eps[i].ring) { | |
3366 | drop_flags |= 1 << i; | |
3367 | num_dropped_eps++; | |
3368 | } | |
3369 | } | |
3370 | xhci->num_active_eps -= num_dropped_eps; | |
3371 | if (num_dropped_eps) | |
4bdfe4c3 XR |
3372 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3373 | "Dropped %u ep ctxs, flags = 0x%x, " | |
3374 | "%u now active.", | |
2cf95c18 SS |
3375 | num_dropped_eps, drop_flags, |
3376 | xhci->num_active_eps); | |
3377 | } | |
3378 | ||
2a8f82c4 SS |
3379 | /* |
3380 | * This submits a Reset Device Command, which will set the device state to 0, | |
3381 | * set the device address to 0, and disable all the endpoints except the default | |
3382 | * control endpoint. The USB core should come back and call | |
3383 | * xhci_address_device(), and then re-set up the configuration. If this is | |
3384 | * called because of a usb_reset_and_verify_device(), then the old alternate | |
3385 | * settings will be re-installed through the normal bandwidth allocation | |
3386 | * functions. | |
3387 | * | |
3388 | * Wait for the Reset Device command to finish. Remove all structures | |
3389 | * associated with the endpoints that were disabled. Clear the input device | |
3390 | * structure? Cache the rings? Reset the control endpoint 0 max packet size? | |
f0615c45 AX |
3391 | * |
3392 | * If the virt_dev to be reset does not exist or does not match the udev, | |
3393 | * it means the device is lost, possibly due to the xHC restore error and | |
3394 | * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to | |
3395 | * re-allocate the device. | |
2a8f82c4 | 3396 | */ |
f0615c45 | 3397 | int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev) |
2a8f82c4 SS |
3398 | { |
3399 | int ret, i; | |
3400 | unsigned long flags; | |
3401 | struct xhci_hcd *xhci; | |
3402 | unsigned int slot_id; | |
3403 | struct xhci_virt_device *virt_dev; | |
3404 | struct xhci_command *reset_device_cmd; | |
2a8f82c4 | 3405 | int last_freed_endpoint; |
001fd382 | 3406 | struct xhci_slot_ctx *slot_ctx; |
2e27980e | 3407 | int old_active_eps = 0; |
2a8f82c4 | 3408 | |
f0615c45 | 3409 | ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__); |
2a8f82c4 SS |
3410 | if (ret <= 0) |
3411 | return ret; | |
3412 | xhci = hcd_to_xhci(hcd); | |
3413 | slot_id = udev->slot_id; | |
3414 | virt_dev = xhci->devs[slot_id]; | |
f0615c45 AX |
3415 | if (!virt_dev) { |
3416 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3417 | "not exist. Re-allocate the device\n", slot_id); | |
3418 | ret = xhci_alloc_dev(hcd, udev); | |
3419 | if (ret == 1) | |
3420 | return 0; | |
3421 | else | |
3422 | return -EINVAL; | |
3423 | } | |
3424 | ||
326124a0 BC |
3425 | if (virt_dev->tt_info) |
3426 | old_active_eps = virt_dev->tt_info->active_eps; | |
3427 | ||
f0615c45 AX |
3428 | if (virt_dev->udev != udev) { |
3429 | /* If the virt_dev and the udev does not match, this virt_dev | |
3430 | * may belong to another udev. | |
3431 | * Re-allocate the device. | |
3432 | */ | |
3433 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3434 | "not match the udev. Re-allocate the device\n", | |
3435 | slot_id); | |
3436 | ret = xhci_alloc_dev(hcd, udev); | |
3437 | if (ret == 1) | |
3438 | return 0; | |
3439 | else | |
3440 | return -EINVAL; | |
3441 | } | |
2a8f82c4 | 3442 | |
001fd382 ML |
3443 | /* If device is not setup, there is no point in resetting it */ |
3444 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
3445 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == | |
3446 | SLOT_STATE_DISABLED) | |
3447 | return 0; | |
3448 | ||
2a8f82c4 SS |
3449 | xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id); |
3450 | /* Allocate the command structure that holds the struct completion. | |
3451 | * Assume we're in process context, since the normal device reset | |
3452 | * process has to wait for the device anyway. Storage devices are | |
3453 | * reset as part of error handling, so use GFP_NOIO instead of | |
3454 | * GFP_KERNEL. | |
3455 | */ | |
3456 | reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); | |
3457 | if (!reset_device_cmd) { | |
3458 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | |
3459 | return -ENOMEM; | |
3460 | } | |
3461 | ||
3462 | /* Attempt to submit the Reset Device command to the command ring */ | |
3463 | spin_lock_irqsave(&xhci->lock, flags); | |
7a3783ef | 3464 | |
ddba5cd0 | 3465 | ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id); |
2a8f82c4 SS |
3466 | if (ret) { |
3467 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
2a8f82c4 SS |
3468 | spin_unlock_irqrestore(&xhci->lock, flags); |
3469 | goto command_cleanup; | |
3470 | } | |
3471 | xhci_ring_cmd_db(xhci); | |
3472 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3473 | ||
3474 | /* Wait for the Reset Device command to finish */ | |
c311e391 | 3475 | wait_for_completion(reset_device_cmd->completion); |
2a8f82c4 SS |
3476 | |
3477 | /* The Reset Device command can't fail, according to the 0.95/0.96 spec, | |
3478 | * unless we tried to reset a slot ID that wasn't enabled, | |
3479 | * or the device wasn't in the addressed or configured state. | |
3480 | */ | |
3481 | ret = reset_device_cmd->status; | |
3482 | switch (ret) { | |
0b7c105a FB |
3483 | case COMP_COMMAND_ABORTED: |
3484 | case COMP_STOPPED: | |
c311e391 MN |
3485 | xhci_warn(xhci, "Timeout waiting for reset device command\n"); |
3486 | ret = -ETIME; | |
3487 | goto command_cleanup; | |
0b7c105a FB |
3488 | case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */ |
3489 | case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */ | |
38a532a6 | 3490 | xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n", |
2a8f82c4 SS |
3491 | slot_id, |
3492 | xhci_get_slot_state(xhci, virt_dev->out_ctx)); | |
38a532a6 | 3493 | xhci_dbg(xhci, "Not freeing device rings.\n"); |
2a8f82c4 SS |
3494 | /* Don't treat this as an error. May change my mind later. */ |
3495 | ret = 0; | |
3496 | goto command_cleanup; | |
3497 | case COMP_SUCCESS: | |
3498 | xhci_dbg(xhci, "Successful reset device command.\n"); | |
3499 | break; | |
3500 | default: | |
3501 | if (xhci_is_vendor_info_code(xhci, ret)) | |
3502 | break; | |
3503 | xhci_warn(xhci, "Unknown completion code %u for " | |
3504 | "reset device command.\n", ret); | |
3505 | ret = -EINVAL; | |
3506 | goto command_cleanup; | |
3507 | } | |
3508 | ||
2cf95c18 SS |
3509 | /* Free up host controller endpoint resources */ |
3510 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3511 | spin_lock_irqsave(&xhci->lock, flags); | |
3512 | /* Don't delete the default control endpoint resources */ | |
3513 | xhci_free_device_endpoint_resources(xhci, virt_dev, false); | |
3514 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3515 | } | |
3516 | ||
2a8f82c4 SS |
3517 | /* Everything but endpoint 0 is disabled, so free or cache the rings. */ |
3518 | last_freed_endpoint = 1; | |
98871e94 | 3519 | for (i = 1; i < 31; i++) { |
2dea75d9 DT |
3520 | struct xhci_virt_ep *ep = &virt_dev->eps[i]; |
3521 | ||
3522 | if (ep->ep_state & EP_HAS_STREAMS) { | |
df613834 HG |
3523 | xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n", |
3524 | xhci_get_endpoint_address(i)); | |
2dea75d9 DT |
3525 | xhci_free_stream_info(xhci, ep->stream_info); |
3526 | ep->stream_info = NULL; | |
3527 | ep->ep_state &= ~EP_HAS_STREAMS; | |
3528 | } | |
3529 | ||
3530 | if (ep->ring) { | |
3531 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); | |
3532 | last_freed_endpoint = i; | |
3533 | } | |
2e27980e SS |
3534 | if (!list_empty(&virt_dev->eps[i].bw_endpoint_list)) |
3535 | xhci_drop_ep_from_interval_table(xhci, | |
3536 | &virt_dev->eps[i].bw_info, | |
3537 | virt_dev->bw_table, | |
3538 | udev, | |
3539 | &virt_dev->eps[i], | |
3540 | virt_dev->tt_info); | |
9af5d71d | 3541 | xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info); |
2a8f82c4 | 3542 | } |
2e27980e SS |
3543 | /* If necessary, update the number of active TTs on this root port */ |
3544 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
3545 | ||
2a8f82c4 SS |
3546 | xhci_dbg(xhci, "Output context after successful reset device cmd:\n"); |
3547 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint); | |
3548 | ret = 0; | |
3549 | ||
3550 | command_cleanup: | |
3551 | xhci_free_command(xhci, reset_device_cmd); | |
3552 | return ret; | |
3553 | } | |
3554 | ||
3ffbba95 SS |
3555 | /* |
3556 | * At this point, the struct usb_device is about to go away, the device has | |
3557 | * disconnected, and all traffic has been stopped and the endpoints have been | |
3558 | * disabled. Free any HC data structures associated with that device. | |
3559 | */ | |
3560 | void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3561 | { | |
3562 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
6f5165cf | 3563 | struct xhci_virt_device *virt_dev; |
64927730 | 3564 | int i, ret; |
ddba5cd0 MN |
3565 | struct xhci_command *command; |
3566 | ||
3567 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); | |
3568 | if (!command) | |
3569 | return; | |
3ffbba95 | 3570 | |
c8476fb8 SN |
3571 | #ifndef CONFIG_USB_DEFAULT_PERSIST |
3572 | /* | |
3573 | * We called pm_runtime_get_noresume when the device was attached. | |
3574 | * Decrement the counter here to allow controller to runtime suspend | |
3575 | * if no devices remain. | |
3576 | */ | |
3577 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3578 | pm_runtime_put_noidle(hcd->self.controller); |
c8476fb8 SN |
3579 | #endif |
3580 | ||
64927730 | 3581 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
7bd89b40 SS |
3582 | /* If the host is halted due to driver unload, we still need to free the |
3583 | * device. | |
3584 | */ | |
ddba5cd0 MN |
3585 | if (ret <= 0 && ret != -ENODEV) { |
3586 | kfree(command); | |
3ffbba95 | 3587 | return; |
ddba5cd0 | 3588 | } |
64927730 | 3589 | |
6f5165cf | 3590 | virt_dev = xhci->devs[udev->slot_id]; |
6f5165cf SS |
3591 | |
3592 | /* Stop any wayward timer functions (which may grab the lock) */ | |
98871e94 | 3593 | for (i = 0; i < 31; i++) { |
9983a5fc | 3594 | virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING; |
6f5165cf SS |
3595 | del_timer_sync(&virt_dev->eps[i].stop_cmd_timer); |
3596 | } | |
3ffbba95 | 3597 | |
f9e609b8 GZ |
3598 | xhci_disable_slot(xhci, command, udev->slot_id); |
3599 | /* | |
3600 | * Event command completion handler will free any data structures | |
3601 | * associated with the slot. XXX Can free sleep? | |
3602 | */ | |
3603 | } | |
3604 | ||
3605 | int xhci_disable_slot(struct xhci_hcd *xhci, struct xhci_command *command, | |
3606 | u32 slot_id) | |
3607 | { | |
3608 | unsigned long flags; | |
3609 | u32 state; | |
3610 | int ret = 0; | |
3611 | struct xhci_virt_device *virt_dev; | |
3612 | ||
3613 | virt_dev = xhci->devs[slot_id]; | |
3614 | if (!virt_dev) | |
3615 | return -EINVAL; | |
3616 | if (!command) | |
3617 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); | |
3618 | if (!command) | |
3619 | return -ENOMEM; | |
3620 | ||
3ffbba95 | 3621 | spin_lock_irqsave(&xhci->lock, flags); |
c526d0d4 | 3622 | /* Don't disable the slot if the host controller is dead. */ |
b0ba9720 | 3623 | state = readl(&xhci->op_regs->status); |
7bd89b40 SS |
3624 | if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) || |
3625 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
f9e609b8 | 3626 | xhci_free_virt_device(xhci, slot_id); |
c526d0d4 | 3627 | spin_unlock_irqrestore(&xhci->lock, flags); |
ddba5cd0 | 3628 | kfree(command); |
f9e609b8 | 3629 | return ret; |
c526d0d4 SS |
3630 | } |
3631 | ||
f9e609b8 GZ |
3632 | ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT, |
3633 | slot_id); | |
3634 | if (ret) { | |
3ffbba95 SS |
3635 | spin_unlock_irqrestore(&xhci->lock, flags); |
3636 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
f9e609b8 | 3637 | return ret; |
3ffbba95 | 3638 | } |
23e3be11 | 3639 | xhci_ring_cmd_db(xhci); |
3ffbba95 | 3640 | spin_unlock_irqrestore(&xhci->lock, flags); |
f9e609b8 | 3641 | return ret; |
3ffbba95 SS |
3642 | } |
3643 | ||
2cf95c18 SS |
3644 | /* |
3645 | * Checks if we have enough host controller resources for the default control | |
3646 | * endpoint. | |
3647 | * | |
3648 | * Must be called with xhci->lock held. | |
3649 | */ | |
3650 | static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci) | |
3651 | { | |
3652 | if (xhci->num_active_eps + 1 > xhci->limit_active_eps) { | |
4bdfe4c3 XR |
3653 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3654 | "Not enough ep ctxs: " | |
3655 | "%u active, need to add 1, limit is %u.", | |
2cf95c18 SS |
3656 | xhci->num_active_eps, xhci->limit_active_eps); |
3657 | return -ENOMEM; | |
3658 | } | |
3659 | xhci->num_active_eps += 1; | |
4bdfe4c3 XR |
3660 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3661 | "Adding 1 ep ctx, %u now active.", | |
2cf95c18 SS |
3662 | xhci->num_active_eps); |
3663 | return 0; | |
3664 | } | |
3665 | ||
3666 | ||
3ffbba95 SS |
3667 | /* |
3668 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command | |
3669 | * timed out, or allocating memory failed. Returns 1 on success. | |
3670 | */ | |
3671 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3672 | { | |
3673 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
3674 | unsigned long flags; | |
a00918d0 | 3675 | int ret, slot_id; |
ddba5cd0 MN |
3676 | struct xhci_command *command; |
3677 | ||
87e44f2a | 3678 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); |
ddba5cd0 MN |
3679 | if (!command) |
3680 | return 0; | |
3ffbba95 | 3681 | |
a00918d0 CB |
3682 | /* xhci->slot_id and xhci->addr_dev are not thread-safe */ |
3683 | mutex_lock(&xhci->mutex); | |
3ffbba95 | 3684 | spin_lock_irqsave(&xhci->lock, flags); |
ddba5cd0 | 3685 | ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0); |
3ffbba95 SS |
3686 | if (ret) { |
3687 | spin_unlock_irqrestore(&xhci->lock, flags); | |
a00918d0 | 3688 | mutex_unlock(&xhci->mutex); |
3ffbba95 | 3689 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); |
87e44f2a | 3690 | xhci_free_command(xhci, command); |
3ffbba95 SS |
3691 | return 0; |
3692 | } | |
23e3be11 | 3693 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3694 | spin_unlock_irqrestore(&xhci->lock, flags); |
3695 | ||
c311e391 | 3696 | wait_for_completion(command->completion); |
c2d3d49b | 3697 | slot_id = command->slot_id; |
a00918d0 | 3698 | mutex_unlock(&xhci->mutex); |
3ffbba95 | 3699 | |
a00918d0 | 3700 | if (!slot_id || command->status != COMP_SUCCESS) { |
3ffbba95 | 3701 | xhci_err(xhci, "Error while assigning device slot ID\n"); |
be982038 SS |
3702 | xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n", |
3703 | HCS_MAX_SLOTS( | |
3704 | readl(&xhci->cap_regs->hcs_params1))); | |
87e44f2a | 3705 | xhci_free_command(xhci, command); |
3ffbba95 SS |
3706 | return 0; |
3707 | } | |
2cf95c18 SS |
3708 | |
3709 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3710 | spin_lock_irqsave(&xhci->lock, flags); | |
3711 | ret = xhci_reserve_host_control_ep_resources(xhci); | |
3712 | if (ret) { | |
3713 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3714 | xhci_warn(xhci, "Not enough host resources, " | |
3715 | "active endpoint contexts = %u\n", | |
3716 | xhci->num_active_eps); | |
3717 | goto disable_slot; | |
3718 | } | |
3719 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3720 | } | |
3721 | /* Use GFP_NOIO, since this function can be called from | |
a6d940dd SS |
3722 | * xhci_discover_or_reset_device(), which may be called as part of |
3723 | * mass storage driver error handling. | |
3724 | */ | |
a00918d0 | 3725 | if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) { |
3ffbba95 | 3726 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); |
2cf95c18 | 3727 | goto disable_slot; |
3ffbba95 | 3728 | } |
a00918d0 | 3729 | udev->slot_id = slot_id; |
c8476fb8 SN |
3730 | |
3731 | #ifndef CONFIG_USB_DEFAULT_PERSIST | |
3732 | /* | |
3733 | * If resetting upon resume, we can't put the controller into runtime | |
3734 | * suspend if there is a device attached. | |
3735 | */ | |
3736 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3737 | pm_runtime_get_noresume(hcd->self.controller); |
c8476fb8 SN |
3738 | #endif |
3739 | ||
ddba5cd0 | 3740 | |
87e44f2a | 3741 | xhci_free_command(xhci, command); |
3ffbba95 SS |
3742 | /* Is this a LS or FS device under a HS hub? */ |
3743 | /* Hub or peripherial? */ | |
3ffbba95 | 3744 | return 1; |
2cf95c18 SS |
3745 | |
3746 | disable_slot: | |
3747 | /* Disable slot, if we can do it without mem alloc */ | |
87e44f2a | 3748 | kfree(command->completion); |
ddba5cd0 MN |
3749 | command->completion = NULL; |
3750 | command->status = 0; | |
f9e609b8 | 3751 | return xhci_disable_slot(xhci, command, udev->slot_id); |
3ffbba95 SS |
3752 | } |
3753 | ||
3754 | /* | |
48fc7dbd DW |
3755 | * Issue an Address Device command and optionally send a corresponding |
3756 | * SetAddress request to the device. | |
3ffbba95 | 3757 | */ |
48fc7dbd DW |
3758 | static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, |
3759 | enum xhci_setup_dev setup) | |
3ffbba95 | 3760 | { |
6f8ffc0b | 3761 | const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address"; |
3ffbba95 | 3762 | unsigned long flags; |
3ffbba95 SS |
3763 | struct xhci_virt_device *virt_dev; |
3764 | int ret = 0; | |
3765 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
d115b048 JY |
3766 | struct xhci_slot_ctx *slot_ctx; |
3767 | struct xhci_input_control_ctx *ctrl_ctx; | |
8e595a5d | 3768 | u64 temp_64; |
a00918d0 CB |
3769 | struct xhci_command *command = NULL; |
3770 | ||
3771 | mutex_lock(&xhci->mutex); | |
3ffbba95 | 3772 | |
90797aee LB |
3773 | if (xhci->xhc_state) { /* dying, removing or halted */ |
3774 | ret = -ESHUTDOWN; | |
448116bf | 3775 | goto out; |
90797aee | 3776 | } |
448116bf | 3777 | |
3ffbba95 | 3778 | if (!udev->slot_id) { |
84a99f6f XR |
3779 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3780 | "Bad Slot ID %d", udev->slot_id); | |
a00918d0 CB |
3781 | ret = -EINVAL; |
3782 | goto out; | |
3ffbba95 SS |
3783 | } |
3784 | ||
3ffbba95 SS |
3785 | virt_dev = xhci->devs[udev->slot_id]; |
3786 | ||
7ed603ec ME |
3787 | if (WARN_ON(!virt_dev)) { |
3788 | /* | |
3789 | * In plug/unplug torture test with an NEC controller, | |
3790 | * a zero-dereference was observed once due to virt_dev = 0. | |
3791 | * Print useful debug rather than crash if it is observed again! | |
3792 | */ | |
3793 | xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n", | |
3794 | udev->slot_id); | |
a00918d0 CB |
3795 | ret = -EINVAL; |
3796 | goto out; | |
7ed603ec ME |
3797 | } |
3798 | ||
f161ead7 MN |
3799 | if (setup == SETUP_CONTEXT_ONLY) { |
3800 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
3801 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == | |
3802 | SLOT_STATE_DEFAULT) { | |
3803 | xhci_dbg(xhci, "Slot already in default state\n"); | |
a00918d0 | 3804 | goto out; |
f161ead7 MN |
3805 | } |
3806 | } | |
3807 | ||
87e44f2a | 3808 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); |
a00918d0 CB |
3809 | if (!command) { |
3810 | ret = -ENOMEM; | |
3811 | goto out; | |
3812 | } | |
ddba5cd0 MN |
3813 | |
3814 | command->in_ctx = virt_dev->in_ctx; | |
ddba5cd0 | 3815 | |
f0615c45 | 3816 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
4daf9df5 | 3817 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
92f8e767 SS |
3818 | if (!ctrl_ctx) { |
3819 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3820 | __func__); | |
a00918d0 CB |
3821 | ret = -EINVAL; |
3822 | goto out; | |
92f8e767 | 3823 | } |
f0615c45 AX |
3824 | /* |
3825 | * If this is the first Set Address since device plug-in or | |
3826 | * virt_device realloaction after a resume with an xHCI power loss, | |
3827 | * then set up the slot context. | |
3828 | */ | |
3829 | if (!slot_ctx->dev_info) | |
3ffbba95 | 3830 | xhci_setup_addressable_virt_dev(xhci, udev); |
f0615c45 | 3831 | /* Otherwise, update the control endpoint ring enqueue pointer. */ |
2d1ee590 SS |
3832 | else |
3833 | xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev); | |
d31c285b SS |
3834 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); |
3835 | ctrl_ctx->drop_flags = 0; | |
3836 | ||
66e49d87 | 3837 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
d115b048 | 3838 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
1d27fabe | 3839 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 3840 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 | 3841 | |
f88ba78d | 3842 | spin_lock_irqsave(&xhci->lock, flags); |
a711edee | 3843 | trace_xhci_setup_device(virt_dev); |
ddba5cd0 | 3844 | ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma, |
48fc7dbd | 3845 | udev->slot_id, setup); |
3ffbba95 SS |
3846 | if (ret) { |
3847 | spin_unlock_irqrestore(&xhci->lock, flags); | |
84a99f6f XR |
3848 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3849 | "FIXME: allocate a command ring segment"); | |
a00918d0 | 3850 | goto out; |
3ffbba95 | 3851 | } |
23e3be11 | 3852 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3853 | spin_unlock_irqrestore(&xhci->lock, flags); |
3854 | ||
3855 | /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */ | |
c311e391 MN |
3856 | wait_for_completion(command->completion); |
3857 | ||
3ffbba95 SS |
3858 | /* FIXME: From section 4.3.4: "Software shall be responsible for timing |
3859 | * the SetAddress() "recovery interval" required by USB and aborting the | |
3860 | * command on a timeout. | |
3861 | */ | |
9ea1833e | 3862 | switch (command->status) { |
0b7c105a FB |
3863 | case COMP_COMMAND_ABORTED: |
3864 | case COMP_STOPPED: | |
c311e391 MN |
3865 | xhci_warn(xhci, "Timeout while waiting for setup device command\n"); |
3866 | ret = -ETIME; | |
3867 | break; | |
0b7c105a FB |
3868 | case COMP_CONTEXT_STATE_ERROR: |
3869 | case COMP_SLOT_NOT_ENABLED_ERROR: | |
6f8ffc0b DW |
3870 | xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n", |
3871 | act, udev->slot_id); | |
3ffbba95 SS |
3872 | ret = -EINVAL; |
3873 | break; | |
0b7c105a | 3874 | case COMP_USB_TRANSACTION_ERROR: |
6f8ffc0b | 3875 | dev_warn(&udev->dev, "Device not responding to setup %s.\n", act); |
3ffbba95 SS |
3876 | ret = -EPROTO; |
3877 | break; | |
0b7c105a | 3878 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
6f8ffc0b DW |
3879 | dev_warn(&udev->dev, |
3880 | "ERROR: Incompatible device for setup %s command\n", act); | |
f6ba6fe2 AH |
3881 | ret = -ENODEV; |
3882 | break; | |
3ffbba95 | 3883 | case COMP_SUCCESS: |
84a99f6f | 3884 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
6f8ffc0b | 3885 | "Successful setup %s command", act); |
3ffbba95 SS |
3886 | break; |
3887 | default: | |
6f8ffc0b DW |
3888 | xhci_err(xhci, |
3889 | "ERROR: unexpected setup %s command completion code 0x%x.\n", | |
9ea1833e | 3890 | act, command->status); |
66e49d87 | 3891 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
d115b048 | 3892 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); |
1d27fabe | 3893 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1); |
3ffbba95 SS |
3894 | ret = -EINVAL; |
3895 | break; | |
3896 | } | |
a00918d0 CB |
3897 | if (ret) |
3898 | goto out; | |
f7b2e403 | 3899 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
84a99f6f XR |
3900 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3901 | "Op regs DCBAA ptr = %#016llx", temp_64); | |
3902 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3903 | "Slot ID %d dcbaa entry @%p = %#016llx", | |
3904 | udev->slot_id, | |
3905 | &xhci->dcbaa->dev_context_ptrs[udev->slot_id], | |
3906 | (unsigned long long) | |
3907 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id])); | |
3908 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3909 | "Output Context DMA address = %#08llx", | |
d115b048 | 3910 | (unsigned long long)virt_dev->out_ctx->dma); |
3ffbba95 | 3911 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
d115b048 | 3912 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
1d27fabe | 3913 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 3914 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 | 3915 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
d115b048 | 3916 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); |
3ffbba95 SS |
3917 | /* |
3918 | * USB core uses address 1 for the roothubs, so we add one to the | |
3919 | * address given back to us by the HC. | |
3920 | */ | |
d115b048 | 3921 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
1d27fabe | 3922 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, |
0c052aab | 3923 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
f94e0186 | 3924 | /* Zero the input context control for later use */ |
d115b048 JY |
3925 | ctrl_ctx->add_flags = 0; |
3926 | ctrl_ctx->drop_flags = 0; | |
3ffbba95 | 3927 | |
84a99f6f | 3928 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
a2cdc343 DW |
3929 | "Internal device address = %d", |
3930 | le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); | |
a00918d0 CB |
3931 | out: |
3932 | mutex_unlock(&xhci->mutex); | |
87e44f2a LB |
3933 | if (command) { |
3934 | kfree(command->completion); | |
3935 | kfree(command); | |
3936 | } | |
a00918d0 | 3937 | return ret; |
3ffbba95 SS |
3938 | } |
3939 | ||
48fc7dbd DW |
3940 | int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) |
3941 | { | |
3942 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS); | |
3943 | } | |
3944 | ||
3945 | int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev) | |
3946 | { | |
3947 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY); | |
3948 | } | |
3949 | ||
3f5eb141 LT |
3950 | /* |
3951 | * Transfer the port index into real index in the HW port status | |
3952 | * registers. Caculate offset between the port's PORTSC register | |
3953 | * and port status base. Divide the number of per port register | |
3954 | * to get the real index. The raw port number bases 1. | |
3955 | */ | |
3956 | int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1) | |
3957 | { | |
3958 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
3959 | __le32 __iomem *base_addr = &xhci->op_regs->port_status_base; | |
3960 | __le32 __iomem *addr; | |
3961 | int raw_port; | |
3962 | ||
b50107bb | 3963 | if (hcd->speed < HCD_USB3) |
3f5eb141 LT |
3964 | addr = xhci->usb2_ports[port1 - 1]; |
3965 | else | |
3966 | addr = xhci->usb3_ports[port1 - 1]; | |
3967 | ||
3968 | raw_port = (addr - base_addr)/NUM_PORT_REGS + 1; | |
3969 | return raw_port; | |
3970 | } | |
3971 | ||
a558ccdc MN |
3972 | /* |
3973 | * Issue an Evaluate Context command to change the Maximum Exit Latency in the | |
3974 | * slot context. If that succeeds, store the new MEL in the xhci_virt_device. | |
3975 | */ | |
d5c82feb | 3976 | static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, |
a558ccdc MN |
3977 | struct usb_device *udev, u16 max_exit_latency) |
3978 | { | |
3979 | struct xhci_virt_device *virt_dev; | |
3980 | struct xhci_command *command; | |
3981 | struct xhci_input_control_ctx *ctrl_ctx; | |
3982 | struct xhci_slot_ctx *slot_ctx; | |
3983 | unsigned long flags; | |
3984 | int ret; | |
3985 | ||
3986 | spin_lock_irqsave(&xhci->lock, flags); | |
96044694 MN |
3987 | |
3988 | virt_dev = xhci->devs[udev->slot_id]; | |
3989 | ||
3990 | /* | |
3991 | * virt_dev might not exists yet if xHC resumed from hibernate (S4) and | |
3992 | * xHC was re-initialized. Exit latency will be set later after | |
3993 | * hub_port_finish_reset() is done and xhci->devs[] are re-allocated | |
3994 | */ | |
3995 | ||
3996 | if (!virt_dev || max_exit_latency == virt_dev->current_mel) { | |
a558ccdc MN |
3997 | spin_unlock_irqrestore(&xhci->lock, flags); |
3998 | return 0; | |
3999 | } | |
4000 | ||
4001 | /* Attempt to issue an Evaluate Context command to change the MEL. */ | |
a558ccdc | 4002 | command = xhci->lpm_command; |
4daf9df5 | 4003 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
4004 | if (!ctrl_ctx) { |
4005 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4006 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
4007 | __func__); | |
4008 | return -ENOMEM; | |
4009 | } | |
4010 | ||
a558ccdc MN |
4011 | xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx); |
4012 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4013 | ||
a558ccdc MN |
4014 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
4015 | slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx); | |
4016 | slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT)); | |
4017 | slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency); | |
4801d4ea | 4018 | slot_ctx->dev_state = 0; |
a558ccdc | 4019 | |
3a7fa5be XR |
4020 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
4021 | "Set up evaluate context for LPM MEL change."); | |
a558ccdc MN |
4022 | xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id); |
4023 | xhci_dbg_ctx(xhci, command->in_ctx, 0); | |
4024 | ||
4025 | /* Issue and wait for the evaluate context command. */ | |
4026 | ret = xhci_configure_endpoint(xhci, udev, command, | |
4027 | true, true); | |
4028 | xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id); | |
4029 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0); | |
4030 | ||
4031 | if (!ret) { | |
4032 | spin_lock_irqsave(&xhci->lock, flags); | |
4033 | virt_dev->current_mel = max_exit_latency; | |
4034 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4035 | } | |
4036 | return ret; | |
4037 | } | |
4038 | ||
ceb6c9c8 | 4039 | #ifdef CONFIG_PM |
9574323c AX |
4040 | |
4041 | /* BESL to HIRD Encoding array for USB2 LPM */ | |
4042 | static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000, | |
4043 | 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000}; | |
4044 | ||
4045 | /* Calculate HIRD/BESL for USB2 PORTPMSC*/ | |
f99298bf AX |
4046 | static int xhci_calculate_hird_besl(struct xhci_hcd *xhci, |
4047 | struct usb_device *udev) | |
9574323c | 4048 | { |
f99298bf AX |
4049 | int u2del, besl, besl_host; |
4050 | int besl_device = 0; | |
4051 | u32 field; | |
4052 | ||
4053 | u2del = HCS_U2_LATENCY(xhci->hcs_params3); | |
4054 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
9574323c | 4055 | |
f99298bf AX |
4056 | if (field & USB_BESL_SUPPORT) { |
4057 | for (besl_host = 0; besl_host < 16; besl_host++) { | |
4058 | if (xhci_besl_encoding[besl_host] >= u2del) | |
9574323c AX |
4059 | break; |
4060 | } | |
f99298bf AX |
4061 | /* Use baseline BESL value as default */ |
4062 | if (field & USB_BESL_BASELINE_VALID) | |
4063 | besl_device = USB_GET_BESL_BASELINE(field); | |
4064 | else if (field & USB_BESL_DEEP_VALID) | |
4065 | besl_device = USB_GET_BESL_DEEP(field); | |
9574323c AX |
4066 | } else { |
4067 | if (u2del <= 50) | |
f99298bf | 4068 | besl_host = 0; |
9574323c | 4069 | else |
f99298bf | 4070 | besl_host = (u2del - 51) / 75 + 1; |
9574323c AX |
4071 | } |
4072 | ||
f99298bf AX |
4073 | besl = besl_host + besl_device; |
4074 | if (besl > 15) | |
4075 | besl = 15; | |
4076 | ||
4077 | return besl; | |
9574323c AX |
4078 | } |
4079 | ||
a558ccdc MN |
4080 | /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */ |
4081 | static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev) | |
4082 | { | |
4083 | u32 field; | |
4084 | int l1; | |
4085 | int besld = 0; | |
4086 | int hirdm = 0; | |
4087 | ||
4088 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
4089 | ||
4090 | /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */ | |
17f34867 | 4091 | l1 = udev->l1_params.timeout / 256; |
a558ccdc MN |
4092 | |
4093 | /* device has preferred BESLD */ | |
4094 | if (field & USB_BESL_DEEP_VALID) { | |
4095 | besld = USB_GET_BESL_DEEP(field); | |
4096 | hirdm = 1; | |
4097 | } | |
4098 | ||
4099 | return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm); | |
4100 | } | |
4101 | ||
65580b43 AX |
4102 | int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
4103 | struct usb_device *udev, int enable) | |
4104 | { | |
4105 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4106 | __le32 __iomem **port_array; | |
a558ccdc MN |
4107 | __le32 __iomem *pm_addr, *hlpm_addr; |
4108 | u32 pm_val, hlpm_val, field; | |
65580b43 AX |
4109 | unsigned int port_num; |
4110 | unsigned long flags; | |
a558ccdc MN |
4111 | int hird, exit_latency; |
4112 | int ret; | |
65580b43 | 4113 | |
b50107bb | 4114 | if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support || |
65580b43 AX |
4115 | !udev->lpm_capable) |
4116 | return -EPERM; | |
4117 | ||
4118 | if (!udev->parent || udev->parent->parent || | |
4119 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4120 | return -EPERM; | |
4121 | ||
4122 | if (udev->usb2_hw_lpm_capable != 1) | |
4123 | return -EPERM; | |
4124 | ||
4125 | spin_lock_irqsave(&xhci->lock, flags); | |
4126 | ||
4127 | port_array = xhci->usb2_ports; | |
4128 | port_num = udev->portnum - 1; | |
b6e76371 | 4129 | pm_addr = port_array[port_num] + PORTPMSC; |
b0ba9720 | 4130 | pm_val = readl(pm_addr); |
a558ccdc MN |
4131 | hlpm_addr = port_array[port_num] + PORTHLPMC; |
4132 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
65580b43 AX |
4133 | |
4134 | xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n", | |
654a55d3 | 4135 | enable ? "enable" : "disable", port_num + 1); |
65580b43 | 4136 | |
65580b43 | 4137 | if (enable) { |
a558ccdc MN |
4138 | /* Host supports BESL timeout instead of HIRD */ |
4139 | if (udev->usb2_hw_lpm_besl_capable) { | |
4140 | /* if device doesn't have a preferred BESL value use a | |
4141 | * default one which works with mixed HIRD and BESL | |
4142 | * systems. See XHCI_DEFAULT_BESL definition in xhci.h | |
4143 | */ | |
4144 | if ((field & USB_BESL_SUPPORT) && | |
4145 | (field & USB_BESL_BASELINE_VALID)) | |
4146 | hird = USB_GET_BESL_BASELINE(field); | |
4147 | else | |
17f34867 | 4148 | hird = udev->l1_params.besl; |
a558ccdc MN |
4149 | |
4150 | exit_latency = xhci_besl_encoding[hird]; | |
4151 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4152 | ||
4153 | /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx | |
4154 | * input context for link powermanagement evaluate | |
4155 | * context commands. It is protected by hcd->bandwidth | |
4156 | * mutex and is shared by all devices. We need to set | |
4157 | * the max ext latency in USB 2 BESL LPM as well, so | |
4158 | * use the same mutex and xhci_change_max_exit_latency() | |
4159 | */ | |
4160 | mutex_lock(hcd->bandwidth_mutex); | |
4161 | ret = xhci_change_max_exit_latency(xhci, udev, | |
4162 | exit_latency); | |
4163 | mutex_unlock(hcd->bandwidth_mutex); | |
4164 | ||
4165 | if (ret < 0) | |
4166 | return ret; | |
4167 | spin_lock_irqsave(&xhci->lock, flags); | |
4168 | ||
4169 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); | |
204b7793 | 4170 | writel(hlpm_val, hlpm_addr); |
a558ccdc | 4171 | /* flush write */ |
b0ba9720 | 4172 | readl(hlpm_addr); |
a558ccdc MN |
4173 | } else { |
4174 | hird = xhci_calculate_hird_besl(xhci, udev); | |
4175 | } | |
4176 | ||
4177 | pm_val &= ~PORT_HIRD_MASK; | |
58e21f73 | 4178 | pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id); |
204b7793 | 4179 | writel(pm_val, pm_addr); |
b0ba9720 | 4180 | pm_val = readl(pm_addr); |
a558ccdc | 4181 | pm_val |= PORT_HLE; |
204b7793 | 4182 | writel(pm_val, pm_addr); |
a558ccdc | 4183 | /* flush write */ |
b0ba9720 | 4184 | readl(pm_addr); |
65580b43 | 4185 | } else { |
58e21f73 | 4186 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK); |
204b7793 | 4187 | writel(pm_val, pm_addr); |
a558ccdc | 4188 | /* flush write */ |
b0ba9720 | 4189 | readl(pm_addr); |
a558ccdc MN |
4190 | if (udev->usb2_hw_lpm_besl_capable) { |
4191 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4192 | mutex_lock(hcd->bandwidth_mutex); | |
4193 | xhci_change_max_exit_latency(xhci, udev, 0); | |
4194 | mutex_unlock(hcd->bandwidth_mutex); | |
4195 | return 0; | |
4196 | } | |
65580b43 AX |
4197 | } |
4198 | ||
4199 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4200 | return 0; | |
4201 | } | |
4202 | ||
b630d4b9 MN |
4203 | /* check if a usb2 port supports a given extened capability protocol |
4204 | * only USB2 ports extended protocol capability values are cached. | |
4205 | * Return 1 if capability is supported | |
4206 | */ | |
4207 | static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port, | |
4208 | unsigned capability) | |
4209 | { | |
4210 | u32 port_offset, port_count; | |
4211 | int i; | |
4212 | ||
4213 | for (i = 0; i < xhci->num_ext_caps; i++) { | |
4214 | if (xhci->ext_caps[i] & capability) { | |
4215 | /* port offsets starts at 1 */ | |
4216 | port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1; | |
4217 | port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]); | |
4218 | if (port >= port_offset && | |
4219 | port < port_offset + port_count) | |
4220 | return 1; | |
4221 | } | |
4222 | } | |
4223 | return 0; | |
4224 | } | |
4225 | ||
b01bcbf7 SS |
4226 | int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
4227 | { | |
4228 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
b630d4b9 | 4229 | int portnum = udev->portnum - 1; |
b01bcbf7 | 4230 | |
b50107bb | 4231 | if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support || |
de68bab4 SS |
4232 | !udev->lpm_capable) |
4233 | return 0; | |
4234 | ||
4235 | /* we only support lpm for non-hub device connected to root hub yet */ | |
4236 | if (!udev->parent || udev->parent->parent || | |
4237 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4238 | return 0; | |
4239 | ||
4240 | if (xhci->hw_lpm_support == 1 && | |
4241 | xhci_check_usb2_port_capability( | |
4242 | xhci, portnum, XHCI_HLC)) { | |
4243 | udev->usb2_hw_lpm_capable = 1; | |
4244 | udev->l1_params.timeout = XHCI_L1_TIMEOUT; | |
4245 | udev->l1_params.besl = XHCI_DEFAULT_BESL; | |
4246 | if (xhci_check_usb2_port_capability(xhci, portnum, | |
4247 | XHCI_BLC)) | |
4248 | udev->usb2_hw_lpm_besl_capable = 1; | |
b01bcbf7 SS |
4249 | } |
4250 | ||
4251 | return 0; | |
4252 | } | |
4253 | ||
3b3db026 SS |
4254 | /*---------------------- USB 3.0 Link PM functions ------------------------*/ |
4255 | ||
e3567d2c SS |
4256 | /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */ |
4257 | static unsigned long long xhci_service_interval_to_ns( | |
4258 | struct usb_endpoint_descriptor *desc) | |
4259 | { | |
16b45fdf | 4260 | return (1ULL << (desc->bInterval - 1)) * 125 * 1000; |
e3567d2c SS |
4261 | } |
4262 | ||
3b3db026 SS |
4263 | static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev, |
4264 | enum usb3_link_state state) | |
4265 | { | |
4266 | unsigned long long sel; | |
4267 | unsigned long long pel; | |
4268 | unsigned int max_sel_pel; | |
4269 | char *state_name; | |
4270 | ||
4271 | switch (state) { | |
4272 | case USB3_LPM_U1: | |
4273 | /* Convert SEL and PEL stored in nanoseconds to microseconds */ | |
4274 | sel = DIV_ROUND_UP(udev->u1_params.sel, 1000); | |
4275 | pel = DIV_ROUND_UP(udev->u1_params.pel, 1000); | |
4276 | max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL; | |
4277 | state_name = "U1"; | |
4278 | break; | |
4279 | case USB3_LPM_U2: | |
4280 | sel = DIV_ROUND_UP(udev->u2_params.sel, 1000); | |
4281 | pel = DIV_ROUND_UP(udev->u2_params.pel, 1000); | |
4282 | max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL; | |
4283 | state_name = "U2"; | |
4284 | break; | |
4285 | default: | |
4286 | dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n", | |
4287 | __func__); | |
e25e62ae | 4288 | return USB3_LPM_DISABLED; |
3b3db026 SS |
4289 | } |
4290 | ||
4291 | if (sel <= max_sel_pel && pel <= max_sel_pel) | |
4292 | return USB3_LPM_DEVICE_INITIATED; | |
4293 | ||
4294 | if (sel > max_sel_pel) | |
4295 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
4296 | "due to long SEL %llu ms\n", | |
4297 | state_name, sel); | |
4298 | else | |
4299 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
03e64e96 | 4300 | "due to long PEL %llu ms\n", |
3b3db026 SS |
4301 | state_name, pel); |
4302 | return USB3_LPM_DISABLED; | |
4303 | } | |
4304 | ||
9502c46c | 4305 | /* The U1 timeout should be the maximum of the following values: |
e3567d2c SS |
4306 | * - For control endpoints, U1 system exit latency (SEL) * 3 |
4307 | * - For bulk endpoints, U1 SEL * 5 | |
4308 | * - For interrupt endpoints: | |
4309 | * - Notification EPs, U1 SEL * 3 | |
4310 | * - Periodic EPs, max(105% of bInterval, U1 SEL * 2) | |
4311 | * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2) | |
4312 | */ | |
9502c46c PA |
4313 | static unsigned long long xhci_calculate_intel_u1_timeout( |
4314 | struct usb_device *udev, | |
e3567d2c SS |
4315 | struct usb_endpoint_descriptor *desc) |
4316 | { | |
4317 | unsigned long long timeout_ns; | |
4318 | int ep_type; | |
4319 | int intr_type; | |
4320 | ||
4321 | ep_type = usb_endpoint_type(desc); | |
4322 | switch (ep_type) { | |
4323 | case USB_ENDPOINT_XFER_CONTROL: | |
4324 | timeout_ns = udev->u1_params.sel * 3; | |
4325 | break; | |
4326 | case USB_ENDPOINT_XFER_BULK: | |
4327 | timeout_ns = udev->u1_params.sel * 5; | |
4328 | break; | |
4329 | case USB_ENDPOINT_XFER_INT: | |
4330 | intr_type = usb_endpoint_interrupt_type(desc); | |
4331 | if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) { | |
4332 | timeout_ns = udev->u1_params.sel * 3; | |
4333 | break; | |
4334 | } | |
4335 | /* Otherwise the calculation is the same as isoc eps */ | |
4336 | case USB_ENDPOINT_XFER_ISOC: | |
4337 | timeout_ns = xhci_service_interval_to_ns(desc); | |
c88db160 | 4338 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100); |
e3567d2c SS |
4339 | if (timeout_ns < udev->u1_params.sel * 2) |
4340 | timeout_ns = udev->u1_params.sel * 2; | |
4341 | break; | |
4342 | default: | |
4343 | return 0; | |
4344 | } | |
4345 | ||
9502c46c PA |
4346 | return timeout_ns; |
4347 | } | |
4348 | ||
4349 | /* Returns the hub-encoded U1 timeout value. */ | |
4350 | static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci, | |
4351 | struct usb_device *udev, | |
4352 | struct usb_endpoint_descriptor *desc) | |
4353 | { | |
4354 | unsigned long long timeout_ns; | |
4355 | ||
4356 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4357 | timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc); | |
4358 | else | |
4359 | timeout_ns = udev->u1_params.sel; | |
4360 | ||
4361 | /* The U1 timeout is encoded in 1us intervals. | |
4362 | * Don't return a timeout of zero, because that's USB3_LPM_DISABLED. | |
4363 | */ | |
e3567d2c | 4364 | if (timeout_ns == USB3_LPM_DISABLED) |
9502c46c PA |
4365 | timeout_ns = 1; |
4366 | else | |
4367 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000); | |
e3567d2c SS |
4368 | |
4369 | /* If the necessary timeout value is bigger than what we can set in the | |
4370 | * USB 3.0 hub, we have to disable hub-initiated U1. | |
4371 | */ | |
4372 | if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT) | |
4373 | return timeout_ns; | |
4374 | dev_dbg(&udev->dev, "Hub-initiated U1 disabled " | |
4375 | "due to long timeout %llu ms\n", timeout_ns); | |
4376 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1); | |
4377 | } | |
4378 | ||
9502c46c | 4379 | /* The U2 timeout should be the maximum of: |
e3567d2c SS |
4380 | * - 10 ms (to avoid the bandwidth impact on the scheduler) |
4381 | * - largest bInterval of any active periodic endpoint (to avoid going | |
4382 | * into lower power link states between intervals). | |
4383 | * - the U2 Exit Latency of the device | |
4384 | */ | |
9502c46c PA |
4385 | static unsigned long long xhci_calculate_intel_u2_timeout( |
4386 | struct usb_device *udev, | |
e3567d2c SS |
4387 | struct usb_endpoint_descriptor *desc) |
4388 | { | |
4389 | unsigned long long timeout_ns; | |
4390 | unsigned long long u2_del_ns; | |
4391 | ||
4392 | timeout_ns = 10 * 1000 * 1000; | |
4393 | ||
4394 | if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) && | |
4395 | (xhci_service_interval_to_ns(desc) > timeout_ns)) | |
4396 | timeout_ns = xhci_service_interval_to_ns(desc); | |
4397 | ||
966e7a85 | 4398 | u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL; |
e3567d2c SS |
4399 | if (u2_del_ns > timeout_ns) |
4400 | timeout_ns = u2_del_ns; | |
4401 | ||
9502c46c PA |
4402 | return timeout_ns; |
4403 | } | |
4404 | ||
4405 | /* Returns the hub-encoded U2 timeout value. */ | |
4406 | static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci, | |
4407 | struct usb_device *udev, | |
4408 | struct usb_endpoint_descriptor *desc) | |
4409 | { | |
4410 | unsigned long long timeout_ns; | |
4411 | ||
4412 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4413 | timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc); | |
4414 | else | |
4415 | timeout_ns = udev->u2_params.sel; | |
4416 | ||
e3567d2c | 4417 | /* The U2 timeout is encoded in 256us intervals */ |
c88db160 | 4418 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000); |
e3567d2c SS |
4419 | /* If the necessary timeout value is bigger than what we can set in the |
4420 | * USB 3.0 hub, we have to disable hub-initiated U2. | |
4421 | */ | |
4422 | if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT) | |
4423 | return timeout_ns; | |
4424 | dev_dbg(&udev->dev, "Hub-initiated U2 disabled " | |
4425 | "due to long timeout %llu ms\n", timeout_ns); | |
4426 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2); | |
4427 | } | |
4428 | ||
3b3db026 SS |
4429 | static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci, |
4430 | struct usb_device *udev, | |
4431 | struct usb_endpoint_descriptor *desc, | |
4432 | enum usb3_link_state state, | |
4433 | u16 *timeout) | |
4434 | { | |
9502c46c PA |
4435 | if (state == USB3_LPM_U1) |
4436 | return xhci_calculate_u1_timeout(xhci, udev, desc); | |
4437 | else if (state == USB3_LPM_U2) | |
4438 | return xhci_calculate_u2_timeout(xhci, udev, desc); | |
e3567d2c | 4439 | |
3b3db026 SS |
4440 | return USB3_LPM_DISABLED; |
4441 | } | |
4442 | ||
4443 | static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci, | |
4444 | struct usb_device *udev, | |
4445 | struct usb_endpoint_descriptor *desc, | |
4446 | enum usb3_link_state state, | |
4447 | u16 *timeout) | |
4448 | { | |
4449 | u16 alt_timeout; | |
4450 | ||
4451 | alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev, | |
4452 | desc, state, timeout); | |
4453 | ||
4454 | /* If we found we can't enable hub-initiated LPM, or | |
4455 | * the U1 or U2 exit latency was too high to allow | |
4456 | * device-initiated LPM as well, just stop searching. | |
4457 | */ | |
4458 | if (alt_timeout == USB3_LPM_DISABLED || | |
4459 | alt_timeout == USB3_LPM_DEVICE_INITIATED) { | |
4460 | *timeout = alt_timeout; | |
4461 | return -E2BIG; | |
4462 | } | |
4463 | if (alt_timeout > *timeout) | |
4464 | *timeout = alt_timeout; | |
4465 | return 0; | |
4466 | } | |
4467 | ||
4468 | static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci, | |
4469 | struct usb_device *udev, | |
4470 | struct usb_host_interface *alt, | |
4471 | enum usb3_link_state state, | |
4472 | u16 *timeout) | |
4473 | { | |
4474 | int j; | |
4475 | ||
4476 | for (j = 0; j < alt->desc.bNumEndpoints; j++) { | |
4477 | if (xhci_update_timeout_for_endpoint(xhci, udev, | |
4478 | &alt->endpoint[j].desc, state, timeout)) | |
4479 | return -E2BIG; | |
4480 | continue; | |
4481 | } | |
4482 | return 0; | |
4483 | } | |
4484 | ||
e3567d2c SS |
4485 | static int xhci_check_intel_tier_policy(struct usb_device *udev, |
4486 | enum usb3_link_state state) | |
4487 | { | |
4488 | struct usb_device *parent; | |
4489 | unsigned int num_hubs; | |
4490 | ||
4491 | if (state == USB3_LPM_U2) | |
4492 | return 0; | |
4493 | ||
4494 | /* Don't enable U1 if the device is on a 2nd tier hub or lower. */ | |
4495 | for (parent = udev->parent, num_hubs = 0; parent->parent; | |
4496 | parent = parent->parent) | |
4497 | num_hubs++; | |
4498 | ||
4499 | if (num_hubs < 2) | |
4500 | return 0; | |
4501 | ||
4502 | dev_dbg(&udev->dev, "Disabling U1 link state for device" | |
4503 | " below second-tier hub.\n"); | |
4504 | dev_dbg(&udev->dev, "Plug device into first-tier hub " | |
4505 | "to decrease power consumption.\n"); | |
4506 | return -E2BIG; | |
4507 | } | |
4508 | ||
3b3db026 SS |
4509 | static int xhci_check_tier_policy(struct xhci_hcd *xhci, |
4510 | struct usb_device *udev, | |
4511 | enum usb3_link_state state) | |
4512 | { | |
e3567d2c SS |
4513 | if (xhci->quirks & XHCI_INTEL_HOST) |
4514 | return xhci_check_intel_tier_policy(udev, state); | |
9502c46c PA |
4515 | else |
4516 | return 0; | |
3b3db026 SS |
4517 | } |
4518 | ||
4519 | /* Returns the U1 or U2 timeout that should be enabled. | |
4520 | * If the tier check or timeout setting functions return with a non-zero exit | |
4521 | * code, that means the timeout value has been finalized and we shouldn't look | |
4522 | * at any more endpoints. | |
4523 | */ | |
4524 | static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd, | |
4525 | struct usb_device *udev, enum usb3_link_state state) | |
4526 | { | |
4527 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4528 | struct usb_host_config *config; | |
4529 | char *state_name; | |
4530 | int i; | |
4531 | u16 timeout = USB3_LPM_DISABLED; | |
4532 | ||
4533 | if (state == USB3_LPM_U1) | |
4534 | state_name = "U1"; | |
4535 | else if (state == USB3_LPM_U2) | |
4536 | state_name = "U2"; | |
4537 | else { | |
4538 | dev_warn(&udev->dev, "Can't enable unknown link state %i\n", | |
4539 | state); | |
4540 | return timeout; | |
4541 | } | |
4542 | ||
4543 | if (xhci_check_tier_policy(xhci, udev, state) < 0) | |
4544 | return timeout; | |
4545 | ||
4546 | /* Gather some information about the currently installed configuration | |
4547 | * and alternate interface settings. | |
4548 | */ | |
4549 | if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc, | |
4550 | state, &timeout)) | |
4551 | return timeout; | |
4552 | ||
4553 | config = udev->actconfig; | |
4554 | if (!config) | |
4555 | return timeout; | |
4556 | ||
64ba419b | 4557 | for (i = 0; i < config->desc.bNumInterfaces; i++) { |
3b3db026 SS |
4558 | struct usb_driver *driver; |
4559 | struct usb_interface *intf = config->interface[i]; | |
4560 | ||
4561 | if (!intf) | |
4562 | continue; | |
4563 | ||
4564 | /* Check if any currently bound drivers want hub-initiated LPM | |
4565 | * disabled. | |
4566 | */ | |
4567 | if (intf->dev.driver) { | |
4568 | driver = to_usb_driver(intf->dev.driver); | |
4569 | if (driver && driver->disable_hub_initiated_lpm) { | |
4570 | dev_dbg(&udev->dev, "Hub-initiated %s disabled " | |
4571 | "at request of driver %s\n", | |
4572 | state_name, driver->name); | |
4573 | return xhci_get_timeout_no_hub_lpm(udev, state); | |
4574 | } | |
4575 | } | |
4576 | ||
4577 | /* Not sure how this could happen... */ | |
4578 | if (!intf->cur_altsetting) | |
4579 | continue; | |
4580 | ||
4581 | if (xhci_update_timeout_for_interface(xhci, udev, | |
4582 | intf->cur_altsetting, | |
4583 | state, &timeout)) | |
4584 | return timeout; | |
4585 | } | |
4586 | return timeout; | |
4587 | } | |
4588 | ||
3b3db026 SS |
4589 | static int calculate_max_exit_latency(struct usb_device *udev, |
4590 | enum usb3_link_state state_changed, | |
4591 | u16 hub_encoded_timeout) | |
4592 | { | |
4593 | unsigned long long u1_mel_us = 0; | |
4594 | unsigned long long u2_mel_us = 0; | |
4595 | unsigned long long mel_us = 0; | |
4596 | bool disabling_u1; | |
4597 | bool disabling_u2; | |
4598 | bool enabling_u1; | |
4599 | bool enabling_u2; | |
4600 | ||
4601 | disabling_u1 = (state_changed == USB3_LPM_U1 && | |
4602 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4603 | disabling_u2 = (state_changed == USB3_LPM_U2 && | |
4604 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4605 | ||
4606 | enabling_u1 = (state_changed == USB3_LPM_U1 && | |
4607 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4608 | enabling_u2 = (state_changed == USB3_LPM_U2 && | |
4609 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4610 | ||
4611 | /* If U1 was already enabled and we're not disabling it, | |
4612 | * or we're going to enable U1, account for the U1 max exit latency. | |
4613 | */ | |
4614 | if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) || | |
4615 | enabling_u1) | |
4616 | u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000); | |
4617 | if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) || | |
4618 | enabling_u2) | |
4619 | u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000); | |
4620 | ||
4621 | if (u1_mel_us > u2_mel_us) | |
4622 | mel_us = u1_mel_us; | |
4623 | else | |
4624 | mel_us = u2_mel_us; | |
4625 | /* xHCI host controller max exit latency field is only 16 bits wide. */ | |
4626 | if (mel_us > MAX_EXIT) { | |
4627 | dev_warn(&udev->dev, "Link PM max exit latency of %lluus " | |
4628 | "is too big.\n", mel_us); | |
4629 | return -E2BIG; | |
4630 | } | |
4631 | return mel_us; | |
4632 | } | |
4633 | ||
4634 | /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */ | |
4635 | int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, | |
4636 | struct usb_device *udev, enum usb3_link_state state) | |
4637 | { | |
4638 | struct xhci_hcd *xhci; | |
4639 | u16 hub_encoded_timeout; | |
4640 | int mel; | |
4641 | int ret; | |
4642 | ||
4643 | xhci = hcd_to_xhci(hcd); | |
4644 | /* The LPM timeout values are pretty host-controller specific, so don't | |
4645 | * enable hub-initiated timeouts unless the vendor has provided | |
4646 | * information about their timeout algorithm. | |
4647 | */ | |
4648 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4649 | !xhci->devs[udev->slot_id]) | |
4650 | return USB3_LPM_DISABLED; | |
4651 | ||
4652 | hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state); | |
4653 | mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout); | |
4654 | if (mel < 0) { | |
4655 | /* Max Exit Latency is too big, disable LPM. */ | |
4656 | hub_encoded_timeout = USB3_LPM_DISABLED; | |
4657 | mel = 0; | |
4658 | } | |
4659 | ||
4660 | ret = xhci_change_max_exit_latency(xhci, udev, mel); | |
4661 | if (ret) | |
4662 | return ret; | |
4663 | return hub_encoded_timeout; | |
4664 | } | |
4665 | ||
4666 | int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, | |
4667 | struct usb_device *udev, enum usb3_link_state state) | |
4668 | { | |
4669 | struct xhci_hcd *xhci; | |
4670 | u16 mel; | |
3b3db026 SS |
4671 | |
4672 | xhci = hcd_to_xhci(hcd); | |
4673 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4674 | !xhci->devs[udev->slot_id]) | |
4675 | return 0; | |
4676 | ||
4677 | mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED); | |
f1cda54c | 4678 | return xhci_change_max_exit_latency(xhci, udev, mel); |
3b3db026 | 4679 | } |
b01bcbf7 | 4680 | #else /* CONFIG_PM */ |
9574323c | 4681 | |
ceb6c9c8 RW |
4682 | int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
4683 | struct usb_device *udev, int enable) | |
4684 | { | |
4685 | return 0; | |
4686 | } | |
4687 | ||
4688 | int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) | |
4689 | { | |
4690 | return 0; | |
4691 | } | |
4692 | ||
b01bcbf7 SS |
4693 | int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
4694 | struct usb_device *udev, enum usb3_link_state state) | |
65580b43 | 4695 | { |
b01bcbf7 | 4696 | return USB3_LPM_DISABLED; |
65580b43 AX |
4697 | } |
4698 | ||
b01bcbf7 SS |
4699 | int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, |
4700 | struct usb_device *udev, enum usb3_link_state state) | |
9574323c AX |
4701 | { |
4702 | return 0; | |
4703 | } | |
b01bcbf7 | 4704 | #endif /* CONFIG_PM */ |
9574323c | 4705 | |
b01bcbf7 | 4706 | /*-------------------------------------------------------------------------*/ |
9574323c | 4707 | |
ac1c1b7f SS |
4708 | /* Once a hub descriptor is fetched for a device, we need to update the xHC's |
4709 | * internal data structures for the device. | |
4710 | */ | |
4711 | int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, | |
4712 | struct usb_tt *tt, gfp_t mem_flags) | |
4713 | { | |
4714 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4715 | struct xhci_virt_device *vdev; | |
4716 | struct xhci_command *config_cmd; | |
4717 | struct xhci_input_control_ctx *ctrl_ctx; | |
4718 | struct xhci_slot_ctx *slot_ctx; | |
4719 | unsigned long flags; | |
4720 | unsigned think_time; | |
4721 | int ret; | |
4722 | ||
4723 | /* Ignore root hubs */ | |
4724 | if (!hdev->parent) | |
4725 | return 0; | |
4726 | ||
4727 | vdev = xhci->devs[hdev->slot_id]; | |
4728 | if (!vdev) { | |
4729 | xhci_warn(xhci, "Cannot update hub desc for unknown device.\n"); | |
4730 | return -EINVAL; | |
4731 | } | |
a1d78c16 | 4732 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); |
ac1c1b7f SS |
4733 | if (!config_cmd) { |
4734 | xhci_dbg(xhci, "Could not allocate xHCI command structure.\n"); | |
4735 | return -ENOMEM; | |
4736 | } | |
4daf9df5 | 4737 | ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx); |
92f8e767 SS |
4738 | if (!ctrl_ctx) { |
4739 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
4740 | __func__); | |
4741 | xhci_free_command(xhci, config_cmd); | |
4742 | return -ENOMEM; | |
4743 | } | |
ac1c1b7f SS |
4744 | |
4745 | spin_lock_irqsave(&xhci->lock, flags); | |
839c817c SS |
4746 | if (hdev->speed == USB_SPEED_HIGH && |
4747 | xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) { | |
4748 | xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n"); | |
4749 | xhci_free_command(xhci, config_cmd); | |
4750 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4751 | return -ENOMEM; | |
4752 | } | |
4753 | ||
ac1c1b7f | 4754 | xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx); |
28ccd296 | 4755 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
ac1c1b7f | 4756 | slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx); |
28ccd296 | 4757 | slot_ctx->dev_info |= cpu_to_le32(DEV_HUB); |
096b110a CY |
4758 | /* |
4759 | * refer to section 6.2.2: MTT should be 0 for full speed hub, | |
4760 | * but it may be already set to 1 when setup an xHCI virtual | |
4761 | * device, so clear it anyway. | |
4762 | */ | |
ac1c1b7f | 4763 | if (tt->multi) |
28ccd296 | 4764 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
096b110a CY |
4765 | else if (hdev->speed == USB_SPEED_FULL) |
4766 | slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT); | |
4767 | ||
ac1c1b7f SS |
4768 | if (xhci->hci_version > 0x95) { |
4769 | xhci_dbg(xhci, "xHCI version %x needs hub " | |
4770 | "TT think time and number of ports\n", | |
4771 | (unsigned int) xhci->hci_version); | |
28ccd296 | 4772 | slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild)); |
ac1c1b7f SS |
4773 | /* Set TT think time - convert from ns to FS bit times. |
4774 | * 0 = 8 FS bit times, 1 = 16 FS bit times, | |
4775 | * 2 = 24 FS bit times, 3 = 32 FS bit times. | |
700b4173 AX |
4776 | * |
4777 | * xHCI 1.0: this field shall be 0 if the device is not a | |
4778 | * High-spped hub. | |
ac1c1b7f SS |
4779 | */ |
4780 | think_time = tt->think_time; | |
4781 | if (think_time != 0) | |
4782 | think_time = (think_time / 666) - 1; | |
700b4173 AX |
4783 | if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH) |
4784 | slot_ctx->tt_info |= | |
4785 | cpu_to_le32(TT_THINK_TIME(think_time)); | |
ac1c1b7f SS |
4786 | } else { |
4787 | xhci_dbg(xhci, "xHCI version %x doesn't need hub " | |
4788 | "TT think time or number of ports\n", | |
4789 | (unsigned int) xhci->hci_version); | |
4790 | } | |
4791 | slot_ctx->dev_state = 0; | |
4792 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4793 | ||
4794 | xhci_dbg(xhci, "Set up %s for hub device.\n", | |
4795 | (xhci->hci_version > 0x95) ? | |
4796 | "configure endpoint" : "evaluate context"); | |
4797 | xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id); | |
4798 | xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0); | |
4799 | ||
4800 | /* Issue and wait for the configure endpoint or | |
4801 | * evaluate context command. | |
4802 | */ | |
4803 | if (xhci->hci_version > 0x95) | |
4804 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4805 | false, false); | |
4806 | else | |
4807 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4808 | true, false); | |
4809 | ||
4810 | xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id); | |
4811 | xhci_dbg_ctx(xhci, vdev->out_ctx, 0); | |
4812 | ||
4813 | xhci_free_command(xhci, config_cmd); | |
4814 | return ret; | |
4815 | } | |
4816 | ||
66d4eadd SS |
4817 | int xhci_get_frame(struct usb_hcd *hcd) |
4818 | { | |
4819 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4820 | /* EHCI mods by the periodic size. Why? */ | |
b0ba9720 | 4821 | return readl(&xhci->run_regs->microframe_index) >> 3; |
66d4eadd SS |
4822 | } |
4823 | ||
552e0c4f SAS |
4824 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) |
4825 | { | |
4826 | struct xhci_hcd *xhci; | |
4c39d4b9 AB |
4827 | /* |
4828 | * TODO: Check with DWC3 clients for sysdev according to | |
4829 | * quirks | |
4830 | */ | |
4831 | struct device *dev = hcd->self.sysdev; | |
552e0c4f | 4832 | int retval; |
552e0c4f | 4833 | |
1386ff75 SS |
4834 | /* Accept arbitrarily long scatter-gather lists */ |
4835 | hcd->self.sg_tablesize = ~0; | |
fc76051c | 4836 | |
e2ed5114 MN |
4837 | /* support to build packet from discontinuous buffers */ |
4838 | hcd->self.no_sg_constraint = 1; | |
4839 | ||
19181bc5 HG |
4840 | /* XHCI controllers don't stop the ep queue on short packets :| */ |
4841 | hcd->self.no_stop_on_short = 1; | |
552e0c4f | 4842 | |
b50107bb MN |
4843 | xhci = hcd_to_xhci(hcd); |
4844 | ||
552e0c4f | 4845 | if (usb_hcd_is_primary_hcd(hcd)) { |
552e0c4f SAS |
4846 | xhci->main_hcd = hcd; |
4847 | /* Mark the first roothub as being USB 2.0. | |
4848 | * The xHCI driver will register the USB 3.0 roothub. | |
4849 | */ | |
4850 | hcd->speed = HCD_USB2; | |
4851 | hcd->self.root_hub->speed = USB_SPEED_HIGH; | |
4852 | /* | |
4853 | * USB 2.0 roothub under xHCI has an integrated TT, | |
4854 | * (rate matching hub) as opposed to having an OHCI/UHCI | |
4855 | * companion controller. | |
4856 | */ | |
4857 | hcd->has_tt = 1; | |
4858 | } else { | |
b50107bb MN |
4859 | if (xhci->sbrn == 0x31) { |
4860 | xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n"); | |
4861 | hcd->speed = HCD_USB31; | |
2c0e06f8 | 4862 | hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS; |
b50107bb | 4863 | } |
552e0c4f SAS |
4864 | /* xHCI private pointer was set in xhci_pci_probe for the second |
4865 | * registered roothub. | |
4866 | */ | |
552e0c4f SAS |
4867 | return 0; |
4868 | } | |
4869 | ||
a00918d0 | 4870 | mutex_init(&xhci->mutex); |
552e0c4f SAS |
4871 | xhci->cap_regs = hcd->regs; |
4872 | xhci->op_regs = hcd->regs + | |
b0ba9720 | 4873 | HC_LENGTH(readl(&xhci->cap_regs->hc_capbase)); |
552e0c4f | 4874 | xhci->run_regs = hcd->regs + |
b0ba9720 | 4875 | (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK); |
552e0c4f | 4876 | /* Cache read-only capability registers */ |
b0ba9720 XR |
4877 | xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1); |
4878 | xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2); | |
4879 | xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3); | |
4880 | xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase); | |
552e0c4f | 4881 | xhci->hci_version = HC_VERSION(xhci->hcc_params); |
b0ba9720 | 4882 | xhci->hcc_params = readl(&xhci->cap_regs->hcc_params); |
04abb6de LB |
4883 | if (xhci->hci_version > 0x100) |
4884 | xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2); | |
552e0c4f SAS |
4885 | xhci_print_registers(xhci); |
4886 | ||
757de492 | 4887 | xhci->quirks |= quirks; |
4e6a1ee7 | 4888 | |
552e0c4f SAS |
4889 | get_quirks(dev, xhci); |
4890 | ||
07f3cb7c GC |
4891 | /* In xhci controllers which follow xhci 1.0 spec gives a spurious |
4892 | * success event after a short transfer. This quirk will ignore such | |
4893 | * spurious event. | |
4894 | */ | |
4895 | if (xhci->hci_version > 0x96) | |
4896 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; | |
4897 | ||
552e0c4f SAS |
4898 | /* Make sure the HC is halted. */ |
4899 | retval = xhci_halt(xhci); | |
4900 | if (retval) | |
cd33a321 | 4901 | return retval; |
552e0c4f SAS |
4902 | |
4903 | xhci_dbg(xhci, "Resetting HCD\n"); | |
4904 | /* Reset the internal HC memory state and registers. */ | |
4905 | retval = xhci_reset(xhci); | |
4906 | if (retval) | |
cd33a321 | 4907 | return retval; |
552e0c4f SAS |
4908 | xhci_dbg(xhci, "Reset complete\n"); |
4909 | ||
0a380be8 YS |
4910 | /* |
4911 | * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0) | |
4912 | * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit | |
4913 | * address memory pointers actually. So, this driver clears the AC64 | |
4914 | * bit of xhci->hcc_params to call dma_set_coherent_mask(dev, | |
4915 | * DMA_BIT_MASK(32)) in this xhci_gen_setup(). | |
4916 | */ | |
4917 | if (xhci->quirks & XHCI_NO_64BIT_SUPPORT) | |
4918 | xhci->hcc_params &= ~BIT(0); | |
4919 | ||
c10cf118 XR |
4920 | /* Set dma_mask and coherent_dma_mask to 64-bits, |
4921 | * if xHC supports 64-bit addressing */ | |
4922 | if (HCC_64BIT_ADDR(xhci->hcc_params) && | |
4923 | !dma_set_mask(dev, DMA_BIT_MASK(64))) { | |
552e0c4f | 4924 | xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); |
c10cf118 | 4925 | dma_set_coherent_mask(dev, DMA_BIT_MASK(64)); |
fda182d8 DD |
4926 | } else { |
4927 | /* | |
4928 | * This is to avoid error in cases where a 32-bit USB | |
4929 | * controller is used on a 64-bit capable system. | |
4930 | */ | |
4931 | retval = dma_set_mask(dev, DMA_BIT_MASK(32)); | |
4932 | if (retval) | |
4933 | return retval; | |
4934 | xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n"); | |
4935 | dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); | |
552e0c4f SAS |
4936 | } |
4937 | ||
4938 | xhci_dbg(xhci, "Calling HCD init\n"); | |
4939 | /* Initialize HCD and host controller data structures. */ | |
4940 | retval = xhci_init(hcd); | |
4941 | if (retval) | |
cd33a321 | 4942 | return retval; |
552e0c4f | 4943 | xhci_dbg(xhci, "Called HCD init\n"); |
99705092 HG |
4944 | |
4945 | xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n", | |
4946 | xhci->hcc_params, xhci->hci_version, xhci->quirks); | |
4947 | ||
552e0c4f | 4948 | return 0; |
552e0c4f | 4949 | } |
436e8c7d | 4950 | EXPORT_SYMBOL_GPL(xhci_gen_setup); |
552e0c4f | 4951 | |
1885d9a3 AB |
4952 | static const struct hc_driver xhci_hc_driver = { |
4953 | .description = "xhci-hcd", | |
4954 | .product_desc = "xHCI Host Controller", | |
32479d4b | 4955 | .hcd_priv_size = sizeof(struct xhci_hcd), |
1885d9a3 AB |
4956 | |
4957 | /* | |
4958 | * generic hardware linkage | |
4959 | */ | |
4960 | .irq = xhci_irq, | |
4961 | .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, | |
4962 | ||
4963 | /* | |
4964 | * basic lifecycle operations | |
4965 | */ | |
4966 | .reset = NULL, /* set in xhci_init_driver() */ | |
4967 | .start = xhci_run, | |
4968 | .stop = xhci_stop, | |
4969 | .shutdown = xhci_shutdown, | |
4970 | ||
4971 | /* | |
4972 | * managing i/o requests and associated device resources | |
4973 | */ | |
4974 | .urb_enqueue = xhci_urb_enqueue, | |
4975 | .urb_dequeue = xhci_urb_dequeue, | |
4976 | .alloc_dev = xhci_alloc_dev, | |
4977 | .free_dev = xhci_free_dev, | |
4978 | .alloc_streams = xhci_alloc_streams, | |
4979 | .free_streams = xhci_free_streams, | |
4980 | .add_endpoint = xhci_add_endpoint, | |
4981 | .drop_endpoint = xhci_drop_endpoint, | |
4982 | .endpoint_reset = xhci_endpoint_reset, | |
4983 | .check_bandwidth = xhci_check_bandwidth, | |
4984 | .reset_bandwidth = xhci_reset_bandwidth, | |
4985 | .address_device = xhci_address_device, | |
4986 | .enable_device = xhci_enable_device, | |
4987 | .update_hub_device = xhci_update_hub_device, | |
4988 | .reset_device = xhci_discover_or_reset_device, | |
4989 | ||
4990 | /* | |
4991 | * scheduling support | |
4992 | */ | |
4993 | .get_frame_number = xhci_get_frame, | |
4994 | ||
4995 | /* | |
4996 | * root hub support | |
4997 | */ | |
4998 | .hub_control = xhci_hub_control, | |
4999 | .hub_status_data = xhci_hub_status_data, | |
5000 | .bus_suspend = xhci_bus_suspend, | |
5001 | .bus_resume = xhci_bus_resume, | |
5002 | ||
5003 | /* | |
5004 | * call back when device connected and addressed | |
5005 | */ | |
5006 | .update_device = xhci_update_device, | |
5007 | .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, | |
5008 | .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, | |
5009 | .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, | |
5010 | .find_raw_port_number = xhci_find_raw_port_number, | |
5011 | }; | |
5012 | ||
cd33a321 RQ |
5013 | void xhci_init_driver(struct hc_driver *drv, |
5014 | const struct xhci_driver_overrides *over) | |
1885d9a3 | 5015 | { |
cd33a321 RQ |
5016 | BUG_ON(!over); |
5017 | ||
5018 | /* Copy the generic table to drv then apply the overrides */ | |
1885d9a3 | 5019 | *drv = xhci_hc_driver; |
cd33a321 RQ |
5020 | |
5021 | if (over) { | |
5022 | drv->hcd_priv_size += over->extra_priv_size; | |
5023 | if (over->reset) | |
5024 | drv->reset = over->reset; | |
5025 | if (over->start) | |
5026 | drv->start = over->start; | |
5027 | } | |
1885d9a3 AB |
5028 | } |
5029 | EXPORT_SYMBOL_GPL(xhci_init_driver); | |
5030 | ||
66d4eadd SS |
5031 | MODULE_DESCRIPTION(DRIVER_DESC); |
5032 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
5033 | MODULE_LICENSE("GPL"); | |
5034 | ||
5035 | static int __init xhci_hcd_init(void) | |
5036 | { | |
98441973 SS |
5037 | /* |
5038 | * Check the compiler generated sizes of structures that must be laid | |
5039 | * out in specific ways for hardware access. | |
5040 | */ | |
5041 | BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8); | |
5042 | BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8); | |
5043 | BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8); | |
5044 | /* xhci_device_control has eight fields, and also | |
5045 | * embeds one xhci_slot_ctx and 31 xhci_ep_ctx | |
5046 | */ | |
98441973 SS |
5047 | BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8); |
5048 | BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8); | |
5049 | BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8); | |
04abb6de | 5050 | BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8); |
98441973 SS |
5051 | BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8); |
5052 | /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */ | |
5053 | BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8); | |
1eaf35e4 ON |
5054 | |
5055 | if (usb_disabled()) | |
5056 | return -ENODEV; | |
5057 | ||
66d4eadd SS |
5058 | return 0; |
5059 | } | |
b04c846c AD |
5060 | |
5061 | /* | |
5062 | * If an init function is provided, an exit function must also be provided | |
5063 | * to allow module unload. | |
5064 | */ | |
5065 | static void __exit xhci_hcd_fini(void) { } | |
5066 | ||
66d4eadd | 5067 | module_init(xhci_hcd_init); |
b04c846c | 5068 | module_exit(xhci_hcd_fini); |