usb: Don't fail port power resume on device disconnect.
[linux-block.git] / drivers / usb / host / xhci.c
CommitLineData
66d4eadd
SS
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
43b86af8 23#include <linux/pci.h>
66d4eadd 24#include <linux/irq.h>
8df75f42 25#include <linux/log2.h>
66d4eadd 26#include <linux/module.h>
b0567b3f 27#include <linux/moduleparam.h>
5a0e3ad6 28#include <linux/slab.h>
71c731a2 29#include <linux/dmi.h>
008eb957 30#include <linux/dma-mapping.h>
66d4eadd
SS
31
32#include "xhci.h"
33
34#define DRIVER_AUTHOR "Sarah Sharp"
35#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
36
b0567b3f
SS
37/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
38static int link_quirk;
39module_param(link_quirk, int, S_IRUGO | S_IWUSR);
40MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
41
66d4eadd
SS
42/* TODO: copied from ehci-hcd.c - can this be refactored? */
43/*
2611bd18 44 * xhci_handshake - spin reading hc until handshake completes or fails
66d4eadd
SS
45 * @ptr: address of hc register to be read
46 * @mask: bits to look at in result of read
47 * @done: value of those bits when handshake succeeds
48 * @usec: timeout in microseconds
49 *
50 * Returns negative errno, or zero on success
51 *
52 * Success happens when the "mask" bits have the specified value (hardware
53 * handshake done). There are two failure modes: "usec" have passed (major
54 * hardware flakeout), or the register reads as all-ones (hardware removed).
55 */
2611bd18 56int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
66d4eadd
SS
57 u32 mask, u32 done, int usec)
58{
59 u32 result;
60
61 do {
62 result = xhci_readl(xhci, ptr);
63 if (result == ~(u32)0) /* card removed */
64 return -ENODEV;
65 result &= mask;
66 if (result == done)
67 return 0;
68 udelay(1);
69 usec--;
70 } while (usec > 0);
71 return -ETIMEDOUT;
72}
73
74/*
4f0f0bae 75 * Disable interrupts and begin the xHCI halting process.
66d4eadd 76 */
4f0f0bae 77void xhci_quiesce(struct xhci_hcd *xhci)
66d4eadd
SS
78{
79 u32 halted;
80 u32 cmd;
81 u32 mask;
82
66d4eadd
SS
83 mask = ~(XHCI_IRQS);
84 halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
85 if (!halted)
86 mask &= ~CMD_RUN;
87
88 cmd = xhci_readl(xhci, &xhci->op_regs->command);
89 cmd &= mask;
90 xhci_writel(xhci, cmd, &xhci->op_regs->command);
4f0f0bae
SS
91}
92
93/*
94 * Force HC into halt state.
95 *
96 * Disable any IRQs and clear the run/stop bit.
97 * HC will complete any current and actively pipelined transactions, and
bdfca502 98 * should halt within 16 ms of the run/stop bit being cleared.
4f0f0bae 99 * Read HC Halted bit in the status register to see when the HC is finished.
4f0f0bae
SS
100 */
101int xhci_halt(struct xhci_hcd *xhci)
102{
c6cc27c7 103 int ret;
4f0f0bae
SS
104 xhci_dbg(xhci, "// Halt the HC\n");
105 xhci_quiesce(xhci);
66d4eadd 106
2611bd18 107 ret = xhci_handshake(xhci, &xhci->op_regs->status,
66d4eadd 108 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
c181bc5b 109 if (!ret) {
c6cc27c7 110 xhci->xhc_state |= XHCI_STATE_HALTED;
c181bc5b
EF
111 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
112 } else
5af98bb0
SS
113 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
114 XHCI_MAX_HALT_USEC);
c6cc27c7 115 return ret;
66d4eadd
SS
116}
117
ed07453f
SS
118/*
119 * Set the run bit and wait for the host to be running.
120 */
8212a49d 121static int xhci_start(struct xhci_hcd *xhci)
ed07453f
SS
122{
123 u32 temp;
124 int ret;
125
126 temp = xhci_readl(xhci, &xhci->op_regs->command);
127 temp |= (CMD_RUN);
128 xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
129 temp);
130 xhci_writel(xhci, temp, &xhci->op_regs->command);
131
132 /*
133 * Wait for the HCHalted Status bit to be 0 to indicate the host is
134 * running.
135 */
2611bd18 136 ret = xhci_handshake(xhci, &xhci->op_regs->status,
ed07453f
SS
137 STS_HALT, 0, XHCI_MAX_HALT_USEC);
138 if (ret == -ETIMEDOUT)
139 xhci_err(xhci, "Host took too long to start, "
140 "waited %u microseconds.\n",
141 XHCI_MAX_HALT_USEC);
c6cc27c7
SS
142 if (!ret)
143 xhci->xhc_state &= ~XHCI_STATE_HALTED;
ed07453f
SS
144 return ret;
145}
146
66d4eadd 147/*
ac04e6ff 148 * Reset a halted HC.
66d4eadd
SS
149 *
150 * This resets pipelines, timers, counters, state machines, etc.
151 * Transactions will be terminated immediately, and operational registers
152 * will be set to their defaults.
153 */
154int xhci_reset(struct xhci_hcd *xhci)
155{
156 u32 command;
157 u32 state;
f370b996 158 int ret, i;
66d4eadd
SS
159
160 state = xhci_readl(xhci, &xhci->op_regs->status);
d3512f63
SS
161 if ((state & STS_HALT) == 0) {
162 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
163 return 0;
164 }
66d4eadd
SS
165
166 xhci_dbg(xhci, "// Reset the HC\n");
167 command = xhci_readl(xhci, &xhci->op_regs->command);
168 command |= CMD_RESET;
169 xhci_writel(xhci, command, &xhci->op_regs->command);
66d4eadd 170
2611bd18 171 ret = xhci_handshake(xhci, &xhci->op_regs->command,
22ceac19 172 CMD_RESET, 0, 10 * 1000 * 1000);
2d62f3ee
SS
173 if (ret)
174 return ret;
175
176 xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
177 /*
178 * xHCI cannot write to any doorbells or operational registers other
179 * than status until the "Controller Not Ready" flag is cleared.
180 */
2611bd18 181 ret = xhci_handshake(xhci, &xhci->op_regs->status,
22ceac19 182 STS_CNR, 0, 10 * 1000 * 1000);
f370b996
AX
183
184 for (i = 0; i < 2; ++i) {
185 xhci->bus_state[i].port_c_suspend = 0;
186 xhci->bus_state[i].suspended_ports = 0;
187 xhci->bus_state[i].resuming_ports = 0;
188 }
189
190 return ret;
66d4eadd
SS
191}
192
421aa841
SAS
193#ifdef CONFIG_PCI
194static int xhci_free_msi(struct xhci_hcd *xhci)
43b86af8
DN
195{
196 int i;
43b86af8 197
421aa841
SAS
198 if (!xhci->msix_entries)
199 return -EINVAL;
43b86af8 200
421aa841
SAS
201 for (i = 0; i < xhci->msix_count; i++)
202 if (xhci->msix_entries[i].vector)
203 free_irq(xhci->msix_entries[i].vector,
204 xhci_to_hcd(xhci));
205 return 0;
43b86af8
DN
206}
207
208/*
209 * Set up MSI
210 */
211static int xhci_setup_msi(struct xhci_hcd *xhci)
66d4eadd
SS
212{
213 int ret;
43b86af8
DN
214 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
215
216 ret = pci_enable_msi(pdev);
217 if (ret) {
3b9783b2 218 xhci_dbg(xhci, "failed to allocate MSI entry\n");
43b86af8
DN
219 return ret;
220 }
221
851ec164 222 ret = request_irq(pdev->irq, xhci_msi_irq,
43b86af8
DN
223 0, "xhci_hcd", xhci_to_hcd(xhci));
224 if (ret) {
3b9783b2 225 xhci_dbg(xhci, "disable MSI interrupt\n");
43b86af8
DN
226 pci_disable_msi(pdev);
227 }
228
229 return ret;
230}
231
421aa841
SAS
232/*
233 * Free IRQs
234 * free all IRQs request
235 */
236static void xhci_free_irq(struct xhci_hcd *xhci)
237{
238 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
239 int ret;
240
241 /* return if using legacy interrupt */
cd70469d 242 if (xhci_to_hcd(xhci)->irq > 0)
421aa841
SAS
243 return;
244
245 ret = xhci_free_msi(xhci);
246 if (!ret)
247 return;
cd70469d 248 if (pdev->irq > 0)
421aa841
SAS
249 free_irq(pdev->irq, xhci_to_hcd(xhci));
250
251 return;
252}
253
43b86af8
DN
254/*
255 * Set up MSI-X
256 */
257static int xhci_setup_msix(struct xhci_hcd *xhci)
258{
259 int i, ret = 0;
0029227f
AX
260 struct usb_hcd *hcd = xhci_to_hcd(xhci);
261 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
66d4eadd 262
43b86af8
DN
263 /*
264 * calculate number of msi-x vectors supported.
265 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
266 * with max number of interrupters based on the xhci HCSPARAMS1.
267 * - num_online_cpus: maximum msi-x vectors per CPUs core.
268 * Add additional 1 vector to ensure always available interrupt.
269 */
270 xhci->msix_count = min(num_online_cpus() + 1,
271 HCS_MAX_INTRS(xhci->hcs_params1));
272
273 xhci->msix_entries =
274 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
86871975 275 GFP_KERNEL);
66d4eadd
SS
276 if (!xhci->msix_entries) {
277 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
278 return -ENOMEM;
279 }
43b86af8
DN
280
281 for (i = 0; i < xhci->msix_count; i++) {
282 xhci->msix_entries[i].entry = i;
283 xhci->msix_entries[i].vector = 0;
284 }
66d4eadd
SS
285
286 ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
287 if (ret) {
3b9783b2 288 xhci_dbg(xhci, "Failed to enable MSI-X\n");
66d4eadd
SS
289 goto free_entries;
290 }
291
43b86af8
DN
292 for (i = 0; i < xhci->msix_count; i++) {
293 ret = request_irq(xhci->msix_entries[i].vector,
851ec164 294 xhci_msi_irq,
43b86af8
DN
295 0, "xhci_hcd", xhci_to_hcd(xhci));
296 if (ret)
297 goto disable_msix;
66d4eadd 298 }
43b86af8 299
0029227f 300 hcd->msix_enabled = 1;
43b86af8 301 return ret;
66d4eadd
SS
302
303disable_msix:
3b9783b2 304 xhci_dbg(xhci, "disable MSI-X interrupt\n");
43b86af8 305 xhci_free_irq(xhci);
66d4eadd
SS
306 pci_disable_msix(pdev);
307free_entries:
308 kfree(xhci->msix_entries);
309 xhci->msix_entries = NULL;
310 return ret;
311}
312
66d4eadd
SS
313/* Free any IRQs and disable MSI-X */
314static void xhci_cleanup_msix(struct xhci_hcd *xhci)
315{
0029227f
AX
316 struct usb_hcd *hcd = xhci_to_hcd(xhci);
317 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
66d4eadd 318
43b86af8
DN
319 xhci_free_irq(xhci);
320
321 if (xhci->msix_entries) {
322 pci_disable_msix(pdev);
323 kfree(xhci->msix_entries);
324 xhci->msix_entries = NULL;
325 } else {
326 pci_disable_msi(pdev);
327 }
328
0029227f 329 hcd->msix_enabled = 0;
43b86af8 330 return;
66d4eadd 331}
66d4eadd 332
d5c82feb 333static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
421aa841
SAS
334{
335 int i;
336
337 if (xhci->msix_entries) {
338 for (i = 0; i < xhci->msix_count; i++)
339 synchronize_irq(xhci->msix_entries[i].vector);
340 }
341}
342
343static int xhci_try_enable_msi(struct usb_hcd *hcd)
344{
345 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
346 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
347 int ret;
348
349 /*
350 * Some Fresco Logic host controllers advertise MSI, but fail to
351 * generate interrupts. Don't even try to enable MSI.
352 */
353 if (xhci->quirks & XHCI_BROKEN_MSI)
00eed9c8 354 goto legacy_irq;
421aa841
SAS
355
356 /* unregister the legacy interrupt */
357 if (hcd->irq)
358 free_irq(hcd->irq, hcd);
cd70469d 359 hcd->irq = 0;
421aa841
SAS
360
361 ret = xhci_setup_msix(xhci);
362 if (ret)
363 /* fall back to msi*/
364 ret = xhci_setup_msi(xhci);
365
366 if (!ret)
cd70469d 367 /* hcd->irq is 0, we have MSI */
421aa841
SAS
368 return 0;
369
68d07f64
SS
370 if (!pdev->irq) {
371 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
372 return -EINVAL;
373 }
374
00eed9c8 375 legacy_irq:
421aa841
SAS
376 /* fall back to legacy interrupt*/
377 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
378 hcd->irq_descr, hcd);
379 if (ret) {
380 xhci_err(xhci, "request interrupt %d failed\n",
381 pdev->irq);
382 return ret;
383 }
384 hcd->irq = pdev->irq;
385 return 0;
386}
387
388#else
389
390static int xhci_try_enable_msi(struct usb_hcd *hcd)
391{
392 return 0;
393}
394
395static void xhci_cleanup_msix(struct xhci_hcd *xhci)
396{
397}
398
399static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
400{
401}
402
403#endif
404
71c731a2
AC
405static void compliance_mode_recovery(unsigned long arg)
406{
407 struct xhci_hcd *xhci;
408 struct usb_hcd *hcd;
409 u32 temp;
410 int i;
411
412 xhci = (struct xhci_hcd *)arg;
413
414 for (i = 0; i < xhci->num_usb3_ports; i++) {
415 temp = xhci_readl(xhci, xhci->usb3_ports[i]);
416 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
417 /*
418 * Compliance Mode Detected. Letting USB Core
419 * handle the Warm Reset
420 */
58b1d799 421 xhci_dbg(xhci, "Compliance mode detected->port %d\n",
71c731a2 422 i + 1);
58b1d799 423 xhci_dbg(xhci, "Attempting compliance mode recovery\n");
71c731a2
AC
424 hcd = xhci->shared_hcd;
425
426 if (hcd->state == HC_STATE_SUSPENDED)
427 usb_hcd_resume_root_hub(hcd);
428
429 usb_hcd_poll_rh_status(hcd);
430 }
431 }
432
433 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
434 mod_timer(&xhci->comp_mode_recovery_timer,
435 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
436}
437
438/*
439 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
440 * that causes ports behind that hardware to enter compliance mode sometimes.
441 * The quirk creates a timer that polls every 2 seconds the link state of
442 * each host controller's port and recovers it by issuing a Warm reset
443 * if Compliance mode is detected, otherwise the port will become "dead" (no
444 * device connections or disconnections will be detected anymore). Becasue no
445 * status event is generated when entering compliance mode (per xhci spec),
446 * this quirk is needed on systems that have the failing hardware installed.
447 */
448static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
449{
450 xhci->port_status_u0 = 0;
451 init_timer(&xhci->comp_mode_recovery_timer);
452
453 xhci->comp_mode_recovery_timer.data = (unsigned long) xhci;
454 xhci->comp_mode_recovery_timer.function = compliance_mode_recovery;
455 xhci->comp_mode_recovery_timer.expires = jiffies +
456 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
457
458 set_timer_slack(&xhci->comp_mode_recovery_timer,
459 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
460 add_timer(&xhci->comp_mode_recovery_timer);
58b1d799 461 xhci_dbg(xhci, "Compliance mode recovery timer initialized\n");
71c731a2
AC
462}
463
464/*
465 * This function identifies the systems that have installed the SN65LVPE502CP
466 * USB3.0 re-driver and that need the Compliance Mode Quirk.
467 * Systems:
468 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
469 */
c3897aa5 470bool xhci_compliance_mode_recovery_timer_quirk_check(void)
71c731a2
AC
471{
472 const char *dmi_product_name, *dmi_sys_vendor;
473
474 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
475 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
457a73d3
VG
476 if (!dmi_product_name || !dmi_sys_vendor)
477 return false;
71c731a2
AC
478
479 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
480 return false;
481
482 if (strstr(dmi_product_name, "Z420") ||
483 strstr(dmi_product_name, "Z620") ||
47080974 484 strstr(dmi_product_name, "Z820") ||
b0e4e606 485 strstr(dmi_product_name, "Z1 Workstation"))
71c731a2
AC
486 return true;
487
488 return false;
489}
490
491static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
492{
493 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
494}
495
496
66d4eadd
SS
497/*
498 * Initialize memory for HCD and xHC (one-time init).
499 *
500 * Program the PAGESIZE register, initialize the device context array, create
501 * device contexts (?), set up a command ring segment (or two?), create event
502 * ring (one for now).
503 */
504int xhci_init(struct usb_hcd *hcd)
505{
506 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
507 int retval = 0;
508
509 xhci_dbg(xhci, "xhci_init\n");
510 spin_lock_init(&xhci->lock);
d7826599 511 if (xhci->hci_version == 0x95 && link_quirk) {
b0567b3f
SS
512 xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
513 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
514 } else {
ac9d8fe7 515 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
b0567b3f 516 }
66d4eadd
SS
517 retval = xhci_mem_init(xhci, GFP_KERNEL);
518 xhci_dbg(xhci, "Finished xhci_init\n");
519
71c731a2 520 /* Initializing Compliance Mode Recovery Data If Needed */
c3897aa5 521 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
71c731a2
AC
522 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
523 compliance_mode_recovery_timer_init(xhci);
524 }
525
66d4eadd
SS
526 return retval;
527}
528
7f84eef0
SS
529/*-------------------------------------------------------------------------*/
530
7f84eef0
SS
531
532#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
8212a49d 533static void xhci_event_ring_work(unsigned long arg)
7f84eef0
SS
534{
535 unsigned long flags;
536 int temp;
8e595a5d 537 u64 temp_64;
7f84eef0
SS
538 struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
539 int i, j;
540
541 xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
542
543 spin_lock_irqsave(&xhci->lock, flags);
544 temp = xhci_readl(xhci, &xhci->op_regs->status);
545 xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
7bd89b40
SS
546 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
547 (xhci->xhc_state & XHCI_STATE_HALTED)) {
e4ab05df
SS
548 xhci_dbg(xhci, "HW died, polling stopped.\n");
549 spin_unlock_irqrestore(&xhci->lock, flags);
550 return;
551 }
552
7f84eef0
SS
553 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
554 xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
7f84eef0
SS
555 xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
556 xhci->error_bitmask = 0;
557 xhci_dbg(xhci, "Event ring:\n");
558 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
559 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
8e595a5d
SS
560 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
561 temp_64 &= ~ERST_PTR_MASK;
562 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
7f84eef0
SS
563 xhci_dbg(xhci, "Command ring:\n");
564 xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
565 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
566 xhci_dbg_cmd_ptrs(xhci);
3ffbba95 567 for (i = 0; i < MAX_HC_SLOTS; ++i) {
63a0d9ab
SS
568 if (!xhci->devs[i])
569 continue;
570 for (j = 0; j < 31; ++j) {
e9df17eb 571 xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
3ffbba95
SS
572 }
573 }
7f84eef0
SS
574 spin_unlock_irqrestore(&xhci->lock, flags);
575
576 if (!xhci->zombie)
577 mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
578 else
579 xhci_dbg(xhci, "Quit polling the event ring.\n");
580}
581#endif
582
f6ff0ac8
SS
583static int xhci_run_finished(struct xhci_hcd *xhci)
584{
585 if (xhci_start(xhci)) {
586 xhci_halt(xhci);
587 return -ENODEV;
588 }
589 xhci->shared_hcd->state = HC_STATE_RUNNING;
c181bc5b 590 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
f6ff0ac8
SS
591
592 if (xhci->quirks & XHCI_NEC_HOST)
593 xhci_ring_cmd_db(xhci);
594
595 xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
596 return 0;
597}
598
66d4eadd
SS
599/*
600 * Start the HC after it was halted.
601 *
602 * This function is called by the USB core when the HC driver is added.
603 * Its opposite is xhci_stop().
604 *
605 * xhci_init() must be called once before this function can be called.
606 * Reset the HC, enable device slot contexts, program DCBAAP, and
607 * set command ring pointer and event ring pointer.
608 *
609 * Setup MSI-X vectors and enable interrupts.
610 */
611int xhci_run(struct usb_hcd *hcd)
612{
613 u32 temp;
8e595a5d 614 u64 temp_64;
3fd1ec58 615 int ret;
66d4eadd 616 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
66d4eadd 617
f6ff0ac8
SS
618 /* Start the xHCI host controller running only after the USB 2.0 roothub
619 * is setup.
620 */
66d4eadd 621
0f2a7930 622 hcd->uses_new_polling = 1;
f6ff0ac8
SS
623 if (!usb_hcd_is_primary_hcd(hcd))
624 return xhci_run_finished(xhci);
0f2a7930 625
7f84eef0 626 xhci_dbg(xhci, "xhci_run\n");
43b86af8 627
3fd1ec58 628 ret = xhci_try_enable_msi(hcd);
43b86af8 629 if (ret)
3fd1ec58 630 return ret;
66d4eadd 631
7f84eef0
SS
632#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
633 init_timer(&xhci->event_ring_timer);
634 xhci->event_ring_timer.data = (unsigned long) xhci;
23e3be11 635 xhci->event_ring_timer.function = xhci_event_ring_work;
7f84eef0
SS
636 /* Poll the event ring */
637 xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
638 xhci->zombie = 0;
639 xhci_dbg(xhci, "Setting event ring polling timer\n");
640 add_timer(&xhci->event_ring_timer);
641#endif
642
66e49d87
SS
643 xhci_dbg(xhci, "Command ring memory map follows:\n");
644 xhci_debug_ring(xhci, xhci->cmd_ring);
645 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
646 xhci_dbg_cmd_ptrs(xhci);
647
648 xhci_dbg(xhci, "ERST memory map follows:\n");
649 xhci_dbg_erst(xhci, &xhci->erst);
650 xhci_dbg(xhci, "Event ring:\n");
651 xhci_debug_ring(xhci, xhci->event_ring);
652 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
653 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
654 temp_64 &= ~ERST_PTR_MASK;
655 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
656
66d4eadd
SS
657 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
658 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
a4d88302 659 temp &= ~ER_IRQ_INTERVAL_MASK;
66d4eadd
SS
660 temp |= (u32) 160;
661 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
662
663 /* Set the HCD state before we enable the irqs */
66d4eadd
SS
664 temp = xhci_readl(xhci, &xhci->op_regs->command);
665 temp |= (CMD_EIE);
666 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
667 temp);
668 xhci_writel(xhci, temp, &xhci->op_regs->command);
669
670 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
700e2052
GKH
671 xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
672 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
66d4eadd
SS
673 xhci_writel(xhci, ER_IRQ_ENABLE(temp),
674 &xhci->ir_set->irq_pending);
09ece30e 675 xhci_print_ir_set(xhci, 0);
66d4eadd 676
0238634d
SS
677 if (xhci->quirks & XHCI_NEC_HOST)
678 xhci_queue_vendor_command(xhci, 0, 0, 0,
679 TRB_TYPE(TRB_NEC_GET_FW));
7f84eef0 680
f6ff0ac8
SS
681 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
682 return 0;
683}
ed07453f 684
f6ff0ac8
SS
685static void xhci_only_stop_hcd(struct usb_hcd *hcd)
686{
687 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
66d4eadd 688
f6ff0ac8
SS
689 spin_lock_irq(&xhci->lock);
690 xhci_halt(xhci);
691
692 /* The shared_hcd is going to be deallocated shortly (the USB core only
693 * calls this function when allocation fails in usb_add_hcd(), or
694 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
695 */
696 xhci->shared_hcd = NULL;
697 spin_unlock_irq(&xhci->lock);
66d4eadd
SS
698}
699
700/*
701 * Stop xHCI driver.
702 *
703 * This function is called by the USB core when the HC driver is removed.
704 * Its opposite is xhci_run().
705 *
706 * Disable device contexts, disable IRQs, and quiesce the HC.
707 * Reset the HC, finish any completed transactions, and cleanup memory.
708 */
709void xhci_stop(struct usb_hcd *hcd)
710{
711 u32 temp;
712 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
713
f6ff0ac8
SS
714 if (!usb_hcd_is_primary_hcd(hcd)) {
715 xhci_only_stop_hcd(xhci->shared_hcd);
716 return;
717 }
718
66d4eadd 719 spin_lock_irq(&xhci->lock);
f6ff0ac8
SS
720 /* Make sure the xHC is halted for a USB3 roothub
721 * (xhci_stop() could be called as part of failed init).
722 */
66d4eadd
SS
723 xhci_halt(xhci);
724 xhci_reset(xhci);
725 spin_unlock_irq(&xhci->lock);
726
40a9fb17
ZR
727 xhci_cleanup_msix(xhci);
728
7f84eef0
SS
729#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
730 /* Tell the event ring poll function not to reschedule */
731 xhci->zombie = 1;
732 del_timer_sync(&xhci->event_ring_timer);
733#endif
734
71c731a2
AC
735 /* Deleting Compliance Mode Recovery Timer */
736 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
58b1d799 737 (!(xhci_all_ports_seen_u0(xhci)))) {
71c731a2 738 del_timer_sync(&xhci->comp_mode_recovery_timer);
58b1d799
TC
739 xhci_dbg(xhci, "%s: compliance mode recovery timer deleted\n",
740 __func__);
741 }
71c731a2 742
c41136b0
AX
743 if (xhci->quirks & XHCI_AMD_PLL_FIX)
744 usb_amd_dev_put();
745
66d4eadd
SS
746 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
747 temp = xhci_readl(xhci, &xhci->op_regs->status);
748 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
749 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
750 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
751 &xhci->ir_set->irq_pending);
09ece30e 752 xhci_print_ir_set(xhci, 0);
66d4eadd
SS
753
754 xhci_dbg(xhci, "cleaning up memory\n");
755 xhci_mem_cleanup(xhci);
756 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
757 xhci_readl(xhci, &xhci->op_regs->status));
758}
759
760/*
761 * Shutdown HC (not bus-specific)
762 *
763 * This is called when the machine is rebooting or halting. We assume that the
764 * machine will be powered off, and the HC's internal state will be reset.
765 * Don't bother to free memory.
f6ff0ac8
SS
766 *
767 * This will only ever be called with the main usb_hcd (the USB3 roothub).
66d4eadd
SS
768 */
769void xhci_shutdown(struct usb_hcd *hcd)
770{
771 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
772
052c7f9f 773 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
e95829f4
SS
774 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
775
66d4eadd
SS
776 spin_lock_irq(&xhci->lock);
777 xhci_halt(xhci);
43b86af8 778 spin_unlock_irq(&xhci->lock);
66d4eadd 779
40a9fb17
ZR
780 xhci_cleanup_msix(xhci);
781
66d4eadd
SS
782 xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
783 xhci_readl(xhci, &xhci->op_regs->status));
784}
785
b5b5c3ac 786#ifdef CONFIG_PM
5535b1d5
AX
787static void xhci_save_registers(struct xhci_hcd *xhci)
788{
789 xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
790 xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
791 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
792 xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
5535b1d5
AX
793 xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
794 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
795 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
c7713e73
SS
796 xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
797 xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
5535b1d5
AX
798}
799
800static void xhci_restore_registers(struct xhci_hcd *xhci)
801{
802 xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
803 xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
804 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
805 xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
5535b1d5
AX
806 xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
807 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
fb3d85bc 808 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
c7713e73
SS
809 xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
810 xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
5535b1d5
AX
811}
812
89821320
SS
813static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
814{
815 u64 val_64;
816
817 /* step 2: initialize command ring buffer */
818 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
819 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
820 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
821 xhci->cmd_ring->dequeue) &
822 (u64) ~CMD_RING_RSVD_BITS) |
823 xhci->cmd_ring->cycle_state;
824 xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
825 (long unsigned long) val_64);
826 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
827}
828
829/*
830 * The whole command ring must be cleared to zero when we suspend the host.
831 *
832 * The host doesn't save the command ring pointer in the suspend well, so we
833 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
834 * aligned, because of the reserved bits in the command ring dequeue pointer
835 * register. Therefore, we can't just set the dequeue pointer back in the
836 * middle of the ring (TRBs are 16-byte aligned).
837 */
838static void xhci_clear_command_ring(struct xhci_hcd *xhci)
839{
840 struct xhci_ring *ring;
841 struct xhci_segment *seg;
842
843 ring = xhci->cmd_ring;
844 seg = ring->deq_seg;
845 do {
158886cd
AX
846 memset(seg->trbs, 0,
847 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
848 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
849 cpu_to_le32(~TRB_CYCLE);
89821320
SS
850 seg = seg->next;
851 } while (seg != ring->deq_seg);
852
853 /* Reset the software enqueue and dequeue pointers */
854 ring->deq_seg = ring->first_seg;
855 ring->dequeue = ring->first_seg->trbs;
856 ring->enq_seg = ring->deq_seg;
857 ring->enqueue = ring->dequeue;
858
b008df60 859 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
89821320
SS
860 /*
861 * Ring is now zeroed, so the HW should look for change of ownership
862 * when the cycle bit is set to 1.
863 */
864 ring->cycle_state = 1;
865
866 /*
867 * Reset the hardware dequeue pointer.
868 * Yes, this will need to be re-written after resume, but we're paranoid
869 * and want to make sure the hardware doesn't access bogus memory
870 * because, say, the BIOS or an SMI started the host without changing
871 * the command ring pointers.
872 */
873 xhci_set_cmd_ring_deq(xhci);
874}
875
5535b1d5
AX
876/*
877 * Stop HC (not bus-specific)
878 *
879 * This is called when the machine transition into S3/S4 mode.
880 *
881 */
882int xhci_suspend(struct xhci_hcd *xhci)
883{
884 int rc = 0;
885 struct usb_hcd *hcd = xhci_to_hcd(xhci);
886 u32 command;
887
77b84767
FB
888 if (hcd->state != HC_STATE_SUSPENDED ||
889 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
890 return -EINVAL;
891
c52804a4
SS
892 /* Don't poll the roothubs on bus suspend. */
893 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
894 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
895 del_timer_sync(&hcd->rh_timer);
896
5535b1d5
AX
897 spin_lock_irq(&xhci->lock);
898 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
b3209379 899 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
5535b1d5
AX
900 /* step 1: stop endpoint */
901 /* skipped assuming that port suspend has done */
902
903 /* step 2: clear Run/Stop bit */
904 command = xhci_readl(xhci, &xhci->op_regs->command);
905 command &= ~CMD_RUN;
906 xhci_writel(xhci, command, &xhci->op_regs->command);
2611bd18 907 if (xhci_handshake(xhci, &xhci->op_regs->status,
a6e097df 908 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC)) {
5535b1d5
AX
909 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
910 spin_unlock_irq(&xhci->lock);
911 return -ETIMEDOUT;
912 }
89821320 913 xhci_clear_command_ring(xhci);
5535b1d5
AX
914
915 /* step 3: save registers */
916 xhci_save_registers(xhci);
917
918 /* step 4: set CSS flag */
919 command = xhci_readl(xhci, &xhci->op_regs->command);
920 command |= CMD_CSS;
921 xhci_writel(xhci, command, &xhci->op_regs->command);
2611bd18
SS
922 if (xhci_handshake(xhci, &xhci->op_regs->status,
923 STS_SAVE, 0, 10 * 1000)) {
622eb783 924 xhci_warn(xhci, "WARN: xHC save state timeout\n");
5535b1d5
AX
925 spin_unlock_irq(&xhci->lock);
926 return -ETIMEDOUT;
927 }
5535b1d5
AX
928 spin_unlock_irq(&xhci->lock);
929
71c731a2
AC
930 /*
931 * Deleting Compliance Mode Recovery Timer because the xHCI Host
932 * is about to be suspended.
933 */
934 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
935 (!(xhci_all_ports_seen_u0(xhci)))) {
936 del_timer_sync(&xhci->comp_mode_recovery_timer);
58b1d799
TC
937 xhci_dbg(xhci, "%s: compliance mode recovery timer deleted\n",
938 __func__);
71c731a2
AC
939 }
940
0029227f
AX
941 /* step 5: remove core well power */
942 /* synchronize irq when using MSI-X */
421aa841 943 xhci_msix_sync_irqs(xhci);
0029227f 944
5535b1d5
AX
945 return rc;
946}
947
948/*
949 * start xHC (not bus-specific)
950 *
951 * This is called when the machine transition from S3/S4 mode.
952 *
953 */
954int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
955{
956 u32 command, temp = 0;
957 struct usb_hcd *hcd = xhci_to_hcd(xhci);
65b22f93 958 struct usb_hcd *secondary_hcd;
f69e3120 959 int retval = 0;
77df9e0b 960 bool comp_timer_running = false;
5535b1d5 961
f6ff0ac8 962 /* Wait a bit if either of the roothubs need to settle from the
25985edc 963 * transition into bus suspend.
20b67cf5 964 */
f6ff0ac8
SS
965 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
966 time_before(jiffies,
967 xhci->bus_state[1].next_statechange))
5535b1d5
AX
968 msleep(100);
969
f69e3120
AS
970 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
971 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
972
5535b1d5 973 spin_lock_irq(&xhci->lock);
c877b3b2
ML
974 if (xhci->quirks & XHCI_RESET_ON_RESUME)
975 hibernated = true;
5535b1d5
AX
976
977 if (!hibernated) {
978 /* step 1: restore register */
979 xhci_restore_registers(xhci);
980 /* step 2: initialize command ring buffer */
89821320 981 xhci_set_cmd_ring_deq(xhci);
5535b1d5
AX
982 /* step 3: restore state and start state*/
983 /* step 3: set CRS flag */
984 command = xhci_readl(xhci, &xhci->op_regs->command);
985 command |= CMD_CRS;
986 xhci_writel(xhci, command, &xhci->op_regs->command);
2611bd18 987 if (xhci_handshake(xhci, &xhci->op_regs->status,
622eb783
AX
988 STS_RESTORE, 0, 10 * 1000)) {
989 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
5535b1d5
AX
990 spin_unlock_irq(&xhci->lock);
991 return -ETIMEDOUT;
992 }
993 temp = xhci_readl(xhci, &xhci->op_regs->status);
994 }
995
996 /* If restore operation fails, re-initialize the HC during resume */
997 if ((temp & STS_SRE) || hibernated) {
77df9e0b
TC
998
999 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1000 !(xhci_all_ports_seen_u0(xhci))) {
1001 del_timer_sync(&xhci->comp_mode_recovery_timer);
1002 xhci_dbg(xhci, "Compliance Mode Recovery Timer deleted!\n");
1003 }
1004
fedd383e
SS
1005 /* Let the USB core know _both_ roothubs lost power. */
1006 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1007 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
5535b1d5
AX
1008
1009 xhci_dbg(xhci, "Stop HCD\n");
1010 xhci_halt(xhci);
1011 xhci_reset(xhci);
5535b1d5 1012 spin_unlock_irq(&xhci->lock);
0029227f 1013 xhci_cleanup_msix(xhci);
5535b1d5
AX
1014
1015#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1016 /* Tell the event ring poll function not to reschedule */
1017 xhci->zombie = 1;
1018 del_timer_sync(&xhci->event_ring_timer);
1019#endif
1020
1021 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1022 temp = xhci_readl(xhci, &xhci->op_regs->status);
1023 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
1024 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
1025 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
1026 &xhci->ir_set->irq_pending);
09ece30e 1027 xhci_print_ir_set(xhci, 0);
5535b1d5
AX
1028
1029 xhci_dbg(xhci, "cleaning up memory\n");
1030 xhci_mem_cleanup(xhci);
1031 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1032 xhci_readl(xhci, &xhci->op_regs->status));
1033
65b22f93
SS
1034 /* USB core calls the PCI reinit and start functions twice:
1035 * first with the primary HCD, and then with the secondary HCD.
1036 * If we don't do the same, the host will never be started.
1037 */
1038 if (!usb_hcd_is_primary_hcd(hcd))
1039 secondary_hcd = hcd;
1040 else
1041 secondary_hcd = xhci->shared_hcd;
1042
1043 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1044 retval = xhci_init(hcd->primary_hcd);
5535b1d5
AX
1045 if (retval)
1046 return retval;
77df9e0b
TC
1047 comp_timer_running = true;
1048
65b22f93
SS
1049 xhci_dbg(xhci, "Start the primary HCD\n");
1050 retval = xhci_run(hcd->primary_hcd);
b3209379 1051 if (!retval) {
f69e3120
AS
1052 xhci_dbg(xhci, "Start the secondary HCD\n");
1053 retval = xhci_run(secondary_hcd);
b3209379 1054 }
5535b1d5 1055 hcd->state = HC_STATE_SUSPENDED;
b3209379 1056 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
f69e3120 1057 goto done;
5535b1d5
AX
1058 }
1059
5535b1d5
AX
1060 /* step 4: set Run/Stop bit */
1061 command = xhci_readl(xhci, &xhci->op_regs->command);
1062 command |= CMD_RUN;
1063 xhci_writel(xhci, command, &xhci->op_regs->command);
2611bd18 1064 xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT,
5535b1d5
AX
1065 0, 250 * 1000);
1066
1067 /* step 5: walk topology and initialize portsc,
1068 * portpmsc and portli
1069 */
1070 /* this is done in bus_resume */
1071
1072 /* step 6: restart each of the previously
1073 * Running endpoints by ringing their doorbells
1074 */
1075
5535b1d5 1076 spin_unlock_irq(&xhci->lock);
f69e3120
AS
1077
1078 done:
1079 if (retval == 0) {
1080 usb_hcd_resume_root_hub(hcd);
1081 usb_hcd_resume_root_hub(xhci->shared_hcd);
1082 }
71c731a2
AC
1083
1084 /*
1085 * If system is subject to the Quirk, Compliance Mode Timer needs to
1086 * be re-initialized Always after a system resume. Ports are subject
1087 * to suffer the Compliance Mode issue again. It doesn't matter if
1088 * ports have entered previously to U0 before system's suspension.
1089 */
77df9e0b 1090 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
71c731a2
AC
1091 compliance_mode_recovery_timer_init(xhci);
1092
c52804a4
SS
1093 /* Re-enable port polling. */
1094 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1095 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1096 usb_hcd_poll_rh_status(hcd);
1097
f69e3120 1098 return retval;
5535b1d5 1099}
b5b5c3ac
SS
1100#endif /* CONFIG_PM */
1101
7f84eef0
SS
1102/*-------------------------------------------------------------------------*/
1103
d0e96f5a
SS
1104/**
1105 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1106 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1107 * value to right shift 1 for the bitmask.
1108 *
1109 * Index = (epnum * 2) + direction - 1,
1110 * where direction = 0 for OUT, 1 for IN.
1111 * For control endpoints, the IN index is used (OUT index is unused), so
1112 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1113 */
1114unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1115{
1116 unsigned int index;
1117 if (usb_endpoint_xfer_control(desc))
1118 index = (unsigned int) (usb_endpoint_num(desc)*2);
1119 else
1120 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1121 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1122 return index;
1123}
1124
01c5f447
JW
1125/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1126 * address from the XHCI endpoint index.
1127 */
1128unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1129{
1130 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1131 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1132 return direction | number;
1133}
1134
f94e0186
SS
1135/* Find the flag for this endpoint (for use in the control context). Use the
1136 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1137 * bit 1, etc.
1138 */
1139unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1140{
1141 return 1 << (xhci_get_endpoint_index(desc) + 1);
1142}
1143
ac9d8fe7
SS
1144/* Find the flag for this endpoint (for use in the control context). Use the
1145 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1146 * bit 1, etc.
1147 */
1148unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1149{
1150 return 1 << (ep_index + 1);
1151}
1152
f94e0186
SS
1153/* Compute the last valid endpoint context index. Basically, this is the
1154 * endpoint index plus one. For slot contexts with more than valid endpoint,
1155 * we find the most significant bit set in the added contexts flags.
1156 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1157 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1158 */
ac9d8fe7 1159unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
f94e0186
SS
1160{
1161 return fls(added_ctxs) - 1;
1162}
1163
d0e96f5a
SS
1164/* Returns 1 if the arguments are OK;
1165 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1166 */
8212a49d 1167static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
64927730
AX
1168 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1169 const char *func) {
1170 struct xhci_hcd *xhci;
1171 struct xhci_virt_device *virt_dev;
1172
d0e96f5a
SS
1173 if (!hcd || (check_ep && !ep) || !udev) {
1174 printk(KERN_DEBUG "xHCI %s called with invalid args\n",
1175 func);
1176 return -EINVAL;
1177 }
1178 if (!udev->parent) {
1179 printk(KERN_DEBUG "xHCI %s called for root hub\n",
1180 func);
1181 return 0;
1182 }
64927730 1183
7bd89b40 1184 xhci = hcd_to_xhci(hcd);
64927730 1185 if (check_virt_dev) {
73ddc247 1186 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
64927730
AX
1187 printk(KERN_DEBUG "xHCI %s called with unaddressed "
1188 "device\n", func);
1189 return -EINVAL;
1190 }
1191
1192 virt_dev = xhci->devs[udev->slot_id];
1193 if (virt_dev->udev != udev) {
1194 printk(KERN_DEBUG "xHCI %s called with udev and "
1195 "virt_dev does not match\n", func);
1196 return -EINVAL;
1197 }
d0e96f5a 1198 }
64927730 1199
203a8661
SS
1200 if (xhci->xhc_state & XHCI_STATE_HALTED)
1201 return -ENODEV;
1202
d0e96f5a
SS
1203 return 1;
1204}
1205
2d3f1fac 1206static int xhci_configure_endpoint(struct xhci_hcd *xhci,
913a8a34
SS
1207 struct usb_device *udev, struct xhci_command *command,
1208 bool ctx_change, bool must_succeed);
2d3f1fac
SS
1209
1210/*
1211 * Full speed devices may have a max packet size greater than 8 bytes, but the
1212 * USB core doesn't know that until it reads the first 8 bytes of the
1213 * descriptor. If the usb_device's max packet size changes after that point,
1214 * we need to issue an evaluate context command and wait on it.
1215 */
1216static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1217 unsigned int ep_index, struct urb *urb)
1218{
1219 struct xhci_container_ctx *in_ctx;
1220 struct xhci_container_ctx *out_ctx;
1221 struct xhci_input_control_ctx *ctrl_ctx;
1222 struct xhci_ep_ctx *ep_ctx;
1223 int max_packet_size;
1224 int hw_max_packet_size;
1225 int ret = 0;
1226
1227 out_ctx = xhci->devs[slot_id]->out_ctx;
1228 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
28ccd296 1229 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
29cc8897 1230 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
2d3f1fac
SS
1231 if (hw_max_packet_size != max_packet_size) {
1232 xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
1233 xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
1234 max_packet_size);
1235 xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
1236 hw_max_packet_size);
1237 xhci_dbg(xhci, "Issuing evaluate context command.\n");
1238
92f8e767
SS
1239 /* Set up the input context flags for the command */
1240 /* FIXME: This won't work if a non-default control endpoint
1241 * changes max packet sizes.
1242 */
1243 in_ctx = xhci->devs[slot_id]->in_ctx;
1244 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1245 if (!ctrl_ctx) {
1246 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1247 __func__);
1248 return -ENOMEM;
1249 }
2d3f1fac 1250 /* Set up the modified control endpoint 0 */
913a8a34
SS
1251 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1252 xhci->devs[slot_id]->out_ctx, ep_index);
92f8e767 1253
2d3f1fac 1254 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
28ccd296
ME
1255 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1256 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
2d3f1fac 1257
28ccd296 1258 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
2d3f1fac
SS
1259 ctrl_ctx->drop_flags = 0;
1260
1261 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1262 xhci_dbg_ctx(xhci, in_ctx, ep_index);
1263 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1264 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1265
913a8a34
SS
1266 ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
1267 true, false);
2d3f1fac
SS
1268
1269 /* Clean up the input context for later use by bandwidth
1270 * functions.
1271 */
28ccd296 1272 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
2d3f1fac
SS
1273 }
1274 return ret;
1275}
1276
d0e96f5a
SS
1277/*
1278 * non-error returns are a promise to giveback() the urb later
1279 * we drop ownership so next owner (or urb unlink) can get it
1280 */
1281int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1282{
1283 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2ffdea25 1284 struct xhci_td *buffer;
d0e96f5a
SS
1285 unsigned long flags;
1286 int ret = 0;
1287 unsigned int slot_id, ep_index;
8e51adcc
AX
1288 struct urb_priv *urb_priv;
1289 int size, i;
2d3f1fac 1290
64927730
AX
1291 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1292 true, true, __func__) <= 0)
d0e96f5a
SS
1293 return -EINVAL;
1294
1295 slot_id = urb->dev->slot_id;
1296 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
d0e96f5a 1297
541c7d43 1298 if (!HCD_HW_ACCESSIBLE(hcd)) {
d0e96f5a
SS
1299 if (!in_interrupt())
1300 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1301 ret = -ESHUTDOWN;
1302 goto exit;
1303 }
8e51adcc
AX
1304
1305 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1306 size = urb->number_of_packets;
1307 else
1308 size = 1;
1309
1310 urb_priv = kzalloc(sizeof(struct urb_priv) +
1311 size * sizeof(struct xhci_td *), mem_flags);
1312 if (!urb_priv)
1313 return -ENOMEM;
1314
2ffdea25
AX
1315 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1316 if (!buffer) {
1317 kfree(urb_priv);
1318 return -ENOMEM;
1319 }
1320
8e51adcc 1321 for (i = 0; i < size; i++) {
2ffdea25
AX
1322 urb_priv->td[i] = buffer;
1323 buffer++;
8e51adcc
AX
1324 }
1325
1326 urb_priv->length = size;
1327 urb_priv->td_cnt = 0;
1328 urb->hcpriv = urb_priv;
1329
2d3f1fac
SS
1330 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1331 /* Check to see if the max packet size for the default control
1332 * endpoint changed during FS device enumeration
1333 */
1334 if (urb->dev->speed == USB_SPEED_FULL) {
1335 ret = xhci_check_maxpacket(xhci, slot_id,
1336 ep_index, urb);
d13565c1
SS
1337 if (ret < 0) {
1338 xhci_urb_free_priv(xhci, urb_priv);
1339 urb->hcpriv = NULL;
2d3f1fac 1340 return ret;
d13565c1 1341 }
2d3f1fac
SS
1342 }
1343
b11069f5
SS
1344 /* We have a spinlock and interrupts disabled, so we must pass
1345 * atomic context to this function, which may allocate memory.
1346 */
2d3f1fac 1347 spin_lock_irqsave(&xhci->lock, flags);
6f5165cf
SS
1348 if (xhci->xhc_state & XHCI_STATE_DYING)
1349 goto dying;
b11069f5 1350 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
23e3be11 1351 slot_id, ep_index);
d13565c1
SS
1352 if (ret)
1353 goto free_priv;
2d3f1fac
SS
1354 spin_unlock_irqrestore(&xhci->lock, flags);
1355 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1356 spin_lock_irqsave(&xhci->lock, flags);
6f5165cf
SS
1357 if (xhci->xhc_state & XHCI_STATE_DYING)
1358 goto dying;
8df75f42
SS
1359 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1360 EP_GETTING_STREAMS) {
1361 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1362 "is transitioning to using streams.\n");
1363 ret = -EINVAL;
1364 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1365 EP_GETTING_NO_STREAMS) {
1366 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1367 "is transitioning to "
1368 "not having streams.\n");
1369 ret = -EINVAL;
1370 } else {
1371 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1372 slot_id, ep_index);
1373 }
d13565c1
SS
1374 if (ret)
1375 goto free_priv;
2d3f1fac 1376 spin_unlock_irqrestore(&xhci->lock, flags);
624defa1
SS
1377 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1378 spin_lock_irqsave(&xhci->lock, flags);
6f5165cf
SS
1379 if (xhci->xhc_state & XHCI_STATE_DYING)
1380 goto dying;
624defa1
SS
1381 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1382 slot_id, ep_index);
d13565c1
SS
1383 if (ret)
1384 goto free_priv;
624defa1 1385 spin_unlock_irqrestore(&xhci->lock, flags);
2d3f1fac 1386 } else {
787f4e5a
AX
1387 spin_lock_irqsave(&xhci->lock, flags);
1388 if (xhci->xhc_state & XHCI_STATE_DYING)
1389 goto dying;
1390 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1391 slot_id, ep_index);
d13565c1
SS
1392 if (ret)
1393 goto free_priv;
787f4e5a 1394 spin_unlock_irqrestore(&xhci->lock, flags);
2d3f1fac 1395 }
d0e96f5a 1396exit:
d0e96f5a 1397 return ret;
6f5165cf
SS
1398dying:
1399 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1400 "non-responsive xHCI host.\n",
1401 urb->ep->desc.bEndpointAddress, urb);
d13565c1
SS
1402 ret = -ESHUTDOWN;
1403free_priv:
1404 xhci_urb_free_priv(xhci, urb_priv);
1405 urb->hcpriv = NULL;
6f5165cf 1406 spin_unlock_irqrestore(&xhci->lock, flags);
d13565c1 1407 return ret;
d0e96f5a
SS
1408}
1409
021bff91
SS
1410/* Get the right ring for the given URB.
1411 * If the endpoint supports streams, boundary check the URB's stream ID.
1412 * If the endpoint doesn't support streams, return the singular endpoint ring.
1413 */
1414static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1415 struct urb *urb)
1416{
1417 unsigned int slot_id;
1418 unsigned int ep_index;
1419 unsigned int stream_id;
1420 struct xhci_virt_ep *ep;
1421
1422 slot_id = urb->dev->slot_id;
1423 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1424 stream_id = urb->stream_id;
1425 ep = &xhci->devs[slot_id]->eps[ep_index];
1426 /* Common case: no streams */
1427 if (!(ep->ep_state & EP_HAS_STREAMS))
1428 return ep->ring;
1429
1430 if (stream_id == 0) {
1431 xhci_warn(xhci,
1432 "WARN: Slot ID %u, ep index %u has streams, "
1433 "but URB has no stream ID.\n",
1434 slot_id, ep_index);
1435 return NULL;
1436 }
1437
1438 if (stream_id < ep->stream_info->num_streams)
1439 return ep->stream_info->stream_rings[stream_id];
1440
1441 xhci_warn(xhci,
1442 "WARN: Slot ID %u, ep index %u has "
1443 "stream IDs 1 to %u allocated, "
1444 "but stream ID %u is requested.\n",
1445 slot_id, ep_index,
1446 ep->stream_info->num_streams - 1,
1447 stream_id);
1448 return NULL;
1449}
1450
ae636747
SS
1451/*
1452 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1453 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1454 * should pick up where it left off in the TD, unless a Set Transfer Ring
1455 * Dequeue Pointer is issued.
1456 *
1457 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1458 * the ring. Since the ring is a contiguous structure, they can't be physically
1459 * removed. Instead, there are two options:
1460 *
1461 * 1) If the HC is in the middle of processing the URB to be canceled, we
1462 * simply move the ring's dequeue pointer past those TRBs using the Set
1463 * Transfer Ring Dequeue Pointer command. This will be the common case,
1464 * when drivers timeout on the last submitted URB and attempt to cancel.
1465 *
1466 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1467 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1468 * HC will need to invalidate the any TRBs it has cached after the stop
1469 * endpoint command, as noted in the xHCI 0.95 errata.
1470 *
1471 * 3) The TD may have completed by the time the Stop Endpoint Command
1472 * completes, so software needs to handle that case too.
1473 *
1474 * This function should protect against the TD enqueueing code ringing the
1475 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1476 * It also needs to account for multiple cancellations on happening at the same
1477 * time for the same endpoint.
1478 *
1479 * Note that this function can be called in any context, or so says
1480 * usb_hcd_unlink_urb()
d0e96f5a
SS
1481 */
1482int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1483{
ae636747 1484 unsigned long flags;
8e51adcc 1485 int ret, i;
e34b2fbf 1486 u32 temp;
ae636747 1487 struct xhci_hcd *xhci;
8e51adcc 1488 struct urb_priv *urb_priv;
ae636747
SS
1489 struct xhci_td *td;
1490 unsigned int ep_index;
1491 struct xhci_ring *ep_ring;
63a0d9ab 1492 struct xhci_virt_ep *ep;
ae636747
SS
1493
1494 xhci = hcd_to_xhci(hcd);
1495 spin_lock_irqsave(&xhci->lock, flags);
1496 /* Make sure the URB hasn't completed or been unlinked already */
1497 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1498 if (ret || !urb->hcpriv)
1499 goto done;
e34b2fbf 1500 temp = xhci_readl(xhci, &xhci->op_regs->status);
c6cc27c7 1501 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
e34b2fbf 1502 xhci_dbg(xhci, "HW died, freeing TD.\n");
8e51adcc 1503 urb_priv = urb->hcpriv;
585df1d9
SS
1504 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1505 td = urb_priv->td[i];
1506 if (!list_empty(&td->td_list))
1507 list_del_init(&td->td_list);
1508 if (!list_empty(&td->cancelled_td_list))
1509 list_del_init(&td->cancelled_td_list);
1510 }
e34b2fbf
SS
1511
1512 usb_hcd_unlink_urb_from_ep(hcd, urb);
1513 spin_unlock_irqrestore(&xhci->lock, flags);
214f76f7 1514 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
8e51adcc 1515 xhci_urb_free_priv(xhci, urb_priv);
e34b2fbf
SS
1516 return ret;
1517 }
7bd89b40
SS
1518 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1519 (xhci->xhc_state & XHCI_STATE_HALTED)) {
6f5165cf
SS
1520 xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
1521 "non-responsive xHCI host.\n",
1522 urb->ep->desc.bEndpointAddress, urb);
1523 /* Let the stop endpoint command watchdog timer (which set this
1524 * state) finish cleaning up the endpoint TD lists. We must
1525 * have caught it in the middle of dropping a lock and giving
1526 * back an URB.
1527 */
1528 goto done;
1529 }
ae636747 1530
ae636747 1531 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
63a0d9ab 1532 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
e9df17eb
SS
1533 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1534 if (!ep_ring) {
1535 ret = -EINVAL;
1536 goto done;
1537 }
1538
8e51adcc 1539 urb_priv = urb->hcpriv;
79688acf
SS
1540 i = urb_priv->td_cnt;
1541 if (i < urb_priv->length)
1542 xhci_dbg(xhci, "Cancel URB %p, dev %s, ep 0x%x, "
1543 "starting at offset 0x%llx\n",
1544 urb, urb->dev->devpath,
1545 urb->ep->desc.bEndpointAddress,
1546 (unsigned long long) xhci_trb_virt_to_dma(
1547 urb_priv->td[i]->start_seg,
1548 urb_priv->td[i]->first_trb));
1549
1550 for (; i < urb_priv->length; i++) {
8e51adcc
AX
1551 td = urb_priv->td[i];
1552 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1553 }
1554
ae636747
SS
1555 /* Queue a stop endpoint command, but only if this is
1556 * the first cancellation to be handled.
1557 */
678539cf
SS
1558 if (!(ep->ep_state & EP_HALT_PENDING)) {
1559 ep->ep_state |= EP_HALT_PENDING;
6f5165cf
SS
1560 ep->stop_cmds_pending++;
1561 ep->stop_cmd_timer.expires = jiffies +
1562 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1563 add_timer(&ep->stop_cmd_timer);
be88fe4f 1564 xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
23e3be11 1565 xhci_ring_cmd_db(xhci);
ae636747
SS
1566 }
1567done:
1568 spin_unlock_irqrestore(&xhci->lock, flags);
1569 return ret;
d0e96f5a
SS
1570}
1571
f94e0186
SS
1572/* Drop an endpoint from a new bandwidth configuration for this device.
1573 * Only one call to this function is allowed per endpoint before
1574 * check_bandwidth() or reset_bandwidth() must be called.
1575 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1576 * add the endpoint to the schedule with possibly new parameters denoted by a
1577 * different endpoint descriptor in usb_host_endpoint.
1578 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1579 * not allowed.
f88ba78d
SS
1580 *
1581 * The USB core will not allow URBs to be queued to an endpoint that is being
1582 * disabled, so there's no need for mutual exclusion to protect
1583 * the xhci->devs[slot_id] structure.
f94e0186
SS
1584 */
1585int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1586 struct usb_host_endpoint *ep)
1587{
f94e0186 1588 struct xhci_hcd *xhci;
d115b048
JY
1589 struct xhci_container_ctx *in_ctx, *out_ctx;
1590 struct xhci_input_control_ctx *ctrl_ctx;
1591 struct xhci_slot_ctx *slot_ctx;
f94e0186
SS
1592 unsigned int last_ctx;
1593 unsigned int ep_index;
1594 struct xhci_ep_ctx *ep_ctx;
1595 u32 drop_flag;
1596 u32 new_add_flags, new_drop_flags, new_slot_info;
1597 int ret;
1598
64927730 1599 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
f94e0186
SS
1600 if (ret <= 0)
1601 return ret;
1602 xhci = hcd_to_xhci(hcd);
fe6c6c13
SS
1603 if (xhci->xhc_state & XHCI_STATE_DYING)
1604 return -ENODEV;
f94e0186 1605
fe6c6c13 1606 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
f94e0186
SS
1607 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1608 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1609 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1610 __func__, drop_flag);
1611 return 0;
1612 }
1613
f94e0186 1614 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
d115b048
JY
1615 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1616 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
92f8e767
SS
1617 if (!ctrl_ctx) {
1618 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1619 __func__);
1620 return 0;
1621 }
1622
f94e0186 1623 ep_index = xhci_get_endpoint_index(&ep->desc);
d115b048 1624 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
f94e0186
SS
1625 /* If the HC already knows the endpoint is disabled,
1626 * or the HCD has noted it is disabled, ignore this request
1627 */
f5960b69
ME
1628 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1629 cpu_to_le32(EP_STATE_DISABLED)) ||
28ccd296
ME
1630 le32_to_cpu(ctrl_ctx->drop_flags) &
1631 xhci_get_endpoint_flag(&ep->desc)) {
700e2052
GKH
1632 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1633 __func__, ep);
f94e0186
SS
1634 return 0;
1635 }
1636
28ccd296
ME
1637 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1638 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
f94e0186 1639
28ccd296
ME
1640 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1641 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
f94e0186 1642
28ccd296 1643 last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
d115b048 1644 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
f94e0186 1645 /* Update the last valid endpoint context, if we deleted the last one */
28ccd296
ME
1646 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
1647 LAST_CTX(last_ctx)) {
1648 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1649 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
f94e0186 1650 }
28ccd296 1651 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
f94e0186
SS
1652
1653 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1654
f94e0186
SS
1655 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1656 (unsigned int) ep->desc.bEndpointAddress,
1657 udev->slot_id,
1658 (unsigned int) new_drop_flags,
1659 (unsigned int) new_add_flags,
1660 (unsigned int) new_slot_info);
1661 return 0;
1662}
1663
1664/* Add an endpoint to a new possible bandwidth configuration for this device.
1665 * Only one call to this function is allowed per endpoint before
1666 * check_bandwidth() or reset_bandwidth() must be called.
1667 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1668 * add the endpoint to the schedule with possibly new parameters denoted by a
1669 * different endpoint descriptor in usb_host_endpoint.
1670 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1671 * not allowed.
f88ba78d
SS
1672 *
1673 * The USB core will not allow URBs to be queued to an endpoint until the
1674 * configuration or alt setting is installed in the device, so there's no need
1675 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
f94e0186
SS
1676 */
1677int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1678 struct usb_host_endpoint *ep)
1679{
f94e0186 1680 struct xhci_hcd *xhci;
d115b048 1681 struct xhci_container_ctx *in_ctx, *out_ctx;
f94e0186 1682 unsigned int ep_index;
d115b048
JY
1683 struct xhci_slot_ctx *slot_ctx;
1684 struct xhci_input_control_ctx *ctrl_ctx;
f94e0186
SS
1685 u32 added_ctxs;
1686 unsigned int last_ctx;
1687 u32 new_add_flags, new_drop_flags, new_slot_info;
fa75ac37 1688 struct xhci_virt_device *virt_dev;
f94e0186
SS
1689 int ret = 0;
1690
64927730 1691 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
a1587d97
SS
1692 if (ret <= 0) {
1693 /* So we won't queue a reset ep command for a root hub */
1694 ep->hcpriv = NULL;
f94e0186 1695 return ret;
a1587d97 1696 }
f94e0186 1697 xhci = hcd_to_xhci(hcd);
fe6c6c13
SS
1698 if (xhci->xhc_state & XHCI_STATE_DYING)
1699 return -ENODEV;
f94e0186
SS
1700
1701 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1702 last_ctx = xhci_last_valid_endpoint(added_ctxs);
1703 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1704 /* FIXME when we have to issue an evaluate endpoint command to
1705 * deal with ep0 max packet size changing once we get the
1706 * descriptors
1707 */
1708 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1709 __func__, added_ctxs);
1710 return 0;
1711 }
1712
fa75ac37
SS
1713 virt_dev = xhci->devs[udev->slot_id];
1714 in_ctx = virt_dev->in_ctx;
1715 out_ctx = virt_dev->out_ctx;
d115b048 1716 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
92f8e767
SS
1717 if (!ctrl_ctx) {
1718 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1719 __func__);
1720 return 0;
1721 }
fa75ac37 1722
92f8e767 1723 ep_index = xhci_get_endpoint_index(&ep->desc);
fa75ac37
SS
1724 /* If this endpoint is already in use, and the upper layers are trying
1725 * to add it again without dropping it, reject the addition.
1726 */
1727 if (virt_dev->eps[ep_index].ring &&
1728 !(le32_to_cpu(ctrl_ctx->drop_flags) &
1729 xhci_get_endpoint_flag(&ep->desc))) {
1730 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1731 "without dropping it.\n",
1732 (unsigned int) ep->desc.bEndpointAddress);
1733 return -EINVAL;
1734 }
1735
f94e0186
SS
1736 /* If the HCD has already noted the endpoint is enabled,
1737 * ignore this request.
1738 */
28ccd296
ME
1739 if (le32_to_cpu(ctrl_ctx->add_flags) &
1740 xhci_get_endpoint_flag(&ep->desc)) {
700e2052
GKH
1741 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1742 __func__, ep);
f94e0186
SS
1743 return 0;
1744 }
1745
f88ba78d
SS
1746 /*
1747 * Configuration and alternate setting changes must be done in
1748 * process context, not interrupt context (or so documenation
1749 * for usb_set_interface() and usb_set_configuration() claim).
1750 */
fa75ac37 1751 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
f94e0186
SS
1752 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1753 __func__, ep->desc.bEndpointAddress);
f94e0186
SS
1754 return -ENOMEM;
1755 }
1756
28ccd296
ME
1757 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1758 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
f94e0186
SS
1759
1760 /* If xhci_endpoint_disable() was called for this endpoint, but the
1761 * xHC hasn't been notified yet through the check_bandwidth() call,
1762 * this re-adds a new state for the endpoint from the new endpoint
1763 * descriptors. We must drop and re-add this endpoint, so we leave the
1764 * drop flags alone.
1765 */
28ccd296 1766 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
f94e0186 1767
d115b048 1768 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
f94e0186 1769 /* Update the last valid endpoint context, if we just added one past */
28ccd296
ME
1770 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
1771 LAST_CTX(last_ctx)) {
1772 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1773 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
f94e0186 1774 }
28ccd296 1775 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
f94e0186 1776
a1587d97
SS
1777 /* Store the usb_device pointer for later use */
1778 ep->hcpriv = udev;
1779
f94e0186
SS
1780 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1781 (unsigned int) ep->desc.bEndpointAddress,
1782 udev->slot_id,
1783 (unsigned int) new_drop_flags,
1784 (unsigned int) new_add_flags,
1785 (unsigned int) new_slot_info);
1786 return 0;
1787}
1788
d115b048 1789static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
f94e0186 1790{
d115b048 1791 struct xhci_input_control_ctx *ctrl_ctx;
f94e0186 1792 struct xhci_ep_ctx *ep_ctx;
d115b048 1793 struct xhci_slot_ctx *slot_ctx;
f94e0186
SS
1794 int i;
1795
92f8e767
SS
1796 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1797 if (!ctrl_ctx) {
1798 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1799 __func__);
1800 return;
1801 }
1802
f94e0186
SS
1803 /* When a device's add flag and drop flag are zero, any subsequent
1804 * configure endpoint command will leave that endpoint's state
1805 * untouched. Make sure we don't leave any old state in the input
1806 * endpoint contexts.
1807 */
d115b048
JY
1808 ctrl_ctx->drop_flags = 0;
1809 ctrl_ctx->add_flags = 0;
1810 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
28ccd296 1811 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
f94e0186 1812 /* Endpoint 0 is always valid */
28ccd296 1813 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
f94e0186 1814 for (i = 1; i < 31; ++i) {
d115b048 1815 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
f94e0186
SS
1816 ep_ctx->ep_info = 0;
1817 ep_ctx->ep_info2 = 0;
8e595a5d 1818 ep_ctx->deq = 0;
f94e0186
SS
1819 ep_ctx->tx_info = 0;
1820 }
1821}
1822
f2217e8e 1823static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
00161f7d 1824 struct usb_device *udev, u32 *cmd_status)
f2217e8e
SS
1825{
1826 int ret;
1827
913a8a34 1828 switch (*cmd_status) {
f2217e8e
SS
1829 case COMP_ENOMEM:
1830 dev_warn(&udev->dev, "Not enough host controller resources "
1831 "for new device state.\n");
1832 ret = -ENOMEM;
1833 /* FIXME: can we allocate more resources for the HC? */
1834 break;
1835 case COMP_BW_ERR:
71d85724 1836 case COMP_2ND_BW_ERR:
f2217e8e
SS
1837 dev_warn(&udev->dev, "Not enough bandwidth "
1838 "for new device state.\n");
1839 ret = -ENOSPC;
1840 /* FIXME: can we go back to the old state? */
1841 break;
1842 case COMP_TRB_ERR:
1843 /* the HCD set up something wrong */
1844 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1845 "add flag = 1, "
1846 "and endpoint is not disabled.\n");
1847 ret = -EINVAL;
1848 break;
f6ba6fe2
AH
1849 case COMP_DEV_ERR:
1850 dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
1851 "configure command.\n");
1852 ret = -ENODEV;
1853 break;
f2217e8e
SS
1854 case COMP_SUCCESS:
1855 dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
1856 ret = 0;
1857 break;
1858 default:
1859 xhci_err(xhci, "ERROR: unexpected command completion "
913a8a34 1860 "code 0x%x.\n", *cmd_status);
f2217e8e
SS
1861 ret = -EINVAL;
1862 break;
1863 }
1864 return ret;
1865}
1866
1867static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
00161f7d 1868 struct usb_device *udev, u32 *cmd_status)
f2217e8e
SS
1869{
1870 int ret;
913a8a34 1871 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
f2217e8e 1872
913a8a34 1873 switch (*cmd_status) {
f2217e8e
SS
1874 case COMP_EINVAL:
1875 dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1876 "context command.\n");
1877 ret = -EINVAL;
1878 break;
1879 case COMP_EBADSLT:
1880 dev_warn(&udev->dev, "WARN: slot not enabled for"
1881 "evaluate context command.\n");
b8031342
SS
1882 ret = -EINVAL;
1883 break;
f2217e8e
SS
1884 case COMP_CTX_STATE:
1885 dev_warn(&udev->dev, "WARN: invalid context state for "
1886 "evaluate context command.\n");
1887 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1888 ret = -EINVAL;
1889 break;
f6ba6fe2
AH
1890 case COMP_DEV_ERR:
1891 dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
1892 "context command.\n");
1893 ret = -ENODEV;
1894 break;
1bb73a88
AH
1895 case COMP_MEL_ERR:
1896 /* Max Exit Latency too large error */
1897 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1898 ret = -EINVAL;
1899 break;
f2217e8e
SS
1900 case COMP_SUCCESS:
1901 dev_dbg(&udev->dev, "Successful evaluate context command\n");
1902 ret = 0;
1903 break;
1904 default:
1905 xhci_err(xhci, "ERROR: unexpected command completion "
913a8a34 1906 "code 0x%x.\n", *cmd_status);
f2217e8e
SS
1907 ret = -EINVAL;
1908 break;
1909 }
1910 return ret;
1911}
1912
2cf95c18 1913static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
92f8e767 1914 struct xhci_input_control_ctx *ctrl_ctx)
2cf95c18 1915{
2cf95c18
SS
1916 u32 valid_add_flags;
1917 u32 valid_drop_flags;
1918
2cf95c18
SS
1919 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1920 * (bit 1). The default control endpoint is added during the Address
1921 * Device command and is never removed until the slot is disabled.
1922 */
1923 valid_add_flags = ctrl_ctx->add_flags >> 2;
1924 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1925
1926 /* Use hweight32 to count the number of ones in the add flags, or
1927 * number of endpoints added. Don't count endpoints that are changed
1928 * (both added and dropped).
1929 */
1930 return hweight32(valid_add_flags) -
1931 hweight32(valid_add_flags & valid_drop_flags);
1932}
1933
1934static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
92f8e767 1935 struct xhci_input_control_ctx *ctrl_ctx)
2cf95c18 1936{
2cf95c18
SS
1937 u32 valid_add_flags;
1938 u32 valid_drop_flags;
1939
2cf95c18
SS
1940 valid_add_flags = ctrl_ctx->add_flags >> 2;
1941 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1942
1943 return hweight32(valid_drop_flags) -
1944 hweight32(valid_add_flags & valid_drop_flags);
1945}
1946
1947/*
1948 * We need to reserve the new number of endpoints before the configure endpoint
1949 * command completes. We can't subtract the dropped endpoints from the number
1950 * of active endpoints until the command completes because we can oversubscribe
1951 * the host in this case:
1952 *
1953 * - the first configure endpoint command drops more endpoints than it adds
1954 * - a second configure endpoint command that adds more endpoints is queued
1955 * - the first configure endpoint command fails, so the config is unchanged
1956 * - the second command may succeed, even though there isn't enough resources
1957 *
1958 * Must be called with xhci->lock held.
1959 */
1960static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
92f8e767 1961 struct xhci_input_control_ctx *ctrl_ctx)
2cf95c18
SS
1962{
1963 u32 added_eps;
1964
92f8e767 1965 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2cf95c18
SS
1966 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1967 xhci_dbg(xhci, "Not enough ep ctxs: "
1968 "%u active, need to add %u, limit is %u.\n",
1969 xhci->num_active_eps, added_eps,
1970 xhci->limit_active_eps);
1971 return -ENOMEM;
1972 }
1973 xhci->num_active_eps += added_eps;
1974 xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps,
1975 xhci->num_active_eps);
1976 return 0;
1977}
1978
1979/*
1980 * The configure endpoint was failed by the xHC for some other reason, so we
1981 * need to revert the resources that failed configuration would have used.
1982 *
1983 * Must be called with xhci->lock held.
1984 */
1985static void xhci_free_host_resources(struct xhci_hcd *xhci,
92f8e767 1986 struct xhci_input_control_ctx *ctrl_ctx)
2cf95c18
SS
1987{
1988 u32 num_failed_eps;
1989
92f8e767 1990 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2cf95c18
SS
1991 xhci->num_active_eps -= num_failed_eps;
1992 xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n",
1993 num_failed_eps,
1994 xhci->num_active_eps);
1995}
1996
1997/*
1998 * Now that the command has completed, clean up the active endpoint count by
1999 * subtracting out the endpoints that were dropped (but not changed).
2000 *
2001 * Must be called with xhci->lock held.
2002 */
2003static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
92f8e767 2004 struct xhci_input_control_ctx *ctrl_ctx)
2cf95c18
SS
2005{
2006 u32 num_dropped_eps;
2007
92f8e767 2008 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2cf95c18
SS
2009 xhci->num_active_eps -= num_dropped_eps;
2010 if (num_dropped_eps)
2011 xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n",
2012 num_dropped_eps,
2013 xhci->num_active_eps);
2014}
2015
ed384bd3 2016static unsigned int xhci_get_block_size(struct usb_device *udev)
c29eea62
SS
2017{
2018 switch (udev->speed) {
2019 case USB_SPEED_LOW:
2020 case USB_SPEED_FULL:
2021 return FS_BLOCK;
2022 case USB_SPEED_HIGH:
2023 return HS_BLOCK;
2024 case USB_SPEED_SUPER:
2025 return SS_BLOCK;
2026 case USB_SPEED_UNKNOWN:
2027 case USB_SPEED_WIRELESS:
2028 default:
2029 /* Should never happen */
2030 return 1;
2031 }
2032}
2033
ed384bd3
FB
2034static unsigned int
2035xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
c29eea62
SS
2036{
2037 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2038 return LS_OVERHEAD;
2039 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2040 return FS_OVERHEAD;
2041 return HS_OVERHEAD;
2042}
2043
2044/* If we are changing a LS/FS device under a HS hub,
2045 * make sure (if we are activating a new TT) that the HS bus has enough
2046 * bandwidth for this new TT.
2047 */
2048static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2049 struct xhci_virt_device *virt_dev,
2050 int old_active_eps)
2051{
2052 struct xhci_interval_bw_table *bw_table;
2053 struct xhci_tt_bw_info *tt_info;
2054
2055 /* Find the bandwidth table for the root port this TT is attached to. */
2056 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2057 tt_info = virt_dev->tt_info;
2058 /* If this TT already had active endpoints, the bandwidth for this TT
2059 * has already been added. Removing all periodic endpoints (and thus
2060 * making the TT enactive) will only decrease the bandwidth used.
2061 */
2062 if (old_active_eps)
2063 return 0;
2064 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2065 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2066 return -ENOMEM;
2067 return 0;
2068 }
2069 /* Not sure why we would have no new active endpoints...
2070 *
2071 * Maybe because of an Evaluate Context change for a hub update or a
2072 * control endpoint 0 max packet size change?
2073 * FIXME: skip the bandwidth calculation in that case.
2074 */
2075 return 0;
2076}
2077
2b698999
SS
2078static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2079 struct xhci_virt_device *virt_dev)
2080{
2081 unsigned int bw_reserved;
2082
2083 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2084 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2085 return -ENOMEM;
2086
2087 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2088 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2089 return -ENOMEM;
2090
2091 return 0;
2092}
2093
c29eea62
SS
2094/*
2095 * This algorithm is a very conservative estimate of the worst-case scheduling
2096 * scenario for any one interval. The hardware dynamically schedules the
2097 * packets, so we can't tell which microframe could be the limiting factor in
2098 * the bandwidth scheduling. This only takes into account periodic endpoints.
2099 *
2100 * Obviously, we can't solve an NP complete problem to find the minimum worst
2101 * case scenario. Instead, we come up with an estimate that is no less than
2102 * the worst case bandwidth used for any one microframe, but may be an
2103 * over-estimate.
2104 *
2105 * We walk the requirements for each endpoint by interval, starting with the
2106 * smallest interval, and place packets in the schedule where there is only one
2107 * possible way to schedule packets for that interval. In order to simplify
2108 * this algorithm, we record the largest max packet size for each interval, and
2109 * assume all packets will be that size.
2110 *
2111 * For interval 0, we obviously must schedule all packets for each interval.
2112 * The bandwidth for interval 0 is just the amount of data to be transmitted
2113 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2114 * the number of packets).
2115 *
2116 * For interval 1, we have two possible microframes to schedule those packets
2117 * in. For this algorithm, if we can schedule the same number of packets for
2118 * each possible scheduling opportunity (each microframe), we will do so. The
2119 * remaining number of packets will be saved to be transmitted in the gaps in
2120 * the next interval's scheduling sequence.
2121 *
2122 * As we move those remaining packets to be scheduled with interval 2 packets,
2123 * we have to double the number of remaining packets to transmit. This is
2124 * because the intervals are actually powers of 2, and we would be transmitting
2125 * the previous interval's packets twice in this interval. We also have to be
2126 * sure that when we look at the largest max packet size for this interval, we
2127 * also look at the largest max packet size for the remaining packets and take
2128 * the greater of the two.
2129 *
2130 * The algorithm continues to evenly distribute packets in each scheduling
2131 * opportunity, and push the remaining packets out, until we get to the last
2132 * interval. Then those packets and their associated overhead are just added
2133 * to the bandwidth used.
2e27980e
SS
2134 */
2135static int xhci_check_bw_table(struct xhci_hcd *xhci,
2136 struct xhci_virt_device *virt_dev,
2137 int old_active_eps)
2138{
c29eea62
SS
2139 unsigned int bw_reserved;
2140 unsigned int max_bandwidth;
2141 unsigned int bw_used;
2142 unsigned int block_size;
2143 struct xhci_interval_bw_table *bw_table;
2144 unsigned int packet_size = 0;
2145 unsigned int overhead = 0;
2146 unsigned int packets_transmitted = 0;
2147 unsigned int packets_remaining = 0;
2148 unsigned int i;
2149
2b698999
SS
2150 if (virt_dev->udev->speed == USB_SPEED_SUPER)
2151 return xhci_check_ss_bw(xhci, virt_dev);
2152
c29eea62
SS
2153 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2154 max_bandwidth = HS_BW_LIMIT;
2155 /* Convert percent of bus BW reserved to blocks reserved */
2156 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2157 } else {
2158 max_bandwidth = FS_BW_LIMIT;
2159 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2160 }
2161
2162 bw_table = virt_dev->bw_table;
2163 /* We need to translate the max packet size and max ESIT payloads into
2164 * the units the hardware uses.
2165 */
2166 block_size = xhci_get_block_size(virt_dev->udev);
2167
2168 /* If we are manipulating a LS/FS device under a HS hub, double check
2169 * that the HS bus has enough bandwidth if we are activing a new TT.
2170 */
2171 if (virt_dev->tt_info) {
2172 xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
2173 virt_dev->real_port);
2174 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2175 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2176 "newly activated TT.\n");
2177 return -ENOMEM;
2178 }
2179 xhci_dbg(xhci, "Recalculating BW for TT slot %u port %u\n",
2180 virt_dev->tt_info->slot_id,
2181 virt_dev->tt_info->ttport);
2182 } else {
2183 xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
2184 virt_dev->real_port);
2185 }
2186
2187 /* Add in how much bandwidth will be used for interval zero, or the
2188 * rounded max ESIT payload + number of packets * largest overhead.
2189 */
2190 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2191 bw_table->interval_bw[0].num_packets *
2192 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2193
2194 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2195 unsigned int bw_added;
2196 unsigned int largest_mps;
2197 unsigned int interval_overhead;
2198
2199 /*
2200 * How many packets could we transmit in this interval?
2201 * If packets didn't fit in the previous interval, we will need
2202 * to transmit that many packets twice within this interval.
2203 */
2204 packets_remaining = 2 * packets_remaining +
2205 bw_table->interval_bw[i].num_packets;
2206
2207 /* Find the largest max packet size of this or the previous
2208 * interval.
2209 */
2210 if (list_empty(&bw_table->interval_bw[i].endpoints))
2211 largest_mps = 0;
2212 else {
2213 struct xhci_virt_ep *virt_ep;
2214 struct list_head *ep_entry;
2215
2216 ep_entry = bw_table->interval_bw[i].endpoints.next;
2217 virt_ep = list_entry(ep_entry,
2218 struct xhci_virt_ep, bw_endpoint_list);
2219 /* Convert to blocks, rounding up */
2220 largest_mps = DIV_ROUND_UP(
2221 virt_ep->bw_info.max_packet_size,
2222 block_size);
2223 }
2224 if (largest_mps > packet_size)
2225 packet_size = largest_mps;
2226
2227 /* Use the larger overhead of this or the previous interval. */
2228 interval_overhead = xhci_get_largest_overhead(
2229 &bw_table->interval_bw[i]);
2230 if (interval_overhead > overhead)
2231 overhead = interval_overhead;
2232
2233 /* How many packets can we evenly distribute across
2234 * (1 << (i + 1)) possible scheduling opportunities?
2235 */
2236 packets_transmitted = packets_remaining >> (i + 1);
2237
2238 /* Add in the bandwidth used for those scheduled packets */
2239 bw_added = packets_transmitted * (overhead + packet_size);
2240
2241 /* How many packets do we have remaining to transmit? */
2242 packets_remaining = packets_remaining % (1 << (i + 1));
2243
2244 /* What largest max packet size should those packets have? */
2245 /* If we've transmitted all packets, don't carry over the
2246 * largest packet size.
2247 */
2248 if (packets_remaining == 0) {
2249 packet_size = 0;
2250 overhead = 0;
2251 } else if (packets_transmitted > 0) {
2252 /* Otherwise if we do have remaining packets, and we've
2253 * scheduled some packets in this interval, take the
2254 * largest max packet size from endpoints with this
2255 * interval.
2256 */
2257 packet_size = largest_mps;
2258 overhead = interval_overhead;
2259 }
2260 /* Otherwise carry over packet_size and overhead from the last
2261 * time we had a remainder.
2262 */
2263 bw_used += bw_added;
2264 if (bw_used > max_bandwidth) {
2265 xhci_warn(xhci, "Not enough bandwidth. "
2266 "Proposed: %u, Max: %u\n",
2267 bw_used, max_bandwidth);
2268 return -ENOMEM;
2269 }
2270 }
2271 /*
2272 * Ok, we know we have some packets left over after even-handedly
2273 * scheduling interval 15. We don't know which microframes they will
2274 * fit into, so we over-schedule and say they will be scheduled every
2275 * microframe.
2276 */
2277 if (packets_remaining > 0)
2278 bw_used += overhead + packet_size;
2279
2280 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2281 unsigned int port_index = virt_dev->real_port - 1;
2282
2283 /* OK, we're manipulating a HS device attached to a
2284 * root port bandwidth domain. Include the number of active TTs
2285 * in the bandwidth used.
2286 */
2287 bw_used += TT_HS_OVERHEAD *
2288 xhci->rh_bw[port_index].num_active_tts;
2289 }
2290
2291 xhci_dbg(xhci, "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2292 "Available: %u " "percent\n",
2293 bw_used, max_bandwidth, bw_reserved,
2294 (max_bandwidth - bw_used - bw_reserved) * 100 /
2295 max_bandwidth);
2296
2297 bw_used += bw_reserved;
2298 if (bw_used > max_bandwidth) {
2299 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2300 bw_used, max_bandwidth);
2301 return -ENOMEM;
2302 }
2303
2304 bw_table->bw_used = bw_used;
2e27980e
SS
2305 return 0;
2306}
2307
2308static bool xhci_is_async_ep(unsigned int ep_type)
2309{
2310 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2311 ep_type != ISOC_IN_EP &&
2312 ep_type != INT_IN_EP);
2313}
2314
2b698999
SS
2315static bool xhci_is_sync_in_ep(unsigned int ep_type)
2316{
392a07ae 2317 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2b698999
SS
2318}
2319
2320static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2321{
2322 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2323
2324 if (ep_bw->ep_interval == 0)
2325 return SS_OVERHEAD_BURST +
2326 (ep_bw->mult * ep_bw->num_packets *
2327 (SS_OVERHEAD + mps));
2328 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2329 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2330 1 << ep_bw->ep_interval);
2331
2332}
2333
2e27980e
SS
2334void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2335 struct xhci_bw_info *ep_bw,
2336 struct xhci_interval_bw_table *bw_table,
2337 struct usb_device *udev,
2338 struct xhci_virt_ep *virt_ep,
2339 struct xhci_tt_bw_info *tt_info)
2340{
2341 struct xhci_interval_bw *interval_bw;
2342 int normalized_interval;
2343
2b698999 2344 if (xhci_is_async_ep(ep_bw->type))
2e27980e
SS
2345 return;
2346
2b698999
SS
2347 if (udev->speed == USB_SPEED_SUPER) {
2348 if (xhci_is_sync_in_ep(ep_bw->type))
2349 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2350 xhci_get_ss_bw_consumed(ep_bw);
2351 else
2352 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2353 xhci_get_ss_bw_consumed(ep_bw);
2354 return;
2355 }
2356
2357 /* SuperSpeed endpoints never get added to intervals in the table, so
2358 * this check is only valid for HS/FS/LS devices.
2359 */
2360 if (list_empty(&virt_ep->bw_endpoint_list))
2361 return;
2e27980e
SS
2362 /* For LS/FS devices, we need to translate the interval expressed in
2363 * microframes to frames.
2364 */
2365 if (udev->speed == USB_SPEED_HIGH)
2366 normalized_interval = ep_bw->ep_interval;
2367 else
2368 normalized_interval = ep_bw->ep_interval - 3;
2369
2370 if (normalized_interval == 0)
2371 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2372 interval_bw = &bw_table->interval_bw[normalized_interval];
2373 interval_bw->num_packets -= ep_bw->num_packets;
2374 switch (udev->speed) {
2375 case USB_SPEED_LOW:
2376 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2377 break;
2378 case USB_SPEED_FULL:
2379 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2380 break;
2381 case USB_SPEED_HIGH:
2382 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2383 break;
2384 case USB_SPEED_SUPER:
2385 case USB_SPEED_UNKNOWN:
2386 case USB_SPEED_WIRELESS:
2387 /* Should never happen because only LS/FS/HS endpoints will get
2388 * added to the endpoint list.
2389 */
2390 return;
2391 }
2392 if (tt_info)
2393 tt_info->active_eps -= 1;
2394 list_del_init(&virt_ep->bw_endpoint_list);
2395}
2396
2397static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2398 struct xhci_bw_info *ep_bw,
2399 struct xhci_interval_bw_table *bw_table,
2400 struct usb_device *udev,
2401 struct xhci_virt_ep *virt_ep,
2402 struct xhci_tt_bw_info *tt_info)
2403{
2404 struct xhci_interval_bw *interval_bw;
2405 struct xhci_virt_ep *smaller_ep;
2406 int normalized_interval;
2407
2408 if (xhci_is_async_ep(ep_bw->type))
2409 return;
2410
2b698999
SS
2411 if (udev->speed == USB_SPEED_SUPER) {
2412 if (xhci_is_sync_in_ep(ep_bw->type))
2413 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2414 xhci_get_ss_bw_consumed(ep_bw);
2415 else
2416 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2417 xhci_get_ss_bw_consumed(ep_bw);
2418 return;
2419 }
2420
2e27980e
SS
2421 /* For LS/FS devices, we need to translate the interval expressed in
2422 * microframes to frames.
2423 */
2424 if (udev->speed == USB_SPEED_HIGH)
2425 normalized_interval = ep_bw->ep_interval;
2426 else
2427 normalized_interval = ep_bw->ep_interval - 3;
2428
2429 if (normalized_interval == 0)
2430 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2431 interval_bw = &bw_table->interval_bw[normalized_interval];
2432 interval_bw->num_packets += ep_bw->num_packets;
2433 switch (udev->speed) {
2434 case USB_SPEED_LOW:
2435 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2436 break;
2437 case USB_SPEED_FULL:
2438 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2439 break;
2440 case USB_SPEED_HIGH:
2441 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2442 break;
2443 case USB_SPEED_SUPER:
2444 case USB_SPEED_UNKNOWN:
2445 case USB_SPEED_WIRELESS:
2446 /* Should never happen because only LS/FS/HS endpoints will get
2447 * added to the endpoint list.
2448 */
2449 return;
2450 }
2451
2452 if (tt_info)
2453 tt_info->active_eps += 1;
2454 /* Insert the endpoint into the list, largest max packet size first. */
2455 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2456 bw_endpoint_list) {
2457 if (ep_bw->max_packet_size >=
2458 smaller_ep->bw_info.max_packet_size) {
2459 /* Add the new ep before the smaller endpoint */
2460 list_add_tail(&virt_ep->bw_endpoint_list,
2461 &smaller_ep->bw_endpoint_list);
2462 return;
2463 }
2464 }
2465 /* Add the new endpoint at the end of the list. */
2466 list_add_tail(&virt_ep->bw_endpoint_list,
2467 &interval_bw->endpoints);
2468}
2469
2470void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2471 struct xhci_virt_device *virt_dev,
2472 int old_active_eps)
2473{
2474 struct xhci_root_port_bw_info *rh_bw_info;
2475 if (!virt_dev->tt_info)
2476 return;
2477
2478 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2479 if (old_active_eps == 0 &&
2480 virt_dev->tt_info->active_eps != 0) {
2481 rh_bw_info->num_active_tts += 1;
c29eea62 2482 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2e27980e
SS
2483 } else if (old_active_eps != 0 &&
2484 virt_dev->tt_info->active_eps == 0) {
2485 rh_bw_info->num_active_tts -= 1;
c29eea62 2486 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2e27980e
SS
2487 }
2488}
2489
2490static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2491 struct xhci_virt_device *virt_dev,
2492 struct xhci_container_ctx *in_ctx)
2493{
2494 struct xhci_bw_info ep_bw_info[31];
2495 int i;
2496 struct xhci_input_control_ctx *ctrl_ctx;
2497 int old_active_eps = 0;
2498
2e27980e
SS
2499 if (virt_dev->tt_info)
2500 old_active_eps = virt_dev->tt_info->active_eps;
2501
2502 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
92f8e767
SS
2503 if (!ctrl_ctx) {
2504 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2505 __func__);
2506 return -ENOMEM;
2507 }
2e27980e
SS
2508
2509 for (i = 0; i < 31; i++) {
2510 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2511 continue;
2512
2513 /* Make a copy of the BW info in case we need to revert this */
2514 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2515 sizeof(ep_bw_info[i]));
2516 /* Drop the endpoint from the interval table if the endpoint is
2517 * being dropped or changed.
2518 */
2519 if (EP_IS_DROPPED(ctrl_ctx, i))
2520 xhci_drop_ep_from_interval_table(xhci,
2521 &virt_dev->eps[i].bw_info,
2522 virt_dev->bw_table,
2523 virt_dev->udev,
2524 &virt_dev->eps[i],
2525 virt_dev->tt_info);
2526 }
2527 /* Overwrite the information stored in the endpoints' bw_info */
2528 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2529 for (i = 0; i < 31; i++) {
2530 /* Add any changed or added endpoints to the interval table */
2531 if (EP_IS_ADDED(ctrl_ctx, i))
2532 xhci_add_ep_to_interval_table(xhci,
2533 &virt_dev->eps[i].bw_info,
2534 virt_dev->bw_table,
2535 virt_dev->udev,
2536 &virt_dev->eps[i],
2537 virt_dev->tt_info);
2538 }
2539
2540 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2541 /* Ok, this fits in the bandwidth we have.
2542 * Update the number of active TTs.
2543 */
2544 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2545 return 0;
2546 }
2547
2548 /* We don't have enough bandwidth for this, revert the stored info. */
2549 for (i = 0; i < 31; i++) {
2550 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2551 continue;
2552
2553 /* Drop the new copies of any added or changed endpoints from
2554 * the interval table.
2555 */
2556 if (EP_IS_ADDED(ctrl_ctx, i)) {
2557 xhci_drop_ep_from_interval_table(xhci,
2558 &virt_dev->eps[i].bw_info,
2559 virt_dev->bw_table,
2560 virt_dev->udev,
2561 &virt_dev->eps[i],
2562 virt_dev->tt_info);
2563 }
2564 /* Revert the endpoint back to its old information */
2565 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2566 sizeof(ep_bw_info[i]));
2567 /* Add any changed or dropped endpoints back into the table */
2568 if (EP_IS_DROPPED(ctrl_ctx, i))
2569 xhci_add_ep_to_interval_table(xhci,
2570 &virt_dev->eps[i].bw_info,
2571 virt_dev->bw_table,
2572 virt_dev->udev,
2573 &virt_dev->eps[i],
2574 virt_dev->tt_info);
2575 }
2576 return -ENOMEM;
2577}
2578
2579
f2217e8e
SS
2580/* Issue a configure endpoint command or evaluate context command
2581 * and wait for it to finish.
2582 */
2583static int xhci_configure_endpoint(struct xhci_hcd *xhci,
913a8a34
SS
2584 struct usb_device *udev,
2585 struct xhci_command *command,
2586 bool ctx_change, bool must_succeed)
f2217e8e
SS
2587{
2588 int ret;
2589 int timeleft;
2590 unsigned long flags;
913a8a34 2591 struct xhci_container_ctx *in_ctx;
92f8e767 2592 struct xhci_input_control_ctx *ctrl_ctx;
913a8a34 2593 struct completion *cmd_completion;
28ccd296 2594 u32 *cmd_status;
913a8a34 2595 struct xhci_virt_device *virt_dev;
6e4468b9 2596 union xhci_trb *cmd_trb;
f2217e8e
SS
2597
2598 spin_lock_irqsave(&xhci->lock, flags);
913a8a34 2599 virt_dev = xhci->devs[udev->slot_id];
750645f8
SS
2600
2601 if (command)
913a8a34 2602 in_ctx = command->in_ctx;
750645f8
SS
2603 else
2604 in_ctx = virt_dev->in_ctx;
92f8e767
SS
2605 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2606 if (!ctrl_ctx) {
1f21569c 2607 spin_unlock_irqrestore(&xhci->lock, flags);
92f8e767
SS
2608 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2609 __func__);
2610 return -ENOMEM;
2611 }
2cf95c18 2612
750645f8 2613 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
92f8e767 2614 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
750645f8
SS
2615 spin_unlock_irqrestore(&xhci->lock, flags);
2616 xhci_warn(xhci, "Not enough host resources, "
2617 "active endpoint contexts = %u\n",
2618 xhci->num_active_eps);
2619 return -ENOMEM;
2620 }
2e27980e
SS
2621 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2622 xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) {
2623 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
92f8e767 2624 xhci_free_host_resources(xhci, ctrl_ctx);
2e27980e
SS
2625 spin_unlock_irqrestore(&xhci->lock, flags);
2626 xhci_warn(xhci, "Not enough bandwidth\n");
2627 return -ENOMEM;
2628 }
750645f8
SS
2629
2630 if (command) {
913a8a34
SS
2631 cmd_completion = command->completion;
2632 cmd_status = &command->status;
2633 command->command_trb = xhci->cmd_ring->enqueue;
7a3783ef
PZ
2634
2635 /* Enqueue pointer can be left pointing to the link TRB,
2636 * we must handle that
2637 */
f5960b69 2638 if (TRB_TYPE_LINK_LE32(command->command_trb->link.control))
7a3783ef
PZ
2639 command->command_trb =
2640 xhci->cmd_ring->enq_seg->next->trbs;
2641
913a8a34
SS
2642 list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
2643 } else {
913a8a34
SS
2644 cmd_completion = &virt_dev->cmd_completion;
2645 cmd_status = &virt_dev->cmd_status;
2646 }
1d68064a 2647 init_completion(cmd_completion);
913a8a34 2648
6e4468b9 2649 cmd_trb = xhci->cmd_ring->dequeue;
f2217e8e 2650 if (!ctx_change)
913a8a34
SS
2651 ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
2652 udev->slot_id, must_succeed);
f2217e8e 2653 else
913a8a34 2654 ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
4b266541 2655 udev->slot_id, must_succeed);
f2217e8e 2656 if (ret < 0) {
c01591bd
SS
2657 if (command)
2658 list_del(&command->cmd_list);
2cf95c18 2659 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
92f8e767 2660 xhci_free_host_resources(xhci, ctrl_ctx);
f2217e8e
SS
2661 spin_unlock_irqrestore(&xhci->lock, flags);
2662 xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
2663 return -ENOMEM;
2664 }
2665 xhci_ring_cmd_db(xhci);
2666 spin_unlock_irqrestore(&xhci->lock, flags);
2667
2668 /* Wait for the configure endpoint command to complete */
2669 timeleft = wait_for_completion_interruptible_timeout(
913a8a34 2670 cmd_completion,
6e4468b9 2671 XHCI_CMD_DEFAULT_TIMEOUT);
f2217e8e
SS
2672 if (timeleft <= 0) {
2673 xhci_warn(xhci, "%s while waiting for %s command\n",
2674 timeleft == 0 ? "Timeout" : "Signal",
2675 ctx_change == 0 ?
2676 "configure endpoint" :
2677 "evaluate context");
6e4468b9
EF
2678 /* cancel the configure endpoint command */
2679 ret = xhci_cancel_cmd(xhci, command, cmd_trb);
2680 if (ret < 0)
2681 return ret;
f2217e8e
SS
2682 return -ETIME;
2683 }
2684
2685 if (!ctx_change)
2cf95c18
SS
2686 ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
2687 else
2688 ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
2689
2690 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2691 spin_lock_irqsave(&xhci->lock, flags);
2692 /* If the command failed, remove the reserved resources.
2693 * Otherwise, clean up the estimate to include dropped eps.
2694 */
2695 if (ret)
92f8e767 2696 xhci_free_host_resources(xhci, ctrl_ctx);
2cf95c18 2697 else
92f8e767 2698 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2cf95c18
SS
2699 spin_unlock_irqrestore(&xhci->lock, flags);
2700 }
2701 return ret;
f2217e8e
SS
2702}
2703
f88ba78d
SS
2704/* Called after one or more calls to xhci_add_endpoint() or
2705 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2706 * to call xhci_reset_bandwidth().
2707 *
2708 * Since we are in the middle of changing either configuration or
2709 * installing a new alt setting, the USB core won't allow URBs to be
2710 * enqueued for any endpoint on the old config or interface. Nothing
2711 * else should be touching the xhci->devs[slot_id] structure, so we
2712 * don't need to take the xhci->lock for manipulating that.
2713 */
f94e0186
SS
2714int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2715{
2716 int i;
2717 int ret = 0;
f94e0186
SS
2718 struct xhci_hcd *xhci;
2719 struct xhci_virt_device *virt_dev;
d115b048
JY
2720 struct xhci_input_control_ctx *ctrl_ctx;
2721 struct xhci_slot_ctx *slot_ctx;
f94e0186 2722
64927730 2723 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
f94e0186
SS
2724 if (ret <= 0)
2725 return ret;
2726 xhci = hcd_to_xhci(hcd);
fe6c6c13
SS
2727 if (xhci->xhc_state & XHCI_STATE_DYING)
2728 return -ENODEV;
f94e0186 2729
700e2052 2730 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
f94e0186
SS
2731 virt_dev = xhci->devs[udev->slot_id];
2732
2733 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
d115b048 2734 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
92f8e767
SS
2735 if (!ctrl_ctx) {
2736 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2737 __func__);
2738 return -ENOMEM;
2739 }
28ccd296
ME
2740 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2741 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2742 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2dc37539
SS
2743
2744 /* Don't issue the command if there's no endpoints to update. */
2745 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2746 ctrl_ctx->drop_flags == 0)
2747 return 0;
2748
f94e0186 2749 xhci_dbg(xhci, "New Input Control Context:\n");
d115b048
JY
2750 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2751 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
28ccd296 2752 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
f94e0186 2753
913a8a34
SS
2754 ret = xhci_configure_endpoint(xhci, udev, NULL,
2755 false, false);
f94e0186
SS
2756 if (ret) {
2757 /* Callee should call reset_bandwidth() */
f94e0186
SS
2758 return ret;
2759 }
2760
2761 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
d115b048 2762 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
28ccd296 2763 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
f94e0186 2764
834cb0fc
SS
2765 /* Free any rings that were dropped, but not changed. */
2766 for (i = 1; i < 31; ++i) {
4819fef5
ME
2767 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2768 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
834cb0fc
SS
2769 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2770 }
d115b048 2771 xhci_zero_in_ctx(xhci, virt_dev);
834cb0fc
SS
2772 /*
2773 * Install any rings for completely new endpoints or changed endpoints,
2774 * and free or cache any old rings from changed endpoints.
2775 */
f94e0186 2776 for (i = 1; i < 31; ++i) {
74f9fe21
SS
2777 if (!virt_dev->eps[i].new_ring)
2778 continue;
2779 /* Only cache or free the old ring if it exists.
2780 * It may not if this is the first add of an endpoint.
2781 */
2782 if (virt_dev->eps[i].ring) {
412566bd 2783 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
f94e0186 2784 }
74f9fe21
SS
2785 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2786 virt_dev->eps[i].new_ring = NULL;
f94e0186
SS
2787 }
2788
f94e0186
SS
2789 return ret;
2790}
2791
2792void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2793{
f94e0186
SS
2794 struct xhci_hcd *xhci;
2795 struct xhci_virt_device *virt_dev;
2796 int i, ret;
2797
64927730 2798 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
f94e0186
SS
2799 if (ret <= 0)
2800 return;
2801 xhci = hcd_to_xhci(hcd);
2802
700e2052 2803 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
f94e0186
SS
2804 virt_dev = xhci->devs[udev->slot_id];
2805 /* Free any rings allocated for added endpoints */
2806 for (i = 0; i < 31; ++i) {
63a0d9ab
SS
2807 if (virt_dev->eps[i].new_ring) {
2808 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2809 virt_dev->eps[i].new_ring = NULL;
f94e0186
SS
2810 }
2811 }
d115b048 2812 xhci_zero_in_ctx(xhci, virt_dev);
f94e0186
SS
2813}
2814
5270b951 2815static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
913a8a34
SS
2816 struct xhci_container_ctx *in_ctx,
2817 struct xhci_container_ctx *out_ctx,
92f8e767 2818 struct xhci_input_control_ctx *ctrl_ctx,
913a8a34 2819 u32 add_flags, u32 drop_flags)
5270b951 2820{
28ccd296
ME
2821 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2822 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
913a8a34 2823 xhci_slot_copy(xhci, in_ctx, out_ctx);
28ccd296 2824 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5270b951 2825
913a8a34
SS
2826 xhci_dbg(xhci, "Input Context:\n");
2827 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
5270b951
SS
2828}
2829
8212a49d 2830static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
ac9d8fe7
SS
2831 unsigned int slot_id, unsigned int ep_index,
2832 struct xhci_dequeue_state *deq_state)
2833{
92f8e767 2834 struct xhci_input_control_ctx *ctrl_ctx;
ac9d8fe7 2835 struct xhci_container_ctx *in_ctx;
ac9d8fe7
SS
2836 struct xhci_ep_ctx *ep_ctx;
2837 u32 added_ctxs;
2838 dma_addr_t addr;
2839
92f8e767
SS
2840 in_ctx = xhci->devs[slot_id]->in_ctx;
2841 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2842 if (!ctrl_ctx) {
2843 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2844 __func__);
2845 return;
2846 }
2847
913a8a34
SS
2848 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2849 xhci->devs[slot_id]->out_ctx, ep_index);
ac9d8fe7
SS
2850 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2851 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2852 deq_state->new_deq_ptr);
2853 if (addr == 0) {
2854 xhci_warn(xhci, "WARN Cannot submit config ep after "
2855 "reset ep command\n");
2856 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2857 deq_state->new_deq_seg,
2858 deq_state->new_deq_ptr);
2859 return;
2860 }
28ccd296 2861 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
ac9d8fe7 2862
ac9d8fe7 2863 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
913a8a34 2864 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
92f8e767
SS
2865 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2866 added_ctxs, added_ctxs);
ac9d8fe7
SS
2867}
2868
82d1009f 2869void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
63a0d9ab 2870 struct usb_device *udev, unsigned int ep_index)
82d1009f
SS
2871{
2872 struct xhci_dequeue_state deq_state;
63a0d9ab 2873 struct xhci_virt_ep *ep;
82d1009f
SS
2874
2875 xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
63a0d9ab 2876 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
82d1009f
SS
2877 /* We need to move the HW's dequeue pointer past this TD,
2878 * or it will attempt to resend it on the next doorbell ring.
2879 */
2880 xhci_find_new_dequeue_state(xhci, udev->slot_id,
e9df17eb 2881 ep_index, ep->stopped_stream, ep->stopped_td,
ac9d8fe7 2882 &deq_state);
82d1009f 2883
ac9d8fe7
SS
2884 /* HW with the reset endpoint quirk will use the saved dequeue state to
2885 * issue a configure endpoint command later.
2886 */
2887 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2888 xhci_dbg(xhci, "Queueing new dequeue state\n");
63a0d9ab 2889 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
e9df17eb 2890 ep_index, ep->stopped_stream, &deq_state);
ac9d8fe7
SS
2891 } else {
2892 /* Better hope no one uses the input context between now and the
2893 * reset endpoint completion!
e9df17eb
SS
2894 * XXX: No idea how this hardware will react when stream rings
2895 * are enabled.
ac9d8fe7
SS
2896 */
2897 xhci_dbg(xhci, "Setting up input context for "
2898 "configure endpoint command\n");
2899 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2900 ep_index, &deq_state);
2901 }
82d1009f
SS
2902}
2903
a1587d97
SS
2904/* Deal with stalled endpoints. The core should have sent the control message
2905 * to clear the halt condition. However, we need to make the xHCI hardware
2906 * reset its sequence number, since a device will expect a sequence number of
2907 * zero after the halt condition is cleared.
2908 * Context: in_interrupt
2909 */
2910void xhci_endpoint_reset(struct usb_hcd *hcd,
2911 struct usb_host_endpoint *ep)
2912{
2913 struct xhci_hcd *xhci;
2914 struct usb_device *udev;
2915 unsigned int ep_index;
2916 unsigned long flags;
2917 int ret;
63a0d9ab 2918 struct xhci_virt_ep *virt_ep;
a1587d97
SS
2919
2920 xhci = hcd_to_xhci(hcd);
2921 udev = (struct usb_device *) ep->hcpriv;
2922 /* Called with a root hub endpoint (or an endpoint that wasn't added
2923 * with xhci_add_endpoint()
2924 */
2925 if (!ep->hcpriv)
2926 return;
2927 ep_index = xhci_get_endpoint_index(&ep->desc);
63a0d9ab
SS
2928 virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2929 if (!virt_ep->stopped_td) {
c92bcfa7
SS
2930 xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
2931 ep->desc.bEndpointAddress);
2932 return;
2933 }
82d1009f
SS
2934 if (usb_endpoint_xfer_control(&ep->desc)) {
2935 xhci_dbg(xhci, "Control endpoint stall already handled.\n");
2936 return;
2937 }
a1587d97
SS
2938
2939 xhci_dbg(xhci, "Queueing reset endpoint command\n");
2940 spin_lock_irqsave(&xhci->lock, flags);
2941 ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
c92bcfa7
SS
2942 /*
2943 * Can't change the ring dequeue pointer until it's transitioned to the
2944 * stopped state, which is only upon a successful reset endpoint
2945 * command. Better hope that last command worked!
2946 */
a1587d97 2947 if (!ret) {
63a0d9ab
SS
2948 xhci_cleanup_stalled_ring(xhci, udev, ep_index);
2949 kfree(virt_ep->stopped_td);
a1587d97
SS
2950 xhci_ring_cmd_db(xhci);
2951 }
1624ae1c
SS
2952 virt_ep->stopped_td = NULL;
2953 virt_ep->stopped_trb = NULL;
5e5cf6fc 2954 virt_ep->stopped_stream = 0;
a1587d97
SS
2955 spin_unlock_irqrestore(&xhci->lock, flags);
2956
2957 if (ret)
2958 xhci_warn(xhci, "FIXME allocate a new ring segment\n");
2959}
2960
8df75f42
SS
2961static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2962 struct usb_device *udev, struct usb_host_endpoint *ep,
2963 unsigned int slot_id)
2964{
2965 int ret;
2966 unsigned int ep_index;
2967 unsigned int ep_state;
2968
2969 if (!ep)
2970 return -EINVAL;
64927730 2971 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
8df75f42
SS
2972 if (ret <= 0)
2973 return -EINVAL;
842f1690 2974 if (ep->ss_ep_comp.bmAttributes == 0) {
8df75f42
SS
2975 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2976 " descriptor for ep 0x%x does not support streams\n",
2977 ep->desc.bEndpointAddress);
2978 return -EINVAL;
2979 }
2980
2981 ep_index = xhci_get_endpoint_index(&ep->desc);
2982 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2983 if (ep_state & EP_HAS_STREAMS ||
2984 ep_state & EP_GETTING_STREAMS) {
2985 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2986 "already has streams set up.\n",
2987 ep->desc.bEndpointAddress);
2988 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2989 "dynamic stream context array reallocation.\n");
2990 return -EINVAL;
2991 }
2992 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2993 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2994 "endpoint 0x%x; URBs are pending.\n",
2995 ep->desc.bEndpointAddress);
2996 return -EINVAL;
2997 }
2998 return 0;
2999}
3000
3001static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3002 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3003{
3004 unsigned int max_streams;
3005
3006 /* The stream context array size must be a power of two */
3007 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3008 /*
3009 * Find out how many primary stream array entries the host controller
3010 * supports. Later we may use secondary stream arrays (similar to 2nd
3011 * level page entries), but that's an optional feature for xHCI host
3012 * controllers. xHCs must support at least 4 stream IDs.
3013 */
3014 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3015 if (*num_stream_ctxs > max_streams) {
3016 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3017 max_streams);
3018 *num_stream_ctxs = max_streams;
3019 *num_streams = max_streams;
3020 }
3021}
3022
3023/* Returns an error code if one of the endpoint already has streams.
3024 * This does not change any data structures, it only checks and gathers
3025 * information.
3026 */
3027static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3028 struct usb_device *udev,
3029 struct usb_host_endpoint **eps, unsigned int num_eps,
3030 unsigned int *num_streams, u32 *changed_ep_bitmask)
3031{
8df75f42
SS
3032 unsigned int max_streams;
3033 unsigned int endpoint_flag;
3034 int i;
3035 int ret;
3036
3037 for (i = 0; i < num_eps; i++) {
3038 ret = xhci_check_streams_endpoint(xhci, udev,
3039 eps[i], udev->slot_id);
3040 if (ret < 0)
3041 return ret;
3042
18b7ede5 3043 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
8df75f42
SS
3044 if (max_streams < (*num_streams - 1)) {
3045 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3046 eps[i]->desc.bEndpointAddress,
3047 max_streams);
3048 *num_streams = max_streams+1;
3049 }
3050
3051 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3052 if (*changed_ep_bitmask & endpoint_flag)
3053 return -EINVAL;
3054 *changed_ep_bitmask |= endpoint_flag;
3055 }
3056 return 0;
3057}
3058
3059static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3060 struct usb_device *udev,
3061 struct usb_host_endpoint **eps, unsigned int num_eps)
3062{
3063 u32 changed_ep_bitmask = 0;
3064 unsigned int slot_id;
3065 unsigned int ep_index;
3066 unsigned int ep_state;
3067 int i;
3068
3069 slot_id = udev->slot_id;
3070 if (!xhci->devs[slot_id])
3071 return 0;
3072
3073 for (i = 0; i < num_eps; i++) {
3074 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3075 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3076 /* Are streams already being freed for the endpoint? */
3077 if (ep_state & EP_GETTING_NO_STREAMS) {
3078 xhci_warn(xhci, "WARN Can't disable streams for "
3079 "endpoint 0x%x\n, "
3080 "streams are being disabled already.",
3081 eps[i]->desc.bEndpointAddress);
3082 return 0;
3083 }
3084 /* Are there actually any streams to free? */
3085 if (!(ep_state & EP_HAS_STREAMS) &&
3086 !(ep_state & EP_GETTING_STREAMS)) {
3087 xhci_warn(xhci, "WARN Can't disable streams for "
3088 "endpoint 0x%x\n, "
3089 "streams are already disabled!",
3090 eps[i]->desc.bEndpointAddress);
3091 xhci_warn(xhci, "WARN xhci_free_streams() called "
3092 "with non-streams endpoint\n");
3093 return 0;
3094 }
3095 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3096 }
3097 return changed_ep_bitmask;
3098}
3099
3100/*
3101 * The USB device drivers use this function (though the HCD interface in USB
3102 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3103 * coordinate mass storage command queueing across multiple endpoints (basically
3104 * a stream ID == a task ID).
3105 *
3106 * Setting up streams involves allocating the same size stream context array
3107 * for each endpoint and issuing a configure endpoint command for all endpoints.
3108 *
3109 * Don't allow the call to succeed if one endpoint only supports one stream
3110 * (which means it doesn't support streams at all).
3111 *
3112 * Drivers may get less stream IDs than they asked for, if the host controller
3113 * hardware or endpoints claim they can't support the number of requested
3114 * stream IDs.
3115 */
3116int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3117 struct usb_host_endpoint **eps, unsigned int num_eps,
3118 unsigned int num_streams, gfp_t mem_flags)
3119{
3120 int i, ret;
3121 struct xhci_hcd *xhci;
3122 struct xhci_virt_device *vdev;
3123 struct xhci_command *config_cmd;
92f8e767 3124 struct xhci_input_control_ctx *ctrl_ctx;
8df75f42
SS
3125 unsigned int ep_index;
3126 unsigned int num_stream_ctxs;
3127 unsigned long flags;
3128 u32 changed_ep_bitmask = 0;
3129
3130 if (!eps)
3131 return -EINVAL;
3132
3133 /* Add one to the number of streams requested to account for
3134 * stream 0 that is reserved for xHCI usage.
3135 */
3136 num_streams += 1;
3137 xhci = hcd_to_xhci(hcd);
3138 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3139 num_streams);
3140
3141 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3142 if (!config_cmd) {
3143 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3144 return -ENOMEM;
3145 }
92f8e767
SS
3146 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
3147 if (!ctrl_ctx) {
3148 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3149 __func__);
3150 xhci_free_command(xhci, config_cmd);
3151 return -ENOMEM;
3152 }
8df75f42
SS
3153
3154 /* Check to make sure all endpoints are not already configured for
3155 * streams. While we're at it, find the maximum number of streams that
3156 * all the endpoints will support and check for duplicate endpoints.
3157 */
3158 spin_lock_irqsave(&xhci->lock, flags);
3159 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3160 num_eps, &num_streams, &changed_ep_bitmask);
3161 if (ret < 0) {
3162 xhci_free_command(xhci, config_cmd);
3163 spin_unlock_irqrestore(&xhci->lock, flags);
3164 return ret;
3165 }
3166 if (num_streams <= 1) {
3167 xhci_warn(xhci, "WARN: endpoints can't handle "
3168 "more than one stream.\n");
3169 xhci_free_command(xhci, config_cmd);
3170 spin_unlock_irqrestore(&xhci->lock, flags);
3171 return -EINVAL;
3172 }
3173 vdev = xhci->devs[udev->slot_id];
25985edc 3174 /* Mark each endpoint as being in transition, so
8df75f42
SS
3175 * xhci_urb_enqueue() will reject all URBs.
3176 */
3177 for (i = 0; i < num_eps; i++) {
3178 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3179 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3180 }
3181 spin_unlock_irqrestore(&xhci->lock, flags);
3182
3183 /* Setup internal data structures and allocate HW data structures for
3184 * streams (but don't install the HW structures in the input context
3185 * until we're sure all memory allocation succeeded).
3186 */
3187 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3188 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3189 num_stream_ctxs, num_streams);
3190
3191 for (i = 0; i < num_eps; i++) {
3192 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3193 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3194 num_stream_ctxs,
3195 num_streams, mem_flags);
3196 if (!vdev->eps[ep_index].stream_info)
3197 goto cleanup;
3198 /* Set maxPstreams in endpoint context and update deq ptr to
3199 * point to stream context array. FIXME
3200 */
3201 }
3202
3203 /* Set up the input context for a configure endpoint command. */
3204 for (i = 0; i < num_eps; i++) {
3205 struct xhci_ep_ctx *ep_ctx;
3206
3207 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3208 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3209
3210 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3211 vdev->out_ctx, ep_index);
3212 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3213 vdev->eps[ep_index].stream_info);
3214 }
3215 /* Tell the HW to drop its old copy of the endpoint context info
3216 * and add the updated copy from the input context.
3217 */
3218 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
92f8e767
SS
3219 vdev->out_ctx, ctrl_ctx,
3220 changed_ep_bitmask, changed_ep_bitmask);
8df75f42
SS
3221
3222 /* Issue and wait for the configure endpoint command */
3223 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3224 false, false);
3225
3226 /* xHC rejected the configure endpoint command for some reason, so we
3227 * leave the old ring intact and free our internal streams data
3228 * structure.
3229 */
3230 if (ret < 0)
3231 goto cleanup;
3232
3233 spin_lock_irqsave(&xhci->lock, flags);
3234 for (i = 0; i < num_eps; i++) {
3235 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3236 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3237 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3238 udev->slot_id, ep_index);
3239 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3240 }
3241 xhci_free_command(xhci, config_cmd);
3242 spin_unlock_irqrestore(&xhci->lock, flags);
3243
3244 /* Subtract 1 for stream 0, which drivers can't use */
3245 return num_streams - 1;
3246
3247cleanup:
3248 /* If it didn't work, free the streams! */
3249 for (i = 0; i < num_eps; i++) {
3250 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3251 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
8a007748 3252 vdev->eps[ep_index].stream_info = NULL;
8df75f42
SS
3253 /* FIXME Unset maxPstreams in endpoint context and
3254 * update deq ptr to point to normal string ring.
3255 */
3256 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3257 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3258 xhci_endpoint_zero(xhci, vdev, eps[i]);
3259 }
3260 xhci_free_command(xhci, config_cmd);
3261 return -ENOMEM;
3262}
3263
3264/* Transition the endpoint from using streams to being a "normal" endpoint
3265 * without streams.
3266 *
3267 * Modify the endpoint context state, submit a configure endpoint command,
3268 * and free all endpoint rings for streams if that completes successfully.
3269 */
3270int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3271 struct usb_host_endpoint **eps, unsigned int num_eps,
3272 gfp_t mem_flags)
3273{
3274 int i, ret;
3275 struct xhci_hcd *xhci;
3276 struct xhci_virt_device *vdev;
3277 struct xhci_command *command;
92f8e767 3278 struct xhci_input_control_ctx *ctrl_ctx;
8df75f42
SS
3279 unsigned int ep_index;
3280 unsigned long flags;
3281 u32 changed_ep_bitmask;
3282
3283 xhci = hcd_to_xhci(hcd);
3284 vdev = xhci->devs[udev->slot_id];
3285
3286 /* Set up a configure endpoint command to remove the streams rings */
3287 spin_lock_irqsave(&xhci->lock, flags);
3288 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3289 udev, eps, num_eps);
3290 if (changed_ep_bitmask == 0) {
3291 spin_unlock_irqrestore(&xhci->lock, flags);
3292 return -EINVAL;
3293 }
3294
3295 /* Use the xhci_command structure from the first endpoint. We may have
3296 * allocated too many, but the driver may call xhci_free_streams() for
3297 * each endpoint it grouped into one call to xhci_alloc_streams().
3298 */
3299 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3300 command = vdev->eps[ep_index].stream_info->free_streams_command;
92f8e767
SS
3301 ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
3302 if (!ctrl_ctx) {
1f21569c 3303 spin_unlock_irqrestore(&xhci->lock, flags);
92f8e767
SS
3304 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3305 __func__);
3306 return -EINVAL;
3307 }
3308
8df75f42
SS
3309 for (i = 0; i < num_eps; i++) {
3310 struct xhci_ep_ctx *ep_ctx;
3311
3312 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3313 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3314 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3315 EP_GETTING_NO_STREAMS;
3316
3317 xhci_endpoint_copy(xhci, command->in_ctx,
3318 vdev->out_ctx, ep_index);
3319 xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
3320 &vdev->eps[ep_index]);
3321 }
3322 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
92f8e767
SS
3323 vdev->out_ctx, ctrl_ctx,
3324 changed_ep_bitmask, changed_ep_bitmask);
8df75f42
SS
3325 spin_unlock_irqrestore(&xhci->lock, flags);
3326
3327 /* Issue and wait for the configure endpoint command,
3328 * which must succeed.
3329 */
3330 ret = xhci_configure_endpoint(xhci, udev, command,
3331 false, true);
3332
3333 /* xHC rejected the configure endpoint command for some reason, so we
3334 * leave the streams rings intact.
3335 */
3336 if (ret < 0)
3337 return ret;
3338
3339 spin_lock_irqsave(&xhci->lock, flags);
3340 for (i = 0; i < num_eps; i++) {
3341 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3342 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
8a007748 3343 vdev->eps[ep_index].stream_info = NULL;
8df75f42
SS
3344 /* FIXME Unset maxPstreams in endpoint context and
3345 * update deq ptr to point to normal string ring.
3346 */
3347 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3348 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3349 }
3350 spin_unlock_irqrestore(&xhci->lock, flags);
3351
3352 return 0;
3353}
3354
2cf95c18
SS
3355/*
3356 * Deletes endpoint resources for endpoints that were active before a Reset
3357 * Device command, or a Disable Slot command. The Reset Device command leaves
3358 * the control endpoint intact, whereas the Disable Slot command deletes it.
3359 *
3360 * Must be called with xhci->lock held.
3361 */
3362void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3363 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3364{
3365 int i;
3366 unsigned int num_dropped_eps = 0;
3367 unsigned int drop_flags = 0;
3368
3369 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3370 if (virt_dev->eps[i].ring) {
3371 drop_flags |= 1 << i;
3372 num_dropped_eps++;
3373 }
3374 }
3375 xhci->num_active_eps -= num_dropped_eps;
3376 if (num_dropped_eps)
3377 xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, "
3378 "%u now active.\n",
3379 num_dropped_eps, drop_flags,
3380 xhci->num_active_eps);
3381}
3382
2a8f82c4
SS
3383/*
3384 * This submits a Reset Device Command, which will set the device state to 0,
3385 * set the device address to 0, and disable all the endpoints except the default
3386 * control endpoint. The USB core should come back and call
3387 * xhci_address_device(), and then re-set up the configuration. If this is
3388 * called because of a usb_reset_and_verify_device(), then the old alternate
3389 * settings will be re-installed through the normal bandwidth allocation
3390 * functions.
3391 *
3392 * Wait for the Reset Device command to finish. Remove all structures
3393 * associated with the endpoints that were disabled. Clear the input device
3394 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
f0615c45
AX
3395 *
3396 * If the virt_dev to be reset does not exist or does not match the udev,
3397 * it means the device is lost, possibly due to the xHC restore error and
3398 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3399 * re-allocate the device.
2a8f82c4 3400 */
f0615c45 3401int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
2a8f82c4
SS
3402{
3403 int ret, i;
3404 unsigned long flags;
3405 struct xhci_hcd *xhci;
3406 unsigned int slot_id;
3407 struct xhci_virt_device *virt_dev;
3408 struct xhci_command *reset_device_cmd;
3409 int timeleft;
3410 int last_freed_endpoint;
001fd382 3411 struct xhci_slot_ctx *slot_ctx;
2e27980e 3412 int old_active_eps = 0;
2a8f82c4 3413
f0615c45 3414 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
2a8f82c4
SS
3415 if (ret <= 0)
3416 return ret;
3417 xhci = hcd_to_xhci(hcd);
3418 slot_id = udev->slot_id;
3419 virt_dev = xhci->devs[slot_id];
f0615c45
AX
3420 if (!virt_dev) {
3421 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3422 "not exist. Re-allocate the device\n", slot_id);
3423 ret = xhci_alloc_dev(hcd, udev);
3424 if (ret == 1)
3425 return 0;
3426 else
3427 return -EINVAL;
3428 }
3429
3430 if (virt_dev->udev != udev) {
3431 /* If the virt_dev and the udev does not match, this virt_dev
3432 * may belong to another udev.
3433 * Re-allocate the device.
3434 */
3435 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3436 "not match the udev. Re-allocate the device\n",
3437 slot_id);
3438 ret = xhci_alloc_dev(hcd, udev);
3439 if (ret == 1)
3440 return 0;
3441 else
3442 return -EINVAL;
3443 }
2a8f82c4 3444
001fd382
ML
3445 /* If device is not setup, there is no point in resetting it */
3446 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3447 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3448 SLOT_STATE_DISABLED)
3449 return 0;
3450
2a8f82c4
SS
3451 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3452 /* Allocate the command structure that holds the struct completion.
3453 * Assume we're in process context, since the normal device reset
3454 * process has to wait for the device anyway. Storage devices are
3455 * reset as part of error handling, so use GFP_NOIO instead of
3456 * GFP_KERNEL.
3457 */
3458 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3459 if (!reset_device_cmd) {
3460 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3461 return -ENOMEM;
3462 }
3463
3464 /* Attempt to submit the Reset Device command to the command ring */
3465 spin_lock_irqsave(&xhci->lock, flags);
3466 reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
7a3783ef
PZ
3467
3468 /* Enqueue pointer can be left pointing to the link TRB,
3469 * we must handle that
3470 */
f5960b69 3471 if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control))
7a3783ef
PZ
3472 reset_device_cmd->command_trb =
3473 xhci->cmd_ring->enq_seg->next->trbs;
3474
2a8f82c4
SS
3475 list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
3476 ret = xhci_queue_reset_device(xhci, slot_id);
3477 if (ret) {
3478 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3479 list_del(&reset_device_cmd->cmd_list);
3480 spin_unlock_irqrestore(&xhci->lock, flags);
3481 goto command_cleanup;
3482 }
3483 xhci_ring_cmd_db(xhci);
3484 spin_unlock_irqrestore(&xhci->lock, flags);
3485
3486 /* Wait for the Reset Device command to finish */
3487 timeleft = wait_for_completion_interruptible_timeout(
3488 reset_device_cmd->completion,
3489 USB_CTRL_SET_TIMEOUT);
3490 if (timeleft <= 0) {
3491 xhci_warn(xhci, "%s while waiting for reset device command\n",
3492 timeleft == 0 ? "Timeout" : "Signal");
3493 spin_lock_irqsave(&xhci->lock, flags);
3494 /* The timeout might have raced with the event ring handler, so
3495 * only delete from the list if the item isn't poisoned.
3496 */
3497 if (reset_device_cmd->cmd_list.next != LIST_POISON1)
3498 list_del(&reset_device_cmd->cmd_list);
3499 spin_unlock_irqrestore(&xhci->lock, flags);
3500 ret = -ETIME;
3501 goto command_cleanup;
3502 }
3503
3504 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3505 * unless we tried to reset a slot ID that wasn't enabled,
3506 * or the device wasn't in the addressed or configured state.
3507 */
3508 ret = reset_device_cmd->status;
3509 switch (ret) {
3510 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3511 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3512 xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
3513 slot_id,
3514 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3515 xhci_info(xhci, "Not freeing device rings.\n");
3516 /* Don't treat this as an error. May change my mind later. */
3517 ret = 0;
3518 goto command_cleanup;
3519 case COMP_SUCCESS:
3520 xhci_dbg(xhci, "Successful reset device command.\n");
3521 break;
3522 default:
3523 if (xhci_is_vendor_info_code(xhci, ret))
3524 break;
3525 xhci_warn(xhci, "Unknown completion code %u for "
3526 "reset device command.\n", ret);
3527 ret = -EINVAL;
3528 goto command_cleanup;
3529 }
3530
2cf95c18
SS
3531 /* Free up host controller endpoint resources */
3532 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3533 spin_lock_irqsave(&xhci->lock, flags);
3534 /* Don't delete the default control endpoint resources */
3535 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3536 spin_unlock_irqrestore(&xhci->lock, flags);
3537 }
3538
2a8f82c4
SS
3539 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3540 last_freed_endpoint = 1;
3541 for (i = 1; i < 31; ++i) {
2dea75d9
DT
3542 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3543
3544 if (ep->ep_state & EP_HAS_STREAMS) {
3545 xhci_free_stream_info(xhci, ep->stream_info);
3546 ep->stream_info = NULL;
3547 ep->ep_state &= ~EP_HAS_STREAMS;
3548 }
3549
3550 if (ep->ring) {
3551 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3552 last_freed_endpoint = i;
3553 }
2e27980e
SS
3554 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3555 xhci_drop_ep_from_interval_table(xhci,
3556 &virt_dev->eps[i].bw_info,
3557 virt_dev->bw_table,
3558 udev,
3559 &virt_dev->eps[i],
3560 virt_dev->tt_info);
9af5d71d 3561 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
2a8f82c4 3562 }
2e27980e
SS
3563 /* If necessary, update the number of active TTs on this root port */
3564 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3565
2a8f82c4
SS
3566 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3567 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3568 ret = 0;
3569
3570command_cleanup:
3571 xhci_free_command(xhci, reset_device_cmd);
3572 return ret;
3573}
3574
3ffbba95
SS
3575/*
3576 * At this point, the struct usb_device is about to go away, the device has
3577 * disconnected, and all traffic has been stopped and the endpoints have been
3578 * disabled. Free any HC data structures associated with that device.
3579 */
3580void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3581{
3582 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
6f5165cf 3583 struct xhci_virt_device *virt_dev;
3ffbba95 3584 unsigned long flags;
c526d0d4 3585 u32 state;
64927730 3586 int i, ret;
3ffbba95 3587
64927730 3588 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
7bd89b40
SS
3589 /* If the host is halted due to driver unload, we still need to free the
3590 * device.
3591 */
3592 if (ret <= 0 && ret != -ENODEV)
3ffbba95 3593 return;
64927730 3594
6f5165cf 3595 virt_dev = xhci->devs[udev->slot_id];
6f5165cf
SS
3596
3597 /* Stop any wayward timer functions (which may grab the lock) */
3598 for (i = 0; i < 31; ++i) {
3599 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3600 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3601 }
3ffbba95 3602
65580b43
AX
3603 if (udev->usb2_hw_lpm_enabled) {
3604 xhci_set_usb2_hardware_lpm(hcd, udev, 0);
3605 udev->usb2_hw_lpm_enabled = 0;
3606 }
3607
3ffbba95 3608 spin_lock_irqsave(&xhci->lock, flags);
c526d0d4
SS
3609 /* Don't disable the slot if the host controller is dead. */
3610 state = xhci_readl(xhci, &xhci->op_regs->status);
7bd89b40
SS
3611 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3612 (xhci->xhc_state & XHCI_STATE_HALTED)) {
c526d0d4
SS
3613 xhci_free_virt_device(xhci, udev->slot_id);
3614 spin_unlock_irqrestore(&xhci->lock, flags);
3615 return;
3616 }
3617
23e3be11 3618 if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
3ffbba95
SS
3619 spin_unlock_irqrestore(&xhci->lock, flags);
3620 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3621 return;
3622 }
23e3be11 3623 xhci_ring_cmd_db(xhci);
3ffbba95
SS
3624 spin_unlock_irqrestore(&xhci->lock, flags);
3625 /*
3626 * Event command completion handler will free any data structures
f88ba78d 3627 * associated with the slot. XXX Can free sleep?
3ffbba95
SS
3628 */
3629}
3630
2cf95c18
SS
3631/*
3632 * Checks if we have enough host controller resources for the default control
3633 * endpoint.
3634 *
3635 * Must be called with xhci->lock held.
3636 */
3637static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3638{
3639 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3640 xhci_dbg(xhci, "Not enough ep ctxs: "
3641 "%u active, need to add 1, limit is %u.\n",
3642 xhci->num_active_eps, xhci->limit_active_eps);
3643 return -ENOMEM;
3644 }
3645 xhci->num_active_eps += 1;
3646 xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n",
3647 xhci->num_active_eps);
3648 return 0;
3649}
3650
3651
3ffbba95
SS
3652/*
3653 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3654 * timed out, or allocating memory failed. Returns 1 on success.
3655 */
3656int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3657{
3658 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3659 unsigned long flags;
3660 int timeleft;
3661 int ret;
6e4468b9 3662 union xhci_trb *cmd_trb;
3ffbba95
SS
3663
3664 spin_lock_irqsave(&xhci->lock, flags);
6e4468b9 3665 cmd_trb = xhci->cmd_ring->dequeue;
23e3be11 3666 ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
3ffbba95
SS
3667 if (ret) {
3668 spin_unlock_irqrestore(&xhci->lock, flags);
3669 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3670 return 0;
3671 }
23e3be11 3672 xhci_ring_cmd_db(xhci);
3ffbba95
SS
3673 spin_unlock_irqrestore(&xhci->lock, flags);
3674
3675 /* XXX: how much time for xHC slot assignment? */
3676 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
6e4468b9 3677 XHCI_CMD_DEFAULT_TIMEOUT);
3ffbba95
SS
3678 if (timeleft <= 0) {
3679 xhci_warn(xhci, "%s while waiting for a slot\n",
3680 timeleft == 0 ? "Timeout" : "Signal");
6e4468b9
EF
3681 /* cancel the enable slot request */
3682 return xhci_cancel_cmd(xhci, NULL, cmd_trb);
3ffbba95
SS
3683 }
3684
3ffbba95
SS
3685 if (!xhci->slot_id) {
3686 xhci_err(xhci, "Error while assigning device slot ID\n");
3ffbba95
SS
3687 return 0;
3688 }
2cf95c18
SS
3689
3690 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3691 spin_lock_irqsave(&xhci->lock, flags);
3692 ret = xhci_reserve_host_control_ep_resources(xhci);
3693 if (ret) {
3694 spin_unlock_irqrestore(&xhci->lock, flags);
3695 xhci_warn(xhci, "Not enough host resources, "
3696 "active endpoint contexts = %u\n",
3697 xhci->num_active_eps);
3698 goto disable_slot;
3699 }
3700 spin_unlock_irqrestore(&xhci->lock, flags);
3701 }
3702 /* Use GFP_NOIO, since this function can be called from
a6d940dd
SS
3703 * xhci_discover_or_reset_device(), which may be called as part of
3704 * mass storage driver error handling.
3705 */
3706 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
3ffbba95 3707 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
2cf95c18 3708 goto disable_slot;
3ffbba95
SS
3709 }
3710 udev->slot_id = xhci->slot_id;
3711 /* Is this a LS or FS device under a HS hub? */
3712 /* Hub or peripherial? */
3ffbba95 3713 return 1;
2cf95c18
SS
3714
3715disable_slot:
3716 /* Disable slot, if we can do it without mem alloc */
3717 spin_lock_irqsave(&xhci->lock, flags);
3718 if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
3719 xhci_ring_cmd_db(xhci);
3720 spin_unlock_irqrestore(&xhci->lock, flags);
3721 return 0;
3ffbba95
SS
3722}
3723
3724/*
3725 * Issue an Address Device command (which will issue a SetAddress request to
3726 * the device).
3727 * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
3728 * we should only issue and wait on one address command at the same time.
3729 *
3730 * We add one to the device address issued by the hardware because the USB core
3731 * uses address 1 for the root hubs (even though they're not really devices).
3732 */
3733int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3734{
3735 unsigned long flags;
3736 int timeleft;
3737 struct xhci_virt_device *virt_dev;
3738 int ret = 0;
3739 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
d115b048
JY
3740 struct xhci_slot_ctx *slot_ctx;
3741 struct xhci_input_control_ctx *ctrl_ctx;
8e595a5d 3742 u64 temp_64;
6e4468b9 3743 union xhci_trb *cmd_trb;
3ffbba95
SS
3744
3745 if (!udev->slot_id) {
3746 xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
3747 return -EINVAL;
3748 }
3749
3ffbba95
SS
3750 virt_dev = xhci->devs[udev->slot_id];
3751
7ed603ec
ME
3752 if (WARN_ON(!virt_dev)) {
3753 /*
3754 * In plug/unplug torture test with an NEC controller,
3755 * a zero-dereference was observed once due to virt_dev = 0.
3756 * Print useful debug rather than crash if it is observed again!
3757 */
3758 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3759 udev->slot_id);
3760 return -EINVAL;
3761 }
3762
f0615c45 3763 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
92f8e767
SS
3764 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
3765 if (!ctrl_ctx) {
3766 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3767 __func__);
3768 return -EINVAL;
3769 }
f0615c45
AX
3770 /*
3771 * If this is the first Set Address since device plug-in or
3772 * virt_device realloaction after a resume with an xHCI power loss,
3773 * then set up the slot context.
3774 */
3775 if (!slot_ctx->dev_info)
3ffbba95 3776 xhci_setup_addressable_virt_dev(xhci, udev);
f0615c45 3777 /* Otherwise, update the control endpoint ring enqueue pointer. */
2d1ee590
SS
3778 else
3779 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
d31c285b
SS
3780 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3781 ctrl_ctx->drop_flags = 0;
3782
66e49d87 3783 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
d115b048 3784 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3ffbba95 3785
f88ba78d 3786 spin_lock_irqsave(&xhci->lock, flags);
6e4468b9 3787 cmd_trb = xhci->cmd_ring->dequeue;
d115b048
JY
3788 ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
3789 udev->slot_id);
3ffbba95
SS
3790 if (ret) {
3791 spin_unlock_irqrestore(&xhci->lock, flags);
3792 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3793 return ret;
3794 }
23e3be11 3795 xhci_ring_cmd_db(xhci);
3ffbba95
SS
3796 spin_unlock_irqrestore(&xhci->lock, flags);
3797
3798 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3799 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
6e4468b9 3800 XHCI_CMD_DEFAULT_TIMEOUT);
3ffbba95
SS
3801 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3802 * the SetAddress() "recovery interval" required by USB and aborting the
3803 * command on a timeout.
3804 */
3805 if (timeleft <= 0) {
cd68176a 3806 xhci_warn(xhci, "%s while waiting for address device command\n",
3ffbba95 3807 timeleft == 0 ? "Timeout" : "Signal");
6e4468b9
EF
3808 /* cancel the address device command */
3809 ret = xhci_cancel_cmd(xhci, NULL, cmd_trb);
3810 if (ret < 0)
3811 return ret;
3ffbba95
SS
3812 return -ETIME;
3813 }
3814
3ffbba95
SS
3815 switch (virt_dev->cmd_status) {
3816 case COMP_CTX_STATE:
3817 case COMP_EBADSLT:
3818 xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
3819 udev->slot_id);
3820 ret = -EINVAL;
3821 break;
3822 case COMP_TX_ERR:
3823 dev_warn(&udev->dev, "Device not responding to set address.\n");
3824 ret = -EPROTO;
3825 break;
f6ba6fe2
AH
3826 case COMP_DEV_ERR:
3827 dev_warn(&udev->dev, "ERROR: Incompatible device for address "
3828 "device command.\n");
3829 ret = -ENODEV;
3830 break;
3ffbba95
SS
3831 case COMP_SUCCESS:
3832 xhci_dbg(xhci, "Successful Address Device command\n");
3833 break;
3834 default:
3835 xhci_err(xhci, "ERROR: unexpected command completion "
3836 "code 0x%x.\n", virt_dev->cmd_status);
66e49d87 3837 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
d115b048 3838 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3ffbba95
SS
3839 ret = -EINVAL;
3840 break;
3841 }
3842 if (ret) {
3ffbba95
SS
3843 return ret;
3844 }
8e595a5d
SS
3845 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3846 xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
3847 xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
28ccd296
ME
3848 udev->slot_id,
3849 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3850 (unsigned long long)
3851 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
700e2052 3852 xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
d115b048 3853 (unsigned long long)virt_dev->out_ctx->dma);
3ffbba95 3854 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
d115b048 3855 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3ffbba95 3856 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
d115b048 3857 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3ffbba95
SS
3858 /*
3859 * USB core uses address 1 for the roothubs, so we add one to the
3860 * address given back to us by the HC.
3861 */
d115b048 3862 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
c8d4af8e
AX
3863 /* Use kernel assigned address for devices; store xHC assigned
3864 * address locally. */
28ccd296
ME
3865 virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
3866 + 1;
f94e0186 3867 /* Zero the input context control for later use */
d115b048
JY
3868 ctrl_ctx->add_flags = 0;
3869 ctrl_ctx->drop_flags = 0;
3ffbba95 3870
c8d4af8e 3871 xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address);
3ffbba95
SS
3872
3873 return 0;
3874}
3875
3f5eb141
LT
3876/*
3877 * Transfer the port index into real index in the HW port status
3878 * registers. Caculate offset between the port's PORTSC register
3879 * and port status base. Divide the number of per port register
3880 * to get the real index. The raw port number bases 1.
3881 */
3882int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3883{
3884 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3885 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3886 __le32 __iomem *addr;
3887 int raw_port;
3888
3889 if (hcd->speed != HCD_USB3)
3890 addr = xhci->usb2_ports[port1 - 1];
3891 else
3892 addr = xhci->usb3_ports[port1 - 1];
3893
3894 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
3895 return raw_port;
3896}
3897
a558ccdc
MN
3898/*
3899 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3900 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3901 */
d5c82feb 3902static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
a558ccdc
MN
3903 struct usb_device *udev, u16 max_exit_latency)
3904{
3905 struct xhci_virt_device *virt_dev;
3906 struct xhci_command *command;
3907 struct xhci_input_control_ctx *ctrl_ctx;
3908 struct xhci_slot_ctx *slot_ctx;
3909 unsigned long flags;
3910 int ret;
3911
3912 spin_lock_irqsave(&xhci->lock, flags);
3913 if (max_exit_latency == xhci->devs[udev->slot_id]->current_mel) {
3914 spin_unlock_irqrestore(&xhci->lock, flags);
3915 return 0;
3916 }
3917
3918 /* Attempt to issue an Evaluate Context command to change the MEL. */
3919 virt_dev = xhci->devs[udev->slot_id];
3920 command = xhci->lpm_command;
92f8e767
SS
3921 ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
3922 if (!ctrl_ctx) {
3923 spin_unlock_irqrestore(&xhci->lock, flags);
3924 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3925 __func__);
3926 return -ENOMEM;
3927 }
3928
a558ccdc
MN
3929 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
3930 spin_unlock_irqrestore(&xhci->lock, flags);
3931
a558ccdc
MN
3932 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3933 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
3934 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
3935 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
3936
3937 xhci_dbg(xhci, "Set up evaluate context for LPM MEL change.\n");
3938 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
3939 xhci_dbg_ctx(xhci, command->in_ctx, 0);
3940
3941 /* Issue and wait for the evaluate context command. */
3942 ret = xhci_configure_endpoint(xhci, udev, command,
3943 true, true);
3944 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
3945 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
3946
3947 if (!ret) {
3948 spin_lock_irqsave(&xhci->lock, flags);
3949 virt_dev->current_mel = max_exit_latency;
3950 spin_unlock_irqrestore(&xhci->lock, flags);
3951 }
3952 return ret;
3953}
3954
84ebc102 3955#ifdef CONFIG_PM_RUNTIME
9574323c
AX
3956
3957/* BESL to HIRD Encoding array for USB2 LPM */
3958static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
3959 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
3960
3961/* Calculate HIRD/BESL for USB2 PORTPMSC*/
f99298bf
AX
3962static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
3963 struct usb_device *udev)
9574323c 3964{
f99298bf
AX
3965 int u2del, besl, besl_host;
3966 int besl_device = 0;
3967 u32 field;
3968
3969 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
3970 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
9574323c 3971
f99298bf
AX
3972 if (field & USB_BESL_SUPPORT) {
3973 for (besl_host = 0; besl_host < 16; besl_host++) {
3974 if (xhci_besl_encoding[besl_host] >= u2del)
9574323c
AX
3975 break;
3976 }
f99298bf
AX
3977 /* Use baseline BESL value as default */
3978 if (field & USB_BESL_BASELINE_VALID)
3979 besl_device = USB_GET_BESL_BASELINE(field);
3980 else if (field & USB_BESL_DEEP_VALID)
3981 besl_device = USB_GET_BESL_DEEP(field);
9574323c
AX
3982 } else {
3983 if (u2del <= 50)
f99298bf 3984 besl_host = 0;
9574323c 3985 else
f99298bf 3986 besl_host = (u2del - 51) / 75 + 1;
9574323c
AX
3987 }
3988
f99298bf
AX
3989 besl = besl_host + besl_device;
3990 if (besl > 15)
3991 besl = 15;
3992
3993 return besl;
9574323c
AX
3994}
3995
a558ccdc
MN
3996/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
3997static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
3998{
3999 u32 field;
4000 int l1;
4001 int besld = 0;
4002 int hirdm = 0;
4003
4004 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4005
4006 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
17f34867 4007 l1 = udev->l1_params.timeout / 256;
a558ccdc
MN
4008
4009 /* device has preferred BESLD */
4010 if (field & USB_BESL_DEEP_VALID) {
4011 besld = USB_GET_BESL_DEEP(field);
4012 hirdm = 1;
4013 }
4014
4015 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4016}
4017
9574323c
AX
4018static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd,
4019 struct usb_device *udev)
4020{
4021 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4022 struct dev_info *dev_info;
4023 __le32 __iomem **port_array;
4024 __le32 __iomem *addr, *pm_addr;
4025 u32 temp, dev_id;
4026 unsigned int port_num;
4027 unsigned long flags;
f99298bf 4028 int hird;
9574323c
AX
4029 int ret;
4030
4031 if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support ||
4032 !udev->lpm_capable)
4033 return -EINVAL;
4034
4035 /* we only support lpm for non-hub device connected to root hub yet */
4036 if (!udev->parent || udev->parent->parent ||
4037 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4038 return -EINVAL;
4039
4040 spin_lock_irqsave(&xhci->lock, flags);
4041
4042 /* Look for devices in lpm_failed_devs list */
4043 dev_id = le16_to_cpu(udev->descriptor.idVendor) << 16 |
4044 le16_to_cpu(udev->descriptor.idProduct);
4045 list_for_each_entry(dev_info, &xhci->lpm_failed_devs, list) {
4046 if (dev_info->dev_id == dev_id) {
4047 ret = -EINVAL;
4048 goto finish;
4049 }
4050 }
4051
4052 port_array = xhci->usb2_ports;
4053 port_num = udev->portnum - 1;
4054
4055 if (port_num > HCS_MAX_PORTS(xhci->hcs_params1)) {
4056 xhci_dbg(xhci, "invalid port number %d\n", udev->portnum);
4057 ret = -EINVAL;
4058 goto finish;
4059 }
4060
4061 /*
4062 * Test USB 2.0 software LPM.
4063 * FIXME: some xHCI 1.0 hosts may implement a new register to set up
4064 * hardware-controlled USB 2.0 LPM. See section 5.4.11 and 4.23.5.1.1.1
4065 * in the June 2011 errata release.
4066 */
4067 xhci_dbg(xhci, "test port %d software LPM\n", port_num);
4068 /*
4069 * Set L1 Device Slot and HIRD/BESL.
4070 * Check device's USB 2.0 extension descriptor to determine whether
4071 * HIRD or BESL shoule be used. See USB2.0 LPM errata.
4072 */
b6e76371 4073 pm_addr = port_array[port_num] + PORTPMSC;
f99298bf 4074 hird = xhci_calculate_hird_besl(xhci, udev);
9574323c
AX
4075 temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird);
4076 xhci_writel(xhci, temp, pm_addr);
4077
4078 /* Set port link state to U2(L1) */
4079 addr = port_array[port_num];
4080 xhci_set_link_state(xhci, port_array, port_num, XDEV_U2);
4081
4082 /* wait for ACK */
4083 spin_unlock_irqrestore(&xhci->lock, flags);
4084 msleep(10);
4085 spin_lock_irqsave(&xhci->lock, flags);
4086
4087 /* Check L1 Status */
2611bd18
SS
4088 ret = xhci_handshake(xhci, pm_addr,
4089 PORT_L1S_MASK, PORT_L1S_SUCCESS, 125);
9574323c
AX
4090 if (ret != -ETIMEDOUT) {
4091 /* enter L1 successfully */
4092 temp = xhci_readl(xhci, addr);
4093 xhci_dbg(xhci, "port %d entered L1 state, port status 0x%x\n",
4094 port_num, temp);
4095 ret = 0;
4096 } else {
4097 temp = xhci_readl(xhci, pm_addr);
4098 xhci_dbg(xhci, "port %d software lpm failed, L1 status %d\n",
4099 port_num, temp & PORT_L1S_MASK);
4100 ret = -EINVAL;
4101 }
4102
4103 /* Resume the port */
4104 xhci_set_link_state(xhci, port_array, port_num, XDEV_U0);
4105
4106 spin_unlock_irqrestore(&xhci->lock, flags);
4107 msleep(10);
4108 spin_lock_irqsave(&xhci->lock, flags);
4109
4110 /* Clear PLC */
4111 xhci_test_and_clear_bit(xhci, port_array, port_num, PORT_PLC);
4112
4113 /* Check PORTSC to make sure the device is in the right state */
4114 if (!ret) {
4115 temp = xhci_readl(xhci, addr);
4116 xhci_dbg(xhci, "resumed port %d status 0x%x\n", port_num, temp);
4117 if (!(temp & PORT_CONNECT) || !(temp & PORT_PE) ||
4118 (temp & PORT_PLS_MASK) != XDEV_U0) {
4119 xhci_dbg(xhci, "port L1 resume fail\n");
4120 ret = -EINVAL;
4121 }
4122 }
4123
4124 if (ret) {
4125 /* Insert dev to lpm_failed_devs list */
4126 xhci_warn(xhci, "device LPM test failed, may disconnect and "
4127 "re-enumerate\n");
4128 dev_info = kzalloc(sizeof(struct dev_info), GFP_ATOMIC);
4129 if (!dev_info) {
4130 ret = -ENOMEM;
4131 goto finish;
4132 }
4133 dev_info->dev_id = dev_id;
4134 INIT_LIST_HEAD(&dev_info->list);
4135 list_add(&dev_info->list, &xhci->lpm_failed_devs);
4136 } else {
4137 xhci_ring_device(xhci, udev->slot_id);
4138 }
4139
4140finish:
4141 spin_unlock_irqrestore(&xhci->lock, flags);
4142 return ret;
4143}
4144
65580b43
AX
4145int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4146 struct usb_device *udev, int enable)
4147{
4148 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4149 __le32 __iomem **port_array;
a558ccdc
MN
4150 __le32 __iomem *pm_addr, *hlpm_addr;
4151 u32 pm_val, hlpm_val, field;
65580b43
AX
4152 unsigned int port_num;
4153 unsigned long flags;
a558ccdc
MN
4154 int hird, exit_latency;
4155 int ret;
65580b43
AX
4156
4157 if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support ||
4158 !udev->lpm_capable)
4159 return -EPERM;
4160
4161 if (!udev->parent || udev->parent->parent ||
4162 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4163 return -EPERM;
4164
4165 if (udev->usb2_hw_lpm_capable != 1)
4166 return -EPERM;
4167
4168 spin_lock_irqsave(&xhci->lock, flags);
4169
4170 port_array = xhci->usb2_ports;
4171 port_num = udev->portnum - 1;
b6e76371 4172 pm_addr = port_array[port_num] + PORTPMSC;
a558ccdc
MN
4173 pm_val = xhci_readl(xhci, pm_addr);
4174 hlpm_addr = port_array[port_num] + PORTHLPMC;
4175 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
65580b43
AX
4176
4177 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4178 enable ? "enable" : "disable", port_num);
4179
65580b43 4180 if (enable) {
a558ccdc
MN
4181 /* Host supports BESL timeout instead of HIRD */
4182 if (udev->usb2_hw_lpm_besl_capable) {
4183 /* if device doesn't have a preferred BESL value use a
4184 * default one which works with mixed HIRD and BESL
4185 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4186 */
4187 if ((field & USB_BESL_SUPPORT) &&
4188 (field & USB_BESL_BASELINE_VALID))
4189 hird = USB_GET_BESL_BASELINE(field);
4190 else
17f34867 4191 hird = udev->l1_params.besl;
a558ccdc
MN
4192
4193 exit_latency = xhci_besl_encoding[hird];
4194 spin_unlock_irqrestore(&xhci->lock, flags);
4195
4196 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4197 * input context for link powermanagement evaluate
4198 * context commands. It is protected by hcd->bandwidth
4199 * mutex and is shared by all devices. We need to set
4200 * the max ext latency in USB 2 BESL LPM as well, so
4201 * use the same mutex and xhci_change_max_exit_latency()
4202 */
4203 mutex_lock(hcd->bandwidth_mutex);
4204 ret = xhci_change_max_exit_latency(xhci, udev,
4205 exit_latency);
4206 mutex_unlock(hcd->bandwidth_mutex);
4207
4208 if (ret < 0)
4209 return ret;
4210 spin_lock_irqsave(&xhci->lock, flags);
4211
4212 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4213 xhci_writel(xhci, hlpm_val, hlpm_addr);
4214 /* flush write */
4215 xhci_readl(xhci, hlpm_addr);
4216 } else {
4217 hird = xhci_calculate_hird_besl(xhci, udev);
4218 }
4219
4220 pm_val &= ~PORT_HIRD_MASK;
4221 pm_val |= PORT_HIRD(hird) | PORT_RWE;
4222 xhci_writel(xhci, pm_val, pm_addr);
4223 pm_val = xhci_readl(xhci, pm_addr);
4224 pm_val |= PORT_HLE;
4225 xhci_writel(xhci, pm_val, pm_addr);
4226 /* flush write */
4227 xhci_readl(xhci, pm_addr);
65580b43 4228 } else {
a558ccdc
MN
4229 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK);
4230 xhci_writel(xhci, pm_val, pm_addr);
4231 /* flush write */
4232 xhci_readl(xhci, pm_addr);
4233 if (udev->usb2_hw_lpm_besl_capable) {
4234 spin_unlock_irqrestore(&xhci->lock, flags);
4235 mutex_lock(hcd->bandwidth_mutex);
4236 xhci_change_max_exit_latency(xhci, udev, 0);
4237 mutex_unlock(hcd->bandwidth_mutex);
4238 return 0;
4239 }
65580b43
AX
4240 }
4241
4242 spin_unlock_irqrestore(&xhci->lock, flags);
4243 return 0;
4244}
4245
b630d4b9
MN
4246/* check if a usb2 port supports a given extened capability protocol
4247 * only USB2 ports extended protocol capability values are cached.
4248 * Return 1 if capability is supported
4249 */
4250static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4251 unsigned capability)
4252{
4253 u32 port_offset, port_count;
4254 int i;
4255
4256 for (i = 0; i < xhci->num_ext_caps; i++) {
4257 if (xhci->ext_caps[i] & capability) {
4258 /* port offsets starts at 1 */
4259 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4260 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4261 if (port >= port_offset &&
4262 port < port_offset + port_count)
4263 return 1;
4264 }
4265 }
4266 return 0;
4267}
4268
b01bcbf7
SS
4269int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4270{
4271 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4272 int ret;
b630d4b9 4273 int portnum = udev->portnum - 1;
b01bcbf7
SS
4274
4275 ret = xhci_usb2_software_lpm_test(hcd, udev);
4276 if (!ret) {
4277 xhci_dbg(xhci, "software LPM test succeed\n");
b630d4b9
MN
4278 if (xhci->hw_lpm_support == 1 &&
4279 xhci_check_usb2_port_capability(xhci, portnum, XHCI_HLC)) {
b01bcbf7 4280 udev->usb2_hw_lpm_capable = 1;
17f34867
MN
4281 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4282 udev->l1_params.besl = XHCI_DEFAULT_BESL;
a558ccdc
MN
4283 if (xhci_check_usb2_port_capability(xhci, portnum,
4284 XHCI_BLC))
4285 udev->usb2_hw_lpm_besl_capable = 1;
b01bcbf7
SS
4286 ret = xhci_set_usb2_hardware_lpm(hcd, udev, 1);
4287 if (!ret)
4288 udev->usb2_hw_lpm_enabled = 1;
4289 }
4290 }
4291
4292 return 0;
4293}
4294
4295#else
4296
4297int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4298 struct usb_device *udev, int enable)
4299{
4300 return 0;
4301}
4302
4303int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4304{
4305 return 0;
4306}
4307
84ebc102 4308#endif /* CONFIG_PM_RUNTIME */
b01bcbf7 4309
3b3db026
SS
4310/*---------------------- USB 3.0 Link PM functions ------------------------*/
4311
b01bcbf7 4312#ifdef CONFIG_PM
e3567d2c
SS
4313/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4314static unsigned long long xhci_service_interval_to_ns(
4315 struct usb_endpoint_descriptor *desc)
4316{
16b45fdf 4317 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
e3567d2c
SS
4318}
4319
3b3db026
SS
4320static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4321 enum usb3_link_state state)
4322{
4323 unsigned long long sel;
4324 unsigned long long pel;
4325 unsigned int max_sel_pel;
4326 char *state_name;
4327
4328 switch (state) {
4329 case USB3_LPM_U1:
4330 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4331 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4332 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4333 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4334 state_name = "U1";
4335 break;
4336 case USB3_LPM_U2:
4337 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4338 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4339 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4340 state_name = "U2";
4341 break;
4342 default:
4343 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4344 __func__);
e25e62ae 4345 return USB3_LPM_DISABLED;
3b3db026
SS
4346 }
4347
4348 if (sel <= max_sel_pel && pel <= max_sel_pel)
4349 return USB3_LPM_DEVICE_INITIATED;
4350
4351 if (sel > max_sel_pel)
4352 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4353 "due to long SEL %llu ms\n",
4354 state_name, sel);
4355 else
4356 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4357 "due to long PEL %llu\n ms",
4358 state_name, pel);
4359 return USB3_LPM_DISABLED;
4360}
4361
e3567d2c
SS
4362/* Returns the hub-encoded U1 timeout value.
4363 * The U1 timeout should be the maximum of the following values:
4364 * - For control endpoints, U1 system exit latency (SEL) * 3
4365 * - For bulk endpoints, U1 SEL * 5
4366 * - For interrupt endpoints:
4367 * - Notification EPs, U1 SEL * 3
4368 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4369 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4370 */
4371static u16 xhci_calculate_intel_u1_timeout(struct usb_device *udev,
4372 struct usb_endpoint_descriptor *desc)
4373{
4374 unsigned long long timeout_ns;
4375 int ep_type;
4376 int intr_type;
4377
4378 ep_type = usb_endpoint_type(desc);
4379 switch (ep_type) {
4380 case USB_ENDPOINT_XFER_CONTROL:
4381 timeout_ns = udev->u1_params.sel * 3;
4382 break;
4383 case USB_ENDPOINT_XFER_BULK:
4384 timeout_ns = udev->u1_params.sel * 5;
4385 break;
4386 case USB_ENDPOINT_XFER_INT:
4387 intr_type = usb_endpoint_interrupt_type(desc);
4388 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4389 timeout_ns = udev->u1_params.sel * 3;
4390 break;
4391 }
4392 /* Otherwise the calculation is the same as isoc eps */
4393 case USB_ENDPOINT_XFER_ISOC:
4394 timeout_ns = xhci_service_interval_to_ns(desc);
c88db160 4395 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
e3567d2c
SS
4396 if (timeout_ns < udev->u1_params.sel * 2)
4397 timeout_ns = udev->u1_params.sel * 2;
4398 break;
4399 default:
4400 return 0;
4401 }
4402
4403 /* The U1 timeout is encoded in 1us intervals. */
c88db160 4404 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
e3567d2c
SS
4405 /* Don't return a timeout of zero, because that's USB3_LPM_DISABLED. */
4406 if (timeout_ns == USB3_LPM_DISABLED)
4407 timeout_ns++;
4408
4409 /* If the necessary timeout value is bigger than what we can set in the
4410 * USB 3.0 hub, we have to disable hub-initiated U1.
4411 */
4412 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4413 return timeout_ns;
4414 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4415 "due to long timeout %llu ms\n", timeout_ns);
4416 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4417}
4418
4419/* Returns the hub-encoded U2 timeout value.
4420 * The U2 timeout should be the maximum of:
4421 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4422 * - largest bInterval of any active periodic endpoint (to avoid going
4423 * into lower power link states between intervals).
4424 * - the U2 Exit Latency of the device
4425 */
4426static u16 xhci_calculate_intel_u2_timeout(struct usb_device *udev,
4427 struct usb_endpoint_descriptor *desc)
4428{
4429 unsigned long long timeout_ns;
4430 unsigned long long u2_del_ns;
4431
4432 timeout_ns = 10 * 1000 * 1000;
4433
4434 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4435 (xhci_service_interval_to_ns(desc) > timeout_ns))
4436 timeout_ns = xhci_service_interval_to_ns(desc);
4437
966e7a85 4438 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
e3567d2c
SS
4439 if (u2_del_ns > timeout_ns)
4440 timeout_ns = u2_del_ns;
4441
4442 /* The U2 timeout is encoded in 256us intervals */
c88db160 4443 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
e3567d2c
SS
4444 /* If the necessary timeout value is bigger than what we can set in the
4445 * USB 3.0 hub, we have to disable hub-initiated U2.
4446 */
4447 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4448 return timeout_ns;
4449 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4450 "due to long timeout %llu ms\n", timeout_ns);
4451 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4452}
4453
3b3db026
SS
4454static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4455 struct usb_device *udev,
4456 struct usb_endpoint_descriptor *desc,
4457 enum usb3_link_state state,
4458 u16 *timeout)
4459{
e3567d2c
SS
4460 if (state == USB3_LPM_U1) {
4461 if (xhci->quirks & XHCI_INTEL_HOST)
4462 return xhci_calculate_intel_u1_timeout(udev, desc);
4463 } else {
4464 if (xhci->quirks & XHCI_INTEL_HOST)
4465 return xhci_calculate_intel_u2_timeout(udev, desc);
4466 }
4467
3b3db026
SS
4468 return USB3_LPM_DISABLED;
4469}
4470
4471static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4472 struct usb_device *udev,
4473 struct usb_endpoint_descriptor *desc,
4474 enum usb3_link_state state,
4475 u16 *timeout)
4476{
4477 u16 alt_timeout;
4478
4479 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4480 desc, state, timeout);
4481
4482 /* If we found we can't enable hub-initiated LPM, or
4483 * the U1 or U2 exit latency was too high to allow
4484 * device-initiated LPM as well, just stop searching.
4485 */
4486 if (alt_timeout == USB3_LPM_DISABLED ||
4487 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4488 *timeout = alt_timeout;
4489 return -E2BIG;
4490 }
4491 if (alt_timeout > *timeout)
4492 *timeout = alt_timeout;
4493 return 0;
4494}
4495
4496static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4497 struct usb_device *udev,
4498 struct usb_host_interface *alt,
4499 enum usb3_link_state state,
4500 u16 *timeout)
4501{
4502 int j;
4503
4504 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4505 if (xhci_update_timeout_for_endpoint(xhci, udev,
4506 &alt->endpoint[j].desc, state, timeout))
4507 return -E2BIG;
4508 continue;
4509 }
4510 return 0;
4511}
4512
e3567d2c
SS
4513static int xhci_check_intel_tier_policy(struct usb_device *udev,
4514 enum usb3_link_state state)
4515{
4516 struct usb_device *parent;
4517 unsigned int num_hubs;
4518
4519 if (state == USB3_LPM_U2)
4520 return 0;
4521
4522 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4523 for (parent = udev->parent, num_hubs = 0; parent->parent;
4524 parent = parent->parent)
4525 num_hubs++;
4526
4527 if (num_hubs < 2)
4528 return 0;
4529
4530 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4531 " below second-tier hub.\n");
4532 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4533 "to decrease power consumption.\n");
4534 return -E2BIG;
4535}
4536
3b3db026
SS
4537static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4538 struct usb_device *udev,
4539 enum usb3_link_state state)
4540{
e3567d2c
SS
4541 if (xhci->quirks & XHCI_INTEL_HOST)
4542 return xhci_check_intel_tier_policy(udev, state);
3b3db026
SS
4543 return -EINVAL;
4544}
4545
4546/* Returns the U1 or U2 timeout that should be enabled.
4547 * If the tier check or timeout setting functions return with a non-zero exit
4548 * code, that means the timeout value has been finalized and we shouldn't look
4549 * at any more endpoints.
4550 */
4551static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4552 struct usb_device *udev, enum usb3_link_state state)
4553{
4554 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4555 struct usb_host_config *config;
4556 char *state_name;
4557 int i;
4558 u16 timeout = USB3_LPM_DISABLED;
4559
4560 if (state == USB3_LPM_U1)
4561 state_name = "U1";
4562 else if (state == USB3_LPM_U2)
4563 state_name = "U2";
4564 else {
4565 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4566 state);
4567 return timeout;
4568 }
4569
4570 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4571 return timeout;
4572
4573 /* Gather some information about the currently installed configuration
4574 * and alternate interface settings.
4575 */
4576 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4577 state, &timeout))
4578 return timeout;
4579
4580 config = udev->actconfig;
4581 if (!config)
4582 return timeout;
4583
4584 for (i = 0; i < USB_MAXINTERFACES; i++) {
4585 struct usb_driver *driver;
4586 struct usb_interface *intf = config->interface[i];
4587
4588 if (!intf)
4589 continue;
4590
4591 /* Check if any currently bound drivers want hub-initiated LPM
4592 * disabled.
4593 */
4594 if (intf->dev.driver) {
4595 driver = to_usb_driver(intf->dev.driver);
4596 if (driver && driver->disable_hub_initiated_lpm) {
4597 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4598 "at request of driver %s\n",
4599 state_name, driver->name);
4600 return xhci_get_timeout_no_hub_lpm(udev, state);
4601 }
4602 }
4603
4604 /* Not sure how this could happen... */
4605 if (!intf->cur_altsetting)
4606 continue;
4607
4608 if (xhci_update_timeout_for_interface(xhci, udev,
4609 intf->cur_altsetting,
4610 state, &timeout))
4611 return timeout;
4612 }
4613 return timeout;
4614}
4615
3b3db026
SS
4616static int calculate_max_exit_latency(struct usb_device *udev,
4617 enum usb3_link_state state_changed,
4618 u16 hub_encoded_timeout)
4619{
4620 unsigned long long u1_mel_us = 0;
4621 unsigned long long u2_mel_us = 0;
4622 unsigned long long mel_us = 0;
4623 bool disabling_u1;
4624 bool disabling_u2;
4625 bool enabling_u1;
4626 bool enabling_u2;
4627
4628 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4629 hub_encoded_timeout == USB3_LPM_DISABLED);
4630 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4631 hub_encoded_timeout == USB3_LPM_DISABLED);
4632
4633 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4634 hub_encoded_timeout != USB3_LPM_DISABLED);
4635 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4636 hub_encoded_timeout != USB3_LPM_DISABLED);
4637
4638 /* If U1 was already enabled and we're not disabling it,
4639 * or we're going to enable U1, account for the U1 max exit latency.
4640 */
4641 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4642 enabling_u1)
4643 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4644 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4645 enabling_u2)
4646 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4647
4648 if (u1_mel_us > u2_mel_us)
4649 mel_us = u1_mel_us;
4650 else
4651 mel_us = u2_mel_us;
4652 /* xHCI host controller max exit latency field is only 16 bits wide. */
4653 if (mel_us > MAX_EXIT) {
4654 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4655 "is too big.\n", mel_us);
4656 return -E2BIG;
4657 }
4658 return mel_us;
4659}
4660
4661/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4662int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4663 struct usb_device *udev, enum usb3_link_state state)
4664{
4665 struct xhci_hcd *xhci;
4666 u16 hub_encoded_timeout;
4667 int mel;
4668 int ret;
4669
4670 xhci = hcd_to_xhci(hcd);
4671 /* The LPM timeout values are pretty host-controller specific, so don't
4672 * enable hub-initiated timeouts unless the vendor has provided
4673 * information about their timeout algorithm.
4674 */
4675 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4676 !xhci->devs[udev->slot_id])
4677 return USB3_LPM_DISABLED;
4678
4679 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4680 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4681 if (mel < 0) {
4682 /* Max Exit Latency is too big, disable LPM. */
4683 hub_encoded_timeout = USB3_LPM_DISABLED;
4684 mel = 0;
4685 }
4686
4687 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4688 if (ret)
4689 return ret;
4690 return hub_encoded_timeout;
4691}
4692
4693int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4694 struct usb_device *udev, enum usb3_link_state state)
4695{
4696 struct xhci_hcd *xhci;
4697 u16 mel;
4698 int ret;
4699
4700 xhci = hcd_to_xhci(hcd);
4701 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4702 !xhci->devs[udev->slot_id])
4703 return 0;
4704
4705 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4706 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4707 if (ret)
4708 return ret;
4709 return 0;
4710}
b01bcbf7 4711#else /* CONFIG_PM */
9574323c 4712
b01bcbf7
SS
4713int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4714 struct usb_device *udev, enum usb3_link_state state)
65580b43 4715{
b01bcbf7 4716 return USB3_LPM_DISABLED;
65580b43
AX
4717}
4718
b01bcbf7
SS
4719int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4720 struct usb_device *udev, enum usb3_link_state state)
9574323c
AX
4721{
4722 return 0;
4723}
b01bcbf7 4724#endif /* CONFIG_PM */
9574323c 4725
b01bcbf7 4726/*-------------------------------------------------------------------------*/
9574323c 4727
ac1c1b7f
SS
4728/* Once a hub descriptor is fetched for a device, we need to update the xHC's
4729 * internal data structures for the device.
4730 */
4731int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4732 struct usb_tt *tt, gfp_t mem_flags)
4733{
4734 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4735 struct xhci_virt_device *vdev;
4736 struct xhci_command *config_cmd;
4737 struct xhci_input_control_ctx *ctrl_ctx;
4738 struct xhci_slot_ctx *slot_ctx;
4739 unsigned long flags;
4740 unsigned think_time;
4741 int ret;
4742
4743 /* Ignore root hubs */
4744 if (!hdev->parent)
4745 return 0;
4746
4747 vdev = xhci->devs[hdev->slot_id];
4748 if (!vdev) {
4749 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4750 return -EINVAL;
4751 }
a1d78c16 4752 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
ac1c1b7f
SS
4753 if (!config_cmd) {
4754 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4755 return -ENOMEM;
4756 }
92f8e767
SS
4757 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
4758 if (!ctrl_ctx) {
4759 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4760 __func__);
4761 xhci_free_command(xhci, config_cmd);
4762 return -ENOMEM;
4763 }
ac1c1b7f
SS
4764
4765 spin_lock_irqsave(&xhci->lock, flags);
839c817c
SS
4766 if (hdev->speed == USB_SPEED_HIGH &&
4767 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4768 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4769 xhci_free_command(xhci, config_cmd);
4770 spin_unlock_irqrestore(&xhci->lock, flags);
4771 return -ENOMEM;
4772 }
4773
ac1c1b7f 4774 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
28ccd296 4775 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
ac1c1b7f 4776 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
28ccd296 4777 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
ac1c1b7f 4778 if (tt->multi)
28ccd296 4779 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
ac1c1b7f
SS
4780 if (xhci->hci_version > 0x95) {
4781 xhci_dbg(xhci, "xHCI version %x needs hub "
4782 "TT think time and number of ports\n",
4783 (unsigned int) xhci->hci_version);
28ccd296 4784 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
ac1c1b7f
SS
4785 /* Set TT think time - convert from ns to FS bit times.
4786 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4787 * 2 = 24 FS bit times, 3 = 32 FS bit times.
700b4173
AX
4788 *
4789 * xHCI 1.0: this field shall be 0 if the device is not a
4790 * High-spped hub.
ac1c1b7f
SS
4791 */
4792 think_time = tt->think_time;
4793 if (think_time != 0)
4794 think_time = (think_time / 666) - 1;
700b4173
AX
4795 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4796 slot_ctx->tt_info |=
4797 cpu_to_le32(TT_THINK_TIME(think_time));
ac1c1b7f
SS
4798 } else {
4799 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4800 "TT think time or number of ports\n",
4801 (unsigned int) xhci->hci_version);
4802 }
4803 slot_ctx->dev_state = 0;
4804 spin_unlock_irqrestore(&xhci->lock, flags);
4805
4806 xhci_dbg(xhci, "Set up %s for hub device.\n",
4807 (xhci->hci_version > 0x95) ?
4808 "configure endpoint" : "evaluate context");
4809 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4810 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4811
4812 /* Issue and wait for the configure endpoint or
4813 * evaluate context command.
4814 */
4815 if (xhci->hci_version > 0x95)
4816 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4817 false, false);
4818 else
4819 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4820 true, false);
4821
4822 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4823 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4824
4825 xhci_free_command(xhci, config_cmd);
4826 return ret;
4827}
4828
66d4eadd
SS
4829int xhci_get_frame(struct usb_hcd *hcd)
4830{
4831 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4832 /* EHCI mods by the periodic size. Why? */
4833 return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
4834}
4835
552e0c4f
SAS
4836int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4837{
4838 struct xhci_hcd *xhci;
4839 struct device *dev = hcd->self.controller;
4840 int retval;
4841 u32 temp;
4842
fdaf8b31
AX
4843 /* Accept arbitrarily long scatter-gather lists */
4844 hcd->self.sg_tablesize = ~0;
19181bc5
HG
4845 /* XHCI controllers don't stop the ep queue on short packets :| */
4846 hcd->self.no_stop_on_short = 1;
552e0c4f
SAS
4847
4848 if (usb_hcd_is_primary_hcd(hcd)) {
4849 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
4850 if (!xhci)
4851 return -ENOMEM;
4852 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
4853 xhci->main_hcd = hcd;
4854 /* Mark the first roothub as being USB 2.0.
4855 * The xHCI driver will register the USB 3.0 roothub.
4856 */
4857 hcd->speed = HCD_USB2;
4858 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4859 /*
4860 * USB 2.0 roothub under xHCI has an integrated TT,
4861 * (rate matching hub) as opposed to having an OHCI/UHCI
4862 * companion controller.
4863 */
4864 hcd->has_tt = 1;
4865 } else {
4866 /* xHCI private pointer was set in xhci_pci_probe for the second
4867 * registered roothub.
4868 */
4869 xhci = hcd_to_xhci(hcd);
4870 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4871 if (HCC_64BIT_ADDR(temp)) {
4872 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4873 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4874 } else {
4875 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4876 }
4877 return 0;
4878 }
4879
4880 xhci->cap_regs = hcd->regs;
4881 xhci->op_regs = hcd->regs +
4882 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
4883 xhci->run_regs = hcd->regs +
4884 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4885 /* Cache read-only capability registers */
4886 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
4887 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
4888 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
4889 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
4890 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4891 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4892 xhci_print_registers(xhci);
4893
4894 get_quirks(dev, xhci);
4895
07f3cb7c
GC
4896 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4897 * success event after a short transfer. This quirk will ignore such
4898 * spurious event.
4899 */
4900 if (xhci->hci_version > 0x96)
4901 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4902
552e0c4f
SAS
4903 /* Make sure the HC is halted. */
4904 retval = xhci_halt(xhci);
4905 if (retval)
4906 goto error;
4907
4908 xhci_dbg(xhci, "Resetting HCD\n");
4909 /* Reset the internal HC memory state and registers. */
4910 retval = xhci_reset(xhci);
4911 if (retval)
4912 goto error;
4913 xhci_dbg(xhci, "Reset complete\n");
4914
4915 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4916 if (HCC_64BIT_ADDR(temp)) {
4917 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4918 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4919 } else {
4920 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4921 }
4922
4923 xhci_dbg(xhci, "Calling HCD init\n");
4924 /* Initialize HCD and host controller data structures. */
4925 retval = xhci_init(hcd);
4926 if (retval)
4927 goto error;
4928 xhci_dbg(xhci, "Called HCD init\n");
4929 return 0;
4930error:
4931 kfree(xhci);
4932 return retval;
4933}
4934
66d4eadd
SS
4935MODULE_DESCRIPTION(DRIVER_DESC);
4936MODULE_AUTHOR(DRIVER_AUTHOR);
4937MODULE_LICENSE("GPL");
4938
4939static int __init xhci_hcd_init(void)
4940{
0cc47d54 4941 int retval;
66d4eadd
SS
4942
4943 retval = xhci_register_pci();
66d4eadd
SS
4944 if (retval < 0) {
4945 printk(KERN_DEBUG "Problem registering PCI driver.");
4946 return retval;
4947 }
3429e91a
SAS
4948 retval = xhci_register_plat();
4949 if (retval < 0) {
4950 printk(KERN_DEBUG "Problem registering platform driver.");
4951 goto unreg_pci;
4952 }
98441973
SS
4953 /*
4954 * Check the compiler generated sizes of structures that must be laid
4955 * out in specific ways for hardware access.
4956 */
4957 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
4958 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
4959 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
4960 /* xhci_device_control has eight fields, and also
4961 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
4962 */
98441973
SS
4963 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
4964 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
4965 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
4966 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
4967 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
4968 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
4969 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
66d4eadd 4970 return 0;
3429e91a
SAS
4971unreg_pci:
4972 xhci_unregister_pci();
4973 return retval;
66d4eadd
SS
4974}
4975module_init(xhci_hcd_init);
4976
4977static void __exit xhci_hcd_cleanup(void)
4978{
66d4eadd 4979 xhci_unregister_pci();
3429e91a 4980 xhci_unregister_plat();
66d4eadd
SS
4981}
4982module_exit(xhci_hcd_cleanup);