Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
66d4eadd SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
66d4eadd SS |
9 | */ |
10 | ||
43b86af8 | 11 | #include <linux/pci.h> |
f7fac17c | 12 | #include <linux/iopoll.h> |
66d4eadd | 13 | #include <linux/irq.h> |
8df75f42 | 14 | #include <linux/log2.h> |
66d4eadd | 15 | #include <linux/module.h> |
b0567b3f | 16 | #include <linux/moduleparam.h> |
5a0e3ad6 | 17 | #include <linux/slab.h> |
71c731a2 | 18 | #include <linux/dmi.h> |
008eb957 | 19 | #include <linux/dma-mapping.h> |
66d4eadd SS |
20 | |
21 | #include "xhci.h" | |
84a99f6f | 22 | #include "xhci-trace.h" |
0cbd4b34 | 23 | #include "xhci-mtk.h" |
02b6fdc2 | 24 | #include "xhci-debugfs.h" |
dfba2174 | 25 | #include "xhci-dbgcap.h" |
66d4eadd SS |
26 | |
27 | #define DRIVER_AUTHOR "Sarah Sharp" | |
28 | #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" | |
29 | ||
a1377e53 LB |
30 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
31 | ||
b0567b3f SS |
32 | /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */ |
33 | static int link_quirk; | |
34 | module_param(link_quirk, int, S_IRUGO | S_IWUSR); | |
35 | MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); | |
36 | ||
36b68579 MZ |
37 | static unsigned long long quirks; |
38 | module_param(quirks, ullong, S_IRUGO); | |
4e6a1ee7 TI |
39 | MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default"); |
40 | ||
4937213b MN |
41 | static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring) |
42 | { | |
43 | struct xhci_segment *seg = ring->first_seg; | |
44 | ||
45 | if (!td || !td->start_seg) | |
46 | return false; | |
47 | do { | |
48 | if (seg == td->start_seg) | |
49 | return true; | |
50 | seg = seg->next; | |
51 | } while (seg && seg != ring->first_seg); | |
52 | ||
53 | return false; | |
54 | } | |
55 | ||
66d4eadd | 56 | /* |
2611bd18 | 57 | * xhci_handshake - spin reading hc until handshake completes or fails |
66d4eadd SS |
58 | * @ptr: address of hc register to be read |
59 | * @mask: bits to look at in result of read | |
60 | * @done: value of those bits when handshake succeeds | |
61 | * @usec: timeout in microseconds | |
62 | * | |
63 | * Returns negative errno, or zero on success | |
64 | * | |
65 | * Success happens when the "mask" bits have the specified value (hardware | |
66 | * handshake done). There are two failure modes: "usec" have passed (major | |
67 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
68 | */ | |
dc0b177c | 69 | int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec) |
66d4eadd SS |
70 | { |
71 | u32 result; | |
f7fac17c | 72 | int ret; |
66d4eadd | 73 | |
f7fac17c AS |
74 | ret = readl_poll_timeout_atomic(ptr, result, |
75 | (result & mask) == done || | |
76 | result == U32_MAX, | |
77 | 1, usec); | |
78 | if (result == U32_MAX) /* card removed */ | |
79 | return -ENODEV; | |
80 | ||
81 | return ret; | |
66d4eadd SS |
82 | } |
83 | ||
84 | /* | |
4f0f0bae | 85 | * Disable interrupts and begin the xHCI halting process. |
66d4eadd | 86 | */ |
4f0f0bae | 87 | void xhci_quiesce(struct xhci_hcd *xhci) |
66d4eadd SS |
88 | { |
89 | u32 halted; | |
90 | u32 cmd; | |
91 | u32 mask; | |
92 | ||
66d4eadd | 93 | mask = ~(XHCI_IRQS); |
b0ba9720 | 94 | halted = readl(&xhci->op_regs->status) & STS_HALT; |
66d4eadd SS |
95 | if (!halted) |
96 | mask &= ~CMD_RUN; | |
97 | ||
b0ba9720 | 98 | cmd = readl(&xhci->op_regs->command); |
66d4eadd | 99 | cmd &= mask; |
204b7793 | 100 | writel(cmd, &xhci->op_regs->command); |
4f0f0bae SS |
101 | } |
102 | ||
103 | /* | |
104 | * Force HC into halt state. | |
105 | * | |
106 | * Disable any IRQs and clear the run/stop bit. | |
107 | * HC will complete any current and actively pipelined transactions, and | |
bdfca502 | 108 | * should halt within 16 ms of the run/stop bit being cleared. |
4f0f0bae | 109 | * Read HC Halted bit in the status register to see when the HC is finished. |
4f0f0bae SS |
110 | */ |
111 | int xhci_halt(struct xhci_hcd *xhci) | |
112 | { | |
c6cc27c7 | 113 | int ret; |
d195fcff | 114 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC"); |
4f0f0bae | 115 | xhci_quiesce(xhci); |
66d4eadd | 116 | |
dc0b177c | 117 | ret = xhci_handshake(&xhci->op_regs->status, |
66d4eadd | 118 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); |
99154fd3 MN |
119 | if (ret) { |
120 | xhci_warn(xhci, "Host halt failed, %d\n", ret); | |
121 | return ret; | |
122 | } | |
123 | xhci->xhc_state |= XHCI_STATE_HALTED; | |
124 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
c6cc27c7 | 125 | return ret; |
66d4eadd SS |
126 | } |
127 | ||
ed07453f SS |
128 | /* |
129 | * Set the run bit and wait for the host to be running. | |
130 | */ | |
26bba5c7 | 131 | int xhci_start(struct xhci_hcd *xhci) |
ed07453f SS |
132 | { |
133 | u32 temp; | |
134 | int ret; | |
135 | ||
b0ba9720 | 136 | temp = readl(&xhci->op_regs->command); |
ed07453f | 137 | temp |= (CMD_RUN); |
d195fcff | 138 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", |
ed07453f | 139 | temp); |
204b7793 | 140 | writel(temp, &xhci->op_regs->command); |
ed07453f SS |
141 | |
142 | /* | |
143 | * Wait for the HCHalted Status bit to be 0 to indicate the host is | |
144 | * running. | |
145 | */ | |
dc0b177c | 146 | ret = xhci_handshake(&xhci->op_regs->status, |
ed07453f SS |
147 | STS_HALT, 0, XHCI_MAX_HALT_USEC); |
148 | if (ret == -ETIMEDOUT) | |
149 | xhci_err(xhci, "Host took too long to start, " | |
150 | "waited %u microseconds.\n", | |
151 | XHCI_MAX_HALT_USEC); | |
c6cc27c7 | 152 | if (!ret) |
98d74f9c MN |
153 | /* clear state flags. Including dying, halted or removing */ |
154 | xhci->xhc_state = 0; | |
e5bfeab0 | 155 | |
ed07453f SS |
156 | return ret; |
157 | } | |
158 | ||
66d4eadd | 159 | /* |
ac04e6ff | 160 | * Reset a halted HC. |
66d4eadd SS |
161 | * |
162 | * This resets pipelines, timers, counters, state machines, etc. | |
163 | * Transactions will be terminated immediately, and operational registers | |
164 | * will be set to their defaults. | |
165 | */ | |
166 | int xhci_reset(struct xhci_hcd *xhci) | |
167 | { | |
168 | u32 command; | |
169 | u32 state; | |
f6187f42 | 170 | int ret; |
66d4eadd | 171 | |
b0ba9720 | 172 | state = readl(&xhci->op_regs->status); |
c11ae038 MN |
173 | |
174 | if (state == ~(u32)0) { | |
175 | xhci_warn(xhci, "Host not accessible, reset failed.\n"); | |
176 | return -ENODEV; | |
177 | } | |
178 | ||
d3512f63 SS |
179 | if ((state & STS_HALT) == 0) { |
180 | xhci_warn(xhci, "Host controller not halted, aborting reset.\n"); | |
181 | return 0; | |
182 | } | |
66d4eadd | 183 | |
d195fcff | 184 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); |
b0ba9720 | 185 | command = readl(&xhci->op_regs->command); |
66d4eadd | 186 | command |= CMD_RESET; |
204b7793 | 187 | writel(command, &xhci->op_regs->command); |
66d4eadd | 188 | |
a5964396 RM |
189 | /* Existing Intel xHCI controllers require a delay of 1 mS, |
190 | * after setting the CMD_RESET bit, and before accessing any | |
191 | * HC registers. This allows the HC to complete the | |
192 | * reset operation and be ready for HC register access. | |
193 | * Without this delay, the subsequent HC register access, | |
194 | * may result in a system hang very rarely. | |
195 | */ | |
196 | if (xhci->quirks & XHCI_INTEL_HOST) | |
197 | udelay(1000); | |
198 | ||
dc0b177c | 199 | ret = xhci_handshake(&xhci->op_regs->command, |
22ceac19 | 200 | CMD_RESET, 0, 10 * 1000 * 1000); |
2d62f3ee SS |
201 | if (ret) |
202 | return ret; | |
203 | ||
9da5a109 JC |
204 | if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL) |
205 | usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller)); | |
206 | ||
d195fcff XR |
207 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
208 | "Wait for controller to be ready for doorbell rings"); | |
2d62f3ee SS |
209 | /* |
210 | * xHCI cannot write to any doorbells or operational registers other | |
211 | * than status until the "Controller Not Ready" flag is cleared. | |
212 | */ | |
dc0b177c | 213 | ret = xhci_handshake(&xhci->op_regs->status, |
22ceac19 | 214 | STS_CNR, 0, 10 * 1000 * 1000); |
f370b996 | 215 | |
f6187f42 MN |
216 | xhci->usb2_rhub.bus_state.port_c_suspend = 0; |
217 | xhci->usb2_rhub.bus_state.suspended_ports = 0; | |
218 | xhci->usb2_rhub.bus_state.resuming_ports = 0; | |
219 | xhci->usb3_rhub.bus_state.port_c_suspend = 0; | |
220 | xhci->usb3_rhub.bus_state.suspended_ports = 0; | |
221 | xhci->usb3_rhub.bus_state.resuming_ports = 0; | |
f370b996 AX |
222 | |
223 | return ret; | |
66d4eadd SS |
224 | } |
225 | ||
12de0a35 MZ |
226 | static void xhci_zero_64b_regs(struct xhci_hcd *xhci) |
227 | { | |
228 | struct device *dev = xhci_to_hcd(xhci)->self.sysdev; | |
229 | int err, i; | |
230 | u64 val; | |
231 | ||
232 | /* | |
233 | * Some Renesas controllers get into a weird state if they are | |
234 | * reset while programmed with 64bit addresses (they will preserve | |
235 | * the top half of the address in internal, non visible | |
236 | * registers). You end up with half the address coming from the | |
237 | * kernel, and the other half coming from the firmware. Also, | |
238 | * changing the programming leads to extra accesses even if the | |
239 | * controller is supposed to be halted. The controller ends up with | |
240 | * a fatal fault, and is then ripe for being properly reset. | |
241 | * | |
242 | * Special care is taken to only apply this if the device is behind | |
243 | * an iommu. Doing anything when there is no iommu is definitely | |
244 | * unsafe... | |
245 | */ | |
05afde1a | 246 | if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev)) |
12de0a35 MZ |
247 | return; |
248 | ||
249 | xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n"); | |
250 | ||
251 | /* Clear HSEIE so that faults do not get signaled */ | |
252 | val = readl(&xhci->op_regs->command); | |
253 | val &= ~CMD_HSEIE; | |
254 | writel(val, &xhci->op_regs->command); | |
255 | ||
256 | /* Clear HSE (aka FATAL) */ | |
257 | val = readl(&xhci->op_regs->status); | |
258 | val |= STS_FATAL; | |
259 | writel(val, &xhci->op_regs->status); | |
260 | ||
261 | /* Now zero the registers, and brace for impact */ | |
262 | val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); | |
263 | if (upper_32_bits(val)) | |
264 | xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr); | |
265 | val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
266 | if (upper_32_bits(val)) | |
267 | xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring); | |
268 | ||
269 | for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) { | |
270 | struct xhci_intr_reg __iomem *ir; | |
271 | ||
272 | ir = &xhci->run_regs->ir_set[i]; | |
273 | val = xhci_read_64(xhci, &ir->erst_base); | |
274 | if (upper_32_bits(val)) | |
275 | xhci_write_64(xhci, 0, &ir->erst_base); | |
276 | val= xhci_read_64(xhci, &ir->erst_dequeue); | |
277 | if (upper_32_bits(val)) | |
278 | xhci_write_64(xhci, 0, &ir->erst_dequeue); | |
279 | } | |
280 | ||
281 | /* Wait for the fault to appear. It will be cleared on reset */ | |
282 | err = xhci_handshake(&xhci->op_regs->status, | |
283 | STS_FATAL, STS_FATAL, | |
284 | XHCI_MAX_HALT_USEC); | |
285 | if (!err) | |
286 | xhci_info(xhci, "Fault detected\n"); | |
287 | } | |
43b86af8 | 288 | |
77d45b45 | 289 | #ifdef CONFIG_USB_PCI |
43b86af8 DN |
290 | /* |
291 | * Set up MSI | |
292 | */ | |
293 | static int xhci_setup_msi(struct xhci_hcd *xhci) | |
66d4eadd SS |
294 | { |
295 | int ret; | |
4c39d4b9 AB |
296 | /* |
297 | * TODO:Check with MSI Soc for sysdev | |
298 | */ | |
43b86af8 DN |
299 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
300 | ||
77d45b45 CH |
301 | ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); |
302 | if (ret < 0) { | |
d195fcff XR |
303 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
304 | "failed to allocate MSI entry"); | |
43b86af8 DN |
305 | return ret; |
306 | } | |
307 | ||
851ec164 | 308 | ret = request_irq(pdev->irq, xhci_msi_irq, |
43b86af8 DN |
309 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
310 | if (ret) { | |
d195fcff XR |
311 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
312 | "disable MSI interrupt"); | |
77d45b45 | 313 | pci_free_irq_vectors(pdev); |
43b86af8 DN |
314 | } |
315 | ||
316 | return ret; | |
317 | } | |
318 | ||
319 | /* | |
320 | * Set up MSI-X | |
321 | */ | |
322 | static int xhci_setup_msix(struct xhci_hcd *xhci) | |
323 | { | |
324 | int i, ret = 0; | |
0029227f AX |
325 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
326 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 327 | |
43b86af8 DN |
328 | /* |
329 | * calculate number of msi-x vectors supported. | |
330 | * - HCS_MAX_INTRS: the max number of interrupts the host can handle, | |
331 | * with max number of interrupters based on the xhci HCSPARAMS1. | |
332 | * - num_online_cpus: maximum msi-x vectors per CPUs core. | |
333 | * Add additional 1 vector to ensure always available interrupt. | |
334 | */ | |
335 | xhci->msix_count = min(num_online_cpus() + 1, | |
336 | HCS_MAX_INTRS(xhci->hcs_params1)); | |
337 | ||
77d45b45 CH |
338 | ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count, |
339 | PCI_IRQ_MSIX); | |
340 | if (ret < 0) { | |
d195fcff XR |
341 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
342 | "Failed to enable MSI-X"); | |
77d45b45 | 343 | return ret; |
66d4eadd SS |
344 | } |
345 | ||
43b86af8 | 346 | for (i = 0; i < xhci->msix_count; i++) { |
77d45b45 CH |
347 | ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0, |
348 | "xhci_hcd", xhci_to_hcd(xhci)); | |
43b86af8 DN |
349 | if (ret) |
350 | goto disable_msix; | |
66d4eadd | 351 | } |
43b86af8 | 352 | |
0029227f | 353 | hcd->msix_enabled = 1; |
43b86af8 | 354 | return ret; |
66d4eadd SS |
355 | |
356 | disable_msix: | |
d195fcff | 357 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); |
77d45b45 CH |
358 | while (--i >= 0) |
359 | free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); | |
360 | pci_free_irq_vectors(pdev); | |
66d4eadd SS |
361 | return ret; |
362 | } | |
363 | ||
66d4eadd SS |
364 | /* Free any IRQs and disable MSI-X */ |
365 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |
366 | { | |
0029227f AX |
367 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
368 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 369 | |
9005355a JP |
370 | if (xhci->quirks & XHCI_PLAT) |
371 | return; | |
372 | ||
77d45b45 CH |
373 | /* return if using legacy interrupt */ |
374 | if (hcd->irq > 0) | |
375 | return; | |
376 | ||
377 | if (hcd->msix_enabled) { | |
378 | int i; | |
43b86af8 | 379 | |
77d45b45 CH |
380 | for (i = 0; i < xhci->msix_count; i++) |
381 | free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); | |
43b86af8 | 382 | } else { |
77d45b45 | 383 | free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); |
43b86af8 DN |
384 | } |
385 | ||
77d45b45 | 386 | pci_free_irq_vectors(pdev); |
0029227f | 387 | hcd->msix_enabled = 0; |
66d4eadd | 388 | } |
66d4eadd | 389 | |
d5c82feb | 390 | static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 | 391 | { |
77d45b45 CH |
392 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
393 | ||
394 | if (hcd->msix_enabled) { | |
395 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
396 | int i; | |
421aa841 | 397 | |
421aa841 | 398 | for (i = 0; i < xhci->msix_count; i++) |
77d45b45 | 399 | synchronize_irq(pci_irq_vector(pdev, i)); |
421aa841 SAS |
400 | } |
401 | } | |
402 | ||
403 | static int xhci_try_enable_msi(struct usb_hcd *hcd) | |
404 | { | |
405 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
52fb6125 | 406 | struct pci_dev *pdev; |
421aa841 SAS |
407 | int ret; |
408 | ||
52fb6125 SS |
409 | /* The xhci platform device has set up IRQs through usb_add_hcd. */ |
410 | if (xhci->quirks & XHCI_PLAT) | |
411 | return 0; | |
412 | ||
413 | pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
421aa841 SAS |
414 | /* |
415 | * Some Fresco Logic host controllers advertise MSI, but fail to | |
416 | * generate interrupts. Don't even try to enable MSI. | |
417 | */ | |
418 | if (xhci->quirks & XHCI_BROKEN_MSI) | |
00eed9c8 | 419 | goto legacy_irq; |
421aa841 SAS |
420 | |
421 | /* unregister the legacy interrupt */ | |
422 | if (hcd->irq) | |
423 | free_irq(hcd->irq, hcd); | |
cd70469d | 424 | hcd->irq = 0; |
421aa841 SAS |
425 | |
426 | ret = xhci_setup_msix(xhci); | |
427 | if (ret) | |
428 | /* fall back to msi*/ | |
429 | ret = xhci_setup_msi(xhci); | |
430 | ||
6a29beef PC |
431 | if (!ret) { |
432 | hcd->msi_enabled = 1; | |
421aa841 | 433 | return 0; |
6a29beef | 434 | } |
421aa841 | 435 | |
68d07f64 SS |
436 | if (!pdev->irq) { |
437 | xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); | |
438 | return -EINVAL; | |
439 | } | |
440 | ||
00eed9c8 | 441 | legacy_irq: |
79699437 AH |
442 | if (!strlen(hcd->irq_descr)) |
443 | snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", | |
444 | hcd->driver->description, hcd->self.busnum); | |
445 | ||
421aa841 SAS |
446 | /* fall back to legacy interrupt*/ |
447 | ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, | |
448 | hcd->irq_descr, hcd); | |
449 | if (ret) { | |
450 | xhci_err(xhci, "request interrupt %d failed\n", | |
451 | pdev->irq); | |
452 | return ret; | |
453 | } | |
454 | hcd->irq = pdev->irq; | |
455 | return 0; | |
456 | } | |
457 | ||
458 | #else | |
459 | ||
01bb59eb | 460 | static inline int xhci_try_enable_msi(struct usb_hcd *hcd) |
421aa841 SAS |
461 | { |
462 | return 0; | |
463 | } | |
464 | ||
01bb59eb | 465 | static inline void xhci_cleanup_msix(struct xhci_hcd *xhci) |
421aa841 SAS |
466 | { |
467 | } | |
468 | ||
01bb59eb | 469 | static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 SAS |
470 | { |
471 | } | |
472 | ||
473 | #endif | |
474 | ||
e99e88a9 | 475 | static void compliance_mode_recovery(struct timer_list *t) |
71c731a2 AC |
476 | { |
477 | struct xhci_hcd *xhci; | |
478 | struct usb_hcd *hcd; | |
38986ffa | 479 | struct xhci_hub *rhub; |
71c731a2 AC |
480 | u32 temp; |
481 | int i; | |
482 | ||
e99e88a9 | 483 | xhci = from_timer(xhci, t, comp_mode_recovery_timer); |
38986ffa | 484 | rhub = &xhci->usb3_rhub; |
71c731a2 | 485 | |
38986ffa MN |
486 | for (i = 0; i < rhub->num_ports; i++) { |
487 | temp = readl(rhub->ports[i]->addr); | |
71c731a2 AC |
488 | if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) { |
489 | /* | |
490 | * Compliance Mode Detected. Letting USB Core | |
491 | * handle the Warm Reset | |
492 | */ | |
4bdfe4c3 XR |
493 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
494 | "Compliance mode detected->port %d", | |
71c731a2 | 495 | i + 1); |
4bdfe4c3 XR |
496 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
497 | "Attempting compliance mode recovery"); | |
71c731a2 AC |
498 | hcd = xhci->shared_hcd; |
499 | ||
500 | if (hcd->state == HC_STATE_SUSPENDED) | |
501 | usb_hcd_resume_root_hub(hcd); | |
502 | ||
503 | usb_hcd_poll_rh_status(hcd); | |
504 | } | |
505 | } | |
506 | ||
38986ffa | 507 | if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1)) |
71c731a2 AC |
508 | mod_timer(&xhci->comp_mode_recovery_timer, |
509 | jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS)); | |
510 | } | |
511 | ||
512 | /* | |
513 | * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver | |
514 | * that causes ports behind that hardware to enter compliance mode sometimes. | |
515 | * The quirk creates a timer that polls every 2 seconds the link state of | |
516 | * each host controller's port and recovers it by issuing a Warm reset | |
517 | * if Compliance mode is detected, otherwise the port will become "dead" (no | |
518 | * device connections or disconnections will be detected anymore). Becasue no | |
519 | * status event is generated when entering compliance mode (per xhci spec), | |
520 | * this quirk is needed on systems that have the failing hardware installed. | |
521 | */ | |
522 | static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci) | |
523 | { | |
524 | xhci->port_status_u0 = 0; | |
e99e88a9 KC |
525 | timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery, |
526 | 0); | |
71c731a2 AC |
527 | xhci->comp_mode_recovery_timer.expires = jiffies + |
528 | msecs_to_jiffies(COMP_MODE_RCVRY_MSECS); | |
529 | ||
71c731a2 | 530 | add_timer(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
531 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
532 | "Compliance mode recovery timer initialized"); | |
71c731a2 AC |
533 | } |
534 | ||
535 | /* | |
536 | * This function identifies the systems that have installed the SN65LVPE502CP | |
537 | * USB3.0 re-driver and that need the Compliance Mode Quirk. | |
538 | * Systems: | |
539 | * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820 | |
540 | */ | |
e1cd9727 | 541 | static bool xhci_compliance_mode_recovery_timer_quirk_check(void) |
71c731a2 AC |
542 | { |
543 | const char *dmi_product_name, *dmi_sys_vendor; | |
544 | ||
545 | dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); | |
546 | dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR); | |
457a73d3 VG |
547 | if (!dmi_product_name || !dmi_sys_vendor) |
548 | return false; | |
71c731a2 AC |
549 | |
550 | if (!(strstr(dmi_sys_vendor, "Hewlett-Packard"))) | |
551 | return false; | |
552 | ||
553 | if (strstr(dmi_product_name, "Z420") || | |
554 | strstr(dmi_product_name, "Z620") || | |
47080974 | 555 | strstr(dmi_product_name, "Z820") || |
b0e4e606 | 556 | strstr(dmi_product_name, "Z1 Workstation")) |
71c731a2 AC |
557 | return true; |
558 | ||
559 | return false; | |
560 | } | |
561 | ||
562 | static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci) | |
563 | { | |
38986ffa | 564 | return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1)); |
71c731a2 AC |
565 | } |
566 | ||
567 | ||
66d4eadd SS |
568 | /* |
569 | * Initialize memory for HCD and xHC (one-time init). | |
570 | * | |
571 | * Program the PAGESIZE register, initialize the device context array, create | |
572 | * device contexts (?), set up a command ring segment (or two?), create event | |
573 | * ring (one for now). | |
574 | */ | |
3969384c | 575 | static int xhci_init(struct usb_hcd *hcd) |
66d4eadd SS |
576 | { |
577 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
578 | int retval = 0; | |
579 | ||
d195fcff | 580 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init"); |
66d4eadd | 581 | spin_lock_init(&xhci->lock); |
d7826599 | 582 | if (xhci->hci_version == 0x95 && link_quirk) { |
4bdfe4c3 XR |
583 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
584 | "QUIRK: Not clearing Link TRB chain bits."); | |
b0567b3f SS |
585 | xhci->quirks |= XHCI_LINK_TRB_QUIRK; |
586 | } else { | |
d195fcff XR |
587 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
588 | "xHCI doesn't need link TRB QUIRK"); | |
b0567b3f | 589 | } |
66d4eadd | 590 | retval = xhci_mem_init(xhci, GFP_KERNEL); |
d195fcff | 591 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init"); |
66d4eadd | 592 | |
71c731a2 | 593 | /* Initializing Compliance Mode Recovery Data If Needed */ |
c3897aa5 | 594 | if (xhci_compliance_mode_recovery_timer_quirk_check()) { |
71c731a2 AC |
595 | xhci->quirks |= XHCI_COMP_MODE_QUIRK; |
596 | compliance_mode_recovery_timer_init(xhci); | |
597 | } | |
598 | ||
66d4eadd SS |
599 | return retval; |
600 | } | |
601 | ||
7f84eef0 SS |
602 | /*-------------------------------------------------------------------------*/ |
603 | ||
7f84eef0 | 604 | |
f6ff0ac8 SS |
605 | static int xhci_run_finished(struct xhci_hcd *xhci) |
606 | { | |
607 | if (xhci_start(xhci)) { | |
608 | xhci_halt(xhci); | |
609 | return -ENODEV; | |
610 | } | |
611 | xhci->shared_hcd->state = HC_STATE_RUNNING; | |
c181bc5b | 612 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; |
f6ff0ac8 SS |
613 | |
614 | if (xhci->quirks & XHCI_NEC_HOST) | |
615 | xhci_ring_cmd_db(xhci); | |
616 | ||
d195fcff XR |
617 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
618 | "Finished xhci_run for USB3 roothub"); | |
f6ff0ac8 SS |
619 | return 0; |
620 | } | |
621 | ||
66d4eadd SS |
622 | /* |
623 | * Start the HC after it was halted. | |
624 | * | |
625 | * This function is called by the USB core when the HC driver is added. | |
626 | * Its opposite is xhci_stop(). | |
627 | * | |
628 | * xhci_init() must be called once before this function can be called. | |
629 | * Reset the HC, enable device slot contexts, program DCBAAP, and | |
630 | * set command ring pointer and event ring pointer. | |
631 | * | |
632 | * Setup MSI-X vectors and enable interrupts. | |
633 | */ | |
634 | int xhci_run(struct usb_hcd *hcd) | |
635 | { | |
636 | u32 temp; | |
8e595a5d | 637 | u64 temp_64; |
3fd1ec58 | 638 | int ret; |
66d4eadd | 639 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
66d4eadd | 640 | |
f6ff0ac8 SS |
641 | /* Start the xHCI host controller running only after the USB 2.0 roothub |
642 | * is setup. | |
643 | */ | |
66d4eadd | 644 | |
0f2a7930 | 645 | hcd->uses_new_polling = 1; |
f6ff0ac8 SS |
646 | if (!usb_hcd_is_primary_hcd(hcd)) |
647 | return xhci_run_finished(xhci); | |
0f2a7930 | 648 | |
d195fcff | 649 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run"); |
43b86af8 | 650 | |
3fd1ec58 | 651 | ret = xhci_try_enable_msi(hcd); |
43b86af8 | 652 | if (ret) |
3fd1ec58 | 653 | return ret; |
66d4eadd | 654 | |
f7b2e403 | 655 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
66e49d87 | 656 | temp_64 &= ~ERST_PTR_MASK; |
d195fcff XR |
657 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
658 | "ERST deq = 64'h%0lx", (long unsigned int) temp_64); | |
66e49d87 | 659 | |
d195fcff XR |
660 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
661 | "// Set the interrupt modulation register"); | |
b0ba9720 | 662 | temp = readl(&xhci->ir_set->irq_control); |
a4d88302 | 663 | temp &= ~ER_IRQ_INTERVAL_MASK; |
ab725cbe | 664 | temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK; |
204b7793 | 665 | writel(temp, &xhci->ir_set->irq_control); |
66d4eadd SS |
666 | |
667 | /* Set the HCD state before we enable the irqs */ | |
b0ba9720 | 668 | temp = readl(&xhci->op_regs->command); |
66d4eadd | 669 | temp |= (CMD_EIE); |
d195fcff XR |
670 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
671 | "// Enable interrupts, cmd = 0x%x.", temp); | |
204b7793 | 672 | writel(temp, &xhci->op_regs->command); |
66d4eadd | 673 | |
b0ba9720 | 674 | temp = readl(&xhci->ir_set->irq_pending); |
d195fcff XR |
675 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
676 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", | |
700e2052 | 677 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); |
204b7793 | 678 | writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); |
66d4eadd | 679 | |
ddba5cd0 MN |
680 | if (xhci->quirks & XHCI_NEC_HOST) { |
681 | struct xhci_command *command; | |
74e0b564 | 682 | |
103afda0 | 683 | command = xhci_alloc_command(xhci, false, GFP_KERNEL); |
ddba5cd0 MN |
684 | if (!command) |
685 | return -ENOMEM; | |
74e0b564 | 686 | |
d6f5f071 | 687 | ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0, |
0238634d | 688 | TRB_TYPE(TRB_NEC_GET_FW)); |
d6f5f071 SW |
689 | if (ret) |
690 | xhci_free_command(xhci, command); | |
ddba5cd0 | 691 | } |
d195fcff XR |
692 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
693 | "Finished xhci_run for USB2 roothub"); | |
02b6fdc2 | 694 | |
dfba2174 LB |
695 | xhci_dbc_init(xhci); |
696 | ||
02b6fdc2 LB |
697 | xhci_debugfs_init(xhci); |
698 | ||
f6ff0ac8 SS |
699 | return 0; |
700 | } | |
436e8c7d | 701 | EXPORT_SYMBOL_GPL(xhci_run); |
ed07453f | 702 | |
66d4eadd SS |
703 | /* |
704 | * Stop xHCI driver. | |
705 | * | |
706 | * This function is called by the USB core when the HC driver is removed. | |
707 | * Its opposite is xhci_run(). | |
708 | * | |
709 | * Disable device contexts, disable IRQs, and quiesce the HC. | |
710 | * Reset the HC, finish any completed transactions, and cleanup memory. | |
711 | */ | |
3969384c | 712 | static void xhci_stop(struct usb_hcd *hcd) |
66d4eadd SS |
713 | { |
714 | u32 temp; | |
715 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
716 | ||
8c24d6d7 | 717 | mutex_lock(&xhci->mutex); |
8c24d6d7 | 718 | |
fe190ed0 | 719 | /* Only halt host and free memory after both hcds are removed */ |
27a41a83 GKB |
720 | if (!usb_hcd_is_primary_hcd(hcd)) { |
721 | mutex_unlock(&xhci->mutex); | |
722 | return; | |
723 | } | |
66d4eadd | 724 | |
dfba2174 LB |
725 | xhci_dbc_exit(xhci); |
726 | ||
fe190ed0 JS |
727 | spin_lock_irq(&xhci->lock); |
728 | xhci->xhc_state |= XHCI_STATE_HALTED; | |
729 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
730 | xhci_halt(xhci); | |
731 | xhci_reset(xhci); | |
732 | spin_unlock_irq(&xhci->lock); | |
733 | ||
40a9fb17 ZR |
734 | xhci_cleanup_msix(xhci); |
735 | ||
71c731a2 AC |
736 | /* Deleting Compliance Mode Recovery Timer */ |
737 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
58b1d799 | 738 | (!(xhci_all_ports_seen_u0(xhci)))) { |
71c731a2 | 739 | del_timer_sync(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
740 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
741 | "%s: compliance mode recovery timer deleted", | |
58b1d799 TC |
742 | __func__); |
743 | } | |
71c731a2 | 744 | |
c41136b0 AX |
745 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
746 | usb_amd_dev_put(); | |
747 | ||
d195fcff XR |
748 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
749 | "// Disabling event ring interrupts"); | |
b0ba9720 | 750 | temp = readl(&xhci->op_regs->status); |
d1001ab4 | 751 | writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 752 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 753 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
66d4eadd | 754 | |
d195fcff | 755 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); |
66d4eadd | 756 | xhci_mem_cleanup(xhci); |
11cd764d | 757 | xhci_debugfs_exit(xhci); |
d195fcff XR |
758 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
759 | "xhci_stop completed - status = %x", | |
b0ba9720 | 760 | readl(&xhci->op_regs->status)); |
85ac90f8 | 761 | mutex_unlock(&xhci->mutex); |
66d4eadd SS |
762 | } |
763 | ||
764 | /* | |
765 | * Shutdown HC (not bus-specific) | |
766 | * | |
767 | * This is called when the machine is rebooting or halting. We assume that the | |
768 | * machine will be powered off, and the HC's internal state will be reset. | |
769 | * Don't bother to free memory. | |
f6ff0ac8 SS |
770 | * |
771 | * This will only ever be called with the main usb_hcd (the USB3 roothub). | |
66d4eadd | 772 | */ |
f2c710f7 | 773 | void xhci_shutdown(struct usb_hcd *hcd) |
66d4eadd SS |
774 | { |
775 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
776 | ||
052c7f9f | 777 | if (xhci->quirks & XHCI_SPURIOUS_REBOOT) |
4c39d4b9 | 778 | usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev)); |
e95829f4 | 779 | |
66d4eadd SS |
780 | spin_lock_irq(&xhci->lock); |
781 | xhci_halt(xhci); | |
638298dc TI |
782 | /* Workaround for spurious wakeups at shutdown with HSW */ |
783 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
784 | xhci_reset(xhci); | |
43b86af8 | 785 | spin_unlock_irq(&xhci->lock); |
66d4eadd | 786 | |
40a9fb17 ZR |
787 | xhci_cleanup_msix(xhci); |
788 | ||
d195fcff XR |
789 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
790 | "xhci_shutdown completed - status = %x", | |
b0ba9720 | 791 | readl(&xhci->op_regs->status)); |
66d4eadd | 792 | } |
f2c710f7 | 793 | EXPORT_SYMBOL_GPL(xhci_shutdown); |
66d4eadd | 794 | |
b5b5c3ac | 795 | #ifdef CONFIG_PM |
5535b1d5 AX |
796 | static void xhci_save_registers(struct xhci_hcd *xhci) |
797 | { | |
b0ba9720 XR |
798 | xhci->s3.command = readl(&xhci->op_regs->command); |
799 | xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification); | |
f7b2e403 | 800 | xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
b0ba9720 XR |
801 | xhci->s3.config_reg = readl(&xhci->op_regs->config_reg); |
802 | xhci->s3.erst_size = readl(&xhci->ir_set->erst_size); | |
f7b2e403 SS |
803 | xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
804 | xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
b0ba9720 XR |
805 | xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending); |
806 | xhci->s3.irq_control = readl(&xhci->ir_set->irq_control); | |
5535b1d5 AX |
807 | } |
808 | ||
809 | static void xhci_restore_registers(struct xhci_hcd *xhci) | |
810 | { | |
204b7793 XR |
811 | writel(xhci->s3.command, &xhci->op_regs->command); |
812 | writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification); | |
477632df | 813 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); |
204b7793 XR |
814 | writel(xhci->s3.config_reg, &xhci->op_regs->config_reg); |
815 | writel(xhci->s3.erst_size, &xhci->ir_set->erst_size); | |
477632df SS |
816 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); |
817 | xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); | |
204b7793 XR |
818 | writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending); |
819 | writel(xhci->s3.irq_control, &xhci->ir_set->irq_control); | |
5535b1d5 AX |
820 | } |
821 | ||
89821320 SS |
822 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) |
823 | { | |
824 | u64 val_64; | |
825 | ||
826 | /* step 2: initialize command ring buffer */ | |
f7b2e403 | 827 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
89821320 SS |
828 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
829 | (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | |
830 | xhci->cmd_ring->dequeue) & | |
831 | (u64) ~CMD_RING_RSVD_BITS) | | |
832 | xhci->cmd_ring->cycle_state; | |
d195fcff XR |
833 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
834 | "// Setting command ring address to 0x%llx", | |
89821320 | 835 | (long unsigned long) val_64); |
477632df | 836 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); |
89821320 SS |
837 | } |
838 | ||
839 | /* | |
840 | * The whole command ring must be cleared to zero when we suspend the host. | |
841 | * | |
842 | * The host doesn't save the command ring pointer in the suspend well, so we | |
843 | * need to re-program it on resume. Unfortunately, the pointer must be 64-byte | |
844 | * aligned, because of the reserved bits in the command ring dequeue pointer | |
845 | * register. Therefore, we can't just set the dequeue pointer back in the | |
846 | * middle of the ring (TRBs are 16-byte aligned). | |
847 | */ | |
848 | static void xhci_clear_command_ring(struct xhci_hcd *xhci) | |
849 | { | |
850 | struct xhci_ring *ring; | |
851 | struct xhci_segment *seg; | |
852 | ||
853 | ring = xhci->cmd_ring; | |
854 | seg = ring->deq_seg; | |
855 | do { | |
158886cd AX |
856 | memset(seg->trbs, 0, |
857 | sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1)); | |
858 | seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= | |
859 | cpu_to_le32(~TRB_CYCLE); | |
89821320 SS |
860 | seg = seg->next; |
861 | } while (seg != ring->deq_seg); | |
862 | ||
863 | /* Reset the software enqueue and dequeue pointers */ | |
864 | ring->deq_seg = ring->first_seg; | |
865 | ring->dequeue = ring->first_seg->trbs; | |
866 | ring->enq_seg = ring->deq_seg; | |
867 | ring->enqueue = ring->dequeue; | |
868 | ||
b008df60 | 869 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; |
89821320 SS |
870 | /* |
871 | * Ring is now zeroed, so the HW should look for change of ownership | |
872 | * when the cycle bit is set to 1. | |
873 | */ | |
874 | ring->cycle_state = 1; | |
875 | ||
876 | /* | |
877 | * Reset the hardware dequeue pointer. | |
878 | * Yes, this will need to be re-written after resume, but we're paranoid | |
879 | * and want to make sure the hardware doesn't access bogus memory | |
880 | * because, say, the BIOS or an SMI started the host without changing | |
881 | * the command ring pointers. | |
882 | */ | |
883 | xhci_set_cmd_ring_deq(xhci); | |
884 | } | |
885 | ||
a1377e53 LB |
886 | static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci) |
887 | { | |
38986ffa | 888 | struct xhci_port **ports; |
a1377e53 | 889 | int port_index; |
a1377e53 | 890 | unsigned long flags; |
d70d5a84 | 891 | u32 t1, t2, portsc; |
a1377e53 LB |
892 | |
893 | spin_lock_irqsave(&xhci->lock, flags); | |
894 | ||
8a1115ff | 895 | /* disable usb3 ports Wake bits */ |
38986ffa MN |
896 | port_index = xhci->usb3_rhub.num_ports; |
897 | ports = xhci->usb3_rhub.ports; | |
a1377e53 | 898 | while (port_index--) { |
38986ffa | 899 | t1 = readl(ports[port_index]->addr); |
d70d5a84 | 900 | portsc = t1; |
a1377e53 LB |
901 | t1 = xhci_port_state_to_neutral(t1); |
902 | t2 = t1 & ~PORT_WAKE_BITS; | |
d70d5a84 | 903 | if (t1 != t2) { |
38986ffa | 904 | writel(t2, ports[port_index]->addr); |
d70d5a84 MN |
905 | xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n", |
906 | xhci->usb3_rhub.hcd->self.busnum, | |
907 | port_index + 1, portsc, t2); | |
908 | } | |
a1377e53 LB |
909 | } |
910 | ||
8a1115ff | 911 | /* disable usb2 ports Wake bits */ |
38986ffa MN |
912 | port_index = xhci->usb2_rhub.num_ports; |
913 | ports = xhci->usb2_rhub.ports; | |
a1377e53 | 914 | while (port_index--) { |
38986ffa | 915 | t1 = readl(ports[port_index]->addr); |
d70d5a84 | 916 | portsc = t1; |
a1377e53 LB |
917 | t1 = xhci_port_state_to_neutral(t1); |
918 | t2 = t1 & ~PORT_WAKE_BITS; | |
d70d5a84 | 919 | if (t1 != t2) { |
38986ffa | 920 | writel(t2, ports[port_index]->addr); |
d70d5a84 MN |
921 | xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n", |
922 | xhci->usb2_rhub.hcd->self.busnum, | |
923 | port_index + 1, portsc, t2); | |
924 | } | |
a1377e53 | 925 | } |
a1377e53 LB |
926 | spin_unlock_irqrestore(&xhci->lock, flags); |
927 | } | |
928 | ||
229bc19f MN |
929 | static bool xhci_pending_portevent(struct xhci_hcd *xhci) |
930 | { | |
931 | struct xhci_port **ports; | |
932 | int port_index; | |
933 | u32 status; | |
934 | u32 portsc; | |
935 | ||
936 | status = readl(&xhci->op_regs->status); | |
937 | if (status & STS_EINT) | |
938 | return true; | |
939 | /* | |
940 | * Checking STS_EINT is not enough as there is a lag between a change | |
941 | * bit being set and the Port Status Change Event that it generated | |
942 | * being written to the Event Ring. See note in xhci 1.1 section 4.19.2. | |
943 | */ | |
944 | ||
945 | port_index = xhci->usb2_rhub.num_ports; | |
946 | ports = xhci->usb2_rhub.ports; | |
947 | while (port_index--) { | |
948 | portsc = readl(ports[port_index]->addr); | |
949 | if (portsc & PORT_CHANGE_MASK || | |
950 | (portsc & PORT_PLS_MASK) == XDEV_RESUME) | |
951 | return true; | |
952 | } | |
953 | port_index = xhci->usb3_rhub.num_ports; | |
954 | ports = xhci->usb3_rhub.ports; | |
955 | while (port_index--) { | |
956 | portsc = readl(ports[port_index]->addr); | |
957 | if (portsc & PORT_CHANGE_MASK || | |
958 | (portsc & PORT_PLS_MASK) == XDEV_RESUME) | |
959 | return true; | |
960 | } | |
961 | return false; | |
962 | } | |
963 | ||
5535b1d5 AX |
964 | /* |
965 | * Stop HC (not bus-specific) | |
966 | * | |
967 | * This is called when the machine transition into S3/S4 mode. | |
968 | * | |
969 | */ | |
a1377e53 | 970 | int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) |
5535b1d5 AX |
971 | { |
972 | int rc = 0; | |
7c67cf66 | 973 | unsigned int delay = XHCI_MAX_HALT_USEC * 2; |
5535b1d5 AX |
974 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
975 | u32 command; | |
a7d57abc | 976 | u32 res; |
5535b1d5 | 977 | |
9fa733f2 RQ |
978 | if (!hcd->state) |
979 | return 0; | |
980 | ||
77b84767 FB |
981 | if (hcd->state != HC_STATE_SUSPENDED || |
982 | xhci->shared_hcd->state != HC_STATE_SUSPENDED) | |
983 | return -EINVAL; | |
984 | ||
a1377e53 LB |
985 | /* Clear root port wake on bits if wakeup not allowed. */ |
986 | if (!do_wakeup) | |
987 | xhci_disable_port_wake_on_bits(xhci); | |
988 | ||
18a367e8 PC |
989 | if (!HCD_HW_ACCESSIBLE(hcd)) |
990 | return 0; | |
991 | ||
992 | xhci_dbc_suspend(xhci); | |
993 | ||
c52804a4 SS |
994 | /* Don't poll the roothubs on bus suspend. */ |
995 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
996 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
997 | del_timer_sync(&hcd->rh_timer); | |
14e61a1b AC |
998 | clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); |
999 | del_timer_sync(&xhci->shared_hcd->rh_timer); | |
c52804a4 | 1000 | |
191edc5e KHF |
1001 | if (xhci->quirks & XHCI_SUSPEND_DELAY) |
1002 | usleep_range(1000, 1500); | |
1003 | ||
5535b1d5 AX |
1004 | spin_lock_irq(&xhci->lock); |
1005 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
b3209379 | 1006 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); |
5535b1d5 AX |
1007 | /* step 1: stop endpoint */ |
1008 | /* skipped assuming that port suspend has done */ | |
1009 | ||
1010 | /* step 2: clear Run/Stop bit */ | |
b0ba9720 | 1011 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1012 | command &= ~CMD_RUN; |
204b7793 | 1013 | writel(command, &xhci->op_regs->command); |
455f5892 ON |
1014 | |
1015 | /* Some chips from Fresco Logic need an extraordinary delay */ | |
1016 | delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; | |
1017 | ||
dc0b177c | 1018 | if (xhci_handshake(&xhci->op_regs->status, |
455f5892 | 1019 | STS_HALT, STS_HALT, delay)) { |
5535b1d5 AX |
1020 | xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n"); |
1021 | spin_unlock_irq(&xhci->lock); | |
1022 | return -ETIMEDOUT; | |
1023 | } | |
89821320 | 1024 | xhci_clear_command_ring(xhci); |
5535b1d5 AX |
1025 | |
1026 | /* step 3: save registers */ | |
1027 | xhci_save_registers(xhci); | |
1028 | ||
1029 | /* step 4: set CSS flag */ | |
b0ba9720 | 1030 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1031 | command |= CMD_CSS; |
204b7793 | 1032 | writel(command, &xhci->op_regs->command); |
a7d57abc | 1033 | xhci->broken_suspend = 0; |
dc0b177c | 1034 | if (xhci_handshake(&xhci->op_regs->status, |
ac343366 | 1035 | STS_SAVE, 0, 20 * 1000)) { |
a7d57abc SS |
1036 | /* |
1037 | * AMD SNPS xHC 3.0 occasionally does not clear the | |
1038 | * SSS bit of USBSTS and when driver tries to poll | |
1039 | * to see if the xHC clears BIT(8) which never happens | |
1040 | * and driver assumes that controller is not responding | |
1041 | * and times out. To workaround this, its good to check | |
1042 | * if SRE and HCE bits are not set (as per xhci | |
1043 | * Section 5.4.2) and bypass the timeout. | |
1044 | */ | |
1045 | res = readl(&xhci->op_regs->status); | |
1046 | if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) && | |
1047 | (((res & STS_SRE) == 0) && | |
1048 | ((res & STS_HCE) == 0))) { | |
1049 | xhci->broken_suspend = 1; | |
1050 | } else { | |
1051 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); | |
1052 | spin_unlock_irq(&xhci->lock); | |
1053 | return -ETIMEDOUT; | |
1054 | } | |
5535b1d5 | 1055 | } |
5535b1d5 AX |
1056 | spin_unlock_irq(&xhci->lock); |
1057 | ||
71c731a2 AC |
1058 | /* |
1059 | * Deleting Compliance Mode Recovery Timer because the xHCI Host | |
1060 | * is about to be suspended. | |
1061 | */ | |
1062 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
1063 | (!(xhci_all_ports_seen_u0(xhci)))) { | |
1064 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
1065 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1066 | "%s: compliance mode recovery timer deleted", | |
58b1d799 | 1067 | __func__); |
71c731a2 AC |
1068 | } |
1069 | ||
0029227f AX |
1070 | /* step 5: remove core well power */ |
1071 | /* synchronize irq when using MSI-X */ | |
421aa841 | 1072 | xhci_msix_sync_irqs(xhci); |
0029227f | 1073 | |
5535b1d5 AX |
1074 | return rc; |
1075 | } | |
436e8c7d | 1076 | EXPORT_SYMBOL_GPL(xhci_suspend); |
5535b1d5 AX |
1077 | |
1078 | /* | |
1079 | * start xHC (not bus-specific) | |
1080 | * | |
1081 | * This is called when the machine transition from S3/S4 mode. | |
1082 | * | |
1083 | */ | |
1084 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |
1085 | { | |
229bc19f | 1086 | u32 command, temp = 0; |
5535b1d5 | 1087 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
65b22f93 | 1088 | struct usb_hcd *secondary_hcd; |
f69e3120 | 1089 | int retval = 0; |
77df9e0b | 1090 | bool comp_timer_running = false; |
5535b1d5 | 1091 | |
9fa733f2 RQ |
1092 | if (!hcd->state) |
1093 | return 0; | |
1094 | ||
f6ff0ac8 | 1095 | /* Wait a bit if either of the roothubs need to settle from the |
25985edc | 1096 | * transition into bus suspend. |
20b67cf5 | 1097 | */ |
f6187f42 MN |
1098 | |
1099 | if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) || | |
1100 | time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange)) | |
5535b1d5 AX |
1101 | msleep(100); |
1102 | ||
f69e3120 AS |
1103 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
1104 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); | |
1105 | ||
5535b1d5 | 1106 | spin_lock_irq(&xhci->lock); |
a7d57abc | 1107 | if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend) |
c877b3b2 | 1108 | hibernated = true; |
5535b1d5 AX |
1109 | |
1110 | if (!hibernated) { | |
a70bcbc3 RT |
1111 | /* |
1112 | * Some controllers might lose power during suspend, so wait | |
1113 | * for controller not ready bit to clear, just as in xHC init. | |
1114 | */ | |
1115 | retval = xhci_handshake(&xhci->op_regs->status, | |
1116 | STS_CNR, 0, 10 * 1000 * 1000); | |
1117 | if (retval) { | |
1118 | xhci_warn(xhci, "Controller not ready at resume %d\n", | |
1119 | retval); | |
1120 | spin_unlock_irq(&xhci->lock); | |
1121 | return retval; | |
1122 | } | |
5535b1d5 AX |
1123 | /* step 1: restore register */ |
1124 | xhci_restore_registers(xhci); | |
1125 | /* step 2: initialize command ring buffer */ | |
89821320 | 1126 | xhci_set_cmd_ring_deq(xhci); |
5535b1d5 AX |
1127 | /* step 3: restore state and start state*/ |
1128 | /* step 3: set CRS flag */ | |
b0ba9720 | 1129 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1130 | command |= CMD_CRS; |
204b7793 | 1131 | writel(command, &xhci->op_regs->command); |
305886ca AG |
1132 | /* |
1133 | * Some controllers take up to 55+ ms to complete the controller | |
1134 | * restore so setting the timeout to 100ms. Xhci specification | |
1135 | * doesn't mention any timeout value. | |
1136 | */ | |
dc0b177c | 1137 | if (xhci_handshake(&xhci->op_regs->status, |
305886ca | 1138 | STS_RESTORE, 0, 100 * 1000)) { |
622eb783 | 1139 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); |
5535b1d5 AX |
1140 | spin_unlock_irq(&xhci->lock); |
1141 | return -ETIMEDOUT; | |
1142 | } | |
b0ba9720 | 1143 | temp = readl(&xhci->op_regs->status); |
5535b1d5 AX |
1144 | } |
1145 | ||
1146 | /* If restore operation fails, re-initialize the HC during resume */ | |
1147 | if ((temp & STS_SRE) || hibernated) { | |
77df9e0b TC |
1148 | |
1149 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
1150 | !(xhci_all_ports_seen_u0(xhci))) { | |
1151 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
1152 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1153 | "Compliance Mode Recovery Timer deleted!"); | |
77df9e0b TC |
1154 | } |
1155 | ||
fedd383e SS |
1156 | /* Let the USB core know _both_ roothubs lost power. */ |
1157 | usb_root_hub_lost_power(xhci->main_hcd->self.root_hub); | |
1158 | usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub); | |
5535b1d5 AX |
1159 | |
1160 | xhci_dbg(xhci, "Stop HCD\n"); | |
1161 | xhci_halt(xhci); | |
12de0a35 | 1162 | xhci_zero_64b_regs(xhci); |
72ae1947 | 1163 | retval = xhci_reset(xhci); |
5535b1d5 | 1164 | spin_unlock_irq(&xhci->lock); |
72ae1947 MN |
1165 | if (retval) |
1166 | return retval; | |
0029227f | 1167 | xhci_cleanup_msix(xhci); |
5535b1d5 | 1168 | |
5535b1d5 | 1169 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
b0ba9720 | 1170 | temp = readl(&xhci->op_regs->status); |
d1001ab4 | 1171 | writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 1172 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 1173 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
5535b1d5 AX |
1174 | |
1175 | xhci_dbg(xhci, "cleaning up memory\n"); | |
1176 | xhci_mem_cleanup(xhci); | |
d9167671 | 1177 | xhci_debugfs_exit(xhci); |
5535b1d5 | 1178 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", |
b0ba9720 | 1179 | readl(&xhci->op_regs->status)); |
5535b1d5 | 1180 | |
65b22f93 SS |
1181 | /* USB core calls the PCI reinit and start functions twice: |
1182 | * first with the primary HCD, and then with the secondary HCD. | |
1183 | * If we don't do the same, the host will never be started. | |
1184 | */ | |
1185 | if (!usb_hcd_is_primary_hcd(hcd)) | |
1186 | secondary_hcd = hcd; | |
1187 | else | |
1188 | secondary_hcd = xhci->shared_hcd; | |
1189 | ||
1190 | xhci_dbg(xhci, "Initialize the xhci_hcd\n"); | |
1191 | retval = xhci_init(hcd->primary_hcd); | |
5535b1d5 AX |
1192 | if (retval) |
1193 | return retval; | |
77df9e0b TC |
1194 | comp_timer_running = true; |
1195 | ||
65b22f93 SS |
1196 | xhci_dbg(xhci, "Start the primary HCD\n"); |
1197 | retval = xhci_run(hcd->primary_hcd); | |
b3209379 | 1198 | if (!retval) { |
f69e3120 AS |
1199 | xhci_dbg(xhci, "Start the secondary HCD\n"); |
1200 | retval = xhci_run(secondary_hcd); | |
b3209379 | 1201 | } |
5535b1d5 | 1202 | hcd->state = HC_STATE_SUSPENDED; |
b3209379 | 1203 | xhci->shared_hcd->state = HC_STATE_SUSPENDED; |
f69e3120 | 1204 | goto done; |
5535b1d5 AX |
1205 | } |
1206 | ||
5535b1d5 | 1207 | /* step 4: set Run/Stop bit */ |
b0ba9720 | 1208 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1209 | command |= CMD_RUN; |
204b7793 | 1210 | writel(command, &xhci->op_regs->command); |
dc0b177c | 1211 | xhci_handshake(&xhci->op_regs->status, STS_HALT, |
5535b1d5 AX |
1212 | 0, 250 * 1000); |
1213 | ||
1214 | /* step 5: walk topology and initialize portsc, | |
1215 | * portpmsc and portli | |
1216 | */ | |
1217 | /* this is done in bus_resume */ | |
1218 | ||
1219 | /* step 6: restart each of the previously | |
1220 | * Running endpoints by ringing their doorbells | |
1221 | */ | |
1222 | ||
5535b1d5 | 1223 | spin_unlock_irq(&xhci->lock); |
f69e3120 | 1224 | |
dfba2174 LB |
1225 | xhci_dbc_resume(xhci); |
1226 | ||
f69e3120 AS |
1227 | done: |
1228 | if (retval == 0) { | |
d6236f6d | 1229 | /* Resume root hubs only when have pending events. */ |
229bc19f | 1230 | if (xhci_pending_portevent(xhci)) { |
d6236f6d | 1231 | usb_hcd_resume_root_hub(xhci->shared_hcd); |
671ffdff | 1232 | usb_hcd_resume_root_hub(hcd); |
d6236f6d | 1233 | } |
f69e3120 | 1234 | } |
71c731a2 AC |
1235 | |
1236 | /* | |
1237 | * If system is subject to the Quirk, Compliance Mode Timer needs to | |
1238 | * be re-initialized Always after a system resume. Ports are subject | |
1239 | * to suffer the Compliance Mode issue again. It doesn't matter if | |
1240 | * ports have entered previously to U0 before system's suspension. | |
1241 | */ | |
77df9e0b | 1242 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running) |
71c731a2 AC |
1243 | compliance_mode_recovery_timer_init(xhci); |
1244 | ||
9da5a109 JC |
1245 | if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL) |
1246 | usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller)); | |
1247 | ||
c52804a4 SS |
1248 | /* Re-enable port polling. */ |
1249 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
14e61a1b AC |
1250 | set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); |
1251 | usb_hcd_poll_rh_status(xhci->shared_hcd); | |
671ffdff MN |
1252 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
1253 | usb_hcd_poll_rh_status(hcd); | |
c52804a4 | 1254 | |
f69e3120 | 1255 | return retval; |
5535b1d5 | 1256 | } |
436e8c7d | 1257 | EXPORT_SYMBOL_GPL(xhci_resume); |
b5b5c3ac SS |
1258 | #endif /* CONFIG_PM */ |
1259 | ||
7f84eef0 SS |
1260 | /*-------------------------------------------------------------------------*/ |
1261 | ||
33e39350 NSJ |
1262 | /* |
1263 | * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT), | |
1264 | * we'll copy the actual data into the TRB address register. This is limited to | |
1265 | * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize | |
1266 | * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed. | |
1267 | */ | |
1268 | static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, | |
1269 | gfp_t mem_flags) | |
1270 | { | |
1271 | if (xhci_urb_suitable_for_idt(urb)) | |
1272 | return 0; | |
1273 | ||
1274 | return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
1275 | } | |
1276 | ||
f3a9492b | 1277 | /* |
d0e96f5a SS |
1278 | * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and |
1279 | * HCDs. Find the index for an endpoint given its descriptor. Use the return | |
1280 | * value to right shift 1 for the bitmask. | |
1281 | * | |
1282 | * Index = (epnum * 2) + direction - 1, | |
1283 | * where direction = 0 for OUT, 1 for IN. | |
1284 | * For control endpoints, the IN index is used (OUT index is unused), so | |
1285 | * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) | |
1286 | */ | |
1287 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc) | |
1288 | { | |
1289 | unsigned int index; | |
1290 | if (usb_endpoint_xfer_control(desc)) | |
1291 | index = (unsigned int) (usb_endpoint_num(desc)*2); | |
1292 | else | |
1293 | index = (unsigned int) (usb_endpoint_num(desc)*2) + | |
1294 | (usb_endpoint_dir_in(desc) ? 1 : 0) - 1; | |
1295 | return index; | |
1296 | } | |
1297 | ||
01c5f447 JW |
1298 | /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint |
1299 | * address from the XHCI endpoint index. | |
1300 | */ | |
1301 | unsigned int xhci_get_endpoint_address(unsigned int ep_index) | |
1302 | { | |
1303 | unsigned int number = DIV_ROUND_UP(ep_index, 2); | |
1304 | unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN; | |
1305 | return direction | number; | |
1306 | } | |
1307 | ||
f94e0186 SS |
1308 | /* Find the flag for this endpoint (for use in the control context). Use the |
1309 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1310 | * bit 1, etc. | |
1311 | */ | |
3969384c | 1312 | static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc) |
f94e0186 SS |
1313 | { |
1314 | return 1 << (xhci_get_endpoint_index(desc) + 1); | |
1315 | } | |
1316 | ||
ac9d8fe7 SS |
1317 | /* Find the flag for this endpoint (for use in the control context). Use the |
1318 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1319 | * bit 1, etc. | |
1320 | */ | |
3969384c | 1321 | static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index) |
ac9d8fe7 SS |
1322 | { |
1323 | return 1 << (ep_index + 1); | |
1324 | } | |
1325 | ||
f94e0186 SS |
1326 | /* Compute the last valid endpoint context index. Basically, this is the |
1327 | * endpoint index plus one. For slot contexts with more than valid endpoint, | |
1328 | * we find the most significant bit set in the added contexts flags. | |
1329 | * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000 | |
1330 | * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one. | |
1331 | */ | |
ac9d8fe7 | 1332 | unsigned int xhci_last_valid_endpoint(u32 added_ctxs) |
f94e0186 SS |
1333 | { |
1334 | return fls(added_ctxs) - 1; | |
1335 | } | |
1336 | ||
d0e96f5a SS |
1337 | /* Returns 1 if the arguments are OK; |
1338 | * returns 0 this is a root hub; returns -EINVAL for NULL pointers. | |
1339 | */ | |
8212a49d | 1340 | static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, |
64927730 AX |
1341 | struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev, |
1342 | const char *func) { | |
1343 | struct xhci_hcd *xhci; | |
1344 | struct xhci_virt_device *virt_dev; | |
1345 | ||
d0e96f5a | 1346 | if (!hcd || (check_ep && !ep) || !udev) { |
5c1127d3 | 1347 | pr_debug("xHCI %s called with invalid args\n", func); |
d0e96f5a SS |
1348 | return -EINVAL; |
1349 | } | |
1350 | if (!udev->parent) { | |
5c1127d3 | 1351 | pr_debug("xHCI %s called for root hub\n", func); |
d0e96f5a SS |
1352 | return 0; |
1353 | } | |
64927730 | 1354 | |
7bd89b40 | 1355 | xhci = hcd_to_xhci(hcd); |
64927730 | 1356 | if (check_virt_dev) { |
73ddc247 | 1357 | if (!udev->slot_id || !xhci->devs[udev->slot_id]) { |
5c1127d3 XR |
1358 | xhci_dbg(xhci, "xHCI %s called with unaddressed device\n", |
1359 | func); | |
64927730 AX |
1360 | return -EINVAL; |
1361 | } | |
1362 | ||
1363 | virt_dev = xhci->devs[udev->slot_id]; | |
1364 | if (virt_dev->udev != udev) { | |
5c1127d3 | 1365 | xhci_dbg(xhci, "xHCI %s called with udev and " |
64927730 AX |
1366 | "virt_dev does not match\n", func); |
1367 | return -EINVAL; | |
1368 | } | |
d0e96f5a | 1369 | } |
64927730 | 1370 | |
203a8661 SS |
1371 | if (xhci->xhc_state & XHCI_STATE_HALTED) |
1372 | return -ENODEV; | |
1373 | ||
d0e96f5a SS |
1374 | return 1; |
1375 | } | |
1376 | ||
2d3f1fac | 1377 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, |
913a8a34 SS |
1378 | struct usb_device *udev, struct xhci_command *command, |
1379 | bool ctx_change, bool must_succeed); | |
2d3f1fac SS |
1380 | |
1381 | /* | |
1382 | * Full speed devices may have a max packet size greater than 8 bytes, but the | |
1383 | * USB core doesn't know that until it reads the first 8 bytes of the | |
1384 | * descriptor. If the usb_device's max packet size changes after that point, | |
1385 | * we need to issue an evaluate context command and wait on it. | |
1386 | */ | |
1387 | static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, | |
1388 | unsigned int ep_index, struct urb *urb) | |
1389 | { | |
2d3f1fac SS |
1390 | struct xhci_container_ctx *out_ctx; |
1391 | struct xhci_input_control_ctx *ctrl_ctx; | |
1392 | struct xhci_ep_ctx *ep_ctx; | |
ddba5cd0 | 1393 | struct xhci_command *command; |
2d3f1fac SS |
1394 | int max_packet_size; |
1395 | int hw_max_packet_size; | |
1396 | int ret = 0; | |
1397 | ||
1398 | out_ctx = xhci->devs[slot_id]->out_ctx; | |
1399 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); | |
28ccd296 | 1400 | hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); |
29cc8897 | 1401 | max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc); |
2d3f1fac | 1402 | if (hw_max_packet_size != max_packet_size) { |
3a7fa5be XR |
1403 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1404 | "Max Packet Size for ep 0 changed."); | |
1405 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, | |
1406 | "Max packet size in usb_device = %d", | |
2d3f1fac | 1407 | max_packet_size); |
3a7fa5be XR |
1408 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1409 | "Max packet size in xHCI HW = %d", | |
2d3f1fac | 1410 | hw_max_packet_size); |
3a7fa5be XR |
1411 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1412 | "Issuing evaluate context command."); | |
2d3f1fac | 1413 | |
92f8e767 SS |
1414 | /* Set up the input context flags for the command */ |
1415 | /* FIXME: This won't work if a non-default control endpoint | |
1416 | * changes max packet sizes. | |
1417 | */ | |
ddba5cd0 | 1418 | |
103afda0 | 1419 | command = xhci_alloc_command(xhci, true, GFP_KERNEL); |
ddba5cd0 MN |
1420 | if (!command) |
1421 | return -ENOMEM; | |
1422 | ||
1423 | command->in_ctx = xhci->devs[slot_id]->in_ctx; | |
4daf9df5 | 1424 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
1425 | if (!ctrl_ctx) { |
1426 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1427 | __func__); | |
ddba5cd0 MN |
1428 | ret = -ENOMEM; |
1429 | goto command_cleanup; | |
92f8e767 | 1430 | } |
2d3f1fac | 1431 | /* Set up the modified control endpoint 0 */ |
913a8a34 SS |
1432 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
1433 | xhci->devs[slot_id]->out_ctx, ep_index); | |
92f8e767 | 1434 | |
ddba5cd0 | 1435 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); |
a73d9d9c | 1436 | ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */ |
28ccd296 ME |
1437 | ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK); |
1438 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); | |
2d3f1fac | 1439 | |
28ccd296 | 1440 | ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); |
2d3f1fac SS |
1441 | ctrl_ctx->drop_flags = 0; |
1442 | ||
ddba5cd0 | 1443 | ret = xhci_configure_endpoint(xhci, urb->dev, command, |
913a8a34 | 1444 | true, false); |
2d3f1fac SS |
1445 | |
1446 | /* Clean up the input context for later use by bandwidth | |
1447 | * functions. | |
1448 | */ | |
28ccd296 | 1449 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); |
ddba5cd0 MN |
1450 | command_cleanup: |
1451 | kfree(command->completion); | |
1452 | kfree(command); | |
2d3f1fac SS |
1453 | } |
1454 | return ret; | |
1455 | } | |
1456 | ||
d0e96f5a SS |
1457 | /* |
1458 | * non-error returns are a promise to giveback() the urb later | |
1459 | * we drop ownership so next owner (or urb unlink) can get it | |
1460 | */ | |
3969384c | 1461 | static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) |
d0e96f5a SS |
1462 | { |
1463 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
1464 | unsigned long flags; | |
1465 | int ret = 0; | |
15febf5e MN |
1466 | unsigned int slot_id, ep_index; |
1467 | unsigned int *ep_state; | |
8e51adcc | 1468 | struct urb_priv *urb_priv; |
7e64b037 | 1469 | int num_tds; |
2d3f1fac | 1470 | |
64927730 AX |
1471 | if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, |
1472 | true, true, __func__) <= 0) | |
d0e96f5a SS |
1473 | return -EINVAL; |
1474 | ||
1475 | slot_id = urb->dev->slot_id; | |
1476 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
15febf5e | 1477 | ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state; |
d0e96f5a | 1478 | |
541c7d43 | 1479 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
d0e96f5a SS |
1480 | if (!in_interrupt()) |
1481 | xhci_dbg(xhci, "urb submitted during PCI suspend\n"); | |
6969408d | 1482 | return -ESHUTDOWN; |
d0e96f5a | 1483 | } |
b8c3b718 MN |
1484 | if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) { |
1485 | xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n"); | |
1486 | return -ENODEV; | |
1487 | } | |
8e51adcc AX |
1488 | |
1489 | if (usb_endpoint_xfer_isoc(&urb->ep->desc)) | |
e6f7caa3 | 1490 | num_tds = urb->number_of_packets; |
4758dcd1 RA |
1491 | else if (usb_endpoint_is_bulk_out(&urb->ep->desc) && |
1492 | urb->transfer_buffer_length > 0 && | |
1493 | urb->transfer_flags & URB_ZERO_PACKET && | |
1494 | !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc))) | |
e6f7caa3 | 1495 | num_tds = 2; |
8e51adcc | 1496 | else |
e6f7caa3 | 1497 | num_tds = 1; |
8e51adcc | 1498 | |
da79ff6e | 1499 | urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags); |
8e51adcc AX |
1500 | if (!urb_priv) |
1501 | return -ENOMEM; | |
1502 | ||
9ef7fbbb MN |
1503 | urb_priv->num_tds = num_tds; |
1504 | urb_priv->num_tds_done = 0; | |
8e51adcc AX |
1505 | urb->hcpriv = urb_priv; |
1506 | ||
5abdc2e6 FB |
1507 | trace_xhci_urb_enqueue(urb); |
1508 | ||
2d3f1fac SS |
1509 | if (usb_endpoint_xfer_control(&urb->ep->desc)) { |
1510 | /* Check to see if the max packet size for the default control | |
1511 | * endpoint changed during FS device enumeration | |
1512 | */ | |
1513 | if (urb->dev->speed == USB_SPEED_FULL) { | |
1514 | ret = xhci_check_maxpacket(xhci, slot_id, | |
1515 | ep_index, urb); | |
d13565c1 | 1516 | if (ret < 0) { |
4daf9df5 | 1517 | xhci_urb_free_priv(urb_priv); |
d13565c1 | 1518 | urb->hcpriv = NULL; |
2d3f1fac | 1519 | return ret; |
d13565c1 | 1520 | } |
2d3f1fac | 1521 | } |
6969408d | 1522 | } |
2d3f1fac | 1523 | |
6969408d MN |
1524 | spin_lock_irqsave(&xhci->lock, flags); |
1525 | ||
1526 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
1527 | xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n", | |
1528 | urb->ep->desc.bEndpointAddress, urb); | |
1529 | ret = -ESHUTDOWN; | |
1530 | goto free_priv; | |
1531 | } | |
15febf5e MN |
1532 | if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) { |
1533 | xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n", | |
1534 | *ep_state); | |
1535 | ret = -EINVAL; | |
1536 | goto free_priv; | |
1537 | } | |
f5249461 MN |
1538 | if (*ep_state & EP_SOFT_CLEAR_TOGGLE) { |
1539 | xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n"); | |
1540 | ret = -EINVAL; | |
1541 | goto free_priv; | |
1542 | } | |
6969408d MN |
1543 | |
1544 | switch (usb_endpoint_type(&urb->ep->desc)) { | |
1545 | ||
1546 | case USB_ENDPOINT_XFER_CONTROL: | |
b11069f5 | 1547 | ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb, |
6969408d MN |
1548 | slot_id, ep_index); |
1549 | break; | |
1550 | case USB_ENDPOINT_XFER_BULK: | |
6969408d MN |
1551 | ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, |
1552 | slot_id, ep_index); | |
1553 | break; | |
6969408d | 1554 | case USB_ENDPOINT_XFER_INT: |
624defa1 SS |
1555 | ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb, |
1556 | slot_id, ep_index); | |
6969408d | 1557 | break; |
6969408d | 1558 | case USB_ENDPOINT_XFER_ISOC: |
787f4e5a AX |
1559 | ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb, |
1560 | slot_id, ep_index); | |
2d3f1fac | 1561 | } |
6969408d MN |
1562 | |
1563 | if (ret) { | |
d13565c1 | 1564 | free_priv: |
6969408d MN |
1565 | xhci_urb_free_priv(urb_priv); |
1566 | urb->hcpriv = NULL; | |
1567 | } | |
6f5165cf | 1568 | spin_unlock_irqrestore(&xhci->lock, flags); |
d13565c1 | 1569 | return ret; |
d0e96f5a SS |
1570 | } |
1571 | ||
ae636747 SS |
1572 | /* |
1573 | * Remove the URB's TD from the endpoint ring. This may cause the HC to stop | |
1574 | * USB transfers, potentially stopping in the middle of a TRB buffer. The HC | |
1575 | * should pick up where it left off in the TD, unless a Set Transfer Ring | |
1576 | * Dequeue Pointer is issued. | |
1577 | * | |
1578 | * The TRBs that make up the buffers for the canceled URB will be "removed" from | |
1579 | * the ring. Since the ring is a contiguous structure, they can't be physically | |
1580 | * removed. Instead, there are two options: | |
1581 | * | |
1582 | * 1) If the HC is in the middle of processing the URB to be canceled, we | |
1583 | * simply move the ring's dequeue pointer past those TRBs using the Set | |
1584 | * Transfer Ring Dequeue Pointer command. This will be the common case, | |
1585 | * when drivers timeout on the last submitted URB and attempt to cancel. | |
1586 | * | |
1587 | * 2) If the HC is in the middle of a different TD, we turn the TRBs into a | |
1588 | * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The | |
1589 | * HC will need to invalidate the any TRBs it has cached after the stop | |
1590 | * endpoint command, as noted in the xHCI 0.95 errata. | |
1591 | * | |
1592 | * 3) The TD may have completed by the time the Stop Endpoint Command | |
1593 | * completes, so software needs to handle that case too. | |
1594 | * | |
1595 | * This function should protect against the TD enqueueing code ringing the | |
1596 | * doorbell while this code is waiting for a Stop Endpoint command to complete. | |
1597 | * It also needs to account for multiple cancellations on happening at the same | |
1598 | * time for the same endpoint. | |
1599 | * | |
1600 | * Note that this function can be called in any context, or so says | |
1601 | * usb_hcd_unlink_urb() | |
d0e96f5a | 1602 | */ |
3969384c | 1603 | static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
d0e96f5a | 1604 | { |
ae636747 | 1605 | unsigned long flags; |
8e51adcc | 1606 | int ret, i; |
e34b2fbf | 1607 | u32 temp; |
ae636747 | 1608 | struct xhci_hcd *xhci; |
8e51adcc | 1609 | struct urb_priv *urb_priv; |
ae636747 SS |
1610 | struct xhci_td *td; |
1611 | unsigned int ep_index; | |
1612 | struct xhci_ring *ep_ring; | |
63a0d9ab | 1613 | struct xhci_virt_ep *ep; |
ddba5cd0 | 1614 | struct xhci_command *command; |
d3519b9d | 1615 | struct xhci_virt_device *vdev; |
ae636747 SS |
1616 | |
1617 | xhci = hcd_to_xhci(hcd); | |
1618 | spin_lock_irqsave(&xhci->lock, flags); | |
5abdc2e6 FB |
1619 | |
1620 | trace_xhci_urb_dequeue(urb); | |
1621 | ||
ae636747 SS |
1622 | /* Make sure the URB hasn't completed or been unlinked already */ |
1623 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); | |
d3519b9d | 1624 | if (ret) |
ae636747 | 1625 | goto done; |
d3519b9d MN |
1626 | |
1627 | /* give back URB now if we can't queue it for cancel */ | |
1628 | vdev = xhci->devs[urb->dev->slot_id]; | |
1629 | urb_priv = urb->hcpriv; | |
1630 | if (!vdev || !urb_priv) | |
1631 | goto err_giveback; | |
1632 | ||
1633 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
1634 | ep = &vdev->eps[ep_index]; | |
1635 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); | |
1636 | if (!ep || !ep_ring) | |
1637 | goto err_giveback; | |
1638 | ||
d9f11ba9 | 1639 | /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */ |
b0ba9720 | 1640 | temp = readl(&xhci->op_regs->status); |
d9f11ba9 MN |
1641 | if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) { |
1642 | xhci_hc_died(xhci); | |
1643 | goto done; | |
1644 | } | |
1645 | ||
4937213b MN |
1646 | /* |
1647 | * check ring is not re-allocated since URB was enqueued. If it is, then | |
1648 | * make sure none of the ring related pointers in this URB private data | |
1649 | * are touched, such as td_list, otherwise we overwrite freed data | |
1650 | */ | |
1651 | if (!td_on_ring(&urb_priv->td[0], ep_ring)) { | |
1652 | xhci_err(xhci, "Canceled URB td not found on endpoint ring"); | |
1653 | for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) { | |
1654 | td = &urb_priv->td[i]; | |
1655 | if (!list_empty(&td->cancelled_td_list)) | |
1656 | list_del_init(&td->cancelled_td_list); | |
1657 | } | |
1658 | goto err_giveback; | |
1659 | } | |
1660 | ||
d9f11ba9 | 1661 | if (xhci->xhc_state & XHCI_STATE_HALTED) { |
aa50b290 | 1662 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
d9f11ba9 | 1663 | "HC halted, freeing TD manually."); |
9ef7fbbb | 1664 | for (i = urb_priv->num_tds_done; |
d3519b9d | 1665 | i < urb_priv->num_tds; |
5c821711 | 1666 | i++) { |
7e64b037 | 1667 | td = &urb_priv->td[i]; |
585df1d9 SS |
1668 | if (!list_empty(&td->td_list)) |
1669 | list_del_init(&td->td_list); | |
1670 | if (!list_empty(&td->cancelled_td_list)) | |
1671 | list_del_init(&td->cancelled_td_list); | |
1672 | } | |
d3519b9d | 1673 | goto err_giveback; |
e34b2fbf | 1674 | } |
ae636747 | 1675 | |
9ef7fbbb MN |
1676 | i = urb_priv->num_tds_done; |
1677 | if (i < urb_priv->num_tds) | |
aa50b290 XR |
1678 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1679 | "Cancel URB %p, dev %s, ep 0x%x, " | |
1680 | "starting at offset 0x%llx", | |
79688acf SS |
1681 | urb, urb->dev->devpath, |
1682 | urb->ep->desc.bEndpointAddress, | |
1683 | (unsigned long long) xhci_trb_virt_to_dma( | |
7e64b037 MN |
1684 | urb_priv->td[i].start_seg, |
1685 | urb_priv->td[i].first_trb)); | |
79688acf | 1686 | |
9ef7fbbb | 1687 | for (; i < urb_priv->num_tds; i++) { |
7e64b037 | 1688 | td = &urb_priv->td[i]; |
8e51adcc AX |
1689 | list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); |
1690 | } | |
1691 | ||
ae636747 SS |
1692 | /* Queue a stop endpoint command, but only if this is |
1693 | * the first cancellation to be handled. | |
1694 | */ | |
9983a5fc | 1695 | if (!(ep->ep_state & EP_STOP_CMD_PENDING)) { |
103afda0 | 1696 | command = xhci_alloc_command(xhci, false, GFP_ATOMIC); |
a0ee619f HG |
1697 | if (!command) { |
1698 | ret = -ENOMEM; | |
1699 | goto done; | |
1700 | } | |
9983a5fc | 1701 | ep->ep_state |= EP_STOP_CMD_PENDING; |
6f5165cf SS |
1702 | ep->stop_cmd_timer.expires = jiffies + |
1703 | XHCI_STOP_EP_CMD_TIMEOUT * HZ; | |
1704 | add_timer(&ep->stop_cmd_timer); | |
ddba5cd0 MN |
1705 | xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id, |
1706 | ep_index, 0); | |
23e3be11 | 1707 | xhci_ring_cmd_db(xhci); |
ae636747 SS |
1708 | } |
1709 | done: | |
1710 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1711 | return ret; | |
d3519b9d MN |
1712 | |
1713 | err_giveback: | |
1714 | if (urb_priv) | |
1715 | xhci_urb_free_priv(urb_priv); | |
1716 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
1717 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1718 | usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN); | |
1719 | return ret; | |
d0e96f5a SS |
1720 | } |
1721 | ||
f94e0186 SS |
1722 | /* Drop an endpoint from a new bandwidth configuration for this device. |
1723 | * Only one call to this function is allowed per endpoint before | |
1724 | * check_bandwidth() or reset_bandwidth() must be called. | |
1725 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1726 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1727 | * different endpoint descriptor in usb_host_endpoint. | |
1728 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1729 | * not allowed. | |
f88ba78d SS |
1730 | * |
1731 | * The USB core will not allow URBs to be queued to an endpoint that is being | |
1732 | * disabled, so there's no need for mutual exclusion to protect | |
1733 | * the xhci->devs[slot_id] structure. | |
f94e0186 | 1734 | */ |
3969384c | 1735 | static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, |
f94e0186 SS |
1736 | struct usb_host_endpoint *ep) |
1737 | { | |
f94e0186 | 1738 | struct xhci_hcd *xhci; |
d115b048 JY |
1739 | struct xhci_container_ctx *in_ctx, *out_ctx; |
1740 | struct xhci_input_control_ctx *ctrl_ctx; | |
f94e0186 SS |
1741 | unsigned int ep_index; |
1742 | struct xhci_ep_ctx *ep_ctx; | |
1743 | u32 drop_flag; | |
d6759133 | 1744 | u32 new_add_flags, new_drop_flags; |
f94e0186 SS |
1745 | int ret; |
1746 | ||
64927730 | 1747 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
f94e0186 SS |
1748 | if (ret <= 0) |
1749 | return ret; | |
1750 | xhci = hcd_to_xhci(hcd); | |
fe6c6c13 SS |
1751 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1752 | return -ENODEV; | |
f94e0186 | 1753 | |
fe6c6c13 | 1754 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
1755 | drop_flag = xhci_get_endpoint_flag(&ep->desc); |
1756 | if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { | |
1757 | xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", | |
1758 | __func__, drop_flag); | |
1759 | return 0; | |
1760 | } | |
1761 | ||
f94e0186 | 1762 | in_ctx = xhci->devs[udev->slot_id]->in_ctx; |
d115b048 | 1763 | out_ctx = xhci->devs[udev->slot_id]->out_ctx; |
4daf9df5 | 1764 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
1765 | if (!ctrl_ctx) { |
1766 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1767 | __func__); | |
1768 | return 0; | |
1769 | } | |
1770 | ||
f94e0186 | 1771 | ep_index = xhci_get_endpoint_index(&ep->desc); |
d115b048 | 1772 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
f94e0186 SS |
1773 | /* If the HC already knows the endpoint is disabled, |
1774 | * or the HCD has noted it is disabled, ignore this request | |
1775 | */ | |
5071e6b2 | 1776 | if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) || |
28ccd296 ME |
1777 | le32_to_cpu(ctrl_ctx->drop_flags) & |
1778 | xhci_get_endpoint_flag(&ep->desc)) { | |
a6134136 HG |
1779 | /* Do not warn when called after a usb_device_reset */ |
1780 | if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL) | |
1781 | xhci_warn(xhci, "xHCI %s called with disabled ep %p\n", | |
1782 | __func__, ep); | |
f94e0186 SS |
1783 | return 0; |
1784 | } | |
1785 | ||
28ccd296 ME |
1786 | ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag); |
1787 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
f94e0186 | 1788 | |
28ccd296 ME |
1789 | ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag); |
1790 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 | 1791 | |
02b6fdc2 LB |
1792 | xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index); |
1793 | ||
f94e0186 SS |
1794 | xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); |
1795 | ||
0cbd4b34 CY |
1796 | if (xhci->quirks & XHCI_MTK_HOST) |
1797 | xhci_mtk_drop_ep_quirk(hcd, udev, ep); | |
1798 | ||
d6759133 | 1799 | xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", |
f94e0186 SS |
1800 | (unsigned int) ep->desc.bEndpointAddress, |
1801 | udev->slot_id, | |
1802 | (unsigned int) new_drop_flags, | |
d6759133 | 1803 | (unsigned int) new_add_flags); |
f94e0186 SS |
1804 | return 0; |
1805 | } | |
1806 | ||
1807 | /* Add an endpoint to a new possible bandwidth configuration for this device. | |
1808 | * Only one call to this function is allowed per endpoint before | |
1809 | * check_bandwidth() or reset_bandwidth() must be called. | |
1810 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1811 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1812 | * different endpoint descriptor in usb_host_endpoint. | |
1813 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1814 | * not allowed. | |
f88ba78d SS |
1815 | * |
1816 | * The USB core will not allow URBs to be queued to an endpoint until the | |
1817 | * configuration or alt setting is installed in the device, so there's no need | |
1818 | * for mutual exclusion to protect the xhci->devs[slot_id] structure. | |
f94e0186 | 1819 | */ |
3969384c | 1820 | static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, |
f94e0186 SS |
1821 | struct usb_host_endpoint *ep) |
1822 | { | |
f94e0186 | 1823 | struct xhci_hcd *xhci; |
92c9691b | 1824 | struct xhci_container_ctx *in_ctx; |
f94e0186 | 1825 | unsigned int ep_index; |
d115b048 | 1826 | struct xhci_input_control_ctx *ctrl_ctx; |
5afa0a5e | 1827 | struct xhci_ep_ctx *ep_ctx; |
f94e0186 | 1828 | u32 added_ctxs; |
d6759133 | 1829 | u32 new_add_flags, new_drop_flags; |
fa75ac37 | 1830 | struct xhci_virt_device *virt_dev; |
f94e0186 SS |
1831 | int ret = 0; |
1832 | ||
64927730 | 1833 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
a1587d97 SS |
1834 | if (ret <= 0) { |
1835 | /* So we won't queue a reset ep command for a root hub */ | |
1836 | ep->hcpriv = NULL; | |
f94e0186 | 1837 | return ret; |
a1587d97 | 1838 | } |
f94e0186 | 1839 | xhci = hcd_to_xhci(hcd); |
fe6c6c13 SS |
1840 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1841 | return -ENODEV; | |
f94e0186 SS |
1842 | |
1843 | added_ctxs = xhci_get_endpoint_flag(&ep->desc); | |
f94e0186 SS |
1844 | if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) { |
1845 | /* FIXME when we have to issue an evaluate endpoint command to | |
1846 | * deal with ep0 max packet size changing once we get the | |
1847 | * descriptors | |
1848 | */ | |
1849 | xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n", | |
1850 | __func__, added_ctxs); | |
1851 | return 0; | |
1852 | } | |
1853 | ||
fa75ac37 SS |
1854 | virt_dev = xhci->devs[udev->slot_id]; |
1855 | in_ctx = virt_dev->in_ctx; | |
4daf9df5 | 1856 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
1857 | if (!ctrl_ctx) { |
1858 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1859 | __func__); | |
1860 | return 0; | |
1861 | } | |
fa75ac37 | 1862 | |
92f8e767 | 1863 | ep_index = xhci_get_endpoint_index(&ep->desc); |
fa75ac37 SS |
1864 | /* If this endpoint is already in use, and the upper layers are trying |
1865 | * to add it again without dropping it, reject the addition. | |
1866 | */ | |
1867 | if (virt_dev->eps[ep_index].ring && | |
92c9691b | 1868 | !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) { |
fa75ac37 SS |
1869 | xhci_warn(xhci, "Trying to add endpoint 0x%x " |
1870 | "without dropping it.\n", | |
1871 | (unsigned int) ep->desc.bEndpointAddress); | |
1872 | return -EINVAL; | |
1873 | } | |
1874 | ||
f94e0186 SS |
1875 | /* If the HCD has already noted the endpoint is enabled, |
1876 | * ignore this request. | |
1877 | */ | |
92c9691b | 1878 | if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) { |
700e2052 GKH |
1879 | xhci_warn(xhci, "xHCI %s called with enabled ep %p\n", |
1880 | __func__, ep); | |
f94e0186 SS |
1881 | return 0; |
1882 | } | |
1883 | ||
f88ba78d SS |
1884 | /* |
1885 | * Configuration and alternate setting changes must be done in | |
1886 | * process context, not interrupt context (or so documenation | |
1887 | * for usb_set_interface() and usb_set_configuration() claim). | |
1888 | */ | |
fa75ac37 | 1889 | if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) { |
f94e0186 SS |
1890 | dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n", |
1891 | __func__, ep->desc.bEndpointAddress); | |
f94e0186 SS |
1892 | return -ENOMEM; |
1893 | } | |
1894 | ||
0cbd4b34 CY |
1895 | if (xhci->quirks & XHCI_MTK_HOST) { |
1896 | ret = xhci_mtk_add_ep_quirk(hcd, udev, ep); | |
1897 | if (ret < 0) { | |
9821786d LB |
1898 | xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring); |
1899 | virt_dev->eps[ep_index].new_ring = NULL; | |
0cbd4b34 CY |
1900 | return ret; |
1901 | } | |
1902 | } | |
1903 | ||
28ccd296 ME |
1904 | ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs); |
1905 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 SS |
1906 | |
1907 | /* If xhci_endpoint_disable() was called for this endpoint, but the | |
1908 | * xHC hasn't been notified yet through the check_bandwidth() call, | |
1909 | * this re-adds a new state for the endpoint from the new endpoint | |
1910 | * descriptors. We must drop and re-add this endpoint, so we leave the | |
1911 | * drop flags alone. | |
1912 | */ | |
28ccd296 | 1913 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); |
f94e0186 | 1914 | |
a1587d97 SS |
1915 | /* Store the usb_device pointer for later use */ |
1916 | ep->hcpriv = udev; | |
1917 | ||
5afa0a5e MN |
1918 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
1919 | trace_xhci_add_endpoint(ep_ctx); | |
1920 | ||
d6759133 | 1921 | xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", |
f94e0186 SS |
1922 | (unsigned int) ep->desc.bEndpointAddress, |
1923 | udev->slot_id, | |
1924 | (unsigned int) new_drop_flags, | |
d6759133 | 1925 | (unsigned int) new_add_flags); |
f94e0186 SS |
1926 | return 0; |
1927 | } | |
1928 | ||
d115b048 | 1929 | static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev) |
f94e0186 | 1930 | { |
d115b048 | 1931 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1932 | struct xhci_ep_ctx *ep_ctx; |
d115b048 | 1933 | struct xhci_slot_ctx *slot_ctx; |
f94e0186 SS |
1934 | int i; |
1935 | ||
4daf9df5 | 1936 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
92f8e767 SS |
1937 | if (!ctrl_ctx) { |
1938 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1939 | __func__); | |
1940 | return; | |
1941 | } | |
1942 | ||
f94e0186 SS |
1943 | /* When a device's add flag and drop flag are zero, any subsequent |
1944 | * configure endpoint command will leave that endpoint's state | |
1945 | * untouched. Make sure we don't leave any old state in the input | |
1946 | * endpoint contexts. | |
1947 | */ | |
d115b048 JY |
1948 | ctrl_ctx->drop_flags = 0; |
1949 | ctrl_ctx->add_flags = 0; | |
1950 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); | |
28ccd296 | 1951 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); |
f94e0186 | 1952 | /* Endpoint 0 is always valid */ |
28ccd296 | 1953 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); |
98871e94 | 1954 | for (i = 1; i < 31; i++) { |
d115b048 | 1955 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i); |
f94e0186 SS |
1956 | ep_ctx->ep_info = 0; |
1957 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1958 | ep_ctx->deq = 0; |
f94e0186 SS |
1959 | ep_ctx->tx_info = 0; |
1960 | } | |
1961 | } | |
1962 | ||
f2217e8e | 1963 | static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, |
00161f7d | 1964 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1965 | { |
1966 | int ret; | |
1967 | ||
913a8a34 | 1968 | switch (*cmd_status) { |
0b7c105a | 1969 | case COMP_COMMAND_ABORTED: |
604d02a2 | 1970 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
1971 | xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n"); |
1972 | ret = -ETIME; | |
1973 | break; | |
0b7c105a | 1974 | case COMP_RESOURCE_ERROR: |
288c0f44 ON |
1975 | dev_warn(&udev->dev, |
1976 | "Not enough host controller resources for new device state.\n"); | |
f2217e8e SS |
1977 | ret = -ENOMEM; |
1978 | /* FIXME: can we allocate more resources for the HC? */ | |
1979 | break; | |
0b7c105a FB |
1980 | case COMP_BANDWIDTH_ERROR: |
1981 | case COMP_SECONDARY_BANDWIDTH_ERROR: | |
288c0f44 ON |
1982 | dev_warn(&udev->dev, |
1983 | "Not enough bandwidth for new device state.\n"); | |
f2217e8e SS |
1984 | ret = -ENOSPC; |
1985 | /* FIXME: can we go back to the old state? */ | |
1986 | break; | |
0b7c105a | 1987 | case COMP_TRB_ERROR: |
f2217e8e SS |
1988 | /* the HCD set up something wrong */ |
1989 | dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, " | |
1990 | "add flag = 1, " | |
1991 | "and endpoint is not disabled.\n"); | |
1992 | ret = -EINVAL; | |
1993 | break; | |
0b7c105a | 1994 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
288c0f44 ON |
1995 | dev_warn(&udev->dev, |
1996 | "ERROR: Incompatible device for endpoint configure command.\n"); | |
f6ba6fe2 AH |
1997 | ret = -ENODEV; |
1998 | break; | |
f2217e8e | 1999 | case COMP_SUCCESS: |
3a7fa5be XR |
2000 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
2001 | "Successful Endpoint Configure command"); | |
f2217e8e SS |
2002 | ret = 0; |
2003 | break; | |
2004 | default: | |
288c0f44 ON |
2005 | xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n", |
2006 | *cmd_status); | |
f2217e8e SS |
2007 | ret = -EINVAL; |
2008 | break; | |
2009 | } | |
2010 | return ret; | |
2011 | } | |
2012 | ||
2013 | static int xhci_evaluate_context_result(struct xhci_hcd *xhci, | |
00161f7d | 2014 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
2015 | { |
2016 | int ret; | |
2017 | ||
913a8a34 | 2018 | switch (*cmd_status) { |
0b7c105a | 2019 | case COMP_COMMAND_ABORTED: |
604d02a2 | 2020 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
2021 | xhci_warn(xhci, "Timeout while waiting for evaluate context command\n"); |
2022 | ret = -ETIME; | |
2023 | break; | |
0b7c105a | 2024 | case COMP_PARAMETER_ERROR: |
288c0f44 ON |
2025 | dev_warn(&udev->dev, |
2026 | "WARN: xHCI driver setup invalid evaluate context command.\n"); | |
f2217e8e SS |
2027 | ret = -EINVAL; |
2028 | break; | |
0b7c105a | 2029 | case COMP_SLOT_NOT_ENABLED_ERROR: |
288c0f44 ON |
2030 | dev_warn(&udev->dev, |
2031 | "WARN: slot not enabled for evaluate context command.\n"); | |
b8031342 SS |
2032 | ret = -EINVAL; |
2033 | break; | |
0b7c105a | 2034 | case COMP_CONTEXT_STATE_ERROR: |
288c0f44 ON |
2035 | dev_warn(&udev->dev, |
2036 | "WARN: invalid context state for evaluate context command.\n"); | |
f2217e8e SS |
2037 | ret = -EINVAL; |
2038 | break; | |
0b7c105a | 2039 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
288c0f44 ON |
2040 | dev_warn(&udev->dev, |
2041 | "ERROR: Incompatible device for evaluate context command.\n"); | |
f6ba6fe2 AH |
2042 | ret = -ENODEV; |
2043 | break; | |
0b7c105a | 2044 | case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: |
1bb73a88 AH |
2045 | /* Max Exit Latency too large error */ |
2046 | dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n"); | |
2047 | ret = -EINVAL; | |
2048 | break; | |
f2217e8e | 2049 | case COMP_SUCCESS: |
3a7fa5be XR |
2050 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
2051 | "Successful evaluate context command"); | |
f2217e8e SS |
2052 | ret = 0; |
2053 | break; | |
2054 | default: | |
288c0f44 ON |
2055 | xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n", |
2056 | *cmd_status); | |
f2217e8e SS |
2057 | ret = -EINVAL; |
2058 | break; | |
2059 | } | |
2060 | return ret; | |
2061 | } | |
2062 | ||
2cf95c18 | 2063 | static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci, |
92f8e767 | 2064 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 2065 | { |
2cf95c18 SS |
2066 | u32 valid_add_flags; |
2067 | u32 valid_drop_flags; | |
2068 | ||
2cf95c18 SS |
2069 | /* Ignore the slot flag (bit 0), and the default control endpoint flag |
2070 | * (bit 1). The default control endpoint is added during the Address | |
2071 | * Device command and is never removed until the slot is disabled. | |
2072 | */ | |
ef73400c XR |
2073 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
2074 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
2075 | |
2076 | /* Use hweight32 to count the number of ones in the add flags, or | |
2077 | * number of endpoints added. Don't count endpoints that are changed | |
2078 | * (both added and dropped). | |
2079 | */ | |
2080 | return hweight32(valid_add_flags) - | |
2081 | hweight32(valid_add_flags & valid_drop_flags); | |
2082 | } | |
2083 | ||
2084 | static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci, | |
92f8e767 | 2085 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 2086 | { |
2cf95c18 SS |
2087 | u32 valid_add_flags; |
2088 | u32 valid_drop_flags; | |
2089 | ||
78d1ff02 XR |
2090 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
2091 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
2092 | |
2093 | return hweight32(valid_drop_flags) - | |
2094 | hweight32(valid_add_flags & valid_drop_flags); | |
2095 | } | |
2096 | ||
2097 | /* | |
2098 | * We need to reserve the new number of endpoints before the configure endpoint | |
2099 | * command completes. We can't subtract the dropped endpoints from the number | |
2100 | * of active endpoints until the command completes because we can oversubscribe | |
2101 | * the host in this case: | |
2102 | * | |
2103 | * - the first configure endpoint command drops more endpoints than it adds | |
2104 | * - a second configure endpoint command that adds more endpoints is queued | |
2105 | * - the first configure endpoint command fails, so the config is unchanged | |
2106 | * - the second command may succeed, even though there isn't enough resources | |
2107 | * | |
2108 | * Must be called with xhci->lock held. | |
2109 | */ | |
2110 | static int xhci_reserve_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 2111 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
2112 | { |
2113 | u32 added_eps; | |
2114 | ||
92f8e767 | 2115 | added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 2116 | if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) { |
4bdfe4c3 XR |
2117 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2118 | "Not enough ep ctxs: " | |
2119 | "%u active, need to add %u, limit is %u.", | |
2cf95c18 SS |
2120 | xhci->num_active_eps, added_eps, |
2121 | xhci->limit_active_eps); | |
2122 | return -ENOMEM; | |
2123 | } | |
2124 | xhci->num_active_eps += added_eps; | |
4bdfe4c3 XR |
2125 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2126 | "Adding %u ep ctxs, %u now active.", added_eps, | |
2cf95c18 SS |
2127 | xhci->num_active_eps); |
2128 | return 0; | |
2129 | } | |
2130 | ||
2131 | /* | |
2132 | * The configure endpoint was failed by the xHC for some other reason, so we | |
2133 | * need to revert the resources that failed configuration would have used. | |
2134 | * | |
2135 | * Must be called with xhci->lock held. | |
2136 | */ | |
2137 | static void xhci_free_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 2138 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
2139 | { |
2140 | u32 num_failed_eps; | |
2141 | ||
92f8e767 | 2142 | num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 2143 | xhci->num_active_eps -= num_failed_eps; |
4bdfe4c3 XR |
2144 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2145 | "Removing %u failed ep ctxs, %u now active.", | |
2cf95c18 SS |
2146 | num_failed_eps, |
2147 | xhci->num_active_eps); | |
2148 | } | |
2149 | ||
2150 | /* | |
2151 | * Now that the command has completed, clean up the active endpoint count by | |
2152 | * subtracting out the endpoints that were dropped (but not changed). | |
2153 | * | |
2154 | * Must be called with xhci->lock held. | |
2155 | */ | |
2156 | static void xhci_finish_resource_reservation(struct xhci_hcd *xhci, | |
92f8e767 | 2157 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
2158 | { |
2159 | u32 num_dropped_eps; | |
2160 | ||
92f8e767 | 2161 | num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx); |
2cf95c18 SS |
2162 | xhci->num_active_eps -= num_dropped_eps; |
2163 | if (num_dropped_eps) | |
4bdfe4c3 XR |
2164 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2165 | "Removing %u dropped ep ctxs, %u now active.", | |
2cf95c18 SS |
2166 | num_dropped_eps, |
2167 | xhci->num_active_eps); | |
2168 | } | |
2169 | ||
ed384bd3 | 2170 | static unsigned int xhci_get_block_size(struct usb_device *udev) |
c29eea62 SS |
2171 | { |
2172 | switch (udev->speed) { | |
2173 | case USB_SPEED_LOW: | |
2174 | case USB_SPEED_FULL: | |
2175 | return FS_BLOCK; | |
2176 | case USB_SPEED_HIGH: | |
2177 | return HS_BLOCK; | |
2178 | case USB_SPEED_SUPER: | |
0caf6b33 | 2179 | case USB_SPEED_SUPER_PLUS: |
c29eea62 SS |
2180 | return SS_BLOCK; |
2181 | case USB_SPEED_UNKNOWN: | |
2182 | case USB_SPEED_WIRELESS: | |
2183 | default: | |
2184 | /* Should never happen */ | |
2185 | return 1; | |
2186 | } | |
2187 | } | |
2188 | ||
ed384bd3 FB |
2189 | static unsigned int |
2190 | xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw) | |
c29eea62 SS |
2191 | { |
2192 | if (interval_bw->overhead[LS_OVERHEAD_TYPE]) | |
2193 | return LS_OVERHEAD; | |
2194 | if (interval_bw->overhead[FS_OVERHEAD_TYPE]) | |
2195 | return FS_OVERHEAD; | |
2196 | return HS_OVERHEAD; | |
2197 | } | |
2198 | ||
2199 | /* If we are changing a LS/FS device under a HS hub, | |
2200 | * make sure (if we are activating a new TT) that the HS bus has enough | |
2201 | * bandwidth for this new TT. | |
2202 | */ | |
2203 | static int xhci_check_tt_bw_table(struct xhci_hcd *xhci, | |
2204 | struct xhci_virt_device *virt_dev, | |
2205 | int old_active_eps) | |
2206 | { | |
2207 | struct xhci_interval_bw_table *bw_table; | |
2208 | struct xhci_tt_bw_info *tt_info; | |
2209 | ||
2210 | /* Find the bandwidth table for the root port this TT is attached to. */ | |
2211 | bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table; | |
2212 | tt_info = virt_dev->tt_info; | |
2213 | /* If this TT already had active endpoints, the bandwidth for this TT | |
2214 | * has already been added. Removing all periodic endpoints (and thus | |
2215 | * making the TT enactive) will only decrease the bandwidth used. | |
2216 | */ | |
2217 | if (old_active_eps) | |
2218 | return 0; | |
2219 | if (old_active_eps == 0 && tt_info->active_eps != 0) { | |
2220 | if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT) | |
2221 | return -ENOMEM; | |
2222 | return 0; | |
2223 | } | |
2224 | /* Not sure why we would have no new active endpoints... | |
2225 | * | |
2226 | * Maybe because of an Evaluate Context change for a hub update or a | |
2227 | * control endpoint 0 max packet size change? | |
2228 | * FIXME: skip the bandwidth calculation in that case. | |
2229 | */ | |
2230 | return 0; | |
2231 | } | |
2232 | ||
2b698999 SS |
2233 | static int xhci_check_ss_bw(struct xhci_hcd *xhci, |
2234 | struct xhci_virt_device *virt_dev) | |
2235 | { | |
2236 | unsigned int bw_reserved; | |
2237 | ||
2238 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100); | |
2239 | if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved)) | |
2240 | return -ENOMEM; | |
2241 | ||
2242 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100); | |
2243 | if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved)) | |
2244 | return -ENOMEM; | |
2245 | ||
2246 | return 0; | |
2247 | } | |
2248 | ||
c29eea62 SS |
2249 | /* |
2250 | * This algorithm is a very conservative estimate of the worst-case scheduling | |
2251 | * scenario for any one interval. The hardware dynamically schedules the | |
2252 | * packets, so we can't tell which microframe could be the limiting factor in | |
2253 | * the bandwidth scheduling. This only takes into account periodic endpoints. | |
2254 | * | |
2255 | * Obviously, we can't solve an NP complete problem to find the minimum worst | |
2256 | * case scenario. Instead, we come up with an estimate that is no less than | |
2257 | * the worst case bandwidth used for any one microframe, but may be an | |
2258 | * over-estimate. | |
2259 | * | |
2260 | * We walk the requirements for each endpoint by interval, starting with the | |
2261 | * smallest interval, and place packets in the schedule where there is only one | |
2262 | * possible way to schedule packets for that interval. In order to simplify | |
2263 | * this algorithm, we record the largest max packet size for each interval, and | |
2264 | * assume all packets will be that size. | |
2265 | * | |
2266 | * For interval 0, we obviously must schedule all packets for each interval. | |
2267 | * The bandwidth for interval 0 is just the amount of data to be transmitted | |
2268 | * (the sum of all max ESIT payload sizes, plus any overhead per packet times | |
2269 | * the number of packets). | |
2270 | * | |
2271 | * For interval 1, we have two possible microframes to schedule those packets | |
2272 | * in. For this algorithm, if we can schedule the same number of packets for | |
2273 | * each possible scheduling opportunity (each microframe), we will do so. The | |
2274 | * remaining number of packets will be saved to be transmitted in the gaps in | |
2275 | * the next interval's scheduling sequence. | |
2276 | * | |
2277 | * As we move those remaining packets to be scheduled with interval 2 packets, | |
2278 | * we have to double the number of remaining packets to transmit. This is | |
2279 | * because the intervals are actually powers of 2, and we would be transmitting | |
2280 | * the previous interval's packets twice in this interval. We also have to be | |
2281 | * sure that when we look at the largest max packet size for this interval, we | |
2282 | * also look at the largest max packet size for the remaining packets and take | |
2283 | * the greater of the two. | |
2284 | * | |
2285 | * The algorithm continues to evenly distribute packets in each scheduling | |
2286 | * opportunity, and push the remaining packets out, until we get to the last | |
2287 | * interval. Then those packets and their associated overhead are just added | |
2288 | * to the bandwidth used. | |
2e27980e SS |
2289 | */ |
2290 | static int xhci_check_bw_table(struct xhci_hcd *xhci, | |
2291 | struct xhci_virt_device *virt_dev, | |
2292 | int old_active_eps) | |
2293 | { | |
c29eea62 SS |
2294 | unsigned int bw_reserved; |
2295 | unsigned int max_bandwidth; | |
2296 | unsigned int bw_used; | |
2297 | unsigned int block_size; | |
2298 | struct xhci_interval_bw_table *bw_table; | |
2299 | unsigned int packet_size = 0; | |
2300 | unsigned int overhead = 0; | |
2301 | unsigned int packets_transmitted = 0; | |
2302 | unsigned int packets_remaining = 0; | |
2303 | unsigned int i; | |
2304 | ||
0caf6b33 | 2305 | if (virt_dev->udev->speed >= USB_SPEED_SUPER) |
2b698999 SS |
2306 | return xhci_check_ss_bw(xhci, virt_dev); |
2307 | ||
c29eea62 SS |
2308 | if (virt_dev->udev->speed == USB_SPEED_HIGH) { |
2309 | max_bandwidth = HS_BW_LIMIT; | |
2310 | /* Convert percent of bus BW reserved to blocks reserved */ | |
2311 | bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100); | |
2312 | } else { | |
2313 | max_bandwidth = FS_BW_LIMIT; | |
2314 | bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100); | |
2315 | } | |
2316 | ||
2317 | bw_table = virt_dev->bw_table; | |
2318 | /* We need to translate the max packet size and max ESIT payloads into | |
2319 | * the units the hardware uses. | |
2320 | */ | |
2321 | block_size = xhci_get_block_size(virt_dev->udev); | |
2322 | ||
2323 | /* If we are manipulating a LS/FS device under a HS hub, double check | |
2324 | * that the HS bus has enough bandwidth if we are activing a new TT. | |
2325 | */ | |
2326 | if (virt_dev->tt_info) { | |
4bdfe4c3 XR |
2327 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2328 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2329 | virt_dev->real_port); |
2330 | if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) { | |
2331 | xhci_warn(xhci, "Not enough bandwidth on HS bus for " | |
2332 | "newly activated TT.\n"); | |
2333 | return -ENOMEM; | |
2334 | } | |
4bdfe4c3 XR |
2335 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2336 | "Recalculating BW for TT slot %u port %u", | |
c29eea62 SS |
2337 | virt_dev->tt_info->slot_id, |
2338 | virt_dev->tt_info->ttport); | |
2339 | } else { | |
4bdfe4c3 XR |
2340 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2341 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2342 | virt_dev->real_port); |
2343 | } | |
2344 | ||
2345 | /* Add in how much bandwidth will be used for interval zero, or the | |
2346 | * rounded max ESIT payload + number of packets * largest overhead. | |
2347 | */ | |
2348 | bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) + | |
2349 | bw_table->interval_bw[0].num_packets * | |
2350 | xhci_get_largest_overhead(&bw_table->interval_bw[0]); | |
2351 | ||
2352 | for (i = 1; i < XHCI_MAX_INTERVAL; i++) { | |
2353 | unsigned int bw_added; | |
2354 | unsigned int largest_mps; | |
2355 | unsigned int interval_overhead; | |
2356 | ||
2357 | /* | |
2358 | * How many packets could we transmit in this interval? | |
2359 | * If packets didn't fit in the previous interval, we will need | |
2360 | * to transmit that many packets twice within this interval. | |
2361 | */ | |
2362 | packets_remaining = 2 * packets_remaining + | |
2363 | bw_table->interval_bw[i].num_packets; | |
2364 | ||
2365 | /* Find the largest max packet size of this or the previous | |
2366 | * interval. | |
2367 | */ | |
2368 | if (list_empty(&bw_table->interval_bw[i].endpoints)) | |
2369 | largest_mps = 0; | |
2370 | else { | |
2371 | struct xhci_virt_ep *virt_ep; | |
2372 | struct list_head *ep_entry; | |
2373 | ||
2374 | ep_entry = bw_table->interval_bw[i].endpoints.next; | |
2375 | virt_ep = list_entry(ep_entry, | |
2376 | struct xhci_virt_ep, bw_endpoint_list); | |
2377 | /* Convert to blocks, rounding up */ | |
2378 | largest_mps = DIV_ROUND_UP( | |
2379 | virt_ep->bw_info.max_packet_size, | |
2380 | block_size); | |
2381 | } | |
2382 | if (largest_mps > packet_size) | |
2383 | packet_size = largest_mps; | |
2384 | ||
2385 | /* Use the larger overhead of this or the previous interval. */ | |
2386 | interval_overhead = xhci_get_largest_overhead( | |
2387 | &bw_table->interval_bw[i]); | |
2388 | if (interval_overhead > overhead) | |
2389 | overhead = interval_overhead; | |
2390 | ||
2391 | /* How many packets can we evenly distribute across | |
2392 | * (1 << (i + 1)) possible scheduling opportunities? | |
2393 | */ | |
2394 | packets_transmitted = packets_remaining >> (i + 1); | |
2395 | ||
2396 | /* Add in the bandwidth used for those scheduled packets */ | |
2397 | bw_added = packets_transmitted * (overhead + packet_size); | |
2398 | ||
2399 | /* How many packets do we have remaining to transmit? */ | |
2400 | packets_remaining = packets_remaining % (1 << (i + 1)); | |
2401 | ||
2402 | /* What largest max packet size should those packets have? */ | |
2403 | /* If we've transmitted all packets, don't carry over the | |
2404 | * largest packet size. | |
2405 | */ | |
2406 | if (packets_remaining == 0) { | |
2407 | packet_size = 0; | |
2408 | overhead = 0; | |
2409 | } else if (packets_transmitted > 0) { | |
2410 | /* Otherwise if we do have remaining packets, and we've | |
2411 | * scheduled some packets in this interval, take the | |
2412 | * largest max packet size from endpoints with this | |
2413 | * interval. | |
2414 | */ | |
2415 | packet_size = largest_mps; | |
2416 | overhead = interval_overhead; | |
2417 | } | |
2418 | /* Otherwise carry over packet_size and overhead from the last | |
2419 | * time we had a remainder. | |
2420 | */ | |
2421 | bw_used += bw_added; | |
2422 | if (bw_used > max_bandwidth) { | |
2423 | xhci_warn(xhci, "Not enough bandwidth. " | |
2424 | "Proposed: %u, Max: %u\n", | |
2425 | bw_used, max_bandwidth); | |
2426 | return -ENOMEM; | |
2427 | } | |
2428 | } | |
2429 | /* | |
2430 | * Ok, we know we have some packets left over after even-handedly | |
2431 | * scheduling interval 15. We don't know which microframes they will | |
2432 | * fit into, so we over-schedule and say they will be scheduled every | |
2433 | * microframe. | |
2434 | */ | |
2435 | if (packets_remaining > 0) | |
2436 | bw_used += overhead + packet_size; | |
2437 | ||
2438 | if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) { | |
2439 | unsigned int port_index = virt_dev->real_port - 1; | |
2440 | ||
2441 | /* OK, we're manipulating a HS device attached to a | |
2442 | * root port bandwidth domain. Include the number of active TTs | |
2443 | * in the bandwidth used. | |
2444 | */ | |
2445 | bw_used += TT_HS_OVERHEAD * | |
2446 | xhci->rh_bw[port_index].num_active_tts; | |
2447 | } | |
2448 | ||
4bdfe4c3 XR |
2449 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2450 | "Final bandwidth: %u, Limit: %u, Reserved: %u, " | |
2451 | "Available: %u " "percent", | |
c29eea62 SS |
2452 | bw_used, max_bandwidth, bw_reserved, |
2453 | (max_bandwidth - bw_used - bw_reserved) * 100 / | |
2454 | max_bandwidth); | |
2455 | ||
2456 | bw_used += bw_reserved; | |
2457 | if (bw_used > max_bandwidth) { | |
2458 | xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n", | |
2459 | bw_used, max_bandwidth); | |
2460 | return -ENOMEM; | |
2461 | } | |
2462 | ||
2463 | bw_table->bw_used = bw_used; | |
2e27980e SS |
2464 | return 0; |
2465 | } | |
2466 | ||
2467 | static bool xhci_is_async_ep(unsigned int ep_type) | |
2468 | { | |
2469 | return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
2470 | ep_type != ISOC_IN_EP && | |
2471 | ep_type != INT_IN_EP); | |
2472 | } | |
2473 | ||
2b698999 SS |
2474 | static bool xhci_is_sync_in_ep(unsigned int ep_type) |
2475 | { | |
392a07ae | 2476 | return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP); |
2b698999 SS |
2477 | } |
2478 | ||
2479 | static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw) | |
2480 | { | |
2481 | unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK); | |
2482 | ||
2483 | if (ep_bw->ep_interval == 0) | |
2484 | return SS_OVERHEAD_BURST + | |
2485 | (ep_bw->mult * ep_bw->num_packets * | |
2486 | (SS_OVERHEAD + mps)); | |
2487 | return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets * | |
2488 | (SS_OVERHEAD + mps + SS_OVERHEAD_BURST), | |
2489 | 1 << ep_bw->ep_interval); | |
2490 | ||
2491 | } | |
2492 | ||
3969384c | 2493 | static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, |
2e27980e SS |
2494 | struct xhci_bw_info *ep_bw, |
2495 | struct xhci_interval_bw_table *bw_table, | |
2496 | struct usb_device *udev, | |
2497 | struct xhci_virt_ep *virt_ep, | |
2498 | struct xhci_tt_bw_info *tt_info) | |
2499 | { | |
2500 | struct xhci_interval_bw *interval_bw; | |
2501 | int normalized_interval; | |
2502 | ||
2b698999 | 2503 | if (xhci_is_async_ep(ep_bw->type)) |
2e27980e SS |
2504 | return; |
2505 | ||
0caf6b33 | 2506 | if (udev->speed >= USB_SPEED_SUPER) { |
2b698999 SS |
2507 | if (xhci_is_sync_in_ep(ep_bw->type)) |
2508 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in -= | |
2509 | xhci_get_ss_bw_consumed(ep_bw); | |
2510 | else | |
2511 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out -= | |
2512 | xhci_get_ss_bw_consumed(ep_bw); | |
2513 | return; | |
2514 | } | |
2515 | ||
2516 | /* SuperSpeed endpoints never get added to intervals in the table, so | |
2517 | * this check is only valid for HS/FS/LS devices. | |
2518 | */ | |
2519 | if (list_empty(&virt_ep->bw_endpoint_list)) | |
2520 | return; | |
2e27980e SS |
2521 | /* For LS/FS devices, we need to translate the interval expressed in |
2522 | * microframes to frames. | |
2523 | */ | |
2524 | if (udev->speed == USB_SPEED_HIGH) | |
2525 | normalized_interval = ep_bw->ep_interval; | |
2526 | else | |
2527 | normalized_interval = ep_bw->ep_interval - 3; | |
2528 | ||
2529 | if (normalized_interval == 0) | |
2530 | bw_table->interval0_esit_payload -= ep_bw->max_esit_payload; | |
2531 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2532 | interval_bw->num_packets -= ep_bw->num_packets; | |
2533 | switch (udev->speed) { | |
2534 | case USB_SPEED_LOW: | |
2535 | interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1; | |
2536 | break; | |
2537 | case USB_SPEED_FULL: | |
2538 | interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1; | |
2539 | break; | |
2540 | case USB_SPEED_HIGH: | |
2541 | interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1; | |
2542 | break; | |
2543 | case USB_SPEED_SUPER: | |
0caf6b33 | 2544 | case USB_SPEED_SUPER_PLUS: |
2e27980e SS |
2545 | case USB_SPEED_UNKNOWN: |
2546 | case USB_SPEED_WIRELESS: | |
2547 | /* Should never happen because only LS/FS/HS endpoints will get | |
2548 | * added to the endpoint list. | |
2549 | */ | |
2550 | return; | |
2551 | } | |
2552 | if (tt_info) | |
2553 | tt_info->active_eps -= 1; | |
2554 | list_del_init(&virt_ep->bw_endpoint_list); | |
2555 | } | |
2556 | ||
2557 | static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci, | |
2558 | struct xhci_bw_info *ep_bw, | |
2559 | struct xhci_interval_bw_table *bw_table, | |
2560 | struct usb_device *udev, | |
2561 | struct xhci_virt_ep *virt_ep, | |
2562 | struct xhci_tt_bw_info *tt_info) | |
2563 | { | |
2564 | struct xhci_interval_bw *interval_bw; | |
2565 | struct xhci_virt_ep *smaller_ep; | |
2566 | int normalized_interval; | |
2567 | ||
2568 | if (xhci_is_async_ep(ep_bw->type)) | |
2569 | return; | |
2570 | ||
2b698999 SS |
2571 | if (udev->speed == USB_SPEED_SUPER) { |
2572 | if (xhci_is_sync_in_ep(ep_bw->type)) | |
2573 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in += | |
2574 | xhci_get_ss_bw_consumed(ep_bw); | |
2575 | else | |
2576 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out += | |
2577 | xhci_get_ss_bw_consumed(ep_bw); | |
2578 | return; | |
2579 | } | |
2580 | ||
2e27980e SS |
2581 | /* For LS/FS devices, we need to translate the interval expressed in |
2582 | * microframes to frames. | |
2583 | */ | |
2584 | if (udev->speed == USB_SPEED_HIGH) | |
2585 | normalized_interval = ep_bw->ep_interval; | |
2586 | else | |
2587 | normalized_interval = ep_bw->ep_interval - 3; | |
2588 | ||
2589 | if (normalized_interval == 0) | |
2590 | bw_table->interval0_esit_payload += ep_bw->max_esit_payload; | |
2591 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2592 | interval_bw->num_packets += ep_bw->num_packets; | |
2593 | switch (udev->speed) { | |
2594 | case USB_SPEED_LOW: | |
2595 | interval_bw->overhead[LS_OVERHEAD_TYPE] += 1; | |
2596 | break; | |
2597 | case USB_SPEED_FULL: | |
2598 | interval_bw->overhead[FS_OVERHEAD_TYPE] += 1; | |
2599 | break; | |
2600 | case USB_SPEED_HIGH: | |
2601 | interval_bw->overhead[HS_OVERHEAD_TYPE] += 1; | |
2602 | break; | |
2603 | case USB_SPEED_SUPER: | |
0caf6b33 | 2604 | case USB_SPEED_SUPER_PLUS: |
2e27980e SS |
2605 | case USB_SPEED_UNKNOWN: |
2606 | case USB_SPEED_WIRELESS: | |
2607 | /* Should never happen because only LS/FS/HS endpoints will get | |
2608 | * added to the endpoint list. | |
2609 | */ | |
2610 | return; | |
2611 | } | |
2612 | ||
2613 | if (tt_info) | |
2614 | tt_info->active_eps += 1; | |
2615 | /* Insert the endpoint into the list, largest max packet size first. */ | |
2616 | list_for_each_entry(smaller_ep, &interval_bw->endpoints, | |
2617 | bw_endpoint_list) { | |
2618 | if (ep_bw->max_packet_size >= | |
2619 | smaller_ep->bw_info.max_packet_size) { | |
2620 | /* Add the new ep before the smaller endpoint */ | |
2621 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2622 | &smaller_ep->bw_endpoint_list); | |
2623 | return; | |
2624 | } | |
2625 | } | |
2626 | /* Add the new endpoint at the end of the list. */ | |
2627 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2628 | &interval_bw->endpoints); | |
2629 | } | |
2630 | ||
2631 | void xhci_update_tt_active_eps(struct xhci_hcd *xhci, | |
2632 | struct xhci_virt_device *virt_dev, | |
2633 | int old_active_eps) | |
2634 | { | |
2635 | struct xhci_root_port_bw_info *rh_bw_info; | |
2636 | if (!virt_dev->tt_info) | |
2637 | return; | |
2638 | ||
2639 | rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1]; | |
2640 | if (old_active_eps == 0 && | |
2641 | virt_dev->tt_info->active_eps != 0) { | |
2642 | rh_bw_info->num_active_tts += 1; | |
c29eea62 | 2643 | rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD; |
2e27980e SS |
2644 | } else if (old_active_eps != 0 && |
2645 | virt_dev->tt_info->active_eps == 0) { | |
2646 | rh_bw_info->num_active_tts -= 1; | |
c29eea62 | 2647 | rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD; |
2e27980e SS |
2648 | } |
2649 | } | |
2650 | ||
2651 | static int xhci_reserve_bandwidth(struct xhci_hcd *xhci, | |
2652 | struct xhci_virt_device *virt_dev, | |
2653 | struct xhci_container_ctx *in_ctx) | |
2654 | { | |
2655 | struct xhci_bw_info ep_bw_info[31]; | |
2656 | int i; | |
2657 | struct xhci_input_control_ctx *ctrl_ctx; | |
2658 | int old_active_eps = 0; | |
2659 | ||
2e27980e SS |
2660 | if (virt_dev->tt_info) |
2661 | old_active_eps = virt_dev->tt_info->active_eps; | |
2662 | ||
4daf9df5 | 2663 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
2664 | if (!ctrl_ctx) { |
2665 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2666 | __func__); | |
2667 | return -ENOMEM; | |
2668 | } | |
2e27980e SS |
2669 | |
2670 | for (i = 0; i < 31; i++) { | |
2671 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2672 | continue; | |
2673 | ||
2674 | /* Make a copy of the BW info in case we need to revert this */ | |
2675 | memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info, | |
2676 | sizeof(ep_bw_info[i])); | |
2677 | /* Drop the endpoint from the interval table if the endpoint is | |
2678 | * being dropped or changed. | |
2679 | */ | |
2680 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2681 | xhci_drop_ep_from_interval_table(xhci, | |
2682 | &virt_dev->eps[i].bw_info, | |
2683 | virt_dev->bw_table, | |
2684 | virt_dev->udev, | |
2685 | &virt_dev->eps[i], | |
2686 | virt_dev->tt_info); | |
2687 | } | |
2688 | /* Overwrite the information stored in the endpoints' bw_info */ | |
2689 | xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev); | |
2690 | for (i = 0; i < 31; i++) { | |
2691 | /* Add any changed or added endpoints to the interval table */ | |
2692 | if (EP_IS_ADDED(ctrl_ctx, i)) | |
2693 | xhci_add_ep_to_interval_table(xhci, | |
2694 | &virt_dev->eps[i].bw_info, | |
2695 | virt_dev->bw_table, | |
2696 | virt_dev->udev, | |
2697 | &virt_dev->eps[i], | |
2698 | virt_dev->tt_info); | |
2699 | } | |
2700 | ||
2701 | if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) { | |
2702 | /* Ok, this fits in the bandwidth we have. | |
2703 | * Update the number of active TTs. | |
2704 | */ | |
2705 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
2706 | return 0; | |
2707 | } | |
2708 | ||
2709 | /* We don't have enough bandwidth for this, revert the stored info. */ | |
2710 | for (i = 0; i < 31; i++) { | |
2711 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2712 | continue; | |
2713 | ||
2714 | /* Drop the new copies of any added or changed endpoints from | |
2715 | * the interval table. | |
2716 | */ | |
2717 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
2718 | xhci_drop_ep_from_interval_table(xhci, | |
2719 | &virt_dev->eps[i].bw_info, | |
2720 | virt_dev->bw_table, | |
2721 | virt_dev->udev, | |
2722 | &virt_dev->eps[i], | |
2723 | virt_dev->tt_info); | |
2724 | } | |
2725 | /* Revert the endpoint back to its old information */ | |
2726 | memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i], | |
2727 | sizeof(ep_bw_info[i])); | |
2728 | /* Add any changed or dropped endpoints back into the table */ | |
2729 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2730 | xhci_add_ep_to_interval_table(xhci, | |
2731 | &virt_dev->eps[i].bw_info, | |
2732 | virt_dev->bw_table, | |
2733 | virt_dev->udev, | |
2734 | &virt_dev->eps[i], | |
2735 | virt_dev->tt_info); | |
2736 | } | |
2737 | return -ENOMEM; | |
2738 | } | |
2739 | ||
2740 | ||
f2217e8e SS |
2741 | /* Issue a configure endpoint command or evaluate context command |
2742 | * and wait for it to finish. | |
2743 | */ | |
2744 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |
913a8a34 SS |
2745 | struct usb_device *udev, |
2746 | struct xhci_command *command, | |
2747 | bool ctx_change, bool must_succeed) | |
f2217e8e SS |
2748 | { |
2749 | int ret; | |
f2217e8e | 2750 | unsigned long flags; |
92f8e767 | 2751 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 2752 | struct xhci_virt_device *virt_dev; |
e3a78ff0 | 2753 | struct xhci_slot_ctx *slot_ctx; |
ddba5cd0 MN |
2754 | |
2755 | if (!command) | |
2756 | return -EINVAL; | |
f2217e8e SS |
2757 | |
2758 | spin_lock_irqsave(&xhci->lock, flags); | |
d9f11ba9 MN |
2759 | |
2760 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2761 | spin_unlock_irqrestore(&xhci->lock, flags); | |
2762 | return -ESHUTDOWN; | |
2763 | } | |
2764 | ||
913a8a34 | 2765 | virt_dev = xhci->devs[udev->slot_id]; |
750645f8 | 2766 | |
4daf9df5 | 2767 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 | 2768 | if (!ctrl_ctx) { |
1f21569c | 2769 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
2770 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
2771 | __func__); | |
2772 | return -ENOMEM; | |
2773 | } | |
2cf95c18 | 2774 | |
750645f8 | 2775 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && |
92f8e767 | 2776 | xhci_reserve_host_resources(xhci, ctrl_ctx)) { |
750645f8 SS |
2777 | spin_unlock_irqrestore(&xhci->lock, flags); |
2778 | xhci_warn(xhci, "Not enough host resources, " | |
2779 | "active endpoint contexts = %u\n", | |
2780 | xhci->num_active_eps); | |
2781 | return -ENOMEM; | |
2782 | } | |
2e27980e | 2783 | if ((xhci->quirks & XHCI_SW_BW_CHECKING) && |
ddba5cd0 | 2784 | xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) { |
2e27980e | 2785 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2786 | xhci_free_host_resources(xhci, ctrl_ctx); |
2e27980e SS |
2787 | spin_unlock_irqrestore(&xhci->lock, flags); |
2788 | xhci_warn(xhci, "Not enough bandwidth\n"); | |
2789 | return -ENOMEM; | |
2790 | } | |
750645f8 | 2791 | |
e3a78ff0 | 2792 | slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx); |
90d6d573 MN |
2793 | |
2794 | trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx); | |
e3a78ff0 MN |
2795 | trace_xhci_configure_endpoint(slot_ctx); |
2796 | ||
f2217e8e | 2797 | if (!ctx_change) |
ddba5cd0 MN |
2798 | ret = xhci_queue_configure_endpoint(xhci, command, |
2799 | command->in_ctx->dma, | |
913a8a34 | 2800 | udev->slot_id, must_succeed); |
f2217e8e | 2801 | else |
ddba5cd0 MN |
2802 | ret = xhci_queue_evaluate_context(xhci, command, |
2803 | command->in_ctx->dma, | |
4b266541 | 2804 | udev->slot_id, must_succeed); |
f2217e8e | 2805 | if (ret < 0) { |
2cf95c18 | 2806 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2807 | xhci_free_host_resources(xhci, ctrl_ctx); |
f2217e8e | 2808 | spin_unlock_irqrestore(&xhci->lock, flags); |
3a7fa5be XR |
2809 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
2810 | "FIXME allocate a new ring segment"); | |
f2217e8e SS |
2811 | return -ENOMEM; |
2812 | } | |
2813 | xhci_ring_cmd_db(xhci); | |
2814 | spin_unlock_irqrestore(&xhci->lock, flags); | |
2815 | ||
2816 | /* Wait for the configure endpoint command to complete */ | |
c311e391 | 2817 | wait_for_completion(command->completion); |
f2217e8e SS |
2818 | |
2819 | if (!ctx_change) | |
ddba5cd0 MN |
2820 | ret = xhci_configure_endpoint_result(xhci, udev, |
2821 | &command->status); | |
2cf95c18 | 2822 | else |
ddba5cd0 MN |
2823 | ret = xhci_evaluate_context_result(xhci, udev, |
2824 | &command->status); | |
2cf95c18 SS |
2825 | |
2826 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
2827 | spin_lock_irqsave(&xhci->lock, flags); | |
2828 | /* If the command failed, remove the reserved resources. | |
2829 | * Otherwise, clean up the estimate to include dropped eps. | |
2830 | */ | |
2831 | if (ret) | |
92f8e767 | 2832 | xhci_free_host_resources(xhci, ctrl_ctx); |
2cf95c18 | 2833 | else |
92f8e767 | 2834 | xhci_finish_resource_reservation(xhci, ctrl_ctx); |
2cf95c18 SS |
2835 | spin_unlock_irqrestore(&xhci->lock, flags); |
2836 | } | |
2837 | return ret; | |
f2217e8e SS |
2838 | } |
2839 | ||
df613834 HG |
2840 | static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci, |
2841 | struct xhci_virt_device *vdev, int i) | |
2842 | { | |
2843 | struct xhci_virt_ep *ep = &vdev->eps[i]; | |
2844 | ||
2845 | if (ep->ep_state & EP_HAS_STREAMS) { | |
2846 | xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n", | |
2847 | xhci_get_endpoint_address(i)); | |
2848 | xhci_free_stream_info(xhci, ep->stream_info); | |
2849 | ep->stream_info = NULL; | |
2850 | ep->ep_state &= ~EP_HAS_STREAMS; | |
2851 | } | |
2852 | } | |
2853 | ||
f88ba78d SS |
2854 | /* Called after one or more calls to xhci_add_endpoint() or |
2855 | * xhci_drop_endpoint(). If this call fails, the USB core is expected | |
2856 | * to call xhci_reset_bandwidth(). | |
2857 | * | |
2858 | * Since we are in the middle of changing either configuration or | |
2859 | * installing a new alt setting, the USB core won't allow URBs to be | |
2860 | * enqueued for any endpoint on the old config or interface. Nothing | |
2861 | * else should be touching the xhci->devs[slot_id] structure, so we | |
2862 | * don't need to take the xhci->lock for manipulating that. | |
2863 | */ | |
3969384c | 2864 | static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) |
f94e0186 SS |
2865 | { |
2866 | int i; | |
2867 | int ret = 0; | |
f94e0186 SS |
2868 | struct xhci_hcd *xhci; |
2869 | struct xhci_virt_device *virt_dev; | |
d115b048 JY |
2870 | struct xhci_input_control_ctx *ctrl_ctx; |
2871 | struct xhci_slot_ctx *slot_ctx; | |
ddba5cd0 | 2872 | struct xhci_command *command; |
f94e0186 | 2873 | |
64927730 | 2874 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2875 | if (ret <= 0) |
2876 | return ret; | |
2877 | xhci = hcd_to_xhci(hcd); | |
98d74f9c MN |
2878 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
2879 | (xhci->xhc_state & XHCI_STATE_REMOVING)) | |
fe6c6c13 | 2880 | return -ENODEV; |
f94e0186 | 2881 | |
700e2052 | 2882 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2883 | virt_dev = xhci->devs[udev->slot_id]; |
2884 | ||
103afda0 | 2885 | command = xhci_alloc_command(xhci, true, GFP_KERNEL); |
ddba5cd0 MN |
2886 | if (!command) |
2887 | return -ENOMEM; | |
2888 | ||
2889 | command->in_ctx = virt_dev->in_ctx; | |
2890 | ||
f94e0186 | 2891 | /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */ |
4daf9df5 | 2892 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
2893 | if (!ctrl_ctx) { |
2894 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2895 | __func__); | |
ddba5cd0 MN |
2896 | ret = -ENOMEM; |
2897 | goto command_cleanup; | |
92f8e767 | 2898 | } |
28ccd296 ME |
2899 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
2900 | ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG); | |
2901 | ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG)); | |
2dc37539 SS |
2902 | |
2903 | /* Don't issue the command if there's no endpoints to update. */ | |
2904 | if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) && | |
ddba5cd0 MN |
2905 | ctrl_ctx->drop_flags == 0) { |
2906 | ret = 0; | |
2907 | goto command_cleanup; | |
2908 | } | |
d6759133 | 2909 | /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */ |
d115b048 | 2910 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
d6759133 JW |
2911 | for (i = 31; i >= 1; i--) { |
2912 | __le32 le32 = cpu_to_le32(BIT(i)); | |
2913 | ||
2914 | if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32)) | |
2915 | || (ctrl_ctx->add_flags & le32) || i == 1) { | |
2916 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
2917 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i)); | |
2918 | break; | |
2919 | } | |
2920 | } | |
f94e0186 | 2921 | |
ddba5cd0 | 2922 | ret = xhci_configure_endpoint(xhci, udev, command, |
913a8a34 | 2923 | false, false); |
ddba5cd0 | 2924 | if (ret) |
f94e0186 | 2925 | /* Callee should call reset_bandwidth() */ |
ddba5cd0 | 2926 | goto command_cleanup; |
f94e0186 | 2927 | |
834cb0fc | 2928 | /* Free any rings that were dropped, but not changed. */ |
98871e94 | 2929 | for (i = 1; i < 31; i++) { |
4819fef5 | 2930 | if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) && |
df613834 | 2931 | !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) { |
c5628a2a | 2932 | xhci_free_endpoint_ring(xhci, virt_dev, i); |
df613834 HG |
2933 | xhci_check_bw_drop_ep_streams(xhci, virt_dev, i); |
2934 | } | |
834cb0fc | 2935 | } |
d115b048 | 2936 | xhci_zero_in_ctx(xhci, virt_dev); |
834cb0fc SS |
2937 | /* |
2938 | * Install any rings for completely new endpoints or changed endpoints, | |
c5628a2a | 2939 | * and free any old rings from changed endpoints. |
834cb0fc | 2940 | */ |
98871e94 | 2941 | for (i = 1; i < 31; i++) { |
74f9fe21 SS |
2942 | if (!virt_dev->eps[i].new_ring) |
2943 | continue; | |
c5628a2a | 2944 | /* Only free the old ring if it exists. |
74f9fe21 SS |
2945 | * It may not if this is the first add of an endpoint. |
2946 | */ | |
2947 | if (virt_dev->eps[i].ring) { | |
c5628a2a | 2948 | xhci_free_endpoint_ring(xhci, virt_dev, i); |
f94e0186 | 2949 | } |
df613834 | 2950 | xhci_check_bw_drop_ep_streams(xhci, virt_dev, i); |
74f9fe21 SS |
2951 | virt_dev->eps[i].ring = virt_dev->eps[i].new_ring; |
2952 | virt_dev->eps[i].new_ring = NULL; | |
167657a1 | 2953 | xhci_debugfs_create_endpoint(xhci, virt_dev, i); |
f94e0186 | 2954 | } |
ddba5cd0 MN |
2955 | command_cleanup: |
2956 | kfree(command->completion); | |
2957 | kfree(command); | |
f94e0186 | 2958 | |
f94e0186 SS |
2959 | return ret; |
2960 | } | |
2961 | ||
3969384c | 2962 | static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) |
f94e0186 | 2963 | { |
f94e0186 SS |
2964 | struct xhci_hcd *xhci; |
2965 | struct xhci_virt_device *virt_dev; | |
2966 | int i, ret; | |
2967 | ||
64927730 | 2968 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2969 | if (ret <= 0) |
2970 | return; | |
2971 | xhci = hcd_to_xhci(hcd); | |
2972 | ||
700e2052 | 2973 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2974 | virt_dev = xhci->devs[udev->slot_id]; |
2975 | /* Free any rings allocated for added endpoints */ | |
98871e94 | 2976 | for (i = 0; i < 31; i++) { |
63a0d9ab | 2977 | if (virt_dev->eps[i].new_ring) { |
02b6fdc2 | 2978 | xhci_debugfs_remove_endpoint(xhci, virt_dev, i); |
63a0d9ab SS |
2979 | xhci_ring_free(xhci, virt_dev->eps[i].new_ring); |
2980 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 SS |
2981 | } |
2982 | } | |
d115b048 | 2983 | xhci_zero_in_ctx(xhci, virt_dev); |
f94e0186 SS |
2984 | } |
2985 | ||
5270b951 | 2986 | static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci, |
913a8a34 SS |
2987 | struct xhci_container_ctx *in_ctx, |
2988 | struct xhci_container_ctx *out_ctx, | |
92f8e767 | 2989 | struct xhci_input_control_ctx *ctrl_ctx, |
913a8a34 | 2990 | u32 add_flags, u32 drop_flags) |
5270b951 | 2991 | { |
28ccd296 ME |
2992 | ctrl_ctx->add_flags = cpu_to_le32(add_flags); |
2993 | ctrl_ctx->drop_flags = cpu_to_le32(drop_flags); | |
913a8a34 | 2994 | xhci_slot_copy(xhci, in_ctx, out_ctx); |
28ccd296 | 2995 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
5270b951 SS |
2996 | } |
2997 | ||
8212a49d | 2998 | static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, |
ac9d8fe7 SS |
2999 | unsigned int slot_id, unsigned int ep_index, |
3000 | struct xhci_dequeue_state *deq_state) | |
3001 | { | |
92f8e767 | 3002 | struct xhci_input_control_ctx *ctrl_ctx; |
ac9d8fe7 | 3003 | struct xhci_container_ctx *in_ctx; |
ac9d8fe7 SS |
3004 | struct xhci_ep_ctx *ep_ctx; |
3005 | u32 added_ctxs; | |
3006 | dma_addr_t addr; | |
3007 | ||
92f8e767 | 3008 | in_ctx = xhci->devs[slot_id]->in_ctx; |
4daf9df5 | 3009 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
3010 | if (!ctrl_ctx) { |
3011 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3012 | __func__); | |
3013 | return; | |
3014 | } | |
3015 | ||
913a8a34 SS |
3016 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
3017 | xhci->devs[slot_id]->out_ctx, ep_index); | |
ac9d8fe7 SS |
3018 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); |
3019 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
3020 | deq_state->new_deq_ptr); | |
3021 | if (addr == 0) { | |
3022 | xhci_warn(xhci, "WARN Cannot submit config ep after " | |
3023 | "reset ep command\n"); | |
3024 | xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n", | |
3025 | deq_state->new_deq_seg, | |
3026 | deq_state->new_deq_ptr); | |
3027 | return; | |
3028 | } | |
28ccd296 | 3029 | ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state); |
ac9d8fe7 | 3030 | |
ac9d8fe7 | 3031 | added_ctxs = xhci_get_endpoint_flag_from_index(ep_index); |
913a8a34 | 3032 | xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx, |
92f8e767 SS |
3033 | xhci->devs[slot_id]->out_ctx, ctrl_ctx, |
3034 | added_ctxs, added_ctxs); | |
ac9d8fe7 SS |
3035 | } |
3036 | ||
93ceaa80 MN |
3037 | void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id, |
3038 | unsigned int ep_index, unsigned int stream_id, | |
3039 | struct xhci_td *td) | |
82d1009f SS |
3040 | { |
3041 | struct xhci_dequeue_state deq_state; | |
3042 | ||
a0254324 XR |
3043 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
3044 | "Cleaning up stalled endpoint ring"); | |
82d1009f SS |
3045 | /* We need to move the HW's dequeue pointer past this TD, |
3046 | * or it will attempt to resend it on the next doorbell ring. | |
3047 | */ | |
93ceaa80 MN |
3048 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, stream_id, td, |
3049 | &deq_state); | |
82d1009f | 3050 | |
365038d8 MN |
3051 | if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg) |
3052 | return; | |
3053 | ||
ac9d8fe7 SS |
3054 | /* HW with the reset endpoint quirk will use the saved dequeue state to |
3055 | * issue a configure endpoint command later. | |
3056 | */ | |
3057 | if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) { | |
a0254324 XR |
3058 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
3059 | "Queueing new dequeue state"); | |
93ceaa80 | 3060 | xhci_queue_new_dequeue_state(xhci, slot_id, |
8790736d | 3061 | ep_index, &deq_state); |
ac9d8fe7 SS |
3062 | } else { |
3063 | /* Better hope no one uses the input context between now and the | |
3064 | * reset endpoint completion! | |
e9df17eb SS |
3065 | * XXX: No idea how this hardware will react when stream rings |
3066 | * are enabled. | |
ac9d8fe7 | 3067 | */ |
4bdfe4c3 XR |
3068 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3069 | "Setting up input context for " | |
3070 | "configure endpoint command"); | |
93ceaa80 | 3071 | xhci_setup_input_ctx_for_quirk(xhci, slot_id, |
ac9d8fe7 SS |
3072 | ep_index, &deq_state); |
3073 | } | |
82d1009f SS |
3074 | } |
3075 | ||
18b74067 MN |
3076 | static void xhci_endpoint_disable(struct usb_hcd *hcd, |
3077 | struct usb_host_endpoint *host_ep) | |
3078 | { | |
3079 | struct xhci_hcd *xhci; | |
3080 | struct xhci_virt_device *vdev; | |
3081 | struct xhci_virt_ep *ep; | |
3082 | struct usb_device *udev; | |
3083 | unsigned long flags; | |
3084 | unsigned int ep_index; | |
3085 | ||
3086 | xhci = hcd_to_xhci(hcd); | |
3087 | rescan: | |
3088 | spin_lock_irqsave(&xhci->lock, flags); | |
3089 | ||
3090 | udev = (struct usb_device *)host_ep->hcpriv; | |
3091 | if (!udev || !udev->slot_id) | |
3092 | goto done; | |
3093 | ||
3094 | vdev = xhci->devs[udev->slot_id]; | |
3095 | if (!vdev) | |
3096 | goto done; | |
3097 | ||
3098 | ep_index = xhci_get_endpoint_index(&host_ep->desc); | |
3099 | ep = &vdev->eps[ep_index]; | |
3100 | if (!ep) | |
3101 | goto done; | |
3102 | ||
3103 | /* wait for hub_tt_work to finish clearing hub TT */ | |
3104 | if (ep->ep_state & EP_CLEARING_TT) { | |
3105 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3106 | schedule_timeout_uninterruptible(1); | |
3107 | goto rescan; | |
3108 | } | |
3109 | ||
3110 | if (ep->ep_state) | |
3111 | xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n", | |
3112 | ep->ep_state); | |
3113 | done: | |
3114 | host_ep->hcpriv = NULL; | |
3115 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3116 | } | |
3117 | ||
f5249461 MN |
3118 | /* |
3119 | * Called after usb core issues a clear halt control message. | |
3120 | * The host side of the halt should already be cleared by a reset endpoint | |
3121 | * command issued when the STALL event was received. | |
d0167ad2 | 3122 | * |
f5249461 MN |
3123 | * The reset endpoint command may only be issued to endpoints in the halted |
3124 | * state. For software that wishes to reset the data toggle or sequence number | |
3125 | * of an endpoint that isn't in the halted state this function will issue a | |
3126 | * configure endpoint command with the Drop and Add bits set for the target | |
3127 | * endpoint. Refer to the additional note in xhci spcification section 4.6.8. | |
a1587d97 | 3128 | */ |
8e71a322 | 3129 | |
3969384c | 3130 | static void xhci_endpoint_reset(struct usb_hcd *hcd, |
f5249461 | 3131 | struct usb_host_endpoint *host_ep) |
a1587d97 SS |
3132 | { |
3133 | struct xhci_hcd *xhci; | |
f5249461 MN |
3134 | struct usb_device *udev; |
3135 | struct xhci_virt_device *vdev; | |
3136 | struct xhci_virt_ep *ep; | |
3137 | struct xhci_input_control_ctx *ctrl_ctx; | |
3138 | struct xhci_command *stop_cmd, *cfg_cmd; | |
3139 | unsigned int ep_index; | |
3140 | unsigned long flags; | |
3141 | u32 ep_flag; | |
8de66b0e | 3142 | int err; |
a1587d97 SS |
3143 | |
3144 | xhci = hcd_to_xhci(hcd); | |
f5249461 MN |
3145 | if (!host_ep->hcpriv) |
3146 | return; | |
3147 | udev = (struct usb_device *) host_ep->hcpriv; | |
3148 | vdev = xhci->devs[udev->slot_id]; | |
cb53c517 MN |
3149 | |
3150 | /* | |
3151 | * vdev may be lost due to xHC restore error and re-initialization | |
3152 | * during S3/S4 resume. A new vdev will be allocated later by | |
3153 | * xhci_discover_or_reset_device() | |
3154 | */ | |
3155 | if (!udev->slot_id || !vdev) | |
3156 | return; | |
f5249461 MN |
3157 | ep_index = xhci_get_endpoint_index(&host_ep->desc); |
3158 | ep = &vdev->eps[ep_index]; | |
cb53c517 MN |
3159 | if (!ep) |
3160 | return; | |
f5249461 MN |
3161 | |
3162 | /* Bail out if toggle is already being cleared by a endpoint reset */ | |
3163 | if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) { | |
3164 | ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE; | |
3165 | return; | |
3166 | } | |
3167 | /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */ | |
3168 | if (usb_endpoint_xfer_control(&host_ep->desc) || | |
3169 | usb_endpoint_xfer_isoc(&host_ep->desc)) | |
3170 | return; | |
3171 | ||
3172 | ep_flag = xhci_get_endpoint_flag(&host_ep->desc); | |
3173 | ||
3174 | if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG) | |
3175 | return; | |
3176 | ||
3177 | stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT); | |
3178 | if (!stop_cmd) | |
3179 | return; | |
3180 | ||
3181 | cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT); | |
3182 | if (!cfg_cmd) | |
3183 | goto cleanup; | |
3184 | ||
3185 | spin_lock_irqsave(&xhci->lock, flags); | |
3186 | ||
3187 | /* block queuing new trbs and ringing ep doorbell */ | |
3188 | ep->ep_state |= EP_SOFT_CLEAR_TOGGLE; | |
ddba5cd0 | 3189 | |
c92bcfa7 | 3190 | /* |
f5249461 MN |
3191 | * Make sure endpoint ring is empty before resetting the toggle/seq. |
3192 | * Driver is required to synchronously cancel all transfer request. | |
3193 | * Stop the endpoint to force xHC to update the output context | |
c92bcfa7 | 3194 | */ |
a1587d97 | 3195 | |
f5249461 MN |
3196 | if (!list_empty(&ep->ring->td_list)) { |
3197 | dev_err(&udev->dev, "EP not empty, refuse reset\n"); | |
3198 | spin_unlock_irqrestore(&xhci->lock, flags); | |
d89b7664 | 3199 | xhci_free_command(xhci, cfg_cmd); |
f5249461 MN |
3200 | goto cleanup; |
3201 | } | |
8de66b0e BK |
3202 | |
3203 | err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id, | |
3204 | ep_index, 0); | |
3205 | if (err < 0) { | |
3206 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3207 | xhci_free_command(xhci, cfg_cmd); | |
3208 | xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ", | |
3209 | __func__, err); | |
3210 | goto cleanup; | |
3211 | } | |
3212 | ||
f5249461 MN |
3213 | xhci_ring_cmd_db(xhci); |
3214 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3215 | ||
3216 | wait_for_completion(stop_cmd->completion); | |
3217 | ||
3218 | spin_lock_irqsave(&xhci->lock, flags); | |
3219 | ||
3220 | /* config ep command clears toggle if add and drop ep flags are set */ | |
3221 | ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx); | |
3222 | xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx, | |
3223 | ctrl_ctx, ep_flag, ep_flag); | |
3224 | xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index); | |
3225 | ||
8de66b0e | 3226 | err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma, |
f5249461 | 3227 | udev->slot_id, false); |
8de66b0e BK |
3228 | if (err < 0) { |
3229 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3230 | xhci_free_command(xhci, cfg_cmd); | |
3231 | xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ", | |
3232 | __func__, err); | |
3233 | goto cleanup; | |
3234 | } | |
3235 | ||
f5249461 MN |
3236 | xhci_ring_cmd_db(xhci); |
3237 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3238 | ||
3239 | wait_for_completion(cfg_cmd->completion); | |
3240 | ||
f5249461 MN |
3241 | xhci_free_command(xhci, cfg_cmd); |
3242 | cleanup: | |
3243 | xhci_free_command(xhci, stop_cmd); | |
f1ec7ae6 DH |
3244 | if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE) |
3245 | ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE; | |
a1587d97 SS |
3246 | } |
3247 | ||
8df75f42 SS |
3248 | static int xhci_check_streams_endpoint(struct xhci_hcd *xhci, |
3249 | struct usb_device *udev, struct usb_host_endpoint *ep, | |
3250 | unsigned int slot_id) | |
3251 | { | |
3252 | int ret; | |
3253 | unsigned int ep_index; | |
3254 | unsigned int ep_state; | |
3255 | ||
3256 | if (!ep) | |
3257 | return -EINVAL; | |
64927730 | 3258 | ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__); |
8df75f42 SS |
3259 | if (ret <= 0) |
3260 | return -EINVAL; | |
a3901538 | 3261 | if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) { |
8df75f42 SS |
3262 | xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion" |
3263 | " descriptor for ep 0x%x does not support streams\n", | |
3264 | ep->desc.bEndpointAddress); | |
3265 | return -EINVAL; | |
3266 | } | |
3267 | ||
3268 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
3269 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
3270 | if (ep_state & EP_HAS_STREAMS || | |
3271 | ep_state & EP_GETTING_STREAMS) { | |
3272 | xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x " | |
3273 | "already has streams set up.\n", | |
3274 | ep->desc.bEndpointAddress); | |
3275 | xhci_warn(xhci, "Send email to xHCI maintainer and ask for " | |
3276 | "dynamic stream context array reallocation.\n"); | |
3277 | return -EINVAL; | |
3278 | } | |
3279 | if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) { | |
3280 | xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk " | |
3281 | "endpoint 0x%x; URBs are pending.\n", | |
3282 | ep->desc.bEndpointAddress); | |
3283 | return -EINVAL; | |
3284 | } | |
3285 | return 0; | |
3286 | } | |
3287 | ||
3288 | static void xhci_calculate_streams_entries(struct xhci_hcd *xhci, | |
3289 | unsigned int *num_streams, unsigned int *num_stream_ctxs) | |
3290 | { | |
3291 | unsigned int max_streams; | |
3292 | ||
3293 | /* The stream context array size must be a power of two */ | |
3294 | *num_stream_ctxs = roundup_pow_of_two(*num_streams); | |
3295 | /* | |
3296 | * Find out how many primary stream array entries the host controller | |
3297 | * supports. Later we may use secondary stream arrays (similar to 2nd | |
3298 | * level page entries), but that's an optional feature for xHCI host | |
3299 | * controllers. xHCs must support at least 4 stream IDs. | |
3300 | */ | |
3301 | max_streams = HCC_MAX_PSA(xhci->hcc_params); | |
3302 | if (*num_stream_ctxs > max_streams) { | |
3303 | xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n", | |
3304 | max_streams); | |
3305 | *num_stream_ctxs = max_streams; | |
3306 | *num_streams = max_streams; | |
3307 | } | |
3308 | } | |
3309 | ||
3310 | /* Returns an error code if one of the endpoint already has streams. | |
3311 | * This does not change any data structures, it only checks and gathers | |
3312 | * information. | |
3313 | */ | |
3314 | static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci, | |
3315 | struct usb_device *udev, | |
3316 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3317 | unsigned int *num_streams, u32 *changed_ep_bitmask) | |
3318 | { | |
8df75f42 SS |
3319 | unsigned int max_streams; |
3320 | unsigned int endpoint_flag; | |
3321 | int i; | |
3322 | int ret; | |
3323 | ||
3324 | for (i = 0; i < num_eps; i++) { | |
3325 | ret = xhci_check_streams_endpoint(xhci, udev, | |
3326 | eps[i], udev->slot_id); | |
3327 | if (ret < 0) | |
3328 | return ret; | |
3329 | ||
18b7ede5 | 3330 | max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp); |
8df75f42 SS |
3331 | if (max_streams < (*num_streams - 1)) { |
3332 | xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n", | |
3333 | eps[i]->desc.bEndpointAddress, | |
3334 | max_streams); | |
3335 | *num_streams = max_streams+1; | |
3336 | } | |
3337 | ||
3338 | endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc); | |
3339 | if (*changed_ep_bitmask & endpoint_flag) | |
3340 | return -EINVAL; | |
3341 | *changed_ep_bitmask |= endpoint_flag; | |
3342 | } | |
3343 | return 0; | |
3344 | } | |
3345 | ||
3346 | static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci, | |
3347 | struct usb_device *udev, | |
3348 | struct usb_host_endpoint **eps, unsigned int num_eps) | |
3349 | { | |
3350 | u32 changed_ep_bitmask = 0; | |
3351 | unsigned int slot_id; | |
3352 | unsigned int ep_index; | |
3353 | unsigned int ep_state; | |
3354 | int i; | |
3355 | ||
3356 | slot_id = udev->slot_id; | |
3357 | if (!xhci->devs[slot_id]) | |
3358 | return 0; | |
3359 | ||
3360 | for (i = 0; i < num_eps; i++) { | |
3361 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3362 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
3363 | /* Are streams already being freed for the endpoint? */ | |
3364 | if (ep_state & EP_GETTING_NO_STREAMS) { | |
3365 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3366 | "endpoint 0x%x, " |
3367 | "streams are being disabled already\n", | |
8df75f42 SS |
3368 | eps[i]->desc.bEndpointAddress); |
3369 | return 0; | |
3370 | } | |
3371 | /* Are there actually any streams to free? */ | |
3372 | if (!(ep_state & EP_HAS_STREAMS) && | |
3373 | !(ep_state & EP_GETTING_STREAMS)) { | |
3374 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3375 | "endpoint 0x%x, " |
3376 | "streams are already disabled!\n", | |
8df75f42 SS |
3377 | eps[i]->desc.bEndpointAddress); |
3378 | xhci_warn(xhci, "WARN xhci_free_streams() called " | |
3379 | "with non-streams endpoint\n"); | |
3380 | return 0; | |
3381 | } | |
3382 | changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc); | |
3383 | } | |
3384 | return changed_ep_bitmask; | |
3385 | } | |
3386 | ||
3387 | /* | |
c2a298d9 | 3388 | * The USB device drivers use this function (through the HCD interface in USB |
8df75f42 SS |
3389 | * core) to prepare a set of bulk endpoints to use streams. Streams are used to |
3390 | * coordinate mass storage command queueing across multiple endpoints (basically | |
3391 | * a stream ID == a task ID). | |
3392 | * | |
3393 | * Setting up streams involves allocating the same size stream context array | |
3394 | * for each endpoint and issuing a configure endpoint command for all endpoints. | |
3395 | * | |
3396 | * Don't allow the call to succeed if one endpoint only supports one stream | |
3397 | * (which means it doesn't support streams at all). | |
3398 | * | |
3399 | * Drivers may get less stream IDs than they asked for, if the host controller | |
3400 | * hardware or endpoints claim they can't support the number of requested | |
3401 | * stream IDs. | |
3402 | */ | |
3969384c | 3403 | static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, |
8df75f42 SS |
3404 | struct usb_host_endpoint **eps, unsigned int num_eps, |
3405 | unsigned int num_streams, gfp_t mem_flags) | |
3406 | { | |
3407 | int i, ret; | |
3408 | struct xhci_hcd *xhci; | |
3409 | struct xhci_virt_device *vdev; | |
3410 | struct xhci_command *config_cmd; | |
92f8e767 | 3411 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3412 | unsigned int ep_index; |
3413 | unsigned int num_stream_ctxs; | |
f9c589e1 | 3414 | unsigned int max_packet; |
8df75f42 SS |
3415 | unsigned long flags; |
3416 | u32 changed_ep_bitmask = 0; | |
3417 | ||
3418 | if (!eps) | |
3419 | return -EINVAL; | |
3420 | ||
3421 | /* Add one to the number of streams requested to account for | |
3422 | * stream 0 that is reserved for xHCI usage. | |
3423 | */ | |
3424 | num_streams += 1; | |
3425 | xhci = hcd_to_xhci(hcd); | |
3426 | xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n", | |
3427 | num_streams); | |
3428 | ||
f7920884 | 3429 | /* MaxPSASize value 0 (2 streams) means streams are not supported */ |
8f873c1f HG |
3430 | if ((xhci->quirks & XHCI_BROKEN_STREAMS) || |
3431 | HCC_MAX_PSA(xhci->hcc_params) < 4) { | |
f7920884 HG |
3432 | xhci_dbg(xhci, "xHCI controller does not support streams.\n"); |
3433 | return -ENOSYS; | |
3434 | } | |
3435 | ||
14d49b7a | 3436 | config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags); |
74e0b564 | 3437 | if (!config_cmd) |
8df75f42 | 3438 | return -ENOMEM; |
74e0b564 | 3439 | |
4daf9df5 | 3440 | ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx); |
92f8e767 SS |
3441 | if (!ctrl_ctx) { |
3442 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3443 | __func__); | |
3444 | xhci_free_command(xhci, config_cmd); | |
3445 | return -ENOMEM; | |
3446 | } | |
8df75f42 SS |
3447 | |
3448 | /* Check to make sure all endpoints are not already configured for | |
3449 | * streams. While we're at it, find the maximum number of streams that | |
3450 | * all the endpoints will support and check for duplicate endpoints. | |
3451 | */ | |
3452 | spin_lock_irqsave(&xhci->lock, flags); | |
3453 | ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps, | |
3454 | num_eps, &num_streams, &changed_ep_bitmask); | |
3455 | if (ret < 0) { | |
3456 | xhci_free_command(xhci, config_cmd); | |
3457 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3458 | return ret; | |
3459 | } | |
3460 | if (num_streams <= 1) { | |
3461 | xhci_warn(xhci, "WARN: endpoints can't handle " | |
3462 | "more than one stream.\n"); | |
3463 | xhci_free_command(xhci, config_cmd); | |
3464 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3465 | return -EINVAL; | |
3466 | } | |
3467 | vdev = xhci->devs[udev->slot_id]; | |
25985edc | 3468 | /* Mark each endpoint as being in transition, so |
8df75f42 SS |
3469 | * xhci_urb_enqueue() will reject all URBs. |
3470 | */ | |
3471 | for (i = 0; i < num_eps; i++) { | |
3472 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3473 | vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS; | |
3474 | } | |
3475 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3476 | ||
3477 | /* Setup internal data structures and allocate HW data structures for | |
3478 | * streams (but don't install the HW structures in the input context | |
3479 | * until we're sure all memory allocation succeeded). | |
3480 | */ | |
3481 | xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs); | |
3482 | xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n", | |
3483 | num_stream_ctxs, num_streams); | |
3484 | ||
3485 | for (i = 0; i < num_eps; i++) { | |
3486 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
734d3ddd | 3487 | max_packet = usb_endpoint_maxp(&eps[i]->desc); |
8df75f42 SS |
3488 | vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci, |
3489 | num_stream_ctxs, | |
f9c589e1 MN |
3490 | num_streams, |
3491 | max_packet, mem_flags); | |
8df75f42 SS |
3492 | if (!vdev->eps[ep_index].stream_info) |
3493 | goto cleanup; | |
3494 | /* Set maxPstreams in endpoint context and update deq ptr to | |
3495 | * point to stream context array. FIXME | |
3496 | */ | |
3497 | } | |
3498 | ||
3499 | /* Set up the input context for a configure endpoint command. */ | |
3500 | for (i = 0; i < num_eps; i++) { | |
3501 | struct xhci_ep_ctx *ep_ctx; | |
3502 | ||
3503 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3504 | ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index); | |
3505 | ||
3506 | xhci_endpoint_copy(xhci, config_cmd->in_ctx, | |
3507 | vdev->out_ctx, ep_index); | |
3508 | xhci_setup_streams_ep_input_ctx(xhci, ep_ctx, | |
3509 | vdev->eps[ep_index].stream_info); | |
3510 | } | |
3511 | /* Tell the HW to drop its old copy of the endpoint context info | |
3512 | * and add the updated copy from the input context. | |
3513 | */ | |
3514 | xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx, | |
92f8e767 SS |
3515 | vdev->out_ctx, ctrl_ctx, |
3516 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3517 | |
3518 | /* Issue and wait for the configure endpoint command */ | |
3519 | ret = xhci_configure_endpoint(xhci, udev, config_cmd, | |
3520 | false, false); | |
3521 | ||
3522 | /* xHC rejected the configure endpoint command for some reason, so we | |
3523 | * leave the old ring intact and free our internal streams data | |
3524 | * structure. | |
3525 | */ | |
3526 | if (ret < 0) | |
3527 | goto cleanup; | |
3528 | ||
3529 | spin_lock_irqsave(&xhci->lock, flags); | |
3530 | for (i = 0; i < num_eps; i++) { | |
3531 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3532 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3533 | xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n", | |
3534 | udev->slot_id, ep_index); | |
3535 | vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS; | |
673d7468 | 3536 | xhci_debugfs_create_stream_files(xhci, vdev, ep_index); |
8df75f42 SS |
3537 | } |
3538 | xhci_free_command(xhci, config_cmd); | |
3539 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3540 | ||
3541 | /* Subtract 1 for stream 0, which drivers can't use */ | |
3542 | return num_streams - 1; | |
3543 | ||
3544 | cleanup: | |
3545 | /* If it didn't work, free the streams! */ | |
3546 | for (i = 0; i < num_eps; i++) { | |
3547 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3548 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3549 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3550 | /* FIXME Unset maxPstreams in endpoint context and |
3551 | * update deq ptr to point to normal string ring. | |
3552 | */ | |
3553 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3554 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3555 | xhci_endpoint_zero(xhci, vdev, eps[i]); | |
3556 | } | |
3557 | xhci_free_command(xhci, config_cmd); | |
3558 | return -ENOMEM; | |
3559 | } | |
3560 | ||
3561 | /* Transition the endpoint from using streams to being a "normal" endpoint | |
3562 | * without streams. | |
3563 | * | |
3564 | * Modify the endpoint context state, submit a configure endpoint command, | |
3565 | * and free all endpoint rings for streams if that completes successfully. | |
3566 | */ | |
3969384c | 3567 | static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, |
8df75f42 SS |
3568 | struct usb_host_endpoint **eps, unsigned int num_eps, |
3569 | gfp_t mem_flags) | |
3570 | { | |
3571 | int i, ret; | |
3572 | struct xhci_hcd *xhci; | |
3573 | struct xhci_virt_device *vdev; | |
3574 | struct xhci_command *command; | |
92f8e767 | 3575 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3576 | unsigned int ep_index; |
3577 | unsigned long flags; | |
3578 | u32 changed_ep_bitmask; | |
3579 | ||
3580 | xhci = hcd_to_xhci(hcd); | |
3581 | vdev = xhci->devs[udev->slot_id]; | |
3582 | ||
3583 | /* Set up a configure endpoint command to remove the streams rings */ | |
3584 | spin_lock_irqsave(&xhci->lock, flags); | |
3585 | changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci, | |
3586 | udev, eps, num_eps); | |
3587 | if (changed_ep_bitmask == 0) { | |
3588 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3589 | return -EINVAL; | |
3590 | } | |
3591 | ||
3592 | /* Use the xhci_command structure from the first endpoint. We may have | |
3593 | * allocated too many, but the driver may call xhci_free_streams() for | |
3594 | * each endpoint it grouped into one call to xhci_alloc_streams(). | |
3595 | */ | |
3596 | ep_index = xhci_get_endpoint_index(&eps[0]->desc); | |
3597 | command = vdev->eps[ep_index].stream_info->free_streams_command; | |
4daf9df5 | 3598 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 | 3599 | if (!ctrl_ctx) { |
1f21569c | 3600 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
3601 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
3602 | __func__); | |
3603 | return -EINVAL; | |
3604 | } | |
3605 | ||
8df75f42 SS |
3606 | for (i = 0; i < num_eps; i++) { |
3607 | struct xhci_ep_ctx *ep_ctx; | |
3608 | ||
3609 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3610 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); | |
3611 | xhci->devs[udev->slot_id]->eps[ep_index].ep_state |= | |
3612 | EP_GETTING_NO_STREAMS; | |
3613 | ||
3614 | xhci_endpoint_copy(xhci, command->in_ctx, | |
3615 | vdev->out_ctx, ep_index); | |
4daf9df5 | 3616 | xhci_setup_no_streams_ep_input_ctx(ep_ctx, |
8df75f42 SS |
3617 | &vdev->eps[ep_index]); |
3618 | } | |
3619 | xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx, | |
92f8e767 SS |
3620 | vdev->out_ctx, ctrl_ctx, |
3621 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3622 | spin_unlock_irqrestore(&xhci->lock, flags); |
3623 | ||
3624 | /* Issue and wait for the configure endpoint command, | |
3625 | * which must succeed. | |
3626 | */ | |
3627 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3628 | false, true); | |
3629 | ||
3630 | /* xHC rejected the configure endpoint command for some reason, so we | |
3631 | * leave the streams rings intact. | |
3632 | */ | |
3633 | if (ret < 0) | |
3634 | return ret; | |
3635 | ||
3636 | spin_lock_irqsave(&xhci->lock, flags); | |
3637 | for (i = 0; i < num_eps; i++) { | |
3638 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3639 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3640 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3641 | /* FIXME Unset maxPstreams in endpoint context and |
3642 | * update deq ptr to point to normal string ring. | |
3643 | */ | |
3644 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS; | |
3645 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3646 | } | |
3647 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3648 | ||
3649 | return 0; | |
3650 | } | |
3651 | ||
2cf95c18 SS |
3652 | /* |
3653 | * Deletes endpoint resources for endpoints that were active before a Reset | |
3654 | * Device command, or a Disable Slot command. The Reset Device command leaves | |
3655 | * the control endpoint intact, whereas the Disable Slot command deletes it. | |
3656 | * | |
3657 | * Must be called with xhci->lock held. | |
3658 | */ | |
3659 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, | |
3660 | struct xhci_virt_device *virt_dev, bool drop_control_ep) | |
3661 | { | |
3662 | int i; | |
3663 | unsigned int num_dropped_eps = 0; | |
3664 | unsigned int drop_flags = 0; | |
3665 | ||
3666 | for (i = (drop_control_ep ? 0 : 1); i < 31; i++) { | |
3667 | if (virt_dev->eps[i].ring) { | |
3668 | drop_flags |= 1 << i; | |
3669 | num_dropped_eps++; | |
3670 | } | |
3671 | } | |
3672 | xhci->num_active_eps -= num_dropped_eps; | |
3673 | if (num_dropped_eps) | |
4bdfe4c3 XR |
3674 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3675 | "Dropped %u ep ctxs, flags = 0x%x, " | |
3676 | "%u now active.", | |
2cf95c18 SS |
3677 | num_dropped_eps, drop_flags, |
3678 | xhci->num_active_eps); | |
3679 | } | |
3680 | ||
2a8f82c4 SS |
3681 | /* |
3682 | * This submits a Reset Device Command, which will set the device state to 0, | |
3683 | * set the device address to 0, and disable all the endpoints except the default | |
3684 | * control endpoint. The USB core should come back and call | |
3685 | * xhci_address_device(), and then re-set up the configuration. If this is | |
3686 | * called because of a usb_reset_and_verify_device(), then the old alternate | |
3687 | * settings will be re-installed through the normal bandwidth allocation | |
3688 | * functions. | |
3689 | * | |
3690 | * Wait for the Reset Device command to finish. Remove all structures | |
3691 | * associated with the endpoints that were disabled. Clear the input device | |
c5628a2a | 3692 | * structure? Reset the control endpoint 0 max packet size? |
f0615c45 AX |
3693 | * |
3694 | * If the virt_dev to be reset does not exist or does not match the udev, | |
3695 | * it means the device is lost, possibly due to the xHC restore error and | |
3696 | * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to | |
3697 | * re-allocate the device. | |
2a8f82c4 | 3698 | */ |
3969384c LB |
3699 | static int xhci_discover_or_reset_device(struct usb_hcd *hcd, |
3700 | struct usb_device *udev) | |
2a8f82c4 SS |
3701 | { |
3702 | int ret, i; | |
3703 | unsigned long flags; | |
3704 | struct xhci_hcd *xhci; | |
3705 | unsigned int slot_id; | |
3706 | struct xhci_virt_device *virt_dev; | |
3707 | struct xhci_command *reset_device_cmd; | |
001fd382 | 3708 | struct xhci_slot_ctx *slot_ctx; |
2e27980e | 3709 | int old_active_eps = 0; |
2a8f82c4 | 3710 | |
f0615c45 | 3711 | ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__); |
2a8f82c4 SS |
3712 | if (ret <= 0) |
3713 | return ret; | |
3714 | xhci = hcd_to_xhci(hcd); | |
3715 | slot_id = udev->slot_id; | |
3716 | virt_dev = xhci->devs[slot_id]; | |
f0615c45 AX |
3717 | if (!virt_dev) { |
3718 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3719 | "not exist. Re-allocate the device\n", slot_id); | |
3720 | ret = xhci_alloc_dev(hcd, udev); | |
3721 | if (ret == 1) | |
3722 | return 0; | |
3723 | else | |
3724 | return -EINVAL; | |
3725 | } | |
3726 | ||
326124a0 BC |
3727 | if (virt_dev->tt_info) |
3728 | old_active_eps = virt_dev->tt_info->active_eps; | |
3729 | ||
f0615c45 AX |
3730 | if (virt_dev->udev != udev) { |
3731 | /* If the virt_dev and the udev does not match, this virt_dev | |
3732 | * may belong to another udev. | |
3733 | * Re-allocate the device. | |
3734 | */ | |
3735 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3736 | "not match the udev. Re-allocate the device\n", | |
3737 | slot_id); | |
3738 | ret = xhci_alloc_dev(hcd, udev); | |
3739 | if (ret == 1) | |
3740 | return 0; | |
3741 | else | |
3742 | return -EINVAL; | |
3743 | } | |
2a8f82c4 | 3744 | |
001fd382 ML |
3745 | /* If device is not setup, there is no point in resetting it */ |
3746 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
3747 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == | |
3748 | SLOT_STATE_DISABLED) | |
3749 | return 0; | |
3750 | ||
19a7d0d6 FB |
3751 | trace_xhci_discover_or_reset_device(slot_ctx); |
3752 | ||
2a8f82c4 SS |
3753 | xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id); |
3754 | /* Allocate the command structure that holds the struct completion. | |
3755 | * Assume we're in process context, since the normal device reset | |
3756 | * process has to wait for the device anyway. Storage devices are | |
3757 | * reset as part of error handling, so use GFP_NOIO instead of | |
3758 | * GFP_KERNEL. | |
3759 | */ | |
103afda0 | 3760 | reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO); |
2a8f82c4 SS |
3761 | if (!reset_device_cmd) { |
3762 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | |
3763 | return -ENOMEM; | |
3764 | } | |
3765 | ||
3766 | /* Attempt to submit the Reset Device command to the command ring */ | |
3767 | spin_lock_irqsave(&xhci->lock, flags); | |
7a3783ef | 3768 | |
ddba5cd0 | 3769 | ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id); |
2a8f82c4 SS |
3770 | if (ret) { |
3771 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
2a8f82c4 SS |
3772 | spin_unlock_irqrestore(&xhci->lock, flags); |
3773 | goto command_cleanup; | |
3774 | } | |
3775 | xhci_ring_cmd_db(xhci); | |
3776 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3777 | ||
3778 | /* Wait for the Reset Device command to finish */ | |
c311e391 | 3779 | wait_for_completion(reset_device_cmd->completion); |
2a8f82c4 SS |
3780 | |
3781 | /* The Reset Device command can't fail, according to the 0.95/0.96 spec, | |
3782 | * unless we tried to reset a slot ID that wasn't enabled, | |
3783 | * or the device wasn't in the addressed or configured state. | |
3784 | */ | |
3785 | ret = reset_device_cmd->status; | |
3786 | switch (ret) { | |
0b7c105a | 3787 | case COMP_COMMAND_ABORTED: |
604d02a2 | 3788 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
3789 | xhci_warn(xhci, "Timeout waiting for reset device command\n"); |
3790 | ret = -ETIME; | |
3791 | goto command_cleanup; | |
0b7c105a FB |
3792 | case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */ |
3793 | case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */ | |
38a532a6 | 3794 | xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n", |
2a8f82c4 SS |
3795 | slot_id, |
3796 | xhci_get_slot_state(xhci, virt_dev->out_ctx)); | |
38a532a6 | 3797 | xhci_dbg(xhci, "Not freeing device rings.\n"); |
2a8f82c4 SS |
3798 | /* Don't treat this as an error. May change my mind later. */ |
3799 | ret = 0; | |
3800 | goto command_cleanup; | |
3801 | case COMP_SUCCESS: | |
3802 | xhci_dbg(xhci, "Successful reset device command.\n"); | |
3803 | break; | |
3804 | default: | |
3805 | if (xhci_is_vendor_info_code(xhci, ret)) | |
3806 | break; | |
3807 | xhci_warn(xhci, "Unknown completion code %u for " | |
3808 | "reset device command.\n", ret); | |
3809 | ret = -EINVAL; | |
3810 | goto command_cleanup; | |
3811 | } | |
3812 | ||
2cf95c18 SS |
3813 | /* Free up host controller endpoint resources */ |
3814 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3815 | spin_lock_irqsave(&xhci->lock, flags); | |
3816 | /* Don't delete the default control endpoint resources */ | |
3817 | xhci_free_device_endpoint_resources(xhci, virt_dev, false); | |
3818 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3819 | } | |
3820 | ||
c5628a2a | 3821 | /* Everything but endpoint 0 is disabled, so free the rings. */ |
98871e94 | 3822 | for (i = 1; i < 31; i++) { |
2dea75d9 DT |
3823 | struct xhci_virt_ep *ep = &virt_dev->eps[i]; |
3824 | ||
3825 | if (ep->ep_state & EP_HAS_STREAMS) { | |
df613834 HG |
3826 | xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n", |
3827 | xhci_get_endpoint_address(i)); | |
2dea75d9 DT |
3828 | xhci_free_stream_info(xhci, ep->stream_info); |
3829 | ep->stream_info = NULL; | |
3830 | ep->ep_state &= ~EP_HAS_STREAMS; | |
3831 | } | |
3832 | ||
3833 | if (ep->ring) { | |
02b6fdc2 | 3834 | xhci_debugfs_remove_endpoint(xhci, virt_dev, i); |
c5628a2a | 3835 | xhci_free_endpoint_ring(xhci, virt_dev, i); |
2dea75d9 | 3836 | } |
2e27980e SS |
3837 | if (!list_empty(&virt_dev->eps[i].bw_endpoint_list)) |
3838 | xhci_drop_ep_from_interval_table(xhci, | |
3839 | &virt_dev->eps[i].bw_info, | |
3840 | virt_dev->bw_table, | |
3841 | udev, | |
3842 | &virt_dev->eps[i], | |
3843 | virt_dev->tt_info); | |
9af5d71d | 3844 | xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info); |
2a8f82c4 | 3845 | } |
2e27980e SS |
3846 | /* If necessary, update the number of active TTs on this root port */ |
3847 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
b8c3b718 | 3848 | virt_dev->flags = 0; |
2a8f82c4 SS |
3849 | ret = 0; |
3850 | ||
3851 | command_cleanup: | |
3852 | xhci_free_command(xhci, reset_device_cmd); | |
3853 | return ret; | |
3854 | } | |
3855 | ||
3ffbba95 SS |
3856 | /* |
3857 | * At this point, the struct usb_device is about to go away, the device has | |
3858 | * disconnected, and all traffic has been stopped and the endpoints have been | |
3859 | * disabled. Free any HC data structures associated with that device. | |
3860 | */ | |
3969384c | 3861 | static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) |
3ffbba95 SS |
3862 | { |
3863 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
6f5165cf | 3864 | struct xhci_virt_device *virt_dev; |
19a7d0d6 | 3865 | struct xhci_slot_ctx *slot_ctx; |
64927730 | 3866 | int i, ret; |
ddba5cd0 | 3867 | |
c8476fb8 SN |
3868 | #ifndef CONFIG_USB_DEFAULT_PERSIST |
3869 | /* | |
3870 | * We called pm_runtime_get_noresume when the device was attached. | |
3871 | * Decrement the counter here to allow controller to runtime suspend | |
3872 | * if no devices remain. | |
3873 | */ | |
3874 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3875 | pm_runtime_put_noidle(hcd->self.controller); |
c8476fb8 SN |
3876 | #endif |
3877 | ||
64927730 | 3878 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
7bd89b40 SS |
3879 | /* If the host is halted due to driver unload, we still need to free the |
3880 | * device. | |
3881 | */ | |
cd3f1790 | 3882 | if (ret <= 0 && ret != -ENODEV) |
3ffbba95 | 3883 | return; |
64927730 | 3884 | |
6f5165cf | 3885 | virt_dev = xhci->devs[udev->slot_id]; |
19a7d0d6 FB |
3886 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
3887 | trace_xhci_free_dev(slot_ctx); | |
6f5165cf SS |
3888 | |
3889 | /* Stop any wayward timer functions (which may grab the lock) */ | |
98871e94 | 3890 | for (i = 0; i < 31; i++) { |
9983a5fc | 3891 | virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING; |
6f5165cf SS |
3892 | del_timer_sync(&virt_dev->eps[i].stop_cmd_timer); |
3893 | } | |
44a182b9 | 3894 | virt_dev->udev = NULL; |
11ec7588 | 3895 | ret = xhci_disable_slot(xhci, udev->slot_id); |
8c5a93eb | 3896 | if (ret) |
11ec7588 | 3897 | xhci_free_virt_device(xhci, udev->slot_id); |
f9e609b8 GZ |
3898 | } |
3899 | ||
cd3f1790 | 3900 | int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id) |
f9e609b8 | 3901 | { |
cd3f1790 | 3902 | struct xhci_command *command; |
f9e609b8 GZ |
3903 | unsigned long flags; |
3904 | u32 state; | |
3905 | int ret = 0; | |
f9e609b8 | 3906 | |
103afda0 | 3907 | command = xhci_alloc_command(xhci, false, GFP_KERNEL); |
f9e609b8 GZ |
3908 | if (!command) |
3909 | return -ENOMEM; | |
3910 | ||
9334367c IJ |
3911 | xhci_debugfs_remove_slot(xhci, slot_id); |
3912 | ||
3ffbba95 | 3913 | spin_lock_irqsave(&xhci->lock, flags); |
c526d0d4 | 3914 | /* Don't disable the slot if the host controller is dead. */ |
b0ba9720 | 3915 | state = readl(&xhci->op_regs->status); |
7bd89b40 SS |
3916 | if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) || |
3917 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
c526d0d4 | 3918 | spin_unlock_irqrestore(&xhci->lock, flags); |
ddba5cd0 | 3919 | kfree(command); |
dcabc76f | 3920 | return -ENODEV; |
c526d0d4 SS |
3921 | } |
3922 | ||
f9e609b8 GZ |
3923 | ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT, |
3924 | slot_id); | |
3925 | if (ret) { | |
3ffbba95 | 3926 | spin_unlock_irqrestore(&xhci->lock, flags); |
cd3f1790 | 3927 | kfree(command); |
f9e609b8 | 3928 | return ret; |
3ffbba95 | 3929 | } |
23e3be11 | 3930 | xhci_ring_cmd_db(xhci); |
3ffbba95 | 3931 | spin_unlock_irqrestore(&xhci->lock, flags); |
f9e609b8 | 3932 | return ret; |
3ffbba95 SS |
3933 | } |
3934 | ||
2cf95c18 SS |
3935 | /* |
3936 | * Checks if we have enough host controller resources for the default control | |
3937 | * endpoint. | |
3938 | * | |
3939 | * Must be called with xhci->lock held. | |
3940 | */ | |
3941 | static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci) | |
3942 | { | |
3943 | if (xhci->num_active_eps + 1 > xhci->limit_active_eps) { | |
4bdfe4c3 XR |
3944 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3945 | "Not enough ep ctxs: " | |
3946 | "%u active, need to add 1, limit is %u.", | |
2cf95c18 SS |
3947 | xhci->num_active_eps, xhci->limit_active_eps); |
3948 | return -ENOMEM; | |
3949 | } | |
3950 | xhci->num_active_eps += 1; | |
4bdfe4c3 XR |
3951 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3952 | "Adding 1 ep ctx, %u now active.", | |
2cf95c18 SS |
3953 | xhci->num_active_eps); |
3954 | return 0; | |
3955 | } | |
3956 | ||
3957 | ||
3ffbba95 SS |
3958 | /* |
3959 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command | |
3960 | * timed out, or allocating memory failed. Returns 1 on success. | |
3961 | */ | |
3962 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3963 | { | |
3964 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
19a7d0d6 FB |
3965 | struct xhci_virt_device *vdev; |
3966 | struct xhci_slot_ctx *slot_ctx; | |
3ffbba95 | 3967 | unsigned long flags; |
a00918d0 | 3968 | int ret, slot_id; |
ddba5cd0 MN |
3969 | struct xhci_command *command; |
3970 | ||
103afda0 | 3971 | command = xhci_alloc_command(xhci, true, GFP_KERNEL); |
ddba5cd0 MN |
3972 | if (!command) |
3973 | return 0; | |
3ffbba95 SS |
3974 | |
3975 | spin_lock_irqsave(&xhci->lock, flags); | |
ddba5cd0 | 3976 | ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0); |
3ffbba95 SS |
3977 | if (ret) { |
3978 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3979 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
87e44f2a | 3980 | xhci_free_command(xhci, command); |
3ffbba95 SS |
3981 | return 0; |
3982 | } | |
23e3be11 | 3983 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3984 | spin_unlock_irqrestore(&xhci->lock, flags); |
3985 | ||
c311e391 | 3986 | wait_for_completion(command->completion); |
c2d3d49b | 3987 | slot_id = command->slot_id; |
3ffbba95 | 3988 | |
a00918d0 | 3989 | if (!slot_id || command->status != COMP_SUCCESS) { |
3ffbba95 | 3990 | xhci_err(xhci, "Error while assigning device slot ID\n"); |
be982038 SS |
3991 | xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n", |
3992 | HCS_MAX_SLOTS( | |
3993 | readl(&xhci->cap_regs->hcs_params1))); | |
87e44f2a | 3994 | xhci_free_command(xhci, command); |
3ffbba95 SS |
3995 | return 0; |
3996 | } | |
2cf95c18 | 3997 | |
cd3f1790 LB |
3998 | xhci_free_command(xhci, command); |
3999 | ||
2cf95c18 SS |
4000 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { |
4001 | spin_lock_irqsave(&xhci->lock, flags); | |
4002 | ret = xhci_reserve_host_control_ep_resources(xhci); | |
4003 | if (ret) { | |
4004 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4005 | xhci_warn(xhci, "Not enough host resources, " | |
4006 | "active endpoint contexts = %u\n", | |
4007 | xhci->num_active_eps); | |
4008 | goto disable_slot; | |
4009 | } | |
4010 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4011 | } | |
4012 | /* Use GFP_NOIO, since this function can be called from | |
a6d940dd SS |
4013 | * xhci_discover_or_reset_device(), which may be called as part of |
4014 | * mass storage driver error handling. | |
4015 | */ | |
a00918d0 | 4016 | if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) { |
3ffbba95 | 4017 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); |
2cf95c18 | 4018 | goto disable_slot; |
3ffbba95 | 4019 | } |
19a7d0d6 FB |
4020 | vdev = xhci->devs[slot_id]; |
4021 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
4022 | trace_xhci_alloc_dev(slot_ctx); | |
4023 | ||
a00918d0 | 4024 | udev->slot_id = slot_id; |
c8476fb8 | 4025 | |
02b6fdc2 LB |
4026 | xhci_debugfs_create_slot(xhci, slot_id); |
4027 | ||
c8476fb8 SN |
4028 | #ifndef CONFIG_USB_DEFAULT_PERSIST |
4029 | /* | |
4030 | * If resetting upon resume, we can't put the controller into runtime | |
4031 | * suspend if there is a device attached. | |
4032 | */ | |
4033 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 4034 | pm_runtime_get_noresume(hcd->self.controller); |
c8476fb8 SN |
4035 | #endif |
4036 | ||
3ffbba95 SS |
4037 | /* Is this a LS or FS device under a HS hub? */ |
4038 | /* Hub or peripherial? */ | |
3ffbba95 | 4039 | return 1; |
2cf95c18 SS |
4040 | |
4041 | disable_slot: | |
11ec7588 LB |
4042 | ret = xhci_disable_slot(xhci, udev->slot_id); |
4043 | if (ret) | |
4044 | xhci_free_virt_device(xhci, udev->slot_id); | |
4045 | ||
4046 | return 0; | |
3ffbba95 SS |
4047 | } |
4048 | ||
4049 | /* | |
48fc7dbd DW |
4050 | * Issue an Address Device command and optionally send a corresponding |
4051 | * SetAddress request to the device. | |
3ffbba95 | 4052 | */ |
48fc7dbd DW |
4053 | static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, |
4054 | enum xhci_setup_dev setup) | |
3ffbba95 | 4055 | { |
6f8ffc0b | 4056 | const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address"; |
3ffbba95 | 4057 | unsigned long flags; |
3ffbba95 SS |
4058 | struct xhci_virt_device *virt_dev; |
4059 | int ret = 0; | |
4060 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
d115b048 JY |
4061 | struct xhci_slot_ctx *slot_ctx; |
4062 | struct xhci_input_control_ctx *ctrl_ctx; | |
8e595a5d | 4063 | u64 temp_64; |
a00918d0 CB |
4064 | struct xhci_command *command = NULL; |
4065 | ||
4066 | mutex_lock(&xhci->mutex); | |
3ffbba95 | 4067 | |
90797aee LB |
4068 | if (xhci->xhc_state) { /* dying, removing or halted */ |
4069 | ret = -ESHUTDOWN; | |
448116bf | 4070 | goto out; |
90797aee | 4071 | } |
448116bf | 4072 | |
3ffbba95 | 4073 | if (!udev->slot_id) { |
84a99f6f XR |
4074 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
4075 | "Bad Slot ID %d", udev->slot_id); | |
a00918d0 CB |
4076 | ret = -EINVAL; |
4077 | goto out; | |
3ffbba95 SS |
4078 | } |
4079 | ||
3ffbba95 SS |
4080 | virt_dev = xhci->devs[udev->slot_id]; |
4081 | ||
7ed603ec ME |
4082 | if (WARN_ON(!virt_dev)) { |
4083 | /* | |
4084 | * In plug/unplug torture test with an NEC controller, | |
4085 | * a zero-dereference was observed once due to virt_dev = 0. | |
4086 | * Print useful debug rather than crash if it is observed again! | |
4087 | */ | |
4088 | xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n", | |
4089 | udev->slot_id); | |
a00918d0 CB |
4090 | ret = -EINVAL; |
4091 | goto out; | |
7ed603ec | 4092 | } |
19a7d0d6 FB |
4093 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
4094 | trace_xhci_setup_device_slot(slot_ctx); | |
7ed603ec | 4095 | |
f161ead7 | 4096 | if (setup == SETUP_CONTEXT_ONLY) { |
f161ead7 MN |
4097 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == |
4098 | SLOT_STATE_DEFAULT) { | |
4099 | xhci_dbg(xhci, "Slot already in default state\n"); | |
a00918d0 | 4100 | goto out; |
f161ead7 MN |
4101 | } |
4102 | } | |
4103 | ||
103afda0 | 4104 | command = xhci_alloc_command(xhci, true, GFP_KERNEL); |
a00918d0 CB |
4105 | if (!command) { |
4106 | ret = -ENOMEM; | |
4107 | goto out; | |
4108 | } | |
ddba5cd0 MN |
4109 | |
4110 | command->in_ctx = virt_dev->in_ctx; | |
ddba5cd0 | 4111 | |
f0615c45 | 4112 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
4daf9df5 | 4113 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
92f8e767 SS |
4114 | if (!ctrl_ctx) { |
4115 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
4116 | __func__); | |
a00918d0 CB |
4117 | ret = -EINVAL; |
4118 | goto out; | |
92f8e767 | 4119 | } |
f0615c45 AX |
4120 | /* |
4121 | * If this is the first Set Address since device plug-in or | |
4122 | * virt_device realloaction after a resume with an xHCI power loss, | |
4123 | * then set up the slot context. | |
4124 | */ | |
4125 | if (!slot_ctx->dev_info) | |
3ffbba95 | 4126 | xhci_setup_addressable_virt_dev(xhci, udev); |
f0615c45 | 4127 | /* Otherwise, update the control endpoint ring enqueue pointer. */ |
2d1ee590 SS |
4128 | else |
4129 | xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev); | |
d31c285b SS |
4130 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); |
4131 | ctrl_ctx->drop_flags = 0; | |
4132 | ||
1d27fabe | 4133 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 4134 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 | 4135 | |
90d6d573 | 4136 | trace_xhci_address_ctrl_ctx(ctrl_ctx); |
f88ba78d | 4137 | spin_lock_irqsave(&xhci->lock, flags); |
a711edee | 4138 | trace_xhci_setup_device(virt_dev); |
ddba5cd0 | 4139 | ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma, |
48fc7dbd | 4140 | udev->slot_id, setup); |
3ffbba95 SS |
4141 | if (ret) { |
4142 | spin_unlock_irqrestore(&xhci->lock, flags); | |
84a99f6f XR |
4143 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
4144 | "FIXME: allocate a command ring segment"); | |
a00918d0 | 4145 | goto out; |
3ffbba95 | 4146 | } |
23e3be11 | 4147 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
4148 | spin_unlock_irqrestore(&xhci->lock, flags); |
4149 | ||
4150 | /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */ | |
c311e391 MN |
4151 | wait_for_completion(command->completion); |
4152 | ||
3ffbba95 SS |
4153 | /* FIXME: From section 4.3.4: "Software shall be responsible for timing |
4154 | * the SetAddress() "recovery interval" required by USB and aborting the | |
4155 | * command on a timeout. | |
4156 | */ | |
9ea1833e | 4157 | switch (command->status) { |
0b7c105a | 4158 | case COMP_COMMAND_ABORTED: |
604d02a2 | 4159 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
4160 | xhci_warn(xhci, "Timeout while waiting for setup device command\n"); |
4161 | ret = -ETIME; | |
4162 | break; | |
0b7c105a FB |
4163 | case COMP_CONTEXT_STATE_ERROR: |
4164 | case COMP_SLOT_NOT_ENABLED_ERROR: | |
6f8ffc0b DW |
4165 | xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n", |
4166 | act, udev->slot_id); | |
3ffbba95 SS |
4167 | ret = -EINVAL; |
4168 | break; | |
0b7c105a | 4169 | case COMP_USB_TRANSACTION_ERROR: |
6f8ffc0b | 4170 | dev_warn(&udev->dev, "Device not responding to setup %s.\n", act); |
651aaf36 LB |
4171 | |
4172 | mutex_unlock(&xhci->mutex); | |
4173 | ret = xhci_disable_slot(xhci, udev->slot_id); | |
4174 | if (!ret) | |
4175 | xhci_alloc_dev(hcd, udev); | |
4176 | kfree(command->completion); | |
4177 | kfree(command); | |
4178 | return -EPROTO; | |
0b7c105a | 4179 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
6f8ffc0b DW |
4180 | dev_warn(&udev->dev, |
4181 | "ERROR: Incompatible device for setup %s command\n", act); | |
f6ba6fe2 AH |
4182 | ret = -ENODEV; |
4183 | break; | |
3ffbba95 | 4184 | case COMP_SUCCESS: |
84a99f6f | 4185 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
6f8ffc0b | 4186 | "Successful setup %s command", act); |
3ffbba95 SS |
4187 | break; |
4188 | default: | |
6f8ffc0b DW |
4189 | xhci_err(xhci, |
4190 | "ERROR: unexpected setup %s command completion code 0x%x.\n", | |
9ea1833e | 4191 | act, command->status); |
1d27fabe | 4192 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1); |
3ffbba95 SS |
4193 | ret = -EINVAL; |
4194 | break; | |
4195 | } | |
a00918d0 CB |
4196 | if (ret) |
4197 | goto out; | |
f7b2e403 | 4198 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
84a99f6f XR |
4199 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
4200 | "Op regs DCBAA ptr = %#016llx", temp_64); | |
4201 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
4202 | "Slot ID %d dcbaa entry @%p = %#016llx", | |
4203 | udev->slot_id, | |
4204 | &xhci->dcbaa->dev_context_ptrs[udev->slot_id], | |
4205 | (unsigned long long) | |
4206 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id])); | |
4207 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
4208 | "Output Context DMA address = %#08llx", | |
d115b048 | 4209 | (unsigned long long)virt_dev->out_ctx->dma); |
1d27fabe | 4210 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 4211 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 SS |
4212 | /* |
4213 | * USB core uses address 1 for the roothubs, so we add one to the | |
4214 | * address given back to us by the HC. | |
4215 | */ | |
1d27fabe | 4216 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, |
0c052aab | 4217 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
f94e0186 | 4218 | /* Zero the input context control for later use */ |
d115b048 JY |
4219 | ctrl_ctx->add_flags = 0; |
4220 | ctrl_ctx->drop_flags = 0; | |
4998f1ef JL |
4221 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
4222 | udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); | |
3ffbba95 | 4223 | |
84a99f6f | 4224 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
a2cdc343 DW |
4225 | "Internal device address = %d", |
4226 | le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); | |
a00918d0 CB |
4227 | out: |
4228 | mutex_unlock(&xhci->mutex); | |
87e44f2a LB |
4229 | if (command) { |
4230 | kfree(command->completion); | |
4231 | kfree(command); | |
4232 | } | |
a00918d0 | 4233 | return ret; |
3ffbba95 SS |
4234 | } |
4235 | ||
3969384c | 4236 | static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) |
48fc7dbd DW |
4237 | { |
4238 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS); | |
4239 | } | |
4240 | ||
3969384c | 4241 | static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev) |
48fc7dbd DW |
4242 | { |
4243 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY); | |
4244 | } | |
4245 | ||
3f5eb141 LT |
4246 | /* |
4247 | * Transfer the port index into real index in the HW port status | |
4248 | * registers. Caculate offset between the port's PORTSC register | |
4249 | * and port status base. Divide the number of per port register | |
4250 | * to get the real index. The raw port number bases 1. | |
4251 | */ | |
4252 | int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1) | |
4253 | { | |
38986ffa | 4254 | struct xhci_hub *rhub; |
3f5eb141 | 4255 | |
38986ffa MN |
4256 | rhub = xhci_get_rhub(hcd); |
4257 | return rhub->ports[port1 - 1]->hw_portnum + 1; | |
3f5eb141 LT |
4258 | } |
4259 | ||
a558ccdc MN |
4260 | /* |
4261 | * Issue an Evaluate Context command to change the Maximum Exit Latency in the | |
4262 | * slot context. If that succeeds, store the new MEL in the xhci_virt_device. | |
4263 | */ | |
d5c82feb | 4264 | static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, |
a558ccdc MN |
4265 | struct usb_device *udev, u16 max_exit_latency) |
4266 | { | |
4267 | struct xhci_virt_device *virt_dev; | |
4268 | struct xhci_command *command; | |
4269 | struct xhci_input_control_ctx *ctrl_ctx; | |
4270 | struct xhci_slot_ctx *slot_ctx; | |
4271 | unsigned long flags; | |
4272 | int ret; | |
4273 | ||
4274 | spin_lock_irqsave(&xhci->lock, flags); | |
96044694 MN |
4275 | |
4276 | virt_dev = xhci->devs[udev->slot_id]; | |
4277 | ||
4278 | /* | |
4279 | * virt_dev might not exists yet if xHC resumed from hibernate (S4) and | |
4280 | * xHC was re-initialized. Exit latency will be set later after | |
4281 | * hub_port_finish_reset() is done and xhci->devs[] are re-allocated | |
4282 | */ | |
4283 | ||
4284 | if (!virt_dev || max_exit_latency == virt_dev->current_mel) { | |
a558ccdc MN |
4285 | spin_unlock_irqrestore(&xhci->lock, flags); |
4286 | return 0; | |
4287 | } | |
4288 | ||
4289 | /* Attempt to issue an Evaluate Context command to change the MEL. */ | |
a558ccdc | 4290 | command = xhci->lpm_command; |
4daf9df5 | 4291 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
4292 | if (!ctrl_ctx) { |
4293 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4294 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
4295 | __func__); | |
4296 | return -ENOMEM; | |
4297 | } | |
4298 | ||
a558ccdc MN |
4299 | xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx); |
4300 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4301 | ||
a558ccdc MN |
4302 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
4303 | slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx); | |
4304 | slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT)); | |
4305 | slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency); | |
4801d4ea | 4306 | slot_ctx->dev_state = 0; |
a558ccdc | 4307 | |
3a7fa5be XR |
4308 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
4309 | "Set up evaluate context for LPM MEL change."); | |
a558ccdc MN |
4310 | |
4311 | /* Issue and wait for the evaluate context command. */ | |
4312 | ret = xhci_configure_endpoint(xhci, udev, command, | |
4313 | true, true); | |
a558ccdc MN |
4314 | |
4315 | if (!ret) { | |
4316 | spin_lock_irqsave(&xhci->lock, flags); | |
4317 | virt_dev->current_mel = max_exit_latency; | |
4318 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4319 | } | |
4320 | return ret; | |
4321 | } | |
4322 | ||
ceb6c9c8 | 4323 | #ifdef CONFIG_PM |
9574323c AX |
4324 | |
4325 | /* BESL to HIRD Encoding array for USB2 LPM */ | |
4326 | static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000, | |
4327 | 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000}; | |
4328 | ||
4329 | /* Calculate HIRD/BESL for USB2 PORTPMSC*/ | |
f99298bf AX |
4330 | static int xhci_calculate_hird_besl(struct xhci_hcd *xhci, |
4331 | struct usb_device *udev) | |
9574323c | 4332 | { |
f99298bf AX |
4333 | int u2del, besl, besl_host; |
4334 | int besl_device = 0; | |
4335 | u32 field; | |
4336 | ||
4337 | u2del = HCS_U2_LATENCY(xhci->hcs_params3); | |
4338 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
9574323c | 4339 | |
f99298bf AX |
4340 | if (field & USB_BESL_SUPPORT) { |
4341 | for (besl_host = 0; besl_host < 16; besl_host++) { | |
4342 | if (xhci_besl_encoding[besl_host] >= u2del) | |
9574323c AX |
4343 | break; |
4344 | } | |
f99298bf AX |
4345 | /* Use baseline BESL value as default */ |
4346 | if (field & USB_BESL_BASELINE_VALID) | |
4347 | besl_device = USB_GET_BESL_BASELINE(field); | |
4348 | else if (field & USB_BESL_DEEP_VALID) | |
4349 | besl_device = USB_GET_BESL_DEEP(field); | |
9574323c AX |
4350 | } else { |
4351 | if (u2del <= 50) | |
f99298bf | 4352 | besl_host = 0; |
9574323c | 4353 | else |
f99298bf | 4354 | besl_host = (u2del - 51) / 75 + 1; |
9574323c AX |
4355 | } |
4356 | ||
f99298bf AX |
4357 | besl = besl_host + besl_device; |
4358 | if (besl > 15) | |
4359 | besl = 15; | |
4360 | ||
4361 | return besl; | |
9574323c AX |
4362 | } |
4363 | ||
a558ccdc MN |
4364 | /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */ |
4365 | static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev) | |
4366 | { | |
4367 | u32 field; | |
4368 | int l1; | |
4369 | int besld = 0; | |
4370 | int hirdm = 0; | |
4371 | ||
4372 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
4373 | ||
4374 | /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */ | |
17f34867 | 4375 | l1 = udev->l1_params.timeout / 256; |
a558ccdc MN |
4376 | |
4377 | /* device has preferred BESLD */ | |
4378 | if (field & USB_BESL_DEEP_VALID) { | |
4379 | besld = USB_GET_BESL_DEEP(field); | |
4380 | hirdm = 1; | |
4381 | } | |
4382 | ||
4383 | return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm); | |
4384 | } | |
4385 | ||
3969384c | 4386 | static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
65580b43 AX |
4387 | struct usb_device *udev, int enable) |
4388 | { | |
4389 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
38986ffa | 4390 | struct xhci_port **ports; |
a558ccdc MN |
4391 | __le32 __iomem *pm_addr, *hlpm_addr; |
4392 | u32 pm_val, hlpm_val, field; | |
65580b43 AX |
4393 | unsigned int port_num; |
4394 | unsigned long flags; | |
a558ccdc MN |
4395 | int hird, exit_latency; |
4396 | int ret; | |
65580b43 | 4397 | |
f0c472a6 KHF |
4398 | if (xhci->quirks & XHCI_HW_LPM_DISABLE) |
4399 | return -EPERM; | |
4400 | ||
b50107bb | 4401 | if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support || |
65580b43 AX |
4402 | !udev->lpm_capable) |
4403 | return -EPERM; | |
4404 | ||
4405 | if (!udev->parent || udev->parent->parent || | |
4406 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4407 | return -EPERM; | |
4408 | ||
4409 | if (udev->usb2_hw_lpm_capable != 1) | |
4410 | return -EPERM; | |
4411 | ||
4412 | spin_lock_irqsave(&xhci->lock, flags); | |
4413 | ||
38986ffa | 4414 | ports = xhci->usb2_rhub.ports; |
65580b43 | 4415 | port_num = udev->portnum - 1; |
38986ffa | 4416 | pm_addr = ports[port_num]->addr + PORTPMSC; |
b0ba9720 | 4417 | pm_val = readl(pm_addr); |
38986ffa | 4418 | hlpm_addr = ports[port_num]->addr + PORTHLPMC; |
65580b43 AX |
4419 | |
4420 | xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n", | |
654a55d3 | 4421 | enable ? "enable" : "disable", port_num + 1); |
65580b43 | 4422 | |
f0c472a6 | 4423 | if (enable) { |
a558ccdc MN |
4424 | /* Host supports BESL timeout instead of HIRD */ |
4425 | if (udev->usb2_hw_lpm_besl_capable) { | |
4426 | /* if device doesn't have a preferred BESL value use a | |
4427 | * default one which works with mixed HIRD and BESL | |
4428 | * systems. See XHCI_DEFAULT_BESL definition in xhci.h | |
4429 | */ | |
7aa1bb2f | 4430 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); |
a558ccdc MN |
4431 | if ((field & USB_BESL_SUPPORT) && |
4432 | (field & USB_BESL_BASELINE_VALID)) | |
4433 | hird = USB_GET_BESL_BASELINE(field); | |
4434 | else | |
17f34867 | 4435 | hird = udev->l1_params.besl; |
a558ccdc MN |
4436 | |
4437 | exit_latency = xhci_besl_encoding[hird]; | |
4438 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4439 | ||
4440 | /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx | |
4441 | * input context for link powermanagement evaluate | |
4442 | * context commands. It is protected by hcd->bandwidth | |
4443 | * mutex and is shared by all devices. We need to set | |
4444 | * the max ext latency in USB 2 BESL LPM as well, so | |
4445 | * use the same mutex and xhci_change_max_exit_latency() | |
4446 | */ | |
4447 | mutex_lock(hcd->bandwidth_mutex); | |
4448 | ret = xhci_change_max_exit_latency(xhci, udev, | |
4449 | exit_latency); | |
4450 | mutex_unlock(hcd->bandwidth_mutex); | |
4451 | ||
4452 | if (ret < 0) | |
4453 | return ret; | |
4454 | spin_lock_irqsave(&xhci->lock, flags); | |
4455 | ||
4456 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); | |
204b7793 | 4457 | writel(hlpm_val, hlpm_addr); |
a558ccdc | 4458 | /* flush write */ |
b0ba9720 | 4459 | readl(hlpm_addr); |
a558ccdc MN |
4460 | } else { |
4461 | hird = xhci_calculate_hird_besl(xhci, udev); | |
4462 | } | |
4463 | ||
4464 | pm_val &= ~PORT_HIRD_MASK; | |
58e21f73 | 4465 | pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id); |
204b7793 | 4466 | writel(pm_val, pm_addr); |
b0ba9720 | 4467 | pm_val = readl(pm_addr); |
a558ccdc | 4468 | pm_val |= PORT_HLE; |
204b7793 | 4469 | writel(pm_val, pm_addr); |
a558ccdc | 4470 | /* flush write */ |
b0ba9720 | 4471 | readl(pm_addr); |
65580b43 | 4472 | } else { |
58e21f73 | 4473 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK); |
204b7793 | 4474 | writel(pm_val, pm_addr); |
a558ccdc | 4475 | /* flush write */ |
b0ba9720 | 4476 | readl(pm_addr); |
a558ccdc MN |
4477 | if (udev->usb2_hw_lpm_besl_capable) { |
4478 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4479 | mutex_lock(hcd->bandwidth_mutex); | |
4480 | xhci_change_max_exit_latency(xhci, udev, 0); | |
4481 | mutex_unlock(hcd->bandwidth_mutex); | |
b3d71abd KHF |
4482 | readl_poll_timeout(ports[port_num]->addr, pm_val, |
4483 | (pm_val & PORT_PLS_MASK) == XDEV_U0, | |
4484 | 100, 10000); | |
a558ccdc MN |
4485 | return 0; |
4486 | } | |
65580b43 AX |
4487 | } |
4488 | ||
4489 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4490 | return 0; | |
4491 | } | |
4492 | ||
b630d4b9 MN |
4493 | /* check if a usb2 port supports a given extened capability protocol |
4494 | * only USB2 ports extended protocol capability values are cached. | |
4495 | * Return 1 if capability is supported | |
4496 | */ | |
4497 | static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port, | |
4498 | unsigned capability) | |
4499 | { | |
4500 | u32 port_offset, port_count; | |
4501 | int i; | |
4502 | ||
4503 | for (i = 0; i < xhci->num_ext_caps; i++) { | |
4504 | if (xhci->ext_caps[i] & capability) { | |
4505 | /* port offsets starts at 1 */ | |
4506 | port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1; | |
4507 | port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]); | |
4508 | if (port >= port_offset && | |
4509 | port < port_offset + port_count) | |
4510 | return 1; | |
4511 | } | |
4512 | } | |
4513 | return 0; | |
4514 | } | |
4515 | ||
3969384c | 4516 | static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
b01bcbf7 SS |
4517 | { |
4518 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
b630d4b9 | 4519 | int portnum = udev->portnum - 1; |
b01bcbf7 | 4520 | |
f1fd62a6 | 4521 | if (hcd->speed >= HCD_USB3 || !udev->lpm_capable) |
de68bab4 SS |
4522 | return 0; |
4523 | ||
4524 | /* we only support lpm for non-hub device connected to root hub yet */ | |
4525 | if (!udev->parent || udev->parent->parent || | |
4526 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4527 | return 0; | |
4528 | ||
4529 | if (xhci->hw_lpm_support == 1 && | |
4530 | xhci_check_usb2_port_capability( | |
4531 | xhci, portnum, XHCI_HLC)) { | |
4532 | udev->usb2_hw_lpm_capable = 1; | |
4533 | udev->l1_params.timeout = XHCI_L1_TIMEOUT; | |
4534 | udev->l1_params.besl = XHCI_DEFAULT_BESL; | |
4535 | if (xhci_check_usb2_port_capability(xhci, portnum, | |
4536 | XHCI_BLC)) | |
4537 | udev->usb2_hw_lpm_besl_capable = 1; | |
b01bcbf7 SS |
4538 | } |
4539 | ||
4540 | return 0; | |
4541 | } | |
4542 | ||
3b3db026 SS |
4543 | /*---------------------- USB 3.0 Link PM functions ------------------------*/ |
4544 | ||
e3567d2c SS |
4545 | /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */ |
4546 | static unsigned long long xhci_service_interval_to_ns( | |
4547 | struct usb_endpoint_descriptor *desc) | |
4548 | { | |
16b45fdf | 4549 | return (1ULL << (desc->bInterval - 1)) * 125 * 1000; |
e3567d2c SS |
4550 | } |
4551 | ||
3b3db026 SS |
4552 | static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev, |
4553 | enum usb3_link_state state) | |
4554 | { | |
4555 | unsigned long long sel; | |
4556 | unsigned long long pel; | |
4557 | unsigned int max_sel_pel; | |
4558 | char *state_name; | |
4559 | ||
4560 | switch (state) { | |
4561 | case USB3_LPM_U1: | |
4562 | /* Convert SEL and PEL stored in nanoseconds to microseconds */ | |
4563 | sel = DIV_ROUND_UP(udev->u1_params.sel, 1000); | |
4564 | pel = DIV_ROUND_UP(udev->u1_params.pel, 1000); | |
4565 | max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL; | |
4566 | state_name = "U1"; | |
4567 | break; | |
4568 | case USB3_LPM_U2: | |
4569 | sel = DIV_ROUND_UP(udev->u2_params.sel, 1000); | |
4570 | pel = DIV_ROUND_UP(udev->u2_params.pel, 1000); | |
4571 | max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL; | |
4572 | state_name = "U2"; | |
4573 | break; | |
4574 | default: | |
4575 | dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n", | |
4576 | __func__); | |
e25e62ae | 4577 | return USB3_LPM_DISABLED; |
3b3db026 SS |
4578 | } |
4579 | ||
4580 | if (sel <= max_sel_pel && pel <= max_sel_pel) | |
4581 | return USB3_LPM_DEVICE_INITIATED; | |
4582 | ||
4583 | if (sel > max_sel_pel) | |
4584 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
4585 | "due to long SEL %llu ms\n", | |
4586 | state_name, sel); | |
4587 | else | |
4588 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
03e64e96 | 4589 | "due to long PEL %llu ms\n", |
3b3db026 SS |
4590 | state_name, pel); |
4591 | return USB3_LPM_DISABLED; | |
4592 | } | |
4593 | ||
9502c46c | 4594 | /* The U1 timeout should be the maximum of the following values: |
e3567d2c SS |
4595 | * - For control endpoints, U1 system exit latency (SEL) * 3 |
4596 | * - For bulk endpoints, U1 SEL * 5 | |
4597 | * - For interrupt endpoints: | |
4598 | * - Notification EPs, U1 SEL * 3 | |
4599 | * - Periodic EPs, max(105% of bInterval, U1 SEL * 2) | |
4600 | * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2) | |
4601 | */ | |
9502c46c PA |
4602 | static unsigned long long xhci_calculate_intel_u1_timeout( |
4603 | struct usb_device *udev, | |
e3567d2c SS |
4604 | struct usb_endpoint_descriptor *desc) |
4605 | { | |
4606 | unsigned long long timeout_ns; | |
4607 | int ep_type; | |
4608 | int intr_type; | |
4609 | ||
4610 | ep_type = usb_endpoint_type(desc); | |
4611 | switch (ep_type) { | |
4612 | case USB_ENDPOINT_XFER_CONTROL: | |
4613 | timeout_ns = udev->u1_params.sel * 3; | |
4614 | break; | |
4615 | case USB_ENDPOINT_XFER_BULK: | |
4616 | timeout_ns = udev->u1_params.sel * 5; | |
4617 | break; | |
4618 | case USB_ENDPOINT_XFER_INT: | |
4619 | intr_type = usb_endpoint_interrupt_type(desc); | |
4620 | if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) { | |
4621 | timeout_ns = udev->u1_params.sel * 3; | |
4622 | break; | |
4623 | } | |
4624 | /* Otherwise the calculation is the same as isoc eps */ | |
df561f66 | 4625 | fallthrough; |
e3567d2c SS |
4626 | case USB_ENDPOINT_XFER_ISOC: |
4627 | timeout_ns = xhci_service_interval_to_ns(desc); | |
c88db160 | 4628 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100); |
e3567d2c SS |
4629 | if (timeout_ns < udev->u1_params.sel * 2) |
4630 | timeout_ns = udev->u1_params.sel * 2; | |
4631 | break; | |
4632 | default: | |
4633 | return 0; | |
4634 | } | |
4635 | ||
9502c46c PA |
4636 | return timeout_ns; |
4637 | } | |
4638 | ||
4639 | /* Returns the hub-encoded U1 timeout value. */ | |
4640 | static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci, | |
4641 | struct usb_device *udev, | |
4642 | struct usb_endpoint_descriptor *desc) | |
4643 | { | |
4644 | unsigned long long timeout_ns; | |
4645 | ||
0472bf06 MN |
4646 | /* Prevent U1 if service interval is shorter than U1 exit latency */ |
4647 | if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) { | |
4648 | if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) { | |
4649 | dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n"); | |
4650 | return USB3_LPM_DISABLED; | |
4651 | } | |
4652 | } | |
4653 | ||
9502c46c PA |
4654 | if (xhci->quirks & XHCI_INTEL_HOST) |
4655 | timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc); | |
4656 | else | |
4657 | timeout_ns = udev->u1_params.sel; | |
4658 | ||
4659 | /* The U1 timeout is encoded in 1us intervals. | |
4660 | * Don't return a timeout of zero, because that's USB3_LPM_DISABLED. | |
4661 | */ | |
e3567d2c | 4662 | if (timeout_ns == USB3_LPM_DISABLED) |
9502c46c PA |
4663 | timeout_ns = 1; |
4664 | else | |
4665 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000); | |
e3567d2c SS |
4666 | |
4667 | /* If the necessary timeout value is bigger than what we can set in the | |
4668 | * USB 3.0 hub, we have to disable hub-initiated U1. | |
4669 | */ | |
4670 | if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT) | |
4671 | return timeout_ns; | |
4672 | dev_dbg(&udev->dev, "Hub-initiated U1 disabled " | |
4673 | "due to long timeout %llu ms\n", timeout_ns); | |
4674 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1); | |
4675 | } | |
4676 | ||
9502c46c | 4677 | /* The U2 timeout should be the maximum of: |
e3567d2c SS |
4678 | * - 10 ms (to avoid the bandwidth impact on the scheduler) |
4679 | * - largest bInterval of any active periodic endpoint (to avoid going | |
4680 | * into lower power link states between intervals). | |
4681 | * - the U2 Exit Latency of the device | |
4682 | */ | |
9502c46c PA |
4683 | static unsigned long long xhci_calculate_intel_u2_timeout( |
4684 | struct usb_device *udev, | |
e3567d2c SS |
4685 | struct usb_endpoint_descriptor *desc) |
4686 | { | |
4687 | unsigned long long timeout_ns; | |
4688 | unsigned long long u2_del_ns; | |
4689 | ||
4690 | timeout_ns = 10 * 1000 * 1000; | |
4691 | ||
4692 | if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) && | |
4693 | (xhci_service_interval_to_ns(desc) > timeout_ns)) | |
4694 | timeout_ns = xhci_service_interval_to_ns(desc); | |
4695 | ||
966e7a85 | 4696 | u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL; |
e3567d2c SS |
4697 | if (u2_del_ns > timeout_ns) |
4698 | timeout_ns = u2_del_ns; | |
4699 | ||
9502c46c PA |
4700 | return timeout_ns; |
4701 | } | |
4702 | ||
4703 | /* Returns the hub-encoded U2 timeout value. */ | |
4704 | static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci, | |
4705 | struct usb_device *udev, | |
4706 | struct usb_endpoint_descriptor *desc) | |
4707 | { | |
4708 | unsigned long long timeout_ns; | |
4709 | ||
0472bf06 MN |
4710 | /* Prevent U2 if service interval is shorter than U2 exit latency */ |
4711 | if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) { | |
4712 | if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) { | |
4713 | dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n"); | |
4714 | return USB3_LPM_DISABLED; | |
4715 | } | |
4716 | } | |
4717 | ||
9502c46c PA |
4718 | if (xhci->quirks & XHCI_INTEL_HOST) |
4719 | timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc); | |
4720 | else | |
4721 | timeout_ns = udev->u2_params.sel; | |
4722 | ||
e3567d2c | 4723 | /* The U2 timeout is encoded in 256us intervals */ |
c88db160 | 4724 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000); |
e3567d2c SS |
4725 | /* If the necessary timeout value is bigger than what we can set in the |
4726 | * USB 3.0 hub, we have to disable hub-initiated U2. | |
4727 | */ | |
4728 | if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT) | |
4729 | return timeout_ns; | |
4730 | dev_dbg(&udev->dev, "Hub-initiated U2 disabled " | |
4731 | "due to long timeout %llu ms\n", timeout_ns); | |
4732 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2); | |
4733 | } | |
4734 | ||
3b3db026 SS |
4735 | static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci, |
4736 | struct usb_device *udev, | |
4737 | struct usb_endpoint_descriptor *desc, | |
4738 | enum usb3_link_state state, | |
4739 | u16 *timeout) | |
4740 | { | |
9502c46c PA |
4741 | if (state == USB3_LPM_U1) |
4742 | return xhci_calculate_u1_timeout(xhci, udev, desc); | |
4743 | else if (state == USB3_LPM_U2) | |
4744 | return xhci_calculate_u2_timeout(xhci, udev, desc); | |
e3567d2c | 4745 | |
3b3db026 SS |
4746 | return USB3_LPM_DISABLED; |
4747 | } | |
4748 | ||
4749 | static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci, | |
4750 | struct usb_device *udev, | |
4751 | struct usb_endpoint_descriptor *desc, | |
4752 | enum usb3_link_state state, | |
4753 | u16 *timeout) | |
4754 | { | |
4755 | u16 alt_timeout; | |
4756 | ||
4757 | alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev, | |
4758 | desc, state, timeout); | |
4759 | ||
d500c63f | 4760 | /* If we found we can't enable hub-initiated LPM, and |
3b3db026 | 4761 | * the U1 or U2 exit latency was too high to allow |
d500c63f JS |
4762 | * device-initiated LPM as well, then we will disable LPM |
4763 | * for this device, so stop searching any further. | |
3b3db026 | 4764 | */ |
d500c63f | 4765 | if (alt_timeout == USB3_LPM_DISABLED) { |
3b3db026 SS |
4766 | *timeout = alt_timeout; |
4767 | return -E2BIG; | |
4768 | } | |
4769 | if (alt_timeout > *timeout) | |
4770 | *timeout = alt_timeout; | |
4771 | return 0; | |
4772 | } | |
4773 | ||
4774 | static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci, | |
4775 | struct usb_device *udev, | |
4776 | struct usb_host_interface *alt, | |
4777 | enum usb3_link_state state, | |
4778 | u16 *timeout) | |
4779 | { | |
4780 | int j; | |
4781 | ||
4782 | for (j = 0; j < alt->desc.bNumEndpoints; j++) { | |
4783 | if (xhci_update_timeout_for_endpoint(xhci, udev, | |
4784 | &alt->endpoint[j].desc, state, timeout)) | |
4785 | return -E2BIG; | |
4786 | continue; | |
4787 | } | |
4788 | return 0; | |
4789 | } | |
4790 | ||
e3567d2c SS |
4791 | static int xhci_check_intel_tier_policy(struct usb_device *udev, |
4792 | enum usb3_link_state state) | |
4793 | { | |
4794 | struct usb_device *parent; | |
4795 | unsigned int num_hubs; | |
4796 | ||
4797 | if (state == USB3_LPM_U2) | |
4798 | return 0; | |
4799 | ||
4800 | /* Don't enable U1 if the device is on a 2nd tier hub or lower. */ | |
4801 | for (parent = udev->parent, num_hubs = 0; parent->parent; | |
4802 | parent = parent->parent) | |
4803 | num_hubs++; | |
4804 | ||
4805 | if (num_hubs < 2) | |
4806 | return 0; | |
4807 | ||
4808 | dev_dbg(&udev->dev, "Disabling U1 link state for device" | |
4809 | " below second-tier hub.\n"); | |
4810 | dev_dbg(&udev->dev, "Plug device into first-tier hub " | |
4811 | "to decrease power consumption.\n"); | |
4812 | return -E2BIG; | |
4813 | } | |
4814 | ||
3b3db026 SS |
4815 | static int xhci_check_tier_policy(struct xhci_hcd *xhci, |
4816 | struct usb_device *udev, | |
4817 | enum usb3_link_state state) | |
4818 | { | |
e3567d2c SS |
4819 | if (xhci->quirks & XHCI_INTEL_HOST) |
4820 | return xhci_check_intel_tier_policy(udev, state); | |
9502c46c PA |
4821 | else |
4822 | return 0; | |
3b3db026 SS |
4823 | } |
4824 | ||
4825 | /* Returns the U1 or U2 timeout that should be enabled. | |
4826 | * If the tier check or timeout setting functions return with a non-zero exit | |
4827 | * code, that means the timeout value has been finalized and we shouldn't look | |
4828 | * at any more endpoints. | |
4829 | */ | |
4830 | static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd, | |
4831 | struct usb_device *udev, enum usb3_link_state state) | |
4832 | { | |
4833 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4834 | struct usb_host_config *config; | |
4835 | char *state_name; | |
4836 | int i; | |
4837 | u16 timeout = USB3_LPM_DISABLED; | |
4838 | ||
4839 | if (state == USB3_LPM_U1) | |
4840 | state_name = "U1"; | |
4841 | else if (state == USB3_LPM_U2) | |
4842 | state_name = "U2"; | |
4843 | else { | |
4844 | dev_warn(&udev->dev, "Can't enable unknown link state %i\n", | |
4845 | state); | |
4846 | return timeout; | |
4847 | } | |
4848 | ||
4849 | if (xhci_check_tier_policy(xhci, udev, state) < 0) | |
4850 | return timeout; | |
4851 | ||
4852 | /* Gather some information about the currently installed configuration | |
4853 | * and alternate interface settings. | |
4854 | */ | |
4855 | if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc, | |
4856 | state, &timeout)) | |
4857 | return timeout; | |
4858 | ||
4859 | config = udev->actconfig; | |
4860 | if (!config) | |
4861 | return timeout; | |
4862 | ||
64ba419b | 4863 | for (i = 0; i < config->desc.bNumInterfaces; i++) { |
3b3db026 SS |
4864 | struct usb_driver *driver; |
4865 | struct usb_interface *intf = config->interface[i]; | |
4866 | ||
4867 | if (!intf) | |
4868 | continue; | |
4869 | ||
4870 | /* Check if any currently bound drivers want hub-initiated LPM | |
4871 | * disabled. | |
4872 | */ | |
4873 | if (intf->dev.driver) { | |
4874 | driver = to_usb_driver(intf->dev.driver); | |
4875 | if (driver && driver->disable_hub_initiated_lpm) { | |
cd9d9491 MN |
4876 | dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n", |
4877 | state_name, driver->name); | |
4878 | timeout = xhci_get_timeout_no_hub_lpm(udev, | |
4879 | state); | |
4880 | if (timeout == USB3_LPM_DISABLED) | |
4881 | return timeout; | |
3b3db026 SS |
4882 | } |
4883 | } | |
4884 | ||
4885 | /* Not sure how this could happen... */ | |
4886 | if (!intf->cur_altsetting) | |
4887 | continue; | |
4888 | ||
4889 | if (xhci_update_timeout_for_interface(xhci, udev, | |
4890 | intf->cur_altsetting, | |
4891 | state, &timeout)) | |
4892 | return timeout; | |
4893 | } | |
4894 | return timeout; | |
4895 | } | |
4896 | ||
3b3db026 SS |
4897 | static int calculate_max_exit_latency(struct usb_device *udev, |
4898 | enum usb3_link_state state_changed, | |
4899 | u16 hub_encoded_timeout) | |
4900 | { | |
4901 | unsigned long long u1_mel_us = 0; | |
4902 | unsigned long long u2_mel_us = 0; | |
4903 | unsigned long long mel_us = 0; | |
4904 | bool disabling_u1; | |
4905 | bool disabling_u2; | |
4906 | bool enabling_u1; | |
4907 | bool enabling_u2; | |
4908 | ||
4909 | disabling_u1 = (state_changed == USB3_LPM_U1 && | |
4910 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4911 | disabling_u2 = (state_changed == USB3_LPM_U2 && | |
4912 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4913 | ||
4914 | enabling_u1 = (state_changed == USB3_LPM_U1 && | |
4915 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4916 | enabling_u2 = (state_changed == USB3_LPM_U2 && | |
4917 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4918 | ||
4919 | /* If U1 was already enabled and we're not disabling it, | |
4920 | * or we're going to enable U1, account for the U1 max exit latency. | |
4921 | */ | |
4922 | if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) || | |
4923 | enabling_u1) | |
4924 | u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000); | |
4925 | if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) || | |
4926 | enabling_u2) | |
4927 | u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000); | |
4928 | ||
4929 | if (u1_mel_us > u2_mel_us) | |
4930 | mel_us = u1_mel_us; | |
4931 | else | |
4932 | mel_us = u2_mel_us; | |
4933 | /* xHCI host controller max exit latency field is only 16 bits wide. */ | |
4934 | if (mel_us > MAX_EXIT) { | |
4935 | dev_warn(&udev->dev, "Link PM max exit latency of %lluus " | |
4936 | "is too big.\n", mel_us); | |
4937 | return -E2BIG; | |
4938 | } | |
4939 | return mel_us; | |
4940 | } | |
4941 | ||
4942 | /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */ | |
3969384c | 4943 | static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
3b3db026 SS |
4944 | struct usb_device *udev, enum usb3_link_state state) |
4945 | { | |
4946 | struct xhci_hcd *xhci; | |
4947 | u16 hub_encoded_timeout; | |
4948 | int mel; | |
4949 | int ret; | |
4950 | ||
4951 | xhci = hcd_to_xhci(hcd); | |
4952 | /* The LPM timeout values are pretty host-controller specific, so don't | |
4953 | * enable hub-initiated timeouts unless the vendor has provided | |
4954 | * information about their timeout algorithm. | |
4955 | */ | |
4956 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4957 | !xhci->devs[udev->slot_id]) | |
4958 | return USB3_LPM_DISABLED; | |
4959 | ||
4960 | hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state); | |
4961 | mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout); | |
4962 | if (mel < 0) { | |
4963 | /* Max Exit Latency is too big, disable LPM. */ | |
4964 | hub_encoded_timeout = USB3_LPM_DISABLED; | |
4965 | mel = 0; | |
4966 | } | |
4967 | ||
4968 | ret = xhci_change_max_exit_latency(xhci, udev, mel); | |
4969 | if (ret) | |
4970 | return ret; | |
4971 | return hub_encoded_timeout; | |
4972 | } | |
4973 | ||
3969384c | 4974 | static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, |
3b3db026 SS |
4975 | struct usb_device *udev, enum usb3_link_state state) |
4976 | { | |
4977 | struct xhci_hcd *xhci; | |
4978 | u16 mel; | |
3b3db026 SS |
4979 | |
4980 | xhci = hcd_to_xhci(hcd); | |
4981 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4982 | !xhci->devs[udev->slot_id]) | |
4983 | return 0; | |
4984 | ||
4985 | mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED); | |
f1cda54c | 4986 | return xhci_change_max_exit_latency(xhci, udev, mel); |
3b3db026 | 4987 | } |
b01bcbf7 | 4988 | #else /* CONFIG_PM */ |
9574323c | 4989 | |
3969384c | 4990 | static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
ceb6c9c8 RW |
4991 | struct usb_device *udev, int enable) |
4992 | { | |
4993 | return 0; | |
4994 | } | |
4995 | ||
3969384c | 4996 | static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
ceb6c9c8 RW |
4997 | { |
4998 | return 0; | |
4999 | } | |
5000 | ||
3969384c | 5001 | static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
b01bcbf7 | 5002 | struct usb_device *udev, enum usb3_link_state state) |
65580b43 | 5003 | { |
b01bcbf7 | 5004 | return USB3_LPM_DISABLED; |
65580b43 AX |
5005 | } |
5006 | ||
3969384c | 5007 | static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, |
b01bcbf7 | 5008 | struct usb_device *udev, enum usb3_link_state state) |
9574323c AX |
5009 | { |
5010 | return 0; | |
5011 | } | |
b01bcbf7 | 5012 | #endif /* CONFIG_PM */ |
9574323c | 5013 | |
b01bcbf7 | 5014 | /*-------------------------------------------------------------------------*/ |
9574323c | 5015 | |
ac1c1b7f SS |
5016 | /* Once a hub descriptor is fetched for a device, we need to update the xHC's |
5017 | * internal data structures for the device. | |
5018 | */ | |
3969384c | 5019 | static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, |
ac1c1b7f SS |
5020 | struct usb_tt *tt, gfp_t mem_flags) |
5021 | { | |
5022 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
5023 | struct xhci_virt_device *vdev; | |
5024 | struct xhci_command *config_cmd; | |
5025 | struct xhci_input_control_ctx *ctrl_ctx; | |
5026 | struct xhci_slot_ctx *slot_ctx; | |
5027 | unsigned long flags; | |
5028 | unsigned think_time; | |
5029 | int ret; | |
5030 | ||
5031 | /* Ignore root hubs */ | |
5032 | if (!hdev->parent) | |
5033 | return 0; | |
5034 | ||
5035 | vdev = xhci->devs[hdev->slot_id]; | |
5036 | if (!vdev) { | |
5037 | xhci_warn(xhci, "Cannot update hub desc for unknown device.\n"); | |
5038 | return -EINVAL; | |
5039 | } | |
74e0b564 | 5040 | |
14d49b7a | 5041 | config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags); |
74e0b564 | 5042 | if (!config_cmd) |
ac1c1b7f | 5043 | return -ENOMEM; |
74e0b564 | 5044 | |
4daf9df5 | 5045 | ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx); |
92f8e767 SS |
5046 | if (!ctrl_ctx) { |
5047 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
5048 | __func__); | |
5049 | xhci_free_command(xhci, config_cmd); | |
5050 | return -ENOMEM; | |
5051 | } | |
ac1c1b7f SS |
5052 | |
5053 | spin_lock_irqsave(&xhci->lock, flags); | |
839c817c SS |
5054 | if (hdev->speed == USB_SPEED_HIGH && |
5055 | xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) { | |
5056 | xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n"); | |
5057 | xhci_free_command(xhci, config_cmd); | |
5058 | spin_unlock_irqrestore(&xhci->lock, flags); | |
5059 | return -ENOMEM; | |
5060 | } | |
5061 | ||
ac1c1b7f | 5062 | xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx); |
28ccd296 | 5063 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
ac1c1b7f | 5064 | slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx); |
28ccd296 | 5065 | slot_ctx->dev_info |= cpu_to_le32(DEV_HUB); |
096b110a CY |
5066 | /* |
5067 | * refer to section 6.2.2: MTT should be 0 for full speed hub, | |
5068 | * but it may be already set to 1 when setup an xHCI virtual | |
5069 | * device, so clear it anyway. | |
5070 | */ | |
ac1c1b7f | 5071 | if (tt->multi) |
28ccd296 | 5072 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
096b110a CY |
5073 | else if (hdev->speed == USB_SPEED_FULL) |
5074 | slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT); | |
5075 | ||
ac1c1b7f SS |
5076 | if (xhci->hci_version > 0x95) { |
5077 | xhci_dbg(xhci, "xHCI version %x needs hub " | |
5078 | "TT think time and number of ports\n", | |
5079 | (unsigned int) xhci->hci_version); | |
28ccd296 | 5080 | slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild)); |
ac1c1b7f SS |
5081 | /* Set TT think time - convert from ns to FS bit times. |
5082 | * 0 = 8 FS bit times, 1 = 16 FS bit times, | |
5083 | * 2 = 24 FS bit times, 3 = 32 FS bit times. | |
700b4173 AX |
5084 | * |
5085 | * xHCI 1.0: this field shall be 0 if the device is not a | |
5086 | * High-spped hub. | |
ac1c1b7f SS |
5087 | */ |
5088 | think_time = tt->think_time; | |
5089 | if (think_time != 0) | |
5090 | think_time = (think_time / 666) - 1; | |
700b4173 AX |
5091 | if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH) |
5092 | slot_ctx->tt_info |= | |
5093 | cpu_to_le32(TT_THINK_TIME(think_time)); | |
ac1c1b7f SS |
5094 | } else { |
5095 | xhci_dbg(xhci, "xHCI version %x doesn't need hub " | |
5096 | "TT think time or number of ports\n", | |
5097 | (unsigned int) xhci->hci_version); | |
5098 | } | |
5099 | slot_ctx->dev_state = 0; | |
5100 | spin_unlock_irqrestore(&xhci->lock, flags); | |
5101 | ||
5102 | xhci_dbg(xhci, "Set up %s for hub device.\n", | |
5103 | (xhci->hci_version > 0x95) ? | |
5104 | "configure endpoint" : "evaluate context"); | |
ac1c1b7f SS |
5105 | |
5106 | /* Issue and wait for the configure endpoint or | |
5107 | * evaluate context command. | |
5108 | */ | |
5109 | if (xhci->hci_version > 0x95) | |
5110 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
5111 | false, false); | |
5112 | else | |
5113 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
5114 | true, false); | |
5115 | ||
ac1c1b7f SS |
5116 | xhci_free_command(xhci, config_cmd); |
5117 | return ret; | |
5118 | } | |
5119 | ||
3969384c | 5120 | static int xhci_get_frame(struct usb_hcd *hcd) |
66d4eadd SS |
5121 | { |
5122 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
5123 | /* EHCI mods by the periodic size. Why? */ | |
b0ba9720 | 5124 | return readl(&xhci->run_regs->microframe_index) >> 3; |
66d4eadd SS |
5125 | } |
5126 | ||
552e0c4f SAS |
5127 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) |
5128 | { | |
5129 | struct xhci_hcd *xhci; | |
4c39d4b9 AB |
5130 | /* |
5131 | * TODO: Check with DWC3 clients for sysdev according to | |
5132 | * quirks | |
5133 | */ | |
5134 | struct device *dev = hcd->self.sysdev; | |
0ee78c10 | 5135 | unsigned int minor_rev; |
552e0c4f | 5136 | int retval; |
552e0c4f | 5137 | |
1386ff75 SS |
5138 | /* Accept arbitrarily long scatter-gather lists */ |
5139 | hcd->self.sg_tablesize = ~0; | |
fc76051c | 5140 | |
e2ed5114 MN |
5141 | /* support to build packet from discontinuous buffers */ |
5142 | hcd->self.no_sg_constraint = 1; | |
5143 | ||
19181bc5 HG |
5144 | /* XHCI controllers don't stop the ep queue on short packets :| */ |
5145 | hcd->self.no_stop_on_short = 1; | |
552e0c4f | 5146 | |
b50107bb MN |
5147 | xhci = hcd_to_xhci(hcd); |
5148 | ||
552e0c4f | 5149 | if (usb_hcd_is_primary_hcd(hcd)) { |
552e0c4f | 5150 | xhci->main_hcd = hcd; |
9ea95ecc | 5151 | xhci->usb2_rhub.hcd = hcd; |
552e0c4f SAS |
5152 | /* Mark the first roothub as being USB 2.0. |
5153 | * The xHCI driver will register the USB 3.0 roothub. | |
5154 | */ | |
5155 | hcd->speed = HCD_USB2; | |
5156 | hcd->self.root_hub->speed = USB_SPEED_HIGH; | |
5157 | /* | |
5158 | * USB 2.0 roothub under xHCI has an integrated TT, | |
5159 | * (rate matching hub) as opposed to having an OHCI/UHCI | |
5160 | * companion controller. | |
5161 | */ | |
5162 | hcd->has_tt = 1; | |
5163 | } else { | |
0ee78c10 | 5164 | /* |
47f50d61 MN |
5165 | * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts |
5166 | * should return 0x31 for sbrn, or that the minor revision | |
5167 | * is a two digit BCD containig minor and sub-minor numbers. | |
5168 | * This was later clarified in xHCI 1.2. | |
5169 | * | |
5170 | * Some USB 3.1 capable hosts therefore have sbrn 0x30, and | |
5171 | * minor revision set to 0x1 instead of 0x10. | |
0ee78c10 | 5172 | */ |
47f50d61 MN |
5173 | if (xhci->usb3_rhub.min_rev == 0x1) |
5174 | minor_rev = 1; | |
5175 | else | |
5176 | minor_rev = xhci->usb3_rhub.min_rev / 0x10; | |
ddd57980 MN |
5177 | |
5178 | switch (minor_rev) { | |
5179 | case 2: | |
5180 | hcd->speed = HCD_USB32; | |
5181 | hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS; | |
5182 | hcd->self.root_hub->rx_lanes = 2; | |
5183 | hcd->self.root_hub->tx_lanes = 2; | |
5184 | break; | |
5185 | case 1: | |
b50107bb | 5186 | hcd->speed = HCD_USB31; |
2c0e06f8 | 5187 | hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS; |
ddd57980 | 5188 | break; |
b50107bb | 5189 | } |
ddd57980 | 5190 | xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n", |
0ee78c10 | 5191 | minor_rev, |
ddd57980 | 5192 | minor_rev ? "Enhanced " : ""); |
0ee78c10 | 5193 | |
9ea95ecc | 5194 | xhci->usb3_rhub.hcd = hcd; |
552e0c4f SAS |
5195 | /* xHCI private pointer was set in xhci_pci_probe for the second |
5196 | * registered roothub. | |
5197 | */ | |
552e0c4f SAS |
5198 | return 0; |
5199 | } | |
5200 | ||
a00918d0 | 5201 | mutex_init(&xhci->mutex); |
552e0c4f SAS |
5202 | xhci->cap_regs = hcd->regs; |
5203 | xhci->op_regs = hcd->regs + | |
b0ba9720 | 5204 | HC_LENGTH(readl(&xhci->cap_regs->hc_capbase)); |
552e0c4f | 5205 | xhci->run_regs = hcd->regs + |
b0ba9720 | 5206 | (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK); |
552e0c4f | 5207 | /* Cache read-only capability registers */ |
b0ba9720 XR |
5208 | xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1); |
5209 | xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2); | |
5210 | xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3); | |
5211 | xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase); | |
552e0c4f | 5212 | xhci->hci_version = HC_VERSION(xhci->hcc_params); |
b0ba9720 | 5213 | xhci->hcc_params = readl(&xhci->cap_regs->hcc_params); |
04abb6de LB |
5214 | if (xhci->hci_version > 0x100) |
5215 | xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2); | |
552e0c4f | 5216 | |
757de492 | 5217 | xhci->quirks |= quirks; |
4e6a1ee7 | 5218 | |
552e0c4f SAS |
5219 | get_quirks(dev, xhci); |
5220 | ||
07f3cb7c GC |
5221 | /* In xhci controllers which follow xhci 1.0 spec gives a spurious |
5222 | * success event after a short transfer. This quirk will ignore such | |
5223 | * spurious event. | |
5224 | */ | |
5225 | if (xhci->hci_version > 0x96) | |
5226 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; | |
5227 | ||
552e0c4f SAS |
5228 | /* Make sure the HC is halted. */ |
5229 | retval = xhci_halt(xhci); | |
5230 | if (retval) | |
cd33a321 | 5231 | return retval; |
552e0c4f | 5232 | |
12de0a35 MZ |
5233 | xhci_zero_64b_regs(xhci); |
5234 | ||
552e0c4f SAS |
5235 | xhci_dbg(xhci, "Resetting HCD\n"); |
5236 | /* Reset the internal HC memory state and registers. */ | |
5237 | retval = xhci_reset(xhci); | |
5238 | if (retval) | |
cd33a321 | 5239 | return retval; |
552e0c4f SAS |
5240 | xhci_dbg(xhci, "Reset complete\n"); |
5241 | ||
0a380be8 YS |
5242 | /* |
5243 | * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0) | |
5244 | * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit | |
5245 | * address memory pointers actually. So, this driver clears the AC64 | |
5246 | * bit of xhci->hcc_params to call dma_set_coherent_mask(dev, | |
5247 | * DMA_BIT_MASK(32)) in this xhci_gen_setup(). | |
5248 | */ | |
5249 | if (xhci->quirks & XHCI_NO_64BIT_SUPPORT) | |
5250 | xhci->hcc_params &= ~BIT(0); | |
5251 | ||
c10cf118 XR |
5252 | /* Set dma_mask and coherent_dma_mask to 64-bits, |
5253 | * if xHC supports 64-bit addressing */ | |
5254 | if (HCC_64BIT_ADDR(xhci->hcc_params) && | |
5255 | !dma_set_mask(dev, DMA_BIT_MASK(64))) { | |
552e0c4f | 5256 | xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); |
c10cf118 | 5257 | dma_set_coherent_mask(dev, DMA_BIT_MASK(64)); |
fda182d8 DD |
5258 | } else { |
5259 | /* | |
5260 | * This is to avoid error in cases where a 32-bit USB | |
5261 | * controller is used on a 64-bit capable system. | |
5262 | */ | |
5263 | retval = dma_set_mask(dev, DMA_BIT_MASK(32)); | |
5264 | if (retval) | |
5265 | return retval; | |
5266 | xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n"); | |
5267 | dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); | |
552e0c4f SAS |
5268 | } |
5269 | ||
5270 | xhci_dbg(xhci, "Calling HCD init\n"); | |
5271 | /* Initialize HCD and host controller data structures. */ | |
5272 | retval = xhci_init(hcd); | |
5273 | if (retval) | |
cd33a321 | 5274 | return retval; |
552e0c4f | 5275 | xhci_dbg(xhci, "Called HCD init\n"); |
99705092 | 5276 | |
36b68579 | 5277 | xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n", |
99705092 HG |
5278 | xhci->hcc_params, xhci->hci_version, xhci->quirks); |
5279 | ||
552e0c4f | 5280 | return 0; |
552e0c4f | 5281 | } |
436e8c7d | 5282 | EXPORT_SYMBOL_GPL(xhci_gen_setup); |
552e0c4f | 5283 | |
ef513be0 JL |
5284 | static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd, |
5285 | struct usb_host_endpoint *ep) | |
5286 | { | |
5287 | struct xhci_hcd *xhci; | |
5288 | struct usb_device *udev; | |
5289 | unsigned int slot_id; | |
5290 | unsigned int ep_index; | |
5291 | unsigned long flags; | |
5292 | ||
5293 | xhci = hcd_to_xhci(hcd); | |
18b74067 MN |
5294 | |
5295 | spin_lock_irqsave(&xhci->lock, flags); | |
ef513be0 JL |
5296 | udev = (struct usb_device *)ep->hcpriv; |
5297 | slot_id = udev->slot_id; | |
5298 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
5299 | ||
ef513be0 JL |
5300 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT; |
5301 | xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
5302 | spin_unlock_irqrestore(&xhci->lock, flags); | |
5303 | } | |
5304 | ||
1885d9a3 AB |
5305 | static const struct hc_driver xhci_hc_driver = { |
5306 | .description = "xhci-hcd", | |
5307 | .product_desc = "xHCI Host Controller", | |
32479d4b | 5308 | .hcd_priv_size = sizeof(struct xhci_hcd), |
1885d9a3 AB |
5309 | |
5310 | /* | |
5311 | * generic hardware linkage | |
5312 | */ | |
5313 | .irq = xhci_irq, | |
36dc0165 SK |
5314 | .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED | |
5315 | HCD_BH, | |
1885d9a3 AB |
5316 | |
5317 | /* | |
5318 | * basic lifecycle operations | |
5319 | */ | |
5320 | .reset = NULL, /* set in xhci_init_driver() */ | |
5321 | .start = xhci_run, | |
5322 | .stop = xhci_stop, | |
5323 | .shutdown = xhci_shutdown, | |
5324 | ||
5325 | /* | |
5326 | * managing i/o requests and associated device resources | |
5327 | */ | |
33e39350 | 5328 | .map_urb_for_dma = xhci_map_urb_for_dma, |
1885d9a3 AB |
5329 | .urb_enqueue = xhci_urb_enqueue, |
5330 | .urb_dequeue = xhci_urb_dequeue, | |
5331 | .alloc_dev = xhci_alloc_dev, | |
5332 | .free_dev = xhci_free_dev, | |
5333 | .alloc_streams = xhci_alloc_streams, | |
5334 | .free_streams = xhci_free_streams, | |
5335 | .add_endpoint = xhci_add_endpoint, | |
5336 | .drop_endpoint = xhci_drop_endpoint, | |
18b74067 | 5337 | .endpoint_disable = xhci_endpoint_disable, |
1885d9a3 AB |
5338 | .endpoint_reset = xhci_endpoint_reset, |
5339 | .check_bandwidth = xhci_check_bandwidth, | |
5340 | .reset_bandwidth = xhci_reset_bandwidth, | |
5341 | .address_device = xhci_address_device, | |
5342 | .enable_device = xhci_enable_device, | |
5343 | .update_hub_device = xhci_update_hub_device, | |
5344 | .reset_device = xhci_discover_or_reset_device, | |
5345 | ||
5346 | /* | |
5347 | * scheduling support | |
5348 | */ | |
5349 | .get_frame_number = xhci_get_frame, | |
5350 | ||
5351 | /* | |
5352 | * root hub support | |
5353 | */ | |
5354 | .hub_control = xhci_hub_control, | |
5355 | .hub_status_data = xhci_hub_status_data, | |
5356 | .bus_suspend = xhci_bus_suspend, | |
5357 | .bus_resume = xhci_bus_resume, | |
8f9cc83c | 5358 | .get_resuming_ports = xhci_get_resuming_ports, |
1885d9a3 AB |
5359 | |
5360 | /* | |
5361 | * call back when device connected and addressed | |
5362 | */ | |
5363 | .update_device = xhci_update_device, | |
5364 | .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, | |
5365 | .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, | |
5366 | .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, | |
5367 | .find_raw_port_number = xhci_find_raw_port_number, | |
ef513be0 | 5368 | .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete, |
1885d9a3 AB |
5369 | }; |
5370 | ||
cd33a321 RQ |
5371 | void xhci_init_driver(struct hc_driver *drv, |
5372 | const struct xhci_driver_overrides *over) | |
1885d9a3 | 5373 | { |
cd33a321 RQ |
5374 | BUG_ON(!over); |
5375 | ||
5376 | /* Copy the generic table to drv then apply the overrides */ | |
1885d9a3 | 5377 | *drv = xhci_hc_driver; |
cd33a321 RQ |
5378 | |
5379 | if (over) { | |
5380 | drv->hcd_priv_size += over->extra_priv_size; | |
5381 | if (over->reset) | |
5382 | drv->reset = over->reset; | |
5383 | if (over->start) | |
5384 | drv->start = over->start; | |
5385 | } | |
1885d9a3 AB |
5386 | } |
5387 | EXPORT_SYMBOL_GPL(xhci_init_driver); | |
5388 | ||
66d4eadd SS |
5389 | MODULE_DESCRIPTION(DRIVER_DESC); |
5390 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
5391 | MODULE_LICENSE("GPL"); | |
5392 | ||
5393 | static int __init xhci_hcd_init(void) | |
5394 | { | |
98441973 SS |
5395 | /* |
5396 | * Check the compiler generated sizes of structures that must be laid | |
5397 | * out in specific ways for hardware access. | |
5398 | */ | |
5399 | BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8); | |
5400 | BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8); | |
5401 | BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8); | |
5402 | /* xhci_device_control has eight fields, and also | |
5403 | * embeds one xhci_slot_ctx and 31 xhci_ep_ctx | |
5404 | */ | |
98441973 SS |
5405 | BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8); |
5406 | BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8); | |
5407 | BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8); | |
04abb6de | 5408 | BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8); |
98441973 SS |
5409 | BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8); |
5410 | /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */ | |
5411 | BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8); | |
1eaf35e4 ON |
5412 | |
5413 | if (usb_disabled()) | |
5414 | return -ENODEV; | |
5415 | ||
02b6fdc2 LB |
5416 | xhci_debugfs_create_root(); |
5417 | ||
66d4eadd SS |
5418 | return 0; |
5419 | } | |
b04c846c AD |
5420 | |
5421 | /* | |
5422 | * If an init function is provided, an exit function must also be provided | |
5423 | * to allow module unload. | |
5424 | */ | |
02b6fdc2 LB |
5425 | static void __exit xhci_hcd_fini(void) |
5426 | { | |
5427 | xhci_debugfs_remove_root(); | |
5428 | } | |
b04c846c | 5429 | |
66d4eadd | 5430 | module_init(xhci_hcd_init); |
b04c846c | 5431 | module_exit(xhci_hcd_fini); |