Commit | Line | Data |
---|---|---|
66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
43b86af8 | 23 | #include <linux/pci.h> |
66d4eadd | 24 | #include <linux/irq.h> |
8df75f42 | 25 | #include <linux/log2.h> |
66d4eadd | 26 | #include <linux/module.h> |
b0567b3f | 27 | #include <linux/moduleparam.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
71c731a2 | 29 | #include <linux/dmi.h> |
66d4eadd SS |
30 | |
31 | #include "xhci.h" | |
84a99f6f | 32 | #include "xhci-trace.h" |
66d4eadd SS |
33 | |
34 | #define DRIVER_AUTHOR "Sarah Sharp" | |
35 | #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" | |
36 | ||
b0567b3f SS |
37 | /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */ |
38 | static int link_quirk; | |
39 | module_param(link_quirk, int, S_IRUGO | S_IWUSR); | |
40 | MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); | |
41 | ||
66d4eadd SS |
42 | /* TODO: copied from ehci-hcd.c - can this be refactored? */ |
43 | /* | |
2611bd18 | 44 | * xhci_handshake - spin reading hc until handshake completes or fails |
66d4eadd SS |
45 | * @ptr: address of hc register to be read |
46 | * @mask: bits to look at in result of read | |
47 | * @done: value of those bits when handshake succeeds | |
48 | * @usec: timeout in microseconds | |
49 | * | |
50 | * Returns negative errno, or zero on success | |
51 | * | |
52 | * Success happens when the "mask" bits have the specified value (hardware | |
53 | * handshake done). There are two failure modes: "usec" have passed (major | |
54 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
55 | */ | |
2611bd18 | 56 | int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr, |
66d4eadd SS |
57 | u32 mask, u32 done, int usec) |
58 | { | |
59 | u32 result; | |
60 | ||
61 | do { | |
62 | result = xhci_readl(xhci, ptr); | |
63 | if (result == ~(u32)0) /* card removed */ | |
64 | return -ENODEV; | |
65 | result &= mask; | |
66 | if (result == done) | |
67 | return 0; | |
68 | udelay(1); | |
69 | usec--; | |
70 | } while (usec > 0); | |
71 | return -ETIMEDOUT; | |
72 | } | |
73 | ||
74 | /* | |
4f0f0bae | 75 | * Disable interrupts and begin the xHCI halting process. |
66d4eadd | 76 | */ |
4f0f0bae | 77 | void xhci_quiesce(struct xhci_hcd *xhci) |
66d4eadd SS |
78 | { |
79 | u32 halted; | |
80 | u32 cmd; | |
81 | u32 mask; | |
82 | ||
66d4eadd SS |
83 | mask = ~(XHCI_IRQS); |
84 | halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT; | |
85 | if (!halted) | |
86 | mask &= ~CMD_RUN; | |
87 | ||
88 | cmd = xhci_readl(xhci, &xhci->op_regs->command); | |
89 | cmd &= mask; | |
90 | xhci_writel(xhci, cmd, &xhci->op_regs->command); | |
4f0f0bae SS |
91 | } |
92 | ||
93 | /* | |
94 | * Force HC into halt state. | |
95 | * | |
96 | * Disable any IRQs and clear the run/stop bit. | |
97 | * HC will complete any current and actively pipelined transactions, and | |
bdfca502 | 98 | * should halt within 16 ms of the run/stop bit being cleared. |
4f0f0bae | 99 | * Read HC Halted bit in the status register to see when the HC is finished. |
4f0f0bae SS |
100 | */ |
101 | int xhci_halt(struct xhci_hcd *xhci) | |
102 | { | |
c6cc27c7 | 103 | int ret; |
d195fcff | 104 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC"); |
4f0f0bae | 105 | xhci_quiesce(xhci); |
66d4eadd | 106 | |
2611bd18 | 107 | ret = xhci_handshake(xhci, &xhci->op_regs->status, |
66d4eadd | 108 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); |
c181bc5b | 109 | if (!ret) { |
c6cc27c7 | 110 | xhci->xhc_state |= XHCI_STATE_HALTED; |
c181bc5b EF |
111 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; |
112 | } else | |
5af98bb0 SS |
113 | xhci_warn(xhci, "Host not halted after %u microseconds.\n", |
114 | XHCI_MAX_HALT_USEC); | |
c6cc27c7 | 115 | return ret; |
66d4eadd SS |
116 | } |
117 | ||
ed07453f SS |
118 | /* |
119 | * Set the run bit and wait for the host to be running. | |
120 | */ | |
8212a49d | 121 | static int xhci_start(struct xhci_hcd *xhci) |
ed07453f SS |
122 | { |
123 | u32 temp; | |
124 | int ret; | |
125 | ||
126 | temp = xhci_readl(xhci, &xhci->op_regs->command); | |
127 | temp |= (CMD_RUN); | |
d195fcff | 128 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", |
ed07453f SS |
129 | temp); |
130 | xhci_writel(xhci, temp, &xhci->op_regs->command); | |
131 | ||
132 | /* | |
133 | * Wait for the HCHalted Status bit to be 0 to indicate the host is | |
134 | * running. | |
135 | */ | |
2611bd18 | 136 | ret = xhci_handshake(xhci, &xhci->op_regs->status, |
ed07453f SS |
137 | STS_HALT, 0, XHCI_MAX_HALT_USEC); |
138 | if (ret == -ETIMEDOUT) | |
139 | xhci_err(xhci, "Host took too long to start, " | |
140 | "waited %u microseconds.\n", | |
141 | XHCI_MAX_HALT_USEC); | |
c6cc27c7 SS |
142 | if (!ret) |
143 | xhci->xhc_state &= ~XHCI_STATE_HALTED; | |
ed07453f SS |
144 | return ret; |
145 | } | |
146 | ||
66d4eadd | 147 | /* |
ac04e6ff | 148 | * Reset a halted HC. |
66d4eadd SS |
149 | * |
150 | * This resets pipelines, timers, counters, state machines, etc. | |
151 | * Transactions will be terminated immediately, and operational registers | |
152 | * will be set to their defaults. | |
153 | */ | |
154 | int xhci_reset(struct xhci_hcd *xhci) | |
155 | { | |
156 | u32 command; | |
157 | u32 state; | |
f370b996 | 158 | int ret, i; |
66d4eadd SS |
159 | |
160 | state = xhci_readl(xhci, &xhci->op_regs->status); | |
d3512f63 SS |
161 | if ((state & STS_HALT) == 0) { |
162 | xhci_warn(xhci, "Host controller not halted, aborting reset.\n"); | |
163 | return 0; | |
164 | } | |
66d4eadd | 165 | |
d195fcff | 166 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); |
66d4eadd SS |
167 | command = xhci_readl(xhci, &xhci->op_regs->command); |
168 | command |= CMD_RESET; | |
169 | xhci_writel(xhci, command, &xhci->op_regs->command); | |
66d4eadd | 170 | |
2611bd18 | 171 | ret = xhci_handshake(xhci, &xhci->op_regs->command, |
22ceac19 | 172 | CMD_RESET, 0, 10 * 1000 * 1000); |
2d62f3ee SS |
173 | if (ret) |
174 | return ret; | |
175 | ||
d195fcff XR |
176 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
177 | "Wait for controller to be ready for doorbell rings"); | |
2d62f3ee SS |
178 | /* |
179 | * xHCI cannot write to any doorbells or operational registers other | |
180 | * than status until the "Controller Not Ready" flag is cleared. | |
181 | */ | |
2611bd18 | 182 | ret = xhci_handshake(xhci, &xhci->op_regs->status, |
22ceac19 | 183 | STS_CNR, 0, 10 * 1000 * 1000); |
f370b996 AX |
184 | |
185 | for (i = 0; i < 2; ++i) { | |
186 | xhci->bus_state[i].port_c_suspend = 0; | |
187 | xhci->bus_state[i].suspended_ports = 0; | |
188 | xhci->bus_state[i].resuming_ports = 0; | |
189 | } | |
190 | ||
191 | return ret; | |
66d4eadd SS |
192 | } |
193 | ||
421aa841 SAS |
194 | #ifdef CONFIG_PCI |
195 | static int xhci_free_msi(struct xhci_hcd *xhci) | |
43b86af8 DN |
196 | { |
197 | int i; | |
43b86af8 | 198 | |
421aa841 SAS |
199 | if (!xhci->msix_entries) |
200 | return -EINVAL; | |
43b86af8 | 201 | |
421aa841 SAS |
202 | for (i = 0; i < xhci->msix_count; i++) |
203 | if (xhci->msix_entries[i].vector) | |
204 | free_irq(xhci->msix_entries[i].vector, | |
205 | xhci_to_hcd(xhci)); | |
206 | return 0; | |
43b86af8 DN |
207 | } |
208 | ||
209 | /* | |
210 | * Set up MSI | |
211 | */ | |
212 | static int xhci_setup_msi(struct xhci_hcd *xhci) | |
66d4eadd SS |
213 | { |
214 | int ret; | |
43b86af8 DN |
215 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
216 | ||
217 | ret = pci_enable_msi(pdev); | |
218 | if (ret) { | |
d195fcff XR |
219 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
220 | "failed to allocate MSI entry"); | |
43b86af8 DN |
221 | return ret; |
222 | } | |
223 | ||
851ec164 | 224 | ret = request_irq(pdev->irq, xhci_msi_irq, |
43b86af8 DN |
225 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
226 | if (ret) { | |
d195fcff XR |
227 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
228 | "disable MSI interrupt"); | |
43b86af8 DN |
229 | pci_disable_msi(pdev); |
230 | } | |
231 | ||
232 | return ret; | |
233 | } | |
234 | ||
421aa841 SAS |
235 | /* |
236 | * Free IRQs | |
237 | * free all IRQs request | |
238 | */ | |
239 | static void xhci_free_irq(struct xhci_hcd *xhci) | |
240 | { | |
241 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
242 | int ret; | |
243 | ||
244 | /* return if using legacy interrupt */ | |
cd70469d | 245 | if (xhci_to_hcd(xhci)->irq > 0) |
421aa841 SAS |
246 | return; |
247 | ||
248 | ret = xhci_free_msi(xhci); | |
249 | if (!ret) | |
250 | return; | |
cd70469d | 251 | if (pdev->irq > 0) |
421aa841 SAS |
252 | free_irq(pdev->irq, xhci_to_hcd(xhci)); |
253 | ||
254 | return; | |
255 | } | |
256 | ||
43b86af8 DN |
257 | /* |
258 | * Set up MSI-X | |
259 | */ | |
260 | static int xhci_setup_msix(struct xhci_hcd *xhci) | |
261 | { | |
262 | int i, ret = 0; | |
0029227f AX |
263 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
264 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 265 | |
43b86af8 DN |
266 | /* |
267 | * calculate number of msi-x vectors supported. | |
268 | * - HCS_MAX_INTRS: the max number of interrupts the host can handle, | |
269 | * with max number of interrupters based on the xhci HCSPARAMS1. | |
270 | * - num_online_cpus: maximum msi-x vectors per CPUs core. | |
271 | * Add additional 1 vector to ensure always available interrupt. | |
272 | */ | |
273 | xhci->msix_count = min(num_online_cpus() + 1, | |
274 | HCS_MAX_INTRS(xhci->hcs_params1)); | |
275 | ||
276 | xhci->msix_entries = | |
277 | kmalloc((sizeof(struct msix_entry))*xhci->msix_count, | |
86871975 | 278 | GFP_KERNEL); |
66d4eadd SS |
279 | if (!xhci->msix_entries) { |
280 | xhci_err(xhci, "Failed to allocate MSI-X entries\n"); | |
281 | return -ENOMEM; | |
282 | } | |
43b86af8 DN |
283 | |
284 | for (i = 0; i < xhci->msix_count; i++) { | |
285 | xhci->msix_entries[i].entry = i; | |
286 | xhci->msix_entries[i].vector = 0; | |
287 | } | |
66d4eadd SS |
288 | |
289 | ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count); | |
290 | if (ret) { | |
d195fcff XR |
291 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
292 | "Failed to enable MSI-X"); | |
66d4eadd SS |
293 | goto free_entries; |
294 | } | |
295 | ||
43b86af8 DN |
296 | for (i = 0; i < xhci->msix_count; i++) { |
297 | ret = request_irq(xhci->msix_entries[i].vector, | |
851ec164 | 298 | xhci_msi_irq, |
43b86af8 DN |
299 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
300 | if (ret) | |
301 | goto disable_msix; | |
66d4eadd | 302 | } |
43b86af8 | 303 | |
0029227f | 304 | hcd->msix_enabled = 1; |
43b86af8 | 305 | return ret; |
66d4eadd SS |
306 | |
307 | disable_msix: | |
d195fcff | 308 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); |
43b86af8 | 309 | xhci_free_irq(xhci); |
66d4eadd SS |
310 | pci_disable_msix(pdev); |
311 | free_entries: | |
312 | kfree(xhci->msix_entries); | |
313 | xhci->msix_entries = NULL; | |
314 | return ret; | |
315 | } | |
316 | ||
66d4eadd SS |
317 | /* Free any IRQs and disable MSI-X */ |
318 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |
319 | { | |
0029227f AX |
320 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
321 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 322 | |
43b86af8 DN |
323 | xhci_free_irq(xhci); |
324 | ||
325 | if (xhci->msix_entries) { | |
326 | pci_disable_msix(pdev); | |
327 | kfree(xhci->msix_entries); | |
328 | xhci->msix_entries = NULL; | |
329 | } else { | |
330 | pci_disable_msi(pdev); | |
331 | } | |
332 | ||
0029227f | 333 | hcd->msix_enabled = 0; |
43b86af8 | 334 | return; |
66d4eadd | 335 | } |
66d4eadd | 336 | |
d5c82feb | 337 | static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 SAS |
338 | { |
339 | int i; | |
340 | ||
341 | if (xhci->msix_entries) { | |
342 | for (i = 0; i < xhci->msix_count; i++) | |
343 | synchronize_irq(xhci->msix_entries[i].vector); | |
344 | } | |
345 | } | |
346 | ||
347 | static int xhci_try_enable_msi(struct usb_hcd *hcd) | |
348 | { | |
349 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
350 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
351 | int ret; | |
352 | ||
353 | /* | |
354 | * Some Fresco Logic host controllers advertise MSI, but fail to | |
355 | * generate interrupts. Don't even try to enable MSI. | |
356 | */ | |
357 | if (xhci->quirks & XHCI_BROKEN_MSI) | |
00eed9c8 | 358 | goto legacy_irq; |
421aa841 SAS |
359 | |
360 | /* unregister the legacy interrupt */ | |
361 | if (hcd->irq) | |
362 | free_irq(hcd->irq, hcd); | |
cd70469d | 363 | hcd->irq = 0; |
421aa841 SAS |
364 | |
365 | ret = xhci_setup_msix(xhci); | |
366 | if (ret) | |
367 | /* fall back to msi*/ | |
368 | ret = xhci_setup_msi(xhci); | |
369 | ||
370 | if (!ret) | |
cd70469d | 371 | /* hcd->irq is 0, we have MSI */ |
421aa841 SAS |
372 | return 0; |
373 | ||
68d07f64 SS |
374 | if (!pdev->irq) { |
375 | xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); | |
376 | return -EINVAL; | |
377 | } | |
378 | ||
00eed9c8 | 379 | legacy_irq: |
421aa841 SAS |
380 | /* fall back to legacy interrupt*/ |
381 | ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, | |
382 | hcd->irq_descr, hcd); | |
383 | if (ret) { | |
384 | xhci_err(xhci, "request interrupt %d failed\n", | |
385 | pdev->irq); | |
386 | return ret; | |
387 | } | |
388 | hcd->irq = pdev->irq; | |
389 | return 0; | |
390 | } | |
391 | ||
392 | #else | |
393 | ||
394 | static int xhci_try_enable_msi(struct usb_hcd *hcd) | |
395 | { | |
396 | return 0; | |
397 | } | |
398 | ||
399 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |
400 | { | |
401 | } | |
402 | ||
403 | static void xhci_msix_sync_irqs(struct xhci_hcd *xhci) | |
404 | { | |
405 | } | |
406 | ||
407 | #endif | |
408 | ||
71c731a2 AC |
409 | static void compliance_mode_recovery(unsigned long arg) |
410 | { | |
411 | struct xhci_hcd *xhci; | |
412 | struct usb_hcd *hcd; | |
413 | u32 temp; | |
414 | int i; | |
415 | ||
416 | xhci = (struct xhci_hcd *)arg; | |
417 | ||
418 | for (i = 0; i < xhci->num_usb3_ports; i++) { | |
419 | temp = xhci_readl(xhci, xhci->usb3_ports[i]); | |
420 | if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) { | |
421 | /* | |
422 | * Compliance Mode Detected. Letting USB Core | |
423 | * handle the Warm Reset | |
424 | */ | |
4bdfe4c3 XR |
425 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
426 | "Compliance mode detected->port %d", | |
71c731a2 | 427 | i + 1); |
4bdfe4c3 XR |
428 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
429 | "Attempting compliance mode recovery"); | |
71c731a2 AC |
430 | hcd = xhci->shared_hcd; |
431 | ||
432 | if (hcd->state == HC_STATE_SUSPENDED) | |
433 | usb_hcd_resume_root_hub(hcd); | |
434 | ||
435 | usb_hcd_poll_rh_status(hcd); | |
436 | } | |
437 | } | |
438 | ||
439 | if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1)) | |
440 | mod_timer(&xhci->comp_mode_recovery_timer, | |
441 | jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS)); | |
442 | } | |
443 | ||
444 | /* | |
445 | * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver | |
446 | * that causes ports behind that hardware to enter compliance mode sometimes. | |
447 | * The quirk creates a timer that polls every 2 seconds the link state of | |
448 | * each host controller's port and recovers it by issuing a Warm reset | |
449 | * if Compliance mode is detected, otherwise the port will become "dead" (no | |
450 | * device connections or disconnections will be detected anymore). Becasue no | |
451 | * status event is generated when entering compliance mode (per xhci spec), | |
452 | * this quirk is needed on systems that have the failing hardware installed. | |
453 | */ | |
454 | static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci) | |
455 | { | |
456 | xhci->port_status_u0 = 0; | |
457 | init_timer(&xhci->comp_mode_recovery_timer); | |
458 | ||
459 | xhci->comp_mode_recovery_timer.data = (unsigned long) xhci; | |
460 | xhci->comp_mode_recovery_timer.function = compliance_mode_recovery; | |
461 | xhci->comp_mode_recovery_timer.expires = jiffies + | |
462 | msecs_to_jiffies(COMP_MODE_RCVRY_MSECS); | |
463 | ||
464 | set_timer_slack(&xhci->comp_mode_recovery_timer, | |
465 | msecs_to_jiffies(COMP_MODE_RCVRY_MSECS)); | |
466 | add_timer(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
467 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
468 | "Compliance mode recovery timer initialized"); | |
71c731a2 AC |
469 | } |
470 | ||
471 | /* | |
472 | * This function identifies the systems that have installed the SN65LVPE502CP | |
473 | * USB3.0 re-driver and that need the Compliance Mode Quirk. | |
474 | * Systems: | |
475 | * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820 | |
476 | */ | |
c3897aa5 | 477 | bool xhci_compliance_mode_recovery_timer_quirk_check(void) |
71c731a2 AC |
478 | { |
479 | const char *dmi_product_name, *dmi_sys_vendor; | |
480 | ||
481 | dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); | |
482 | dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR); | |
457a73d3 VG |
483 | if (!dmi_product_name || !dmi_sys_vendor) |
484 | return false; | |
71c731a2 AC |
485 | |
486 | if (!(strstr(dmi_sys_vendor, "Hewlett-Packard"))) | |
487 | return false; | |
488 | ||
489 | if (strstr(dmi_product_name, "Z420") || | |
490 | strstr(dmi_product_name, "Z620") || | |
47080974 | 491 | strstr(dmi_product_name, "Z820") || |
b0e4e606 | 492 | strstr(dmi_product_name, "Z1 Workstation")) |
71c731a2 AC |
493 | return true; |
494 | ||
495 | return false; | |
496 | } | |
497 | ||
498 | static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci) | |
499 | { | |
500 | return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1)); | |
501 | } | |
502 | ||
503 | ||
66d4eadd SS |
504 | /* |
505 | * Initialize memory for HCD and xHC (one-time init). | |
506 | * | |
507 | * Program the PAGESIZE register, initialize the device context array, create | |
508 | * device contexts (?), set up a command ring segment (or two?), create event | |
509 | * ring (one for now). | |
510 | */ | |
511 | int xhci_init(struct usb_hcd *hcd) | |
512 | { | |
513 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
514 | int retval = 0; | |
515 | ||
d195fcff | 516 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init"); |
66d4eadd | 517 | spin_lock_init(&xhci->lock); |
d7826599 | 518 | if (xhci->hci_version == 0x95 && link_quirk) { |
4bdfe4c3 XR |
519 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
520 | "QUIRK: Not clearing Link TRB chain bits."); | |
b0567b3f SS |
521 | xhci->quirks |= XHCI_LINK_TRB_QUIRK; |
522 | } else { | |
d195fcff XR |
523 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
524 | "xHCI doesn't need link TRB QUIRK"); | |
b0567b3f | 525 | } |
66d4eadd | 526 | retval = xhci_mem_init(xhci, GFP_KERNEL); |
d195fcff | 527 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init"); |
66d4eadd | 528 | |
71c731a2 | 529 | /* Initializing Compliance Mode Recovery Data If Needed */ |
c3897aa5 | 530 | if (xhci_compliance_mode_recovery_timer_quirk_check()) { |
71c731a2 AC |
531 | xhci->quirks |= XHCI_COMP_MODE_QUIRK; |
532 | compliance_mode_recovery_timer_init(xhci); | |
533 | } | |
534 | ||
66d4eadd SS |
535 | return retval; |
536 | } | |
537 | ||
7f84eef0 SS |
538 | /*-------------------------------------------------------------------------*/ |
539 | ||
7f84eef0 | 540 | |
f6ff0ac8 SS |
541 | static int xhci_run_finished(struct xhci_hcd *xhci) |
542 | { | |
543 | if (xhci_start(xhci)) { | |
544 | xhci_halt(xhci); | |
545 | return -ENODEV; | |
546 | } | |
547 | xhci->shared_hcd->state = HC_STATE_RUNNING; | |
c181bc5b | 548 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; |
f6ff0ac8 SS |
549 | |
550 | if (xhci->quirks & XHCI_NEC_HOST) | |
551 | xhci_ring_cmd_db(xhci); | |
552 | ||
d195fcff XR |
553 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
554 | "Finished xhci_run for USB3 roothub"); | |
f6ff0ac8 SS |
555 | return 0; |
556 | } | |
557 | ||
66d4eadd SS |
558 | /* |
559 | * Start the HC after it was halted. | |
560 | * | |
561 | * This function is called by the USB core when the HC driver is added. | |
562 | * Its opposite is xhci_stop(). | |
563 | * | |
564 | * xhci_init() must be called once before this function can be called. | |
565 | * Reset the HC, enable device slot contexts, program DCBAAP, and | |
566 | * set command ring pointer and event ring pointer. | |
567 | * | |
568 | * Setup MSI-X vectors and enable interrupts. | |
569 | */ | |
570 | int xhci_run(struct usb_hcd *hcd) | |
571 | { | |
572 | u32 temp; | |
8e595a5d | 573 | u64 temp_64; |
3fd1ec58 | 574 | int ret; |
66d4eadd | 575 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
66d4eadd | 576 | |
f6ff0ac8 SS |
577 | /* Start the xHCI host controller running only after the USB 2.0 roothub |
578 | * is setup. | |
579 | */ | |
66d4eadd | 580 | |
0f2a7930 | 581 | hcd->uses_new_polling = 1; |
f6ff0ac8 SS |
582 | if (!usb_hcd_is_primary_hcd(hcd)) |
583 | return xhci_run_finished(xhci); | |
0f2a7930 | 584 | |
d195fcff | 585 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run"); |
43b86af8 | 586 | |
3fd1ec58 | 587 | ret = xhci_try_enable_msi(hcd); |
43b86af8 | 588 | if (ret) |
3fd1ec58 | 589 | return ret; |
66d4eadd | 590 | |
66e49d87 SS |
591 | xhci_dbg(xhci, "Command ring memory map follows:\n"); |
592 | xhci_debug_ring(xhci, xhci->cmd_ring); | |
593 | xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); | |
594 | xhci_dbg_cmd_ptrs(xhci); | |
595 | ||
596 | xhci_dbg(xhci, "ERST memory map follows:\n"); | |
597 | xhci_dbg_erst(xhci, &xhci->erst); | |
598 | xhci_dbg(xhci, "Event ring:\n"); | |
599 | xhci_debug_ring(xhci, xhci->event_ring); | |
600 | xhci_dbg_ring_ptrs(xhci, xhci->event_ring); | |
601 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
602 | temp_64 &= ~ERST_PTR_MASK; | |
d195fcff XR |
603 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
604 | "ERST deq = 64'h%0lx", (long unsigned int) temp_64); | |
66e49d87 | 605 | |
d195fcff XR |
606 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
607 | "// Set the interrupt modulation register"); | |
66d4eadd | 608 | temp = xhci_readl(xhci, &xhci->ir_set->irq_control); |
a4d88302 | 609 | temp &= ~ER_IRQ_INTERVAL_MASK; |
66d4eadd SS |
610 | temp |= (u32) 160; |
611 | xhci_writel(xhci, temp, &xhci->ir_set->irq_control); | |
612 | ||
613 | /* Set the HCD state before we enable the irqs */ | |
66d4eadd SS |
614 | temp = xhci_readl(xhci, &xhci->op_regs->command); |
615 | temp |= (CMD_EIE); | |
d195fcff XR |
616 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
617 | "// Enable interrupts, cmd = 0x%x.", temp); | |
66d4eadd SS |
618 | xhci_writel(xhci, temp, &xhci->op_regs->command); |
619 | ||
620 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
d195fcff XR |
621 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
622 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", | |
700e2052 | 623 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); |
66d4eadd SS |
624 | xhci_writel(xhci, ER_IRQ_ENABLE(temp), |
625 | &xhci->ir_set->irq_pending); | |
09ece30e | 626 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 627 | |
0238634d SS |
628 | if (xhci->quirks & XHCI_NEC_HOST) |
629 | xhci_queue_vendor_command(xhci, 0, 0, 0, | |
630 | TRB_TYPE(TRB_NEC_GET_FW)); | |
7f84eef0 | 631 | |
d195fcff XR |
632 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
633 | "Finished xhci_run for USB2 roothub"); | |
f6ff0ac8 SS |
634 | return 0; |
635 | } | |
ed07453f | 636 | |
f6ff0ac8 SS |
637 | static void xhci_only_stop_hcd(struct usb_hcd *hcd) |
638 | { | |
639 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
66d4eadd | 640 | |
f6ff0ac8 SS |
641 | spin_lock_irq(&xhci->lock); |
642 | xhci_halt(xhci); | |
643 | ||
644 | /* The shared_hcd is going to be deallocated shortly (the USB core only | |
645 | * calls this function when allocation fails in usb_add_hcd(), or | |
646 | * usb_remove_hcd() is called). So we need to unset xHCI's pointer. | |
647 | */ | |
648 | xhci->shared_hcd = NULL; | |
649 | spin_unlock_irq(&xhci->lock); | |
66d4eadd SS |
650 | } |
651 | ||
652 | /* | |
653 | * Stop xHCI driver. | |
654 | * | |
655 | * This function is called by the USB core when the HC driver is removed. | |
656 | * Its opposite is xhci_run(). | |
657 | * | |
658 | * Disable device contexts, disable IRQs, and quiesce the HC. | |
659 | * Reset the HC, finish any completed transactions, and cleanup memory. | |
660 | */ | |
661 | void xhci_stop(struct usb_hcd *hcd) | |
662 | { | |
663 | u32 temp; | |
664 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
665 | ||
f6ff0ac8 SS |
666 | if (!usb_hcd_is_primary_hcd(hcd)) { |
667 | xhci_only_stop_hcd(xhci->shared_hcd); | |
668 | return; | |
669 | } | |
670 | ||
66d4eadd | 671 | spin_lock_irq(&xhci->lock); |
f6ff0ac8 SS |
672 | /* Make sure the xHC is halted for a USB3 roothub |
673 | * (xhci_stop() could be called as part of failed init). | |
674 | */ | |
66d4eadd SS |
675 | xhci_halt(xhci); |
676 | xhci_reset(xhci); | |
677 | spin_unlock_irq(&xhci->lock); | |
678 | ||
40a9fb17 ZR |
679 | xhci_cleanup_msix(xhci); |
680 | ||
71c731a2 AC |
681 | /* Deleting Compliance Mode Recovery Timer */ |
682 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
58b1d799 | 683 | (!(xhci_all_ports_seen_u0(xhci)))) { |
71c731a2 | 684 | del_timer_sync(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
685 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
686 | "%s: compliance mode recovery timer deleted", | |
58b1d799 TC |
687 | __func__); |
688 | } | |
71c731a2 | 689 | |
c41136b0 AX |
690 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
691 | usb_amd_dev_put(); | |
692 | ||
d195fcff XR |
693 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
694 | "// Disabling event ring interrupts"); | |
66d4eadd SS |
695 | temp = xhci_readl(xhci, &xhci->op_regs->status); |
696 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); | |
697 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
698 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), | |
699 | &xhci->ir_set->irq_pending); | |
09ece30e | 700 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 701 | |
d195fcff | 702 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); |
66d4eadd | 703 | xhci_mem_cleanup(xhci); |
d195fcff XR |
704 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
705 | "xhci_stop completed - status = %x", | |
706 | xhci_readl(xhci, &xhci->op_regs->status)); | |
66d4eadd SS |
707 | } |
708 | ||
709 | /* | |
710 | * Shutdown HC (not bus-specific) | |
711 | * | |
712 | * This is called when the machine is rebooting or halting. We assume that the | |
713 | * machine will be powered off, and the HC's internal state will be reset. | |
714 | * Don't bother to free memory. | |
f6ff0ac8 SS |
715 | * |
716 | * This will only ever be called with the main usb_hcd (the USB3 roothub). | |
66d4eadd SS |
717 | */ |
718 | void xhci_shutdown(struct usb_hcd *hcd) | |
719 | { | |
720 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
721 | ||
052c7f9f | 722 | if (xhci->quirks & XHCI_SPURIOUS_REBOOT) |
e95829f4 SS |
723 | usb_disable_xhci_ports(to_pci_dev(hcd->self.controller)); |
724 | ||
66d4eadd SS |
725 | spin_lock_irq(&xhci->lock); |
726 | xhci_halt(xhci); | |
43b86af8 | 727 | spin_unlock_irq(&xhci->lock); |
66d4eadd | 728 | |
40a9fb17 ZR |
729 | xhci_cleanup_msix(xhci); |
730 | ||
d195fcff XR |
731 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
732 | "xhci_shutdown completed - status = %x", | |
733 | xhci_readl(xhci, &xhci->op_regs->status)); | |
66d4eadd SS |
734 | } |
735 | ||
b5b5c3ac | 736 | #ifdef CONFIG_PM |
5535b1d5 AX |
737 | static void xhci_save_registers(struct xhci_hcd *xhci) |
738 | { | |
739 | xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command); | |
740 | xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification); | |
741 | xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); | |
742 | xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg); | |
5535b1d5 AX |
743 | xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size); |
744 | xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base); | |
745 | xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
c7713e73 SS |
746 | xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending); |
747 | xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control); | |
5535b1d5 AX |
748 | } |
749 | ||
750 | static void xhci_restore_registers(struct xhci_hcd *xhci) | |
751 | { | |
752 | xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command); | |
753 | xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification); | |
754 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); | |
755 | xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg); | |
5535b1d5 AX |
756 | xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size); |
757 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); | |
fb3d85bc | 758 | xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); |
c7713e73 SS |
759 | xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending); |
760 | xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control); | |
5535b1d5 AX |
761 | } |
762 | ||
89821320 SS |
763 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) |
764 | { | |
765 | u64 val_64; | |
766 | ||
767 | /* step 2: initialize command ring buffer */ | |
768 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
769 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | | |
770 | (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | |
771 | xhci->cmd_ring->dequeue) & | |
772 | (u64) ~CMD_RING_RSVD_BITS) | | |
773 | xhci->cmd_ring->cycle_state; | |
d195fcff XR |
774 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
775 | "// Setting command ring address to 0x%llx", | |
89821320 SS |
776 | (long unsigned long) val_64); |
777 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); | |
778 | } | |
779 | ||
780 | /* | |
781 | * The whole command ring must be cleared to zero when we suspend the host. | |
782 | * | |
783 | * The host doesn't save the command ring pointer in the suspend well, so we | |
784 | * need to re-program it on resume. Unfortunately, the pointer must be 64-byte | |
785 | * aligned, because of the reserved bits in the command ring dequeue pointer | |
786 | * register. Therefore, we can't just set the dequeue pointer back in the | |
787 | * middle of the ring (TRBs are 16-byte aligned). | |
788 | */ | |
789 | static void xhci_clear_command_ring(struct xhci_hcd *xhci) | |
790 | { | |
791 | struct xhci_ring *ring; | |
792 | struct xhci_segment *seg; | |
793 | ||
794 | ring = xhci->cmd_ring; | |
795 | seg = ring->deq_seg; | |
796 | do { | |
158886cd AX |
797 | memset(seg->trbs, 0, |
798 | sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1)); | |
799 | seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= | |
800 | cpu_to_le32(~TRB_CYCLE); | |
89821320 SS |
801 | seg = seg->next; |
802 | } while (seg != ring->deq_seg); | |
803 | ||
804 | /* Reset the software enqueue and dequeue pointers */ | |
805 | ring->deq_seg = ring->first_seg; | |
806 | ring->dequeue = ring->first_seg->trbs; | |
807 | ring->enq_seg = ring->deq_seg; | |
808 | ring->enqueue = ring->dequeue; | |
809 | ||
b008df60 | 810 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; |
89821320 SS |
811 | /* |
812 | * Ring is now zeroed, so the HW should look for change of ownership | |
813 | * when the cycle bit is set to 1. | |
814 | */ | |
815 | ring->cycle_state = 1; | |
816 | ||
817 | /* | |
818 | * Reset the hardware dequeue pointer. | |
819 | * Yes, this will need to be re-written after resume, but we're paranoid | |
820 | * and want to make sure the hardware doesn't access bogus memory | |
821 | * because, say, the BIOS or an SMI started the host without changing | |
822 | * the command ring pointers. | |
823 | */ | |
824 | xhci_set_cmd_ring_deq(xhci); | |
825 | } | |
826 | ||
5535b1d5 AX |
827 | /* |
828 | * Stop HC (not bus-specific) | |
829 | * | |
830 | * This is called when the machine transition into S3/S4 mode. | |
831 | * | |
832 | */ | |
833 | int xhci_suspend(struct xhci_hcd *xhci) | |
834 | { | |
835 | int rc = 0; | |
836 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
837 | u32 command; | |
838 | ||
77b84767 FB |
839 | if (hcd->state != HC_STATE_SUSPENDED || |
840 | xhci->shared_hcd->state != HC_STATE_SUSPENDED) | |
841 | return -EINVAL; | |
842 | ||
c52804a4 SS |
843 | /* Don't poll the roothubs on bus suspend. */ |
844 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
845 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
846 | del_timer_sync(&hcd->rh_timer); | |
847 | ||
5535b1d5 AX |
848 | spin_lock_irq(&xhci->lock); |
849 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
b3209379 | 850 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); |
5535b1d5 AX |
851 | /* step 1: stop endpoint */ |
852 | /* skipped assuming that port suspend has done */ | |
853 | ||
854 | /* step 2: clear Run/Stop bit */ | |
855 | command = xhci_readl(xhci, &xhci->op_regs->command); | |
856 | command &= ~CMD_RUN; | |
857 | xhci_writel(xhci, command, &xhci->op_regs->command); | |
2611bd18 | 858 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
a6e097df | 859 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC)) { |
5535b1d5 AX |
860 | xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n"); |
861 | spin_unlock_irq(&xhci->lock); | |
862 | return -ETIMEDOUT; | |
863 | } | |
89821320 | 864 | xhci_clear_command_ring(xhci); |
5535b1d5 AX |
865 | |
866 | /* step 3: save registers */ | |
867 | xhci_save_registers(xhci); | |
868 | ||
869 | /* step 4: set CSS flag */ | |
870 | command = xhci_readl(xhci, &xhci->op_regs->command); | |
871 | command |= CMD_CSS; | |
872 | xhci_writel(xhci, command, &xhci->op_regs->command); | |
2611bd18 SS |
873 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
874 | STS_SAVE, 0, 10 * 1000)) { | |
622eb783 | 875 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); |
5535b1d5 AX |
876 | spin_unlock_irq(&xhci->lock); |
877 | return -ETIMEDOUT; | |
878 | } | |
5535b1d5 AX |
879 | spin_unlock_irq(&xhci->lock); |
880 | ||
71c731a2 AC |
881 | /* |
882 | * Deleting Compliance Mode Recovery Timer because the xHCI Host | |
883 | * is about to be suspended. | |
884 | */ | |
885 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
886 | (!(xhci_all_ports_seen_u0(xhci)))) { | |
887 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
888 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
889 | "%s: compliance mode recovery timer deleted", | |
58b1d799 | 890 | __func__); |
71c731a2 AC |
891 | } |
892 | ||
0029227f AX |
893 | /* step 5: remove core well power */ |
894 | /* synchronize irq when using MSI-X */ | |
421aa841 | 895 | xhci_msix_sync_irqs(xhci); |
0029227f | 896 | |
5535b1d5 AX |
897 | return rc; |
898 | } | |
899 | ||
900 | /* | |
901 | * start xHC (not bus-specific) | |
902 | * | |
903 | * This is called when the machine transition from S3/S4 mode. | |
904 | * | |
905 | */ | |
906 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |
907 | { | |
908 | u32 command, temp = 0; | |
909 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
65b22f93 | 910 | struct usb_hcd *secondary_hcd; |
f69e3120 | 911 | int retval = 0; |
77df9e0b | 912 | bool comp_timer_running = false; |
5535b1d5 | 913 | |
f6ff0ac8 | 914 | /* Wait a bit if either of the roothubs need to settle from the |
25985edc | 915 | * transition into bus suspend. |
20b67cf5 | 916 | */ |
f6ff0ac8 SS |
917 | if (time_before(jiffies, xhci->bus_state[0].next_statechange) || |
918 | time_before(jiffies, | |
919 | xhci->bus_state[1].next_statechange)) | |
5535b1d5 AX |
920 | msleep(100); |
921 | ||
f69e3120 AS |
922 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
923 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); | |
924 | ||
5535b1d5 | 925 | spin_lock_irq(&xhci->lock); |
c877b3b2 ML |
926 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
927 | hibernated = true; | |
5535b1d5 AX |
928 | |
929 | if (!hibernated) { | |
930 | /* step 1: restore register */ | |
931 | xhci_restore_registers(xhci); | |
932 | /* step 2: initialize command ring buffer */ | |
89821320 | 933 | xhci_set_cmd_ring_deq(xhci); |
5535b1d5 AX |
934 | /* step 3: restore state and start state*/ |
935 | /* step 3: set CRS flag */ | |
936 | command = xhci_readl(xhci, &xhci->op_regs->command); | |
937 | command |= CMD_CRS; | |
938 | xhci_writel(xhci, command, &xhci->op_regs->command); | |
2611bd18 | 939 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
622eb783 AX |
940 | STS_RESTORE, 0, 10 * 1000)) { |
941 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); | |
5535b1d5 AX |
942 | spin_unlock_irq(&xhci->lock); |
943 | return -ETIMEDOUT; | |
944 | } | |
945 | temp = xhci_readl(xhci, &xhci->op_regs->status); | |
946 | } | |
947 | ||
948 | /* If restore operation fails, re-initialize the HC during resume */ | |
949 | if ((temp & STS_SRE) || hibernated) { | |
77df9e0b TC |
950 | |
951 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
952 | !(xhci_all_ports_seen_u0(xhci))) { | |
953 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
954 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
955 | "Compliance Mode Recovery Timer deleted!"); | |
77df9e0b TC |
956 | } |
957 | ||
fedd383e SS |
958 | /* Let the USB core know _both_ roothubs lost power. */ |
959 | usb_root_hub_lost_power(xhci->main_hcd->self.root_hub); | |
960 | usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub); | |
5535b1d5 AX |
961 | |
962 | xhci_dbg(xhci, "Stop HCD\n"); | |
963 | xhci_halt(xhci); | |
964 | xhci_reset(xhci); | |
5535b1d5 | 965 | spin_unlock_irq(&xhci->lock); |
0029227f | 966 | xhci_cleanup_msix(xhci); |
5535b1d5 | 967 | |
5535b1d5 AX |
968 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
969 | temp = xhci_readl(xhci, &xhci->op_regs->status); | |
970 | xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status); | |
971 | temp = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
972 | xhci_writel(xhci, ER_IRQ_DISABLE(temp), | |
973 | &xhci->ir_set->irq_pending); | |
09ece30e | 974 | xhci_print_ir_set(xhci, 0); |
5535b1d5 AX |
975 | |
976 | xhci_dbg(xhci, "cleaning up memory\n"); | |
977 | xhci_mem_cleanup(xhci); | |
978 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", | |
979 | xhci_readl(xhci, &xhci->op_regs->status)); | |
980 | ||
65b22f93 SS |
981 | /* USB core calls the PCI reinit and start functions twice: |
982 | * first with the primary HCD, and then with the secondary HCD. | |
983 | * If we don't do the same, the host will never be started. | |
984 | */ | |
985 | if (!usb_hcd_is_primary_hcd(hcd)) | |
986 | secondary_hcd = hcd; | |
987 | else | |
988 | secondary_hcd = xhci->shared_hcd; | |
989 | ||
990 | xhci_dbg(xhci, "Initialize the xhci_hcd\n"); | |
991 | retval = xhci_init(hcd->primary_hcd); | |
5535b1d5 AX |
992 | if (retval) |
993 | return retval; | |
77df9e0b TC |
994 | comp_timer_running = true; |
995 | ||
65b22f93 SS |
996 | xhci_dbg(xhci, "Start the primary HCD\n"); |
997 | retval = xhci_run(hcd->primary_hcd); | |
b3209379 | 998 | if (!retval) { |
f69e3120 AS |
999 | xhci_dbg(xhci, "Start the secondary HCD\n"); |
1000 | retval = xhci_run(secondary_hcd); | |
b3209379 | 1001 | } |
5535b1d5 | 1002 | hcd->state = HC_STATE_SUSPENDED; |
b3209379 | 1003 | xhci->shared_hcd->state = HC_STATE_SUSPENDED; |
f69e3120 | 1004 | goto done; |
5535b1d5 AX |
1005 | } |
1006 | ||
5535b1d5 AX |
1007 | /* step 4: set Run/Stop bit */ |
1008 | command = xhci_readl(xhci, &xhci->op_regs->command); | |
1009 | command |= CMD_RUN; | |
1010 | xhci_writel(xhci, command, &xhci->op_regs->command); | |
2611bd18 | 1011 | xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, |
5535b1d5 AX |
1012 | 0, 250 * 1000); |
1013 | ||
1014 | /* step 5: walk topology and initialize portsc, | |
1015 | * portpmsc and portli | |
1016 | */ | |
1017 | /* this is done in bus_resume */ | |
1018 | ||
1019 | /* step 6: restart each of the previously | |
1020 | * Running endpoints by ringing their doorbells | |
1021 | */ | |
1022 | ||
5535b1d5 | 1023 | spin_unlock_irq(&xhci->lock); |
f69e3120 AS |
1024 | |
1025 | done: | |
1026 | if (retval == 0) { | |
1027 | usb_hcd_resume_root_hub(hcd); | |
1028 | usb_hcd_resume_root_hub(xhci->shared_hcd); | |
1029 | } | |
71c731a2 AC |
1030 | |
1031 | /* | |
1032 | * If system is subject to the Quirk, Compliance Mode Timer needs to | |
1033 | * be re-initialized Always after a system resume. Ports are subject | |
1034 | * to suffer the Compliance Mode issue again. It doesn't matter if | |
1035 | * ports have entered previously to U0 before system's suspension. | |
1036 | */ | |
77df9e0b | 1037 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running) |
71c731a2 AC |
1038 | compliance_mode_recovery_timer_init(xhci); |
1039 | ||
c52804a4 SS |
1040 | /* Re-enable port polling. */ |
1041 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1042 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
1043 | usb_hcd_poll_rh_status(hcd); | |
1044 | ||
f69e3120 | 1045 | return retval; |
5535b1d5 | 1046 | } |
b5b5c3ac SS |
1047 | #endif /* CONFIG_PM */ |
1048 | ||
7f84eef0 SS |
1049 | /*-------------------------------------------------------------------------*/ |
1050 | ||
d0e96f5a SS |
1051 | /** |
1052 | * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and | |
1053 | * HCDs. Find the index for an endpoint given its descriptor. Use the return | |
1054 | * value to right shift 1 for the bitmask. | |
1055 | * | |
1056 | * Index = (epnum * 2) + direction - 1, | |
1057 | * where direction = 0 for OUT, 1 for IN. | |
1058 | * For control endpoints, the IN index is used (OUT index is unused), so | |
1059 | * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) | |
1060 | */ | |
1061 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc) | |
1062 | { | |
1063 | unsigned int index; | |
1064 | if (usb_endpoint_xfer_control(desc)) | |
1065 | index = (unsigned int) (usb_endpoint_num(desc)*2); | |
1066 | else | |
1067 | index = (unsigned int) (usb_endpoint_num(desc)*2) + | |
1068 | (usb_endpoint_dir_in(desc) ? 1 : 0) - 1; | |
1069 | return index; | |
1070 | } | |
1071 | ||
01c5f447 JW |
1072 | /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint |
1073 | * address from the XHCI endpoint index. | |
1074 | */ | |
1075 | unsigned int xhci_get_endpoint_address(unsigned int ep_index) | |
1076 | { | |
1077 | unsigned int number = DIV_ROUND_UP(ep_index, 2); | |
1078 | unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN; | |
1079 | return direction | number; | |
1080 | } | |
1081 | ||
f94e0186 SS |
1082 | /* Find the flag for this endpoint (for use in the control context). Use the |
1083 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1084 | * bit 1, etc. | |
1085 | */ | |
1086 | unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc) | |
1087 | { | |
1088 | return 1 << (xhci_get_endpoint_index(desc) + 1); | |
1089 | } | |
1090 | ||
ac9d8fe7 SS |
1091 | /* Find the flag for this endpoint (for use in the control context). Use the |
1092 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1093 | * bit 1, etc. | |
1094 | */ | |
1095 | unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index) | |
1096 | { | |
1097 | return 1 << (ep_index + 1); | |
1098 | } | |
1099 | ||
f94e0186 SS |
1100 | /* Compute the last valid endpoint context index. Basically, this is the |
1101 | * endpoint index plus one. For slot contexts with more than valid endpoint, | |
1102 | * we find the most significant bit set in the added contexts flags. | |
1103 | * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000 | |
1104 | * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one. | |
1105 | */ | |
ac9d8fe7 | 1106 | unsigned int xhci_last_valid_endpoint(u32 added_ctxs) |
f94e0186 SS |
1107 | { |
1108 | return fls(added_ctxs) - 1; | |
1109 | } | |
1110 | ||
d0e96f5a SS |
1111 | /* Returns 1 if the arguments are OK; |
1112 | * returns 0 this is a root hub; returns -EINVAL for NULL pointers. | |
1113 | */ | |
8212a49d | 1114 | static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, |
64927730 AX |
1115 | struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev, |
1116 | const char *func) { | |
1117 | struct xhci_hcd *xhci; | |
1118 | struct xhci_virt_device *virt_dev; | |
1119 | ||
d0e96f5a | 1120 | if (!hcd || (check_ep && !ep) || !udev) { |
5c1127d3 | 1121 | pr_debug("xHCI %s called with invalid args\n", func); |
d0e96f5a SS |
1122 | return -EINVAL; |
1123 | } | |
1124 | if (!udev->parent) { | |
5c1127d3 | 1125 | pr_debug("xHCI %s called for root hub\n", func); |
d0e96f5a SS |
1126 | return 0; |
1127 | } | |
64927730 | 1128 | |
7bd89b40 | 1129 | xhci = hcd_to_xhci(hcd); |
64927730 | 1130 | if (check_virt_dev) { |
73ddc247 | 1131 | if (!udev->slot_id || !xhci->devs[udev->slot_id]) { |
5c1127d3 XR |
1132 | xhci_dbg(xhci, "xHCI %s called with unaddressed device\n", |
1133 | func); | |
64927730 AX |
1134 | return -EINVAL; |
1135 | } | |
1136 | ||
1137 | virt_dev = xhci->devs[udev->slot_id]; | |
1138 | if (virt_dev->udev != udev) { | |
5c1127d3 | 1139 | xhci_dbg(xhci, "xHCI %s called with udev and " |
64927730 AX |
1140 | "virt_dev does not match\n", func); |
1141 | return -EINVAL; | |
1142 | } | |
d0e96f5a | 1143 | } |
64927730 | 1144 | |
203a8661 SS |
1145 | if (xhci->xhc_state & XHCI_STATE_HALTED) |
1146 | return -ENODEV; | |
1147 | ||
d0e96f5a SS |
1148 | return 1; |
1149 | } | |
1150 | ||
2d3f1fac | 1151 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, |
913a8a34 SS |
1152 | struct usb_device *udev, struct xhci_command *command, |
1153 | bool ctx_change, bool must_succeed); | |
2d3f1fac SS |
1154 | |
1155 | /* | |
1156 | * Full speed devices may have a max packet size greater than 8 bytes, but the | |
1157 | * USB core doesn't know that until it reads the first 8 bytes of the | |
1158 | * descriptor. If the usb_device's max packet size changes after that point, | |
1159 | * we need to issue an evaluate context command and wait on it. | |
1160 | */ | |
1161 | static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, | |
1162 | unsigned int ep_index, struct urb *urb) | |
1163 | { | |
1164 | struct xhci_container_ctx *in_ctx; | |
1165 | struct xhci_container_ctx *out_ctx; | |
1166 | struct xhci_input_control_ctx *ctrl_ctx; | |
1167 | struct xhci_ep_ctx *ep_ctx; | |
1168 | int max_packet_size; | |
1169 | int hw_max_packet_size; | |
1170 | int ret = 0; | |
1171 | ||
1172 | out_ctx = xhci->devs[slot_id]->out_ctx; | |
1173 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); | |
28ccd296 | 1174 | hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); |
29cc8897 | 1175 | max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc); |
2d3f1fac | 1176 | if (hw_max_packet_size != max_packet_size) { |
3a7fa5be XR |
1177 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1178 | "Max Packet Size for ep 0 changed."); | |
1179 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, | |
1180 | "Max packet size in usb_device = %d", | |
2d3f1fac | 1181 | max_packet_size); |
3a7fa5be XR |
1182 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1183 | "Max packet size in xHCI HW = %d", | |
2d3f1fac | 1184 | hw_max_packet_size); |
3a7fa5be XR |
1185 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1186 | "Issuing evaluate context command."); | |
2d3f1fac | 1187 | |
92f8e767 SS |
1188 | /* Set up the input context flags for the command */ |
1189 | /* FIXME: This won't work if a non-default control endpoint | |
1190 | * changes max packet sizes. | |
1191 | */ | |
1192 | in_ctx = xhci->devs[slot_id]->in_ctx; | |
1193 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
1194 | if (!ctrl_ctx) { | |
1195 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1196 | __func__); | |
1197 | return -ENOMEM; | |
1198 | } | |
2d3f1fac | 1199 | /* Set up the modified control endpoint 0 */ |
913a8a34 SS |
1200 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
1201 | xhci->devs[slot_id]->out_ctx, ep_index); | |
92f8e767 | 1202 | |
2d3f1fac | 1203 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); |
28ccd296 ME |
1204 | ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK); |
1205 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); | |
2d3f1fac | 1206 | |
28ccd296 | 1207 | ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); |
2d3f1fac SS |
1208 | ctrl_ctx->drop_flags = 0; |
1209 | ||
1210 | xhci_dbg(xhci, "Slot %d input context\n", slot_id); | |
1211 | xhci_dbg_ctx(xhci, in_ctx, ep_index); | |
1212 | xhci_dbg(xhci, "Slot %d output context\n", slot_id); | |
1213 | xhci_dbg_ctx(xhci, out_ctx, ep_index); | |
1214 | ||
913a8a34 SS |
1215 | ret = xhci_configure_endpoint(xhci, urb->dev, NULL, |
1216 | true, false); | |
2d3f1fac SS |
1217 | |
1218 | /* Clean up the input context for later use by bandwidth | |
1219 | * functions. | |
1220 | */ | |
28ccd296 | 1221 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); |
2d3f1fac SS |
1222 | } |
1223 | return ret; | |
1224 | } | |
1225 | ||
d0e96f5a SS |
1226 | /* |
1227 | * non-error returns are a promise to giveback() the urb later | |
1228 | * we drop ownership so next owner (or urb unlink) can get it | |
1229 | */ | |
1230 | int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) | |
1231 | { | |
1232 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
2ffdea25 | 1233 | struct xhci_td *buffer; |
d0e96f5a SS |
1234 | unsigned long flags; |
1235 | int ret = 0; | |
1236 | unsigned int slot_id, ep_index; | |
8e51adcc AX |
1237 | struct urb_priv *urb_priv; |
1238 | int size, i; | |
2d3f1fac | 1239 | |
64927730 AX |
1240 | if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, |
1241 | true, true, __func__) <= 0) | |
d0e96f5a SS |
1242 | return -EINVAL; |
1243 | ||
1244 | slot_id = urb->dev->slot_id; | |
1245 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
d0e96f5a | 1246 | |
541c7d43 | 1247 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
d0e96f5a SS |
1248 | if (!in_interrupt()) |
1249 | xhci_dbg(xhci, "urb submitted during PCI suspend\n"); | |
1250 | ret = -ESHUTDOWN; | |
1251 | goto exit; | |
1252 | } | |
8e51adcc AX |
1253 | |
1254 | if (usb_endpoint_xfer_isoc(&urb->ep->desc)) | |
1255 | size = urb->number_of_packets; | |
1256 | else | |
1257 | size = 1; | |
1258 | ||
1259 | urb_priv = kzalloc(sizeof(struct urb_priv) + | |
1260 | size * sizeof(struct xhci_td *), mem_flags); | |
1261 | if (!urb_priv) | |
1262 | return -ENOMEM; | |
1263 | ||
2ffdea25 AX |
1264 | buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags); |
1265 | if (!buffer) { | |
1266 | kfree(urb_priv); | |
1267 | return -ENOMEM; | |
1268 | } | |
1269 | ||
8e51adcc | 1270 | for (i = 0; i < size; i++) { |
2ffdea25 AX |
1271 | urb_priv->td[i] = buffer; |
1272 | buffer++; | |
8e51adcc AX |
1273 | } |
1274 | ||
1275 | urb_priv->length = size; | |
1276 | urb_priv->td_cnt = 0; | |
1277 | urb->hcpriv = urb_priv; | |
1278 | ||
2d3f1fac SS |
1279 | if (usb_endpoint_xfer_control(&urb->ep->desc)) { |
1280 | /* Check to see if the max packet size for the default control | |
1281 | * endpoint changed during FS device enumeration | |
1282 | */ | |
1283 | if (urb->dev->speed == USB_SPEED_FULL) { | |
1284 | ret = xhci_check_maxpacket(xhci, slot_id, | |
1285 | ep_index, urb); | |
d13565c1 SS |
1286 | if (ret < 0) { |
1287 | xhci_urb_free_priv(xhci, urb_priv); | |
1288 | urb->hcpriv = NULL; | |
2d3f1fac | 1289 | return ret; |
d13565c1 | 1290 | } |
2d3f1fac SS |
1291 | } |
1292 | ||
b11069f5 SS |
1293 | /* We have a spinlock and interrupts disabled, so we must pass |
1294 | * atomic context to this function, which may allocate memory. | |
1295 | */ | |
2d3f1fac | 1296 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
1297 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1298 | goto dying; | |
b11069f5 | 1299 | ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb, |
23e3be11 | 1300 | slot_id, ep_index); |
d13565c1 SS |
1301 | if (ret) |
1302 | goto free_priv; | |
2d3f1fac SS |
1303 | spin_unlock_irqrestore(&xhci->lock, flags); |
1304 | } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) { | |
1305 | spin_lock_irqsave(&xhci->lock, flags); | |
6f5165cf SS |
1306 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1307 | goto dying; | |
8df75f42 SS |
1308 | if (xhci->devs[slot_id]->eps[ep_index].ep_state & |
1309 | EP_GETTING_STREAMS) { | |
1310 | xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep " | |
1311 | "is transitioning to using streams.\n"); | |
1312 | ret = -EINVAL; | |
1313 | } else if (xhci->devs[slot_id]->eps[ep_index].ep_state & | |
1314 | EP_GETTING_NO_STREAMS) { | |
1315 | xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep " | |
1316 | "is transitioning to " | |
1317 | "not having streams.\n"); | |
1318 | ret = -EINVAL; | |
1319 | } else { | |
1320 | ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, | |
1321 | slot_id, ep_index); | |
1322 | } | |
d13565c1 SS |
1323 | if (ret) |
1324 | goto free_priv; | |
2d3f1fac | 1325 | spin_unlock_irqrestore(&xhci->lock, flags); |
624defa1 SS |
1326 | } else if (usb_endpoint_xfer_int(&urb->ep->desc)) { |
1327 | spin_lock_irqsave(&xhci->lock, flags); | |
6f5165cf SS |
1328 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1329 | goto dying; | |
624defa1 SS |
1330 | ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb, |
1331 | slot_id, ep_index); | |
d13565c1 SS |
1332 | if (ret) |
1333 | goto free_priv; | |
624defa1 | 1334 | spin_unlock_irqrestore(&xhci->lock, flags); |
2d3f1fac | 1335 | } else { |
787f4e5a AX |
1336 | spin_lock_irqsave(&xhci->lock, flags); |
1337 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
1338 | goto dying; | |
1339 | ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb, | |
1340 | slot_id, ep_index); | |
d13565c1 SS |
1341 | if (ret) |
1342 | goto free_priv; | |
787f4e5a | 1343 | spin_unlock_irqrestore(&xhci->lock, flags); |
2d3f1fac | 1344 | } |
d0e96f5a | 1345 | exit: |
d0e96f5a | 1346 | return ret; |
6f5165cf SS |
1347 | dying: |
1348 | xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for " | |
1349 | "non-responsive xHCI host.\n", | |
1350 | urb->ep->desc.bEndpointAddress, urb); | |
d13565c1 SS |
1351 | ret = -ESHUTDOWN; |
1352 | free_priv: | |
1353 | xhci_urb_free_priv(xhci, urb_priv); | |
1354 | urb->hcpriv = NULL; | |
6f5165cf | 1355 | spin_unlock_irqrestore(&xhci->lock, flags); |
d13565c1 | 1356 | return ret; |
d0e96f5a SS |
1357 | } |
1358 | ||
021bff91 SS |
1359 | /* Get the right ring for the given URB. |
1360 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
1361 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
1362 | */ | |
1363 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |
1364 | struct urb *urb) | |
1365 | { | |
1366 | unsigned int slot_id; | |
1367 | unsigned int ep_index; | |
1368 | unsigned int stream_id; | |
1369 | struct xhci_virt_ep *ep; | |
1370 | ||
1371 | slot_id = urb->dev->slot_id; | |
1372 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
1373 | stream_id = urb->stream_id; | |
1374 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
1375 | /* Common case: no streams */ | |
1376 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
1377 | return ep->ring; | |
1378 | ||
1379 | if (stream_id == 0) { | |
1380 | xhci_warn(xhci, | |
1381 | "WARN: Slot ID %u, ep index %u has streams, " | |
1382 | "but URB has no stream ID.\n", | |
1383 | slot_id, ep_index); | |
1384 | return NULL; | |
1385 | } | |
1386 | ||
1387 | if (stream_id < ep->stream_info->num_streams) | |
1388 | return ep->stream_info->stream_rings[stream_id]; | |
1389 | ||
1390 | xhci_warn(xhci, | |
1391 | "WARN: Slot ID %u, ep index %u has " | |
1392 | "stream IDs 1 to %u allocated, " | |
1393 | "but stream ID %u is requested.\n", | |
1394 | slot_id, ep_index, | |
1395 | ep->stream_info->num_streams - 1, | |
1396 | stream_id); | |
1397 | return NULL; | |
1398 | } | |
1399 | ||
ae636747 SS |
1400 | /* |
1401 | * Remove the URB's TD from the endpoint ring. This may cause the HC to stop | |
1402 | * USB transfers, potentially stopping in the middle of a TRB buffer. The HC | |
1403 | * should pick up where it left off in the TD, unless a Set Transfer Ring | |
1404 | * Dequeue Pointer is issued. | |
1405 | * | |
1406 | * The TRBs that make up the buffers for the canceled URB will be "removed" from | |
1407 | * the ring. Since the ring is a contiguous structure, they can't be physically | |
1408 | * removed. Instead, there are two options: | |
1409 | * | |
1410 | * 1) If the HC is in the middle of processing the URB to be canceled, we | |
1411 | * simply move the ring's dequeue pointer past those TRBs using the Set | |
1412 | * Transfer Ring Dequeue Pointer command. This will be the common case, | |
1413 | * when drivers timeout on the last submitted URB and attempt to cancel. | |
1414 | * | |
1415 | * 2) If the HC is in the middle of a different TD, we turn the TRBs into a | |
1416 | * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The | |
1417 | * HC will need to invalidate the any TRBs it has cached after the stop | |
1418 | * endpoint command, as noted in the xHCI 0.95 errata. | |
1419 | * | |
1420 | * 3) The TD may have completed by the time the Stop Endpoint Command | |
1421 | * completes, so software needs to handle that case too. | |
1422 | * | |
1423 | * This function should protect against the TD enqueueing code ringing the | |
1424 | * doorbell while this code is waiting for a Stop Endpoint command to complete. | |
1425 | * It also needs to account for multiple cancellations on happening at the same | |
1426 | * time for the same endpoint. | |
1427 | * | |
1428 | * Note that this function can be called in any context, or so says | |
1429 | * usb_hcd_unlink_urb() | |
d0e96f5a SS |
1430 | */ |
1431 | int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | |
1432 | { | |
ae636747 | 1433 | unsigned long flags; |
8e51adcc | 1434 | int ret, i; |
e34b2fbf | 1435 | u32 temp; |
ae636747 | 1436 | struct xhci_hcd *xhci; |
8e51adcc | 1437 | struct urb_priv *urb_priv; |
ae636747 SS |
1438 | struct xhci_td *td; |
1439 | unsigned int ep_index; | |
1440 | struct xhci_ring *ep_ring; | |
63a0d9ab | 1441 | struct xhci_virt_ep *ep; |
ae636747 SS |
1442 | |
1443 | xhci = hcd_to_xhci(hcd); | |
1444 | spin_lock_irqsave(&xhci->lock, flags); | |
1445 | /* Make sure the URB hasn't completed or been unlinked already */ | |
1446 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); | |
1447 | if (ret || !urb->hcpriv) | |
1448 | goto done; | |
e34b2fbf | 1449 | temp = xhci_readl(xhci, &xhci->op_regs->status); |
c6cc27c7 | 1450 | if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) { |
aa50b290 XR |
1451 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1452 | "HW died, freeing TD."); | |
8e51adcc | 1453 | urb_priv = urb->hcpriv; |
585df1d9 SS |
1454 | for (i = urb_priv->td_cnt; i < urb_priv->length; i++) { |
1455 | td = urb_priv->td[i]; | |
1456 | if (!list_empty(&td->td_list)) | |
1457 | list_del_init(&td->td_list); | |
1458 | if (!list_empty(&td->cancelled_td_list)) | |
1459 | list_del_init(&td->cancelled_td_list); | |
1460 | } | |
e34b2fbf SS |
1461 | |
1462 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
1463 | spin_unlock_irqrestore(&xhci->lock, flags); | |
214f76f7 | 1464 | usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN); |
8e51adcc | 1465 | xhci_urb_free_priv(xhci, urb_priv); |
e34b2fbf SS |
1466 | return ret; |
1467 | } | |
7bd89b40 SS |
1468 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
1469 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
aa50b290 XR |
1470 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1471 | "Ep 0x%x: URB %p to be canceled on " | |
1472 | "non-responsive xHCI host.", | |
6f5165cf SS |
1473 | urb->ep->desc.bEndpointAddress, urb); |
1474 | /* Let the stop endpoint command watchdog timer (which set this | |
1475 | * state) finish cleaning up the endpoint TD lists. We must | |
1476 | * have caught it in the middle of dropping a lock and giving | |
1477 | * back an URB. | |
1478 | */ | |
1479 | goto done; | |
1480 | } | |
ae636747 | 1481 | |
ae636747 | 1482 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); |
63a0d9ab | 1483 | ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index]; |
e9df17eb SS |
1484 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
1485 | if (!ep_ring) { | |
1486 | ret = -EINVAL; | |
1487 | goto done; | |
1488 | } | |
1489 | ||
8e51adcc | 1490 | urb_priv = urb->hcpriv; |
79688acf SS |
1491 | i = urb_priv->td_cnt; |
1492 | if (i < urb_priv->length) | |
aa50b290 XR |
1493 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1494 | "Cancel URB %p, dev %s, ep 0x%x, " | |
1495 | "starting at offset 0x%llx", | |
79688acf SS |
1496 | urb, urb->dev->devpath, |
1497 | urb->ep->desc.bEndpointAddress, | |
1498 | (unsigned long long) xhci_trb_virt_to_dma( | |
1499 | urb_priv->td[i]->start_seg, | |
1500 | urb_priv->td[i]->first_trb)); | |
1501 | ||
1502 | for (; i < urb_priv->length; i++) { | |
8e51adcc AX |
1503 | td = urb_priv->td[i]; |
1504 | list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); | |
1505 | } | |
1506 | ||
ae636747 SS |
1507 | /* Queue a stop endpoint command, but only if this is |
1508 | * the first cancellation to be handled. | |
1509 | */ | |
678539cf SS |
1510 | if (!(ep->ep_state & EP_HALT_PENDING)) { |
1511 | ep->ep_state |= EP_HALT_PENDING; | |
6f5165cf SS |
1512 | ep->stop_cmds_pending++; |
1513 | ep->stop_cmd_timer.expires = jiffies + | |
1514 | XHCI_STOP_EP_CMD_TIMEOUT * HZ; | |
1515 | add_timer(&ep->stop_cmd_timer); | |
be88fe4f | 1516 | xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0); |
23e3be11 | 1517 | xhci_ring_cmd_db(xhci); |
ae636747 SS |
1518 | } |
1519 | done: | |
1520 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1521 | return ret; | |
d0e96f5a SS |
1522 | } |
1523 | ||
f94e0186 SS |
1524 | /* Drop an endpoint from a new bandwidth configuration for this device. |
1525 | * Only one call to this function is allowed per endpoint before | |
1526 | * check_bandwidth() or reset_bandwidth() must be called. | |
1527 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1528 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1529 | * different endpoint descriptor in usb_host_endpoint. | |
1530 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1531 | * not allowed. | |
f88ba78d SS |
1532 | * |
1533 | * The USB core will not allow URBs to be queued to an endpoint that is being | |
1534 | * disabled, so there's no need for mutual exclusion to protect | |
1535 | * the xhci->devs[slot_id] structure. | |
f94e0186 SS |
1536 | */ |
1537 | int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |
1538 | struct usb_host_endpoint *ep) | |
1539 | { | |
f94e0186 | 1540 | struct xhci_hcd *xhci; |
d115b048 JY |
1541 | struct xhci_container_ctx *in_ctx, *out_ctx; |
1542 | struct xhci_input_control_ctx *ctrl_ctx; | |
1543 | struct xhci_slot_ctx *slot_ctx; | |
f94e0186 SS |
1544 | unsigned int last_ctx; |
1545 | unsigned int ep_index; | |
1546 | struct xhci_ep_ctx *ep_ctx; | |
1547 | u32 drop_flag; | |
1548 | u32 new_add_flags, new_drop_flags, new_slot_info; | |
1549 | int ret; | |
1550 | ||
64927730 | 1551 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
f94e0186 SS |
1552 | if (ret <= 0) |
1553 | return ret; | |
1554 | xhci = hcd_to_xhci(hcd); | |
fe6c6c13 SS |
1555 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1556 | return -ENODEV; | |
f94e0186 | 1557 | |
fe6c6c13 | 1558 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
1559 | drop_flag = xhci_get_endpoint_flag(&ep->desc); |
1560 | if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { | |
1561 | xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", | |
1562 | __func__, drop_flag); | |
1563 | return 0; | |
1564 | } | |
1565 | ||
f94e0186 | 1566 | in_ctx = xhci->devs[udev->slot_id]->in_ctx; |
d115b048 JY |
1567 | out_ctx = xhci->devs[udev->slot_id]->out_ctx; |
1568 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
92f8e767 SS |
1569 | if (!ctrl_ctx) { |
1570 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1571 | __func__); | |
1572 | return 0; | |
1573 | } | |
1574 | ||
f94e0186 | 1575 | ep_index = xhci_get_endpoint_index(&ep->desc); |
d115b048 | 1576 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
f94e0186 SS |
1577 | /* If the HC already knows the endpoint is disabled, |
1578 | * or the HCD has noted it is disabled, ignore this request | |
1579 | */ | |
f5960b69 ME |
1580 | if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
1581 | cpu_to_le32(EP_STATE_DISABLED)) || | |
28ccd296 ME |
1582 | le32_to_cpu(ctrl_ctx->drop_flags) & |
1583 | xhci_get_endpoint_flag(&ep->desc)) { | |
700e2052 GKH |
1584 | xhci_warn(xhci, "xHCI %s called with disabled ep %p\n", |
1585 | __func__, ep); | |
f94e0186 SS |
1586 | return 0; |
1587 | } | |
1588 | ||
28ccd296 ME |
1589 | ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag); |
1590 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
f94e0186 | 1591 | |
28ccd296 ME |
1592 | ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag); |
1593 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 | 1594 | |
28ccd296 | 1595 | last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)); |
d115b048 | 1596 | slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
f94e0186 | 1597 | /* Update the last valid endpoint context, if we deleted the last one */ |
28ccd296 ME |
1598 | if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) > |
1599 | LAST_CTX(last_ctx)) { | |
1600 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
1601 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx)); | |
f94e0186 | 1602 | } |
28ccd296 | 1603 | new_slot_info = le32_to_cpu(slot_ctx->dev_info); |
f94e0186 SS |
1604 | |
1605 | xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); | |
1606 | ||
f94e0186 SS |
1607 | xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n", |
1608 | (unsigned int) ep->desc.bEndpointAddress, | |
1609 | udev->slot_id, | |
1610 | (unsigned int) new_drop_flags, | |
1611 | (unsigned int) new_add_flags, | |
1612 | (unsigned int) new_slot_info); | |
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | /* Add an endpoint to a new possible bandwidth configuration for this device. | |
1617 | * Only one call to this function is allowed per endpoint before | |
1618 | * check_bandwidth() or reset_bandwidth() must be called. | |
1619 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1620 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1621 | * different endpoint descriptor in usb_host_endpoint. | |
1622 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1623 | * not allowed. | |
f88ba78d SS |
1624 | * |
1625 | * The USB core will not allow URBs to be queued to an endpoint until the | |
1626 | * configuration or alt setting is installed in the device, so there's no need | |
1627 | * for mutual exclusion to protect the xhci->devs[slot_id] structure. | |
f94e0186 SS |
1628 | */ |
1629 | int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |
1630 | struct usb_host_endpoint *ep) | |
1631 | { | |
f94e0186 | 1632 | struct xhci_hcd *xhci; |
d115b048 | 1633 | struct xhci_container_ctx *in_ctx, *out_ctx; |
f94e0186 | 1634 | unsigned int ep_index; |
d115b048 JY |
1635 | struct xhci_slot_ctx *slot_ctx; |
1636 | struct xhci_input_control_ctx *ctrl_ctx; | |
f94e0186 SS |
1637 | u32 added_ctxs; |
1638 | unsigned int last_ctx; | |
1639 | u32 new_add_flags, new_drop_flags, new_slot_info; | |
fa75ac37 | 1640 | struct xhci_virt_device *virt_dev; |
f94e0186 SS |
1641 | int ret = 0; |
1642 | ||
64927730 | 1643 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
a1587d97 SS |
1644 | if (ret <= 0) { |
1645 | /* So we won't queue a reset ep command for a root hub */ | |
1646 | ep->hcpriv = NULL; | |
f94e0186 | 1647 | return ret; |
a1587d97 | 1648 | } |
f94e0186 | 1649 | xhci = hcd_to_xhci(hcd); |
fe6c6c13 SS |
1650 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1651 | return -ENODEV; | |
f94e0186 SS |
1652 | |
1653 | added_ctxs = xhci_get_endpoint_flag(&ep->desc); | |
1654 | last_ctx = xhci_last_valid_endpoint(added_ctxs); | |
1655 | if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) { | |
1656 | /* FIXME when we have to issue an evaluate endpoint command to | |
1657 | * deal with ep0 max packet size changing once we get the | |
1658 | * descriptors | |
1659 | */ | |
1660 | xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n", | |
1661 | __func__, added_ctxs); | |
1662 | return 0; | |
1663 | } | |
1664 | ||
fa75ac37 SS |
1665 | virt_dev = xhci->devs[udev->slot_id]; |
1666 | in_ctx = virt_dev->in_ctx; | |
1667 | out_ctx = virt_dev->out_ctx; | |
d115b048 | 1668 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); |
92f8e767 SS |
1669 | if (!ctrl_ctx) { |
1670 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1671 | __func__); | |
1672 | return 0; | |
1673 | } | |
fa75ac37 | 1674 | |
92f8e767 | 1675 | ep_index = xhci_get_endpoint_index(&ep->desc); |
fa75ac37 SS |
1676 | /* If this endpoint is already in use, and the upper layers are trying |
1677 | * to add it again without dropping it, reject the addition. | |
1678 | */ | |
1679 | if (virt_dev->eps[ep_index].ring && | |
1680 | !(le32_to_cpu(ctrl_ctx->drop_flags) & | |
1681 | xhci_get_endpoint_flag(&ep->desc))) { | |
1682 | xhci_warn(xhci, "Trying to add endpoint 0x%x " | |
1683 | "without dropping it.\n", | |
1684 | (unsigned int) ep->desc.bEndpointAddress); | |
1685 | return -EINVAL; | |
1686 | } | |
1687 | ||
f94e0186 SS |
1688 | /* If the HCD has already noted the endpoint is enabled, |
1689 | * ignore this request. | |
1690 | */ | |
28ccd296 ME |
1691 | if (le32_to_cpu(ctrl_ctx->add_flags) & |
1692 | xhci_get_endpoint_flag(&ep->desc)) { | |
700e2052 GKH |
1693 | xhci_warn(xhci, "xHCI %s called with enabled ep %p\n", |
1694 | __func__, ep); | |
f94e0186 SS |
1695 | return 0; |
1696 | } | |
1697 | ||
f88ba78d SS |
1698 | /* |
1699 | * Configuration and alternate setting changes must be done in | |
1700 | * process context, not interrupt context (or so documenation | |
1701 | * for usb_set_interface() and usb_set_configuration() claim). | |
1702 | */ | |
fa75ac37 | 1703 | if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) { |
f94e0186 SS |
1704 | dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n", |
1705 | __func__, ep->desc.bEndpointAddress); | |
f94e0186 SS |
1706 | return -ENOMEM; |
1707 | } | |
1708 | ||
28ccd296 ME |
1709 | ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs); |
1710 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 SS |
1711 | |
1712 | /* If xhci_endpoint_disable() was called for this endpoint, but the | |
1713 | * xHC hasn't been notified yet through the check_bandwidth() call, | |
1714 | * this re-adds a new state for the endpoint from the new endpoint | |
1715 | * descriptors. We must drop and re-add this endpoint, so we leave the | |
1716 | * drop flags alone. | |
1717 | */ | |
28ccd296 | 1718 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); |
f94e0186 | 1719 | |
d115b048 | 1720 | slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
f94e0186 | 1721 | /* Update the last valid endpoint context, if we just added one past */ |
28ccd296 ME |
1722 | if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) < |
1723 | LAST_CTX(last_ctx)) { | |
1724 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
1725 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx)); | |
f94e0186 | 1726 | } |
28ccd296 | 1727 | new_slot_info = le32_to_cpu(slot_ctx->dev_info); |
f94e0186 | 1728 | |
a1587d97 SS |
1729 | /* Store the usb_device pointer for later use */ |
1730 | ep->hcpriv = udev; | |
1731 | ||
f94e0186 SS |
1732 | xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n", |
1733 | (unsigned int) ep->desc.bEndpointAddress, | |
1734 | udev->slot_id, | |
1735 | (unsigned int) new_drop_flags, | |
1736 | (unsigned int) new_add_flags, | |
1737 | (unsigned int) new_slot_info); | |
1738 | return 0; | |
1739 | } | |
1740 | ||
d115b048 | 1741 | static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev) |
f94e0186 | 1742 | { |
d115b048 | 1743 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1744 | struct xhci_ep_ctx *ep_ctx; |
d115b048 | 1745 | struct xhci_slot_ctx *slot_ctx; |
f94e0186 SS |
1746 | int i; |
1747 | ||
92f8e767 SS |
1748 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
1749 | if (!ctrl_ctx) { | |
1750 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1751 | __func__); | |
1752 | return; | |
1753 | } | |
1754 | ||
f94e0186 SS |
1755 | /* When a device's add flag and drop flag are zero, any subsequent |
1756 | * configure endpoint command will leave that endpoint's state | |
1757 | * untouched. Make sure we don't leave any old state in the input | |
1758 | * endpoint contexts. | |
1759 | */ | |
d115b048 JY |
1760 | ctrl_ctx->drop_flags = 0; |
1761 | ctrl_ctx->add_flags = 0; | |
1762 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); | |
28ccd296 | 1763 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); |
f94e0186 | 1764 | /* Endpoint 0 is always valid */ |
28ccd296 | 1765 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); |
f94e0186 | 1766 | for (i = 1; i < 31; ++i) { |
d115b048 | 1767 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i); |
f94e0186 SS |
1768 | ep_ctx->ep_info = 0; |
1769 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1770 | ep_ctx->deq = 0; |
f94e0186 SS |
1771 | ep_ctx->tx_info = 0; |
1772 | } | |
1773 | } | |
1774 | ||
f2217e8e | 1775 | static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, |
00161f7d | 1776 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1777 | { |
1778 | int ret; | |
1779 | ||
913a8a34 | 1780 | switch (*cmd_status) { |
f2217e8e SS |
1781 | case COMP_ENOMEM: |
1782 | dev_warn(&udev->dev, "Not enough host controller resources " | |
1783 | "for new device state.\n"); | |
1784 | ret = -ENOMEM; | |
1785 | /* FIXME: can we allocate more resources for the HC? */ | |
1786 | break; | |
1787 | case COMP_BW_ERR: | |
71d85724 | 1788 | case COMP_2ND_BW_ERR: |
f2217e8e SS |
1789 | dev_warn(&udev->dev, "Not enough bandwidth " |
1790 | "for new device state.\n"); | |
1791 | ret = -ENOSPC; | |
1792 | /* FIXME: can we go back to the old state? */ | |
1793 | break; | |
1794 | case COMP_TRB_ERR: | |
1795 | /* the HCD set up something wrong */ | |
1796 | dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, " | |
1797 | "add flag = 1, " | |
1798 | "and endpoint is not disabled.\n"); | |
1799 | ret = -EINVAL; | |
1800 | break; | |
f6ba6fe2 AH |
1801 | case COMP_DEV_ERR: |
1802 | dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint " | |
1803 | "configure command.\n"); | |
1804 | ret = -ENODEV; | |
1805 | break; | |
f2217e8e | 1806 | case COMP_SUCCESS: |
3a7fa5be XR |
1807 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1808 | "Successful Endpoint Configure command"); | |
f2217e8e SS |
1809 | ret = 0; |
1810 | break; | |
1811 | default: | |
1812 | xhci_err(xhci, "ERROR: unexpected command completion " | |
913a8a34 | 1813 | "code 0x%x.\n", *cmd_status); |
f2217e8e SS |
1814 | ret = -EINVAL; |
1815 | break; | |
1816 | } | |
1817 | return ret; | |
1818 | } | |
1819 | ||
1820 | static int xhci_evaluate_context_result(struct xhci_hcd *xhci, | |
00161f7d | 1821 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1822 | { |
1823 | int ret; | |
913a8a34 | 1824 | struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id]; |
f2217e8e | 1825 | |
913a8a34 | 1826 | switch (*cmd_status) { |
f2217e8e SS |
1827 | case COMP_EINVAL: |
1828 | dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate " | |
1829 | "context command.\n"); | |
1830 | ret = -EINVAL; | |
1831 | break; | |
1832 | case COMP_EBADSLT: | |
1833 | dev_warn(&udev->dev, "WARN: slot not enabled for" | |
1834 | "evaluate context command.\n"); | |
b8031342 SS |
1835 | ret = -EINVAL; |
1836 | break; | |
f2217e8e SS |
1837 | case COMP_CTX_STATE: |
1838 | dev_warn(&udev->dev, "WARN: invalid context state for " | |
1839 | "evaluate context command.\n"); | |
1840 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1); | |
1841 | ret = -EINVAL; | |
1842 | break; | |
f6ba6fe2 AH |
1843 | case COMP_DEV_ERR: |
1844 | dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate " | |
1845 | "context command.\n"); | |
1846 | ret = -ENODEV; | |
1847 | break; | |
1bb73a88 AH |
1848 | case COMP_MEL_ERR: |
1849 | /* Max Exit Latency too large error */ | |
1850 | dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n"); | |
1851 | ret = -EINVAL; | |
1852 | break; | |
f2217e8e | 1853 | case COMP_SUCCESS: |
3a7fa5be XR |
1854 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1855 | "Successful evaluate context command"); | |
f2217e8e SS |
1856 | ret = 0; |
1857 | break; | |
1858 | default: | |
1859 | xhci_err(xhci, "ERROR: unexpected command completion " | |
913a8a34 | 1860 | "code 0x%x.\n", *cmd_status); |
f2217e8e SS |
1861 | ret = -EINVAL; |
1862 | break; | |
1863 | } | |
1864 | return ret; | |
1865 | } | |
1866 | ||
2cf95c18 | 1867 | static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci, |
92f8e767 | 1868 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1869 | { |
2cf95c18 SS |
1870 | u32 valid_add_flags; |
1871 | u32 valid_drop_flags; | |
1872 | ||
2cf95c18 SS |
1873 | /* Ignore the slot flag (bit 0), and the default control endpoint flag |
1874 | * (bit 1). The default control endpoint is added during the Address | |
1875 | * Device command and is never removed until the slot is disabled. | |
1876 | */ | |
1877 | valid_add_flags = ctrl_ctx->add_flags >> 2; | |
1878 | valid_drop_flags = ctrl_ctx->drop_flags >> 2; | |
1879 | ||
1880 | /* Use hweight32 to count the number of ones in the add flags, or | |
1881 | * number of endpoints added. Don't count endpoints that are changed | |
1882 | * (both added and dropped). | |
1883 | */ | |
1884 | return hweight32(valid_add_flags) - | |
1885 | hweight32(valid_add_flags & valid_drop_flags); | |
1886 | } | |
1887 | ||
1888 | static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci, | |
92f8e767 | 1889 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1890 | { |
2cf95c18 SS |
1891 | u32 valid_add_flags; |
1892 | u32 valid_drop_flags; | |
1893 | ||
2cf95c18 SS |
1894 | valid_add_flags = ctrl_ctx->add_flags >> 2; |
1895 | valid_drop_flags = ctrl_ctx->drop_flags >> 2; | |
1896 | ||
1897 | return hweight32(valid_drop_flags) - | |
1898 | hweight32(valid_add_flags & valid_drop_flags); | |
1899 | } | |
1900 | ||
1901 | /* | |
1902 | * We need to reserve the new number of endpoints before the configure endpoint | |
1903 | * command completes. We can't subtract the dropped endpoints from the number | |
1904 | * of active endpoints until the command completes because we can oversubscribe | |
1905 | * the host in this case: | |
1906 | * | |
1907 | * - the first configure endpoint command drops more endpoints than it adds | |
1908 | * - a second configure endpoint command that adds more endpoints is queued | |
1909 | * - the first configure endpoint command fails, so the config is unchanged | |
1910 | * - the second command may succeed, even though there isn't enough resources | |
1911 | * | |
1912 | * Must be called with xhci->lock held. | |
1913 | */ | |
1914 | static int xhci_reserve_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1915 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1916 | { |
1917 | u32 added_eps; | |
1918 | ||
92f8e767 | 1919 | added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1920 | if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) { |
4bdfe4c3 XR |
1921 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1922 | "Not enough ep ctxs: " | |
1923 | "%u active, need to add %u, limit is %u.", | |
2cf95c18 SS |
1924 | xhci->num_active_eps, added_eps, |
1925 | xhci->limit_active_eps); | |
1926 | return -ENOMEM; | |
1927 | } | |
1928 | xhci->num_active_eps += added_eps; | |
4bdfe4c3 XR |
1929 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1930 | "Adding %u ep ctxs, %u now active.", added_eps, | |
2cf95c18 SS |
1931 | xhci->num_active_eps); |
1932 | return 0; | |
1933 | } | |
1934 | ||
1935 | /* | |
1936 | * The configure endpoint was failed by the xHC for some other reason, so we | |
1937 | * need to revert the resources that failed configuration would have used. | |
1938 | * | |
1939 | * Must be called with xhci->lock held. | |
1940 | */ | |
1941 | static void xhci_free_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1942 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1943 | { |
1944 | u32 num_failed_eps; | |
1945 | ||
92f8e767 | 1946 | num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1947 | xhci->num_active_eps -= num_failed_eps; |
4bdfe4c3 XR |
1948 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1949 | "Removing %u failed ep ctxs, %u now active.", | |
2cf95c18 SS |
1950 | num_failed_eps, |
1951 | xhci->num_active_eps); | |
1952 | } | |
1953 | ||
1954 | /* | |
1955 | * Now that the command has completed, clean up the active endpoint count by | |
1956 | * subtracting out the endpoints that were dropped (but not changed). | |
1957 | * | |
1958 | * Must be called with xhci->lock held. | |
1959 | */ | |
1960 | static void xhci_finish_resource_reservation(struct xhci_hcd *xhci, | |
92f8e767 | 1961 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1962 | { |
1963 | u32 num_dropped_eps; | |
1964 | ||
92f8e767 | 1965 | num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx); |
2cf95c18 SS |
1966 | xhci->num_active_eps -= num_dropped_eps; |
1967 | if (num_dropped_eps) | |
4bdfe4c3 XR |
1968 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1969 | "Removing %u dropped ep ctxs, %u now active.", | |
2cf95c18 SS |
1970 | num_dropped_eps, |
1971 | xhci->num_active_eps); | |
1972 | } | |
1973 | ||
ed384bd3 | 1974 | static unsigned int xhci_get_block_size(struct usb_device *udev) |
c29eea62 SS |
1975 | { |
1976 | switch (udev->speed) { | |
1977 | case USB_SPEED_LOW: | |
1978 | case USB_SPEED_FULL: | |
1979 | return FS_BLOCK; | |
1980 | case USB_SPEED_HIGH: | |
1981 | return HS_BLOCK; | |
1982 | case USB_SPEED_SUPER: | |
1983 | return SS_BLOCK; | |
1984 | case USB_SPEED_UNKNOWN: | |
1985 | case USB_SPEED_WIRELESS: | |
1986 | default: | |
1987 | /* Should never happen */ | |
1988 | return 1; | |
1989 | } | |
1990 | } | |
1991 | ||
ed384bd3 FB |
1992 | static unsigned int |
1993 | xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw) | |
c29eea62 SS |
1994 | { |
1995 | if (interval_bw->overhead[LS_OVERHEAD_TYPE]) | |
1996 | return LS_OVERHEAD; | |
1997 | if (interval_bw->overhead[FS_OVERHEAD_TYPE]) | |
1998 | return FS_OVERHEAD; | |
1999 | return HS_OVERHEAD; | |
2000 | } | |
2001 | ||
2002 | /* If we are changing a LS/FS device under a HS hub, | |
2003 | * make sure (if we are activating a new TT) that the HS bus has enough | |
2004 | * bandwidth for this new TT. | |
2005 | */ | |
2006 | static int xhci_check_tt_bw_table(struct xhci_hcd *xhci, | |
2007 | struct xhci_virt_device *virt_dev, | |
2008 | int old_active_eps) | |
2009 | { | |
2010 | struct xhci_interval_bw_table *bw_table; | |
2011 | struct xhci_tt_bw_info *tt_info; | |
2012 | ||
2013 | /* Find the bandwidth table for the root port this TT is attached to. */ | |
2014 | bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table; | |
2015 | tt_info = virt_dev->tt_info; | |
2016 | /* If this TT already had active endpoints, the bandwidth for this TT | |
2017 | * has already been added. Removing all periodic endpoints (and thus | |
2018 | * making the TT enactive) will only decrease the bandwidth used. | |
2019 | */ | |
2020 | if (old_active_eps) | |
2021 | return 0; | |
2022 | if (old_active_eps == 0 && tt_info->active_eps != 0) { | |
2023 | if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT) | |
2024 | return -ENOMEM; | |
2025 | return 0; | |
2026 | } | |
2027 | /* Not sure why we would have no new active endpoints... | |
2028 | * | |
2029 | * Maybe because of an Evaluate Context change for a hub update or a | |
2030 | * control endpoint 0 max packet size change? | |
2031 | * FIXME: skip the bandwidth calculation in that case. | |
2032 | */ | |
2033 | return 0; | |
2034 | } | |
2035 | ||
2b698999 SS |
2036 | static int xhci_check_ss_bw(struct xhci_hcd *xhci, |
2037 | struct xhci_virt_device *virt_dev) | |
2038 | { | |
2039 | unsigned int bw_reserved; | |
2040 | ||
2041 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100); | |
2042 | if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved)) | |
2043 | return -ENOMEM; | |
2044 | ||
2045 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100); | |
2046 | if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved)) | |
2047 | return -ENOMEM; | |
2048 | ||
2049 | return 0; | |
2050 | } | |
2051 | ||
c29eea62 SS |
2052 | /* |
2053 | * This algorithm is a very conservative estimate of the worst-case scheduling | |
2054 | * scenario for any one interval. The hardware dynamically schedules the | |
2055 | * packets, so we can't tell which microframe could be the limiting factor in | |
2056 | * the bandwidth scheduling. This only takes into account periodic endpoints. | |
2057 | * | |
2058 | * Obviously, we can't solve an NP complete problem to find the minimum worst | |
2059 | * case scenario. Instead, we come up with an estimate that is no less than | |
2060 | * the worst case bandwidth used for any one microframe, but may be an | |
2061 | * over-estimate. | |
2062 | * | |
2063 | * We walk the requirements for each endpoint by interval, starting with the | |
2064 | * smallest interval, and place packets in the schedule where there is only one | |
2065 | * possible way to schedule packets for that interval. In order to simplify | |
2066 | * this algorithm, we record the largest max packet size for each interval, and | |
2067 | * assume all packets will be that size. | |
2068 | * | |
2069 | * For interval 0, we obviously must schedule all packets for each interval. | |
2070 | * The bandwidth for interval 0 is just the amount of data to be transmitted | |
2071 | * (the sum of all max ESIT payload sizes, plus any overhead per packet times | |
2072 | * the number of packets). | |
2073 | * | |
2074 | * For interval 1, we have two possible microframes to schedule those packets | |
2075 | * in. For this algorithm, if we can schedule the same number of packets for | |
2076 | * each possible scheduling opportunity (each microframe), we will do so. The | |
2077 | * remaining number of packets will be saved to be transmitted in the gaps in | |
2078 | * the next interval's scheduling sequence. | |
2079 | * | |
2080 | * As we move those remaining packets to be scheduled with interval 2 packets, | |
2081 | * we have to double the number of remaining packets to transmit. This is | |
2082 | * because the intervals are actually powers of 2, and we would be transmitting | |
2083 | * the previous interval's packets twice in this interval. We also have to be | |
2084 | * sure that when we look at the largest max packet size for this interval, we | |
2085 | * also look at the largest max packet size for the remaining packets and take | |
2086 | * the greater of the two. | |
2087 | * | |
2088 | * The algorithm continues to evenly distribute packets in each scheduling | |
2089 | * opportunity, and push the remaining packets out, until we get to the last | |
2090 | * interval. Then those packets and their associated overhead are just added | |
2091 | * to the bandwidth used. | |
2e27980e SS |
2092 | */ |
2093 | static int xhci_check_bw_table(struct xhci_hcd *xhci, | |
2094 | struct xhci_virt_device *virt_dev, | |
2095 | int old_active_eps) | |
2096 | { | |
c29eea62 SS |
2097 | unsigned int bw_reserved; |
2098 | unsigned int max_bandwidth; | |
2099 | unsigned int bw_used; | |
2100 | unsigned int block_size; | |
2101 | struct xhci_interval_bw_table *bw_table; | |
2102 | unsigned int packet_size = 0; | |
2103 | unsigned int overhead = 0; | |
2104 | unsigned int packets_transmitted = 0; | |
2105 | unsigned int packets_remaining = 0; | |
2106 | unsigned int i; | |
2107 | ||
2b698999 SS |
2108 | if (virt_dev->udev->speed == USB_SPEED_SUPER) |
2109 | return xhci_check_ss_bw(xhci, virt_dev); | |
2110 | ||
c29eea62 SS |
2111 | if (virt_dev->udev->speed == USB_SPEED_HIGH) { |
2112 | max_bandwidth = HS_BW_LIMIT; | |
2113 | /* Convert percent of bus BW reserved to blocks reserved */ | |
2114 | bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100); | |
2115 | } else { | |
2116 | max_bandwidth = FS_BW_LIMIT; | |
2117 | bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100); | |
2118 | } | |
2119 | ||
2120 | bw_table = virt_dev->bw_table; | |
2121 | /* We need to translate the max packet size and max ESIT payloads into | |
2122 | * the units the hardware uses. | |
2123 | */ | |
2124 | block_size = xhci_get_block_size(virt_dev->udev); | |
2125 | ||
2126 | /* If we are manipulating a LS/FS device under a HS hub, double check | |
2127 | * that the HS bus has enough bandwidth if we are activing a new TT. | |
2128 | */ | |
2129 | if (virt_dev->tt_info) { | |
4bdfe4c3 XR |
2130 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2131 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2132 | virt_dev->real_port); |
2133 | if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) { | |
2134 | xhci_warn(xhci, "Not enough bandwidth on HS bus for " | |
2135 | "newly activated TT.\n"); | |
2136 | return -ENOMEM; | |
2137 | } | |
4bdfe4c3 XR |
2138 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2139 | "Recalculating BW for TT slot %u port %u", | |
c29eea62 SS |
2140 | virt_dev->tt_info->slot_id, |
2141 | virt_dev->tt_info->ttport); | |
2142 | } else { | |
4bdfe4c3 XR |
2143 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2144 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2145 | virt_dev->real_port); |
2146 | } | |
2147 | ||
2148 | /* Add in how much bandwidth will be used for interval zero, or the | |
2149 | * rounded max ESIT payload + number of packets * largest overhead. | |
2150 | */ | |
2151 | bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) + | |
2152 | bw_table->interval_bw[0].num_packets * | |
2153 | xhci_get_largest_overhead(&bw_table->interval_bw[0]); | |
2154 | ||
2155 | for (i = 1; i < XHCI_MAX_INTERVAL; i++) { | |
2156 | unsigned int bw_added; | |
2157 | unsigned int largest_mps; | |
2158 | unsigned int interval_overhead; | |
2159 | ||
2160 | /* | |
2161 | * How many packets could we transmit in this interval? | |
2162 | * If packets didn't fit in the previous interval, we will need | |
2163 | * to transmit that many packets twice within this interval. | |
2164 | */ | |
2165 | packets_remaining = 2 * packets_remaining + | |
2166 | bw_table->interval_bw[i].num_packets; | |
2167 | ||
2168 | /* Find the largest max packet size of this or the previous | |
2169 | * interval. | |
2170 | */ | |
2171 | if (list_empty(&bw_table->interval_bw[i].endpoints)) | |
2172 | largest_mps = 0; | |
2173 | else { | |
2174 | struct xhci_virt_ep *virt_ep; | |
2175 | struct list_head *ep_entry; | |
2176 | ||
2177 | ep_entry = bw_table->interval_bw[i].endpoints.next; | |
2178 | virt_ep = list_entry(ep_entry, | |
2179 | struct xhci_virt_ep, bw_endpoint_list); | |
2180 | /* Convert to blocks, rounding up */ | |
2181 | largest_mps = DIV_ROUND_UP( | |
2182 | virt_ep->bw_info.max_packet_size, | |
2183 | block_size); | |
2184 | } | |
2185 | if (largest_mps > packet_size) | |
2186 | packet_size = largest_mps; | |
2187 | ||
2188 | /* Use the larger overhead of this or the previous interval. */ | |
2189 | interval_overhead = xhci_get_largest_overhead( | |
2190 | &bw_table->interval_bw[i]); | |
2191 | if (interval_overhead > overhead) | |
2192 | overhead = interval_overhead; | |
2193 | ||
2194 | /* How many packets can we evenly distribute across | |
2195 | * (1 << (i + 1)) possible scheduling opportunities? | |
2196 | */ | |
2197 | packets_transmitted = packets_remaining >> (i + 1); | |
2198 | ||
2199 | /* Add in the bandwidth used for those scheduled packets */ | |
2200 | bw_added = packets_transmitted * (overhead + packet_size); | |
2201 | ||
2202 | /* How many packets do we have remaining to transmit? */ | |
2203 | packets_remaining = packets_remaining % (1 << (i + 1)); | |
2204 | ||
2205 | /* What largest max packet size should those packets have? */ | |
2206 | /* If we've transmitted all packets, don't carry over the | |
2207 | * largest packet size. | |
2208 | */ | |
2209 | if (packets_remaining == 0) { | |
2210 | packet_size = 0; | |
2211 | overhead = 0; | |
2212 | } else if (packets_transmitted > 0) { | |
2213 | /* Otherwise if we do have remaining packets, and we've | |
2214 | * scheduled some packets in this interval, take the | |
2215 | * largest max packet size from endpoints with this | |
2216 | * interval. | |
2217 | */ | |
2218 | packet_size = largest_mps; | |
2219 | overhead = interval_overhead; | |
2220 | } | |
2221 | /* Otherwise carry over packet_size and overhead from the last | |
2222 | * time we had a remainder. | |
2223 | */ | |
2224 | bw_used += bw_added; | |
2225 | if (bw_used > max_bandwidth) { | |
2226 | xhci_warn(xhci, "Not enough bandwidth. " | |
2227 | "Proposed: %u, Max: %u\n", | |
2228 | bw_used, max_bandwidth); | |
2229 | return -ENOMEM; | |
2230 | } | |
2231 | } | |
2232 | /* | |
2233 | * Ok, we know we have some packets left over after even-handedly | |
2234 | * scheduling interval 15. We don't know which microframes they will | |
2235 | * fit into, so we over-schedule and say they will be scheduled every | |
2236 | * microframe. | |
2237 | */ | |
2238 | if (packets_remaining > 0) | |
2239 | bw_used += overhead + packet_size; | |
2240 | ||
2241 | if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) { | |
2242 | unsigned int port_index = virt_dev->real_port - 1; | |
2243 | ||
2244 | /* OK, we're manipulating a HS device attached to a | |
2245 | * root port bandwidth domain. Include the number of active TTs | |
2246 | * in the bandwidth used. | |
2247 | */ | |
2248 | bw_used += TT_HS_OVERHEAD * | |
2249 | xhci->rh_bw[port_index].num_active_tts; | |
2250 | } | |
2251 | ||
4bdfe4c3 XR |
2252 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2253 | "Final bandwidth: %u, Limit: %u, Reserved: %u, " | |
2254 | "Available: %u " "percent", | |
c29eea62 SS |
2255 | bw_used, max_bandwidth, bw_reserved, |
2256 | (max_bandwidth - bw_used - bw_reserved) * 100 / | |
2257 | max_bandwidth); | |
2258 | ||
2259 | bw_used += bw_reserved; | |
2260 | if (bw_used > max_bandwidth) { | |
2261 | xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n", | |
2262 | bw_used, max_bandwidth); | |
2263 | return -ENOMEM; | |
2264 | } | |
2265 | ||
2266 | bw_table->bw_used = bw_used; | |
2e27980e SS |
2267 | return 0; |
2268 | } | |
2269 | ||
2270 | static bool xhci_is_async_ep(unsigned int ep_type) | |
2271 | { | |
2272 | return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
2273 | ep_type != ISOC_IN_EP && | |
2274 | ep_type != INT_IN_EP); | |
2275 | } | |
2276 | ||
2b698999 SS |
2277 | static bool xhci_is_sync_in_ep(unsigned int ep_type) |
2278 | { | |
392a07ae | 2279 | return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP); |
2b698999 SS |
2280 | } |
2281 | ||
2282 | static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw) | |
2283 | { | |
2284 | unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK); | |
2285 | ||
2286 | if (ep_bw->ep_interval == 0) | |
2287 | return SS_OVERHEAD_BURST + | |
2288 | (ep_bw->mult * ep_bw->num_packets * | |
2289 | (SS_OVERHEAD + mps)); | |
2290 | return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets * | |
2291 | (SS_OVERHEAD + mps + SS_OVERHEAD_BURST), | |
2292 | 1 << ep_bw->ep_interval); | |
2293 | ||
2294 | } | |
2295 | ||
2e27980e SS |
2296 | void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, |
2297 | struct xhci_bw_info *ep_bw, | |
2298 | struct xhci_interval_bw_table *bw_table, | |
2299 | struct usb_device *udev, | |
2300 | struct xhci_virt_ep *virt_ep, | |
2301 | struct xhci_tt_bw_info *tt_info) | |
2302 | { | |
2303 | struct xhci_interval_bw *interval_bw; | |
2304 | int normalized_interval; | |
2305 | ||
2b698999 | 2306 | if (xhci_is_async_ep(ep_bw->type)) |
2e27980e SS |
2307 | return; |
2308 | ||
2b698999 SS |
2309 | if (udev->speed == USB_SPEED_SUPER) { |
2310 | if (xhci_is_sync_in_ep(ep_bw->type)) | |
2311 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in -= | |
2312 | xhci_get_ss_bw_consumed(ep_bw); | |
2313 | else | |
2314 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out -= | |
2315 | xhci_get_ss_bw_consumed(ep_bw); | |
2316 | return; | |
2317 | } | |
2318 | ||
2319 | /* SuperSpeed endpoints never get added to intervals in the table, so | |
2320 | * this check is only valid for HS/FS/LS devices. | |
2321 | */ | |
2322 | if (list_empty(&virt_ep->bw_endpoint_list)) | |
2323 | return; | |
2e27980e SS |
2324 | /* For LS/FS devices, we need to translate the interval expressed in |
2325 | * microframes to frames. | |
2326 | */ | |
2327 | if (udev->speed == USB_SPEED_HIGH) | |
2328 | normalized_interval = ep_bw->ep_interval; | |
2329 | else | |
2330 | normalized_interval = ep_bw->ep_interval - 3; | |
2331 | ||
2332 | if (normalized_interval == 0) | |
2333 | bw_table->interval0_esit_payload -= ep_bw->max_esit_payload; | |
2334 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2335 | interval_bw->num_packets -= ep_bw->num_packets; | |
2336 | switch (udev->speed) { | |
2337 | case USB_SPEED_LOW: | |
2338 | interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1; | |
2339 | break; | |
2340 | case USB_SPEED_FULL: | |
2341 | interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1; | |
2342 | break; | |
2343 | case USB_SPEED_HIGH: | |
2344 | interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1; | |
2345 | break; | |
2346 | case USB_SPEED_SUPER: | |
2347 | case USB_SPEED_UNKNOWN: | |
2348 | case USB_SPEED_WIRELESS: | |
2349 | /* Should never happen because only LS/FS/HS endpoints will get | |
2350 | * added to the endpoint list. | |
2351 | */ | |
2352 | return; | |
2353 | } | |
2354 | if (tt_info) | |
2355 | tt_info->active_eps -= 1; | |
2356 | list_del_init(&virt_ep->bw_endpoint_list); | |
2357 | } | |
2358 | ||
2359 | static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci, | |
2360 | struct xhci_bw_info *ep_bw, | |
2361 | struct xhci_interval_bw_table *bw_table, | |
2362 | struct usb_device *udev, | |
2363 | struct xhci_virt_ep *virt_ep, | |
2364 | struct xhci_tt_bw_info *tt_info) | |
2365 | { | |
2366 | struct xhci_interval_bw *interval_bw; | |
2367 | struct xhci_virt_ep *smaller_ep; | |
2368 | int normalized_interval; | |
2369 | ||
2370 | if (xhci_is_async_ep(ep_bw->type)) | |
2371 | return; | |
2372 | ||
2b698999 SS |
2373 | if (udev->speed == USB_SPEED_SUPER) { |
2374 | if (xhci_is_sync_in_ep(ep_bw->type)) | |
2375 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in += | |
2376 | xhci_get_ss_bw_consumed(ep_bw); | |
2377 | else | |
2378 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out += | |
2379 | xhci_get_ss_bw_consumed(ep_bw); | |
2380 | return; | |
2381 | } | |
2382 | ||
2e27980e SS |
2383 | /* For LS/FS devices, we need to translate the interval expressed in |
2384 | * microframes to frames. | |
2385 | */ | |
2386 | if (udev->speed == USB_SPEED_HIGH) | |
2387 | normalized_interval = ep_bw->ep_interval; | |
2388 | else | |
2389 | normalized_interval = ep_bw->ep_interval - 3; | |
2390 | ||
2391 | if (normalized_interval == 0) | |
2392 | bw_table->interval0_esit_payload += ep_bw->max_esit_payload; | |
2393 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2394 | interval_bw->num_packets += ep_bw->num_packets; | |
2395 | switch (udev->speed) { | |
2396 | case USB_SPEED_LOW: | |
2397 | interval_bw->overhead[LS_OVERHEAD_TYPE] += 1; | |
2398 | break; | |
2399 | case USB_SPEED_FULL: | |
2400 | interval_bw->overhead[FS_OVERHEAD_TYPE] += 1; | |
2401 | break; | |
2402 | case USB_SPEED_HIGH: | |
2403 | interval_bw->overhead[HS_OVERHEAD_TYPE] += 1; | |
2404 | break; | |
2405 | case USB_SPEED_SUPER: | |
2406 | case USB_SPEED_UNKNOWN: | |
2407 | case USB_SPEED_WIRELESS: | |
2408 | /* Should never happen because only LS/FS/HS endpoints will get | |
2409 | * added to the endpoint list. | |
2410 | */ | |
2411 | return; | |
2412 | } | |
2413 | ||
2414 | if (tt_info) | |
2415 | tt_info->active_eps += 1; | |
2416 | /* Insert the endpoint into the list, largest max packet size first. */ | |
2417 | list_for_each_entry(smaller_ep, &interval_bw->endpoints, | |
2418 | bw_endpoint_list) { | |
2419 | if (ep_bw->max_packet_size >= | |
2420 | smaller_ep->bw_info.max_packet_size) { | |
2421 | /* Add the new ep before the smaller endpoint */ | |
2422 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2423 | &smaller_ep->bw_endpoint_list); | |
2424 | return; | |
2425 | } | |
2426 | } | |
2427 | /* Add the new endpoint at the end of the list. */ | |
2428 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2429 | &interval_bw->endpoints); | |
2430 | } | |
2431 | ||
2432 | void xhci_update_tt_active_eps(struct xhci_hcd *xhci, | |
2433 | struct xhci_virt_device *virt_dev, | |
2434 | int old_active_eps) | |
2435 | { | |
2436 | struct xhci_root_port_bw_info *rh_bw_info; | |
2437 | if (!virt_dev->tt_info) | |
2438 | return; | |
2439 | ||
2440 | rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1]; | |
2441 | if (old_active_eps == 0 && | |
2442 | virt_dev->tt_info->active_eps != 0) { | |
2443 | rh_bw_info->num_active_tts += 1; | |
c29eea62 | 2444 | rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD; |
2e27980e SS |
2445 | } else if (old_active_eps != 0 && |
2446 | virt_dev->tt_info->active_eps == 0) { | |
2447 | rh_bw_info->num_active_tts -= 1; | |
c29eea62 | 2448 | rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD; |
2e27980e SS |
2449 | } |
2450 | } | |
2451 | ||
2452 | static int xhci_reserve_bandwidth(struct xhci_hcd *xhci, | |
2453 | struct xhci_virt_device *virt_dev, | |
2454 | struct xhci_container_ctx *in_ctx) | |
2455 | { | |
2456 | struct xhci_bw_info ep_bw_info[31]; | |
2457 | int i; | |
2458 | struct xhci_input_control_ctx *ctrl_ctx; | |
2459 | int old_active_eps = 0; | |
2460 | ||
2e27980e SS |
2461 | if (virt_dev->tt_info) |
2462 | old_active_eps = virt_dev->tt_info->active_eps; | |
2463 | ||
2464 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
92f8e767 SS |
2465 | if (!ctrl_ctx) { |
2466 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2467 | __func__); | |
2468 | return -ENOMEM; | |
2469 | } | |
2e27980e SS |
2470 | |
2471 | for (i = 0; i < 31; i++) { | |
2472 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2473 | continue; | |
2474 | ||
2475 | /* Make a copy of the BW info in case we need to revert this */ | |
2476 | memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info, | |
2477 | sizeof(ep_bw_info[i])); | |
2478 | /* Drop the endpoint from the interval table if the endpoint is | |
2479 | * being dropped or changed. | |
2480 | */ | |
2481 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2482 | xhci_drop_ep_from_interval_table(xhci, | |
2483 | &virt_dev->eps[i].bw_info, | |
2484 | virt_dev->bw_table, | |
2485 | virt_dev->udev, | |
2486 | &virt_dev->eps[i], | |
2487 | virt_dev->tt_info); | |
2488 | } | |
2489 | /* Overwrite the information stored in the endpoints' bw_info */ | |
2490 | xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev); | |
2491 | for (i = 0; i < 31; i++) { | |
2492 | /* Add any changed or added endpoints to the interval table */ | |
2493 | if (EP_IS_ADDED(ctrl_ctx, i)) | |
2494 | xhci_add_ep_to_interval_table(xhci, | |
2495 | &virt_dev->eps[i].bw_info, | |
2496 | virt_dev->bw_table, | |
2497 | virt_dev->udev, | |
2498 | &virt_dev->eps[i], | |
2499 | virt_dev->tt_info); | |
2500 | } | |
2501 | ||
2502 | if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) { | |
2503 | /* Ok, this fits in the bandwidth we have. | |
2504 | * Update the number of active TTs. | |
2505 | */ | |
2506 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
2507 | return 0; | |
2508 | } | |
2509 | ||
2510 | /* We don't have enough bandwidth for this, revert the stored info. */ | |
2511 | for (i = 0; i < 31; i++) { | |
2512 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2513 | continue; | |
2514 | ||
2515 | /* Drop the new copies of any added or changed endpoints from | |
2516 | * the interval table. | |
2517 | */ | |
2518 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
2519 | xhci_drop_ep_from_interval_table(xhci, | |
2520 | &virt_dev->eps[i].bw_info, | |
2521 | virt_dev->bw_table, | |
2522 | virt_dev->udev, | |
2523 | &virt_dev->eps[i], | |
2524 | virt_dev->tt_info); | |
2525 | } | |
2526 | /* Revert the endpoint back to its old information */ | |
2527 | memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i], | |
2528 | sizeof(ep_bw_info[i])); | |
2529 | /* Add any changed or dropped endpoints back into the table */ | |
2530 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2531 | xhci_add_ep_to_interval_table(xhci, | |
2532 | &virt_dev->eps[i].bw_info, | |
2533 | virt_dev->bw_table, | |
2534 | virt_dev->udev, | |
2535 | &virt_dev->eps[i], | |
2536 | virt_dev->tt_info); | |
2537 | } | |
2538 | return -ENOMEM; | |
2539 | } | |
2540 | ||
2541 | ||
f2217e8e SS |
2542 | /* Issue a configure endpoint command or evaluate context command |
2543 | * and wait for it to finish. | |
2544 | */ | |
2545 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |
913a8a34 SS |
2546 | struct usb_device *udev, |
2547 | struct xhci_command *command, | |
2548 | bool ctx_change, bool must_succeed) | |
f2217e8e SS |
2549 | { |
2550 | int ret; | |
2551 | int timeleft; | |
2552 | unsigned long flags; | |
913a8a34 | 2553 | struct xhci_container_ctx *in_ctx; |
92f8e767 | 2554 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 2555 | struct completion *cmd_completion; |
28ccd296 | 2556 | u32 *cmd_status; |
913a8a34 | 2557 | struct xhci_virt_device *virt_dev; |
6e4468b9 | 2558 | union xhci_trb *cmd_trb; |
f2217e8e SS |
2559 | |
2560 | spin_lock_irqsave(&xhci->lock, flags); | |
913a8a34 | 2561 | virt_dev = xhci->devs[udev->slot_id]; |
750645f8 SS |
2562 | |
2563 | if (command) | |
913a8a34 | 2564 | in_ctx = command->in_ctx; |
750645f8 SS |
2565 | else |
2566 | in_ctx = virt_dev->in_ctx; | |
92f8e767 SS |
2567 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); |
2568 | if (!ctrl_ctx) { | |
1f21569c | 2569 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
2570 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
2571 | __func__); | |
2572 | return -ENOMEM; | |
2573 | } | |
2cf95c18 | 2574 | |
750645f8 | 2575 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && |
92f8e767 | 2576 | xhci_reserve_host_resources(xhci, ctrl_ctx)) { |
750645f8 SS |
2577 | spin_unlock_irqrestore(&xhci->lock, flags); |
2578 | xhci_warn(xhci, "Not enough host resources, " | |
2579 | "active endpoint contexts = %u\n", | |
2580 | xhci->num_active_eps); | |
2581 | return -ENOMEM; | |
2582 | } | |
2e27980e SS |
2583 | if ((xhci->quirks & XHCI_SW_BW_CHECKING) && |
2584 | xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) { | |
2585 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) | |
92f8e767 | 2586 | xhci_free_host_resources(xhci, ctrl_ctx); |
2e27980e SS |
2587 | spin_unlock_irqrestore(&xhci->lock, flags); |
2588 | xhci_warn(xhci, "Not enough bandwidth\n"); | |
2589 | return -ENOMEM; | |
2590 | } | |
750645f8 SS |
2591 | |
2592 | if (command) { | |
913a8a34 SS |
2593 | cmd_completion = command->completion; |
2594 | cmd_status = &command->status; | |
2595 | command->command_trb = xhci->cmd_ring->enqueue; | |
7a3783ef PZ |
2596 | |
2597 | /* Enqueue pointer can be left pointing to the link TRB, | |
2598 | * we must handle that | |
2599 | */ | |
f5960b69 | 2600 | if (TRB_TYPE_LINK_LE32(command->command_trb->link.control)) |
7a3783ef PZ |
2601 | command->command_trb = |
2602 | xhci->cmd_ring->enq_seg->next->trbs; | |
2603 | ||
913a8a34 SS |
2604 | list_add_tail(&command->cmd_list, &virt_dev->cmd_list); |
2605 | } else { | |
913a8a34 SS |
2606 | cmd_completion = &virt_dev->cmd_completion; |
2607 | cmd_status = &virt_dev->cmd_status; | |
2608 | } | |
1d68064a | 2609 | init_completion(cmd_completion); |
913a8a34 | 2610 | |
6e4468b9 | 2611 | cmd_trb = xhci->cmd_ring->dequeue; |
f2217e8e | 2612 | if (!ctx_change) |
913a8a34 SS |
2613 | ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma, |
2614 | udev->slot_id, must_succeed); | |
f2217e8e | 2615 | else |
913a8a34 | 2616 | ret = xhci_queue_evaluate_context(xhci, in_ctx->dma, |
4b266541 | 2617 | udev->slot_id, must_succeed); |
f2217e8e | 2618 | if (ret < 0) { |
c01591bd SS |
2619 | if (command) |
2620 | list_del(&command->cmd_list); | |
2cf95c18 | 2621 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2622 | xhci_free_host_resources(xhci, ctrl_ctx); |
f2217e8e | 2623 | spin_unlock_irqrestore(&xhci->lock, flags); |
3a7fa5be XR |
2624 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
2625 | "FIXME allocate a new ring segment"); | |
f2217e8e SS |
2626 | return -ENOMEM; |
2627 | } | |
2628 | xhci_ring_cmd_db(xhci); | |
2629 | spin_unlock_irqrestore(&xhci->lock, flags); | |
2630 | ||
2631 | /* Wait for the configure endpoint command to complete */ | |
2632 | timeleft = wait_for_completion_interruptible_timeout( | |
913a8a34 | 2633 | cmd_completion, |
6e4468b9 | 2634 | XHCI_CMD_DEFAULT_TIMEOUT); |
f2217e8e SS |
2635 | if (timeleft <= 0) { |
2636 | xhci_warn(xhci, "%s while waiting for %s command\n", | |
2637 | timeleft == 0 ? "Timeout" : "Signal", | |
2638 | ctx_change == 0 ? | |
2639 | "configure endpoint" : | |
2640 | "evaluate context"); | |
6e4468b9 EF |
2641 | /* cancel the configure endpoint command */ |
2642 | ret = xhci_cancel_cmd(xhci, command, cmd_trb); | |
2643 | if (ret < 0) | |
2644 | return ret; | |
f2217e8e SS |
2645 | return -ETIME; |
2646 | } | |
2647 | ||
2648 | if (!ctx_change) | |
2cf95c18 SS |
2649 | ret = xhci_configure_endpoint_result(xhci, udev, cmd_status); |
2650 | else | |
2651 | ret = xhci_evaluate_context_result(xhci, udev, cmd_status); | |
2652 | ||
2653 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
2654 | spin_lock_irqsave(&xhci->lock, flags); | |
2655 | /* If the command failed, remove the reserved resources. | |
2656 | * Otherwise, clean up the estimate to include dropped eps. | |
2657 | */ | |
2658 | if (ret) | |
92f8e767 | 2659 | xhci_free_host_resources(xhci, ctrl_ctx); |
2cf95c18 | 2660 | else |
92f8e767 | 2661 | xhci_finish_resource_reservation(xhci, ctrl_ctx); |
2cf95c18 SS |
2662 | spin_unlock_irqrestore(&xhci->lock, flags); |
2663 | } | |
2664 | return ret; | |
f2217e8e SS |
2665 | } |
2666 | ||
f88ba78d SS |
2667 | /* Called after one or more calls to xhci_add_endpoint() or |
2668 | * xhci_drop_endpoint(). If this call fails, the USB core is expected | |
2669 | * to call xhci_reset_bandwidth(). | |
2670 | * | |
2671 | * Since we are in the middle of changing either configuration or | |
2672 | * installing a new alt setting, the USB core won't allow URBs to be | |
2673 | * enqueued for any endpoint on the old config or interface. Nothing | |
2674 | * else should be touching the xhci->devs[slot_id] structure, so we | |
2675 | * don't need to take the xhci->lock for manipulating that. | |
2676 | */ | |
f94e0186 SS |
2677 | int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) |
2678 | { | |
2679 | int i; | |
2680 | int ret = 0; | |
f94e0186 SS |
2681 | struct xhci_hcd *xhci; |
2682 | struct xhci_virt_device *virt_dev; | |
d115b048 JY |
2683 | struct xhci_input_control_ctx *ctrl_ctx; |
2684 | struct xhci_slot_ctx *slot_ctx; | |
f94e0186 | 2685 | |
64927730 | 2686 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2687 | if (ret <= 0) |
2688 | return ret; | |
2689 | xhci = hcd_to_xhci(hcd); | |
fe6c6c13 SS |
2690 | if (xhci->xhc_state & XHCI_STATE_DYING) |
2691 | return -ENODEV; | |
f94e0186 | 2692 | |
700e2052 | 2693 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2694 | virt_dev = xhci->devs[udev->slot_id]; |
2695 | ||
2696 | /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */ | |
d115b048 | 2697 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
92f8e767 SS |
2698 | if (!ctrl_ctx) { |
2699 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2700 | __func__); | |
2701 | return -ENOMEM; | |
2702 | } | |
28ccd296 ME |
2703 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
2704 | ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG); | |
2705 | ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG)); | |
2dc37539 SS |
2706 | |
2707 | /* Don't issue the command if there's no endpoints to update. */ | |
2708 | if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) && | |
2709 | ctrl_ctx->drop_flags == 0) | |
2710 | return 0; | |
2711 | ||
f94e0186 | 2712 | xhci_dbg(xhci, "New Input Control Context:\n"); |
d115b048 JY |
2713 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
2714 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, | |
28ccd296 | 2715 | LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); |
f94e0186 | 2716 | |
913a8a34 SS |
2717 | ret = xhci_configure_endpoint(xhci, udev, NULL, |
2718 | false, false); | |
f94e0186 SS |
2719 | if (ret) { |
2720 | /* Callee should call reset_bandwidth() */ | |
f94e0186 SS |
2721 | return ret; |
2722 | } | |
2723 | ||
2724 | xhci_dbg(xhci, "Output context after successful config ep cmd:\n"); | |
d115b048 | 2725 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, |
28ccd296 | 2726 | LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); |
f94e0186 | 2727 | |
834cb0fc SS |
2728 | /* Free any rings that were dropped, but not changed. */ |
2729 | for (i = 1; i < 31; ++i) { | |
4819fef5 ME |
2730 | if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) && |
2731 | !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) | |
834cb0fc SS |
2732 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); |
2733 | } | |
d115b048 | 2734 | xhci_zero_in_ctx(xhci, virt_dev); |
834cb0fc SS |
2735 | /* |
2736 | * Install any rings for completely new endpoints or changed endpoints, | |
2737 | * and free or cache any old rings from changed endpoints. | |
2738 | */ | |
f94e0186 | 2739 | for (i = 1; i < 31; ++i) { |
74f9fe21 SS |
2740 | if (!virt_dev->eps[i].new_ring) |
2741 | continue; | |
2742 | /* Only cache or free the old ring if it exists. | |
2743 | * It may not if this is the first add of an endpoint. | |
2744 | */ | |
2745 | if (virt_dev->eps[i].ring) { | |
412566bd | 2746 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); |
f94e0186 | 2747 | } |
74f9fe21 SS |
2748 | virt_dev->eps[i].ring = virt_dev->eps[i].new_ring; |
2749 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 SS |
2750 | } |
2751 | ||
f94e0186 SS |
2752 | return ret; |
2753 | } | |
2754 | ||
2755 | void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) | |
2756 | { | |
f94e0186 SS |
2757 | struct xhci_hcd *xhci; |
2758 | struct xhci_virt_device *virt_dev; | |
2759 | int i, ret; | |
2760 | ||
64927730 | 2761 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2762 | if (ret <= 0) |
2763 | return; | |
2764 | xhci = hcd_to_xhci(hcd); | |
2765 | ||
700e2052 | 2766 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2767 | virt_dev = xhci->devs[udev->slot_id]; |
2768 | /* Free any rings allocated for added endpoints */ | |
2769 | for (i = 0; i < 31; ++i) { | |
63a0d9ab SS |
2770 | if (virt_dev->eps[i].new_ring) { |
2771 | xhci_ring_free(xhci, virt_dev->eps[i].new_ring); | |
2772 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 SS |
2773 | } |
2774 | } | |
d115b048 | 2775 | xhci_zero_in_ctx(xhci, virt_dev); |
f94e0186 SS |
2776 | } |
2777 | ||
5270b951 | 2778 | static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci, |
913a8a34 SS |
2779 | struct xhci_container_ctx *in_ctx, |
2780 | struct xhci_container_ctx *out_ctx, | |
92f8e767 | 2781 | struct xhci_input_control_ctx *ctrl_ctx, |
913a8a34 | 2782 | u32 add_flags, u32 drop_flags) |
5270b951 | 2783 | { |
28ccd296 ME |
2784 | ctrl_ctx->add_flags = cpu_to_le32(add_flags); |
2785 | ctrl_ctx->drop_flags = cpu_to_le32(drop_flags); | |
913a8a34 | 2786 | xhci_slot_copy(xhci, in_ctx, out_ctx); |
28ccd296 | 2787 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
5270b951 | 2788 | |
913a8a34 SS |
2789 | xhci_dbg(xhci, "Input Context:\n"); |
2790 | xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags)); | |
5270b951 SS |
2791 | } |
2792 | ||
8212a49d | 2793 | static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, |
ac9d8fe7 SS |
2794 | unsigned int slot_id, unsigned int ep_index, |
2795 | struct xhci_dequeue_state *deq_state) | |
2796 | { | |
92f8e767 | 2797 | struct xhci_input_control_ctx *ctrl_ctx; |
ac9d8fe7 | 2798 | struct xhci_container_ctx *in_ctx; |
ac9d8fe7 SS |
2799 | struct xhci_ep_ctx *ep_ctx; |
2800 | u32 added_ctxs; | |
2801 | dma_addr_t addr; | |
2802 | ||
92f8e767 SS |
2803 | in_ctx = xhci->devs[slot_id]->in_ctx; |
2804 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
2805 | if (!ctrl_ctx) { | |
2806 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2807 | __func__); | |
2808 | return; | |
2809 | } | |
2810 | ||
913a8a34 SS |
2811 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
2812 | xhci->devs[slot_id]->out_ctx, ep_index); | |
ac9d8fe7 SS |
2813 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); |
2814 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
2815 | deq_state->new_deq_ptr); | |
2816 | if (addr == 0) { | |
2817 | xhci_warn(xhci, "WARN Cannot submit config ep after " | |
2818 | "reset ep command\n"); | |
2819 | xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n", | |
2820 | deq_state->new_deq_seg, | |
2821 | deq_state->new_deq_ptr); | |
2822 | return; | |
2823 | } | |
28ccd296 | 2824 | ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state); |
ac9d8fe7 | 2825 | |
ac9d8fe7 | 2826 | added_ctxs = xhci_get_endpoint_flag_from_index(ep_index); |
913a8a34 | 2827 | xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx, |
92f8e767 SS |
2828 | xhci->devs[slot_id]->out_ctx, ctrl_ctx, |
2829 | added_ctxs, added_ctxs); | |
ac9d8fe7 SS |
2830 | } |
2831 | ||
82d1009f | 2832 | void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, |
63a0d9ab | 2833 | struct usb_device *udev, unsigned int ep_index) |
82d1009f SS |
2834 | { |
2835 | struct xhci_dequeue_state deq_state; | |
63a0d9ab | 2836 | struct xhci_virt_ep *ep; |
82d1009f | 2837 | |
a0254324 XR |
2838 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2839 | "Cleaning up stalled endpoint ring"); | |
63a0d9ab | 2840 | ep = &xhci->devs[udev->slot_id]->eps[ep_index]; |
82d1009f SS |
2841 | /* We need to move the HW's dequeue pointer past this TD, |
2842 | * or it will attempt to resend it on the next doorbell ring. | |
2843 | */ | |
2844 | xhci_find_new_dequeue_state(xhci, udev->slot_id, | |
e9df17eb | 2845 | ep_index, ep->stopped_stream, ep->stopped_td, |
ac9d8fe7 | 2846 | &deq_state); |
82d1009f | 2847 | |
ac9d8fe7 SS |
2848 | /* HW with the reset endpoint quirk will use the saved dequeue state to |
2849 | * issue a configure endpoint command later. | |
2850 | */ | |
2851 | if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) { | |
a0254324 XR |
2852 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2853 | "Queueing new dequeue state"); | |
63a0d9ab | 2854 | xhci_queue_new_dequeue_state(xhci, udev->slot_id, |
e9df17eb | 2855 | ep_index, ep->stopped_stream, &deq_state); |
ac9d8fe7 SS |
2856 | } else { |
2857 | /* Better hope no one uses the input context between now and the | |
2858 | * reset endpoint completion! | |
e9df17eb SS |
2859 | * XXX: No idea how this hardware will react when stream rings |
2860 | * are enabled. | |
ac9d8fe7 | 2861 | */ |
4bdfe4c3 XR |
2862 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2863 | "Setting up input context for " | |
2864 | "configure endpoint command"); | |
ac9d8fe7 SS |
2865 | xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id, |
2866 | ep_index, &deq_state); | |
2867 | } | |
82d1009f SS |
2868 | } |
2869 | ||
a1587d97 SS |
2870 | /* Deal with stalled endpoints. The core should have sent the control message |
2871 | * to clear the halt condition. However, we need to make the xHCI hardware | |
2872 | * reset its sequence number, since a device will expect a sequence number of | |
2873 | * zero after the halt condition is cleared. | |
2874 | * Context: in_interrupt | |
2875 | */ | |
2876 | void xhci_endpoint_reset(struct usb_hcd *hcd, | |
2877 | struct usb_host_endpoint *ep) | |
2878 | { | |
2879 | struct xhci_hcd *xhci; | |
2880 | struct usb_device *udev; | |
2881 | unsigned int ep_index; | |
2882 | unsigned long flags; | |
2883 | int ret; | |
63a0d9ab | 2884 | struct xhci_virt_ep *virt_ep; |
a1587d97 SS |
2885 | |
2886 | xhci = hcd_to_xhci(hcd); | |
2887 | udev = (struct usb_device *) ep->hcpriv; | |
2888 | /* Called with a root hub endpoint (or an endpoint that wasn't added | |
2889 | * with xhci_add_endpoint() | |
2890 | */ | |
2891 | if (!ep->hcpriv) | |
2892 | return; | |
2893 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
63a0d9ab SS |
2894 | virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index]; |
2895 | if (!virt_ep->stopped_td) { | |
a0254324 XR |
2896 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2897 | "Endpoint 0x%x not halted, refusing to reset.", | |
2898 | ep->desc.bEndpointAddress); | |
c92bcfa7 SS |
2899 | return; |
2900 | } | |
82d1009f | 2901 | if (usb_endpoint_xfer_control(&ep->desc)) { |
a0254324 XR |
2902 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2903 | "Control endpoint stall already handled."); | |
82d1009f SS |
2904 | return; |
2905 | } | |
a1587d97 | 2906 | |
a0254324 XR |
2907 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2908 | "Queueing reset endpoint command"); | |
a1587d97 SS |
2909 | spin_lock_irqsave(&xhci->lock, flags); |
2910 | ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index); | |
c92bcfa7 SS |
2911 | /* |
2912 | * Can't change the ring dequeue pointer until it's transitioned to the | |
2913 | * stopped state, which is only upon a successful reset endpoint | |
2914 | * command. Better hope that last command worked! | |
2915 | */ | |
a1587d97 | 2916 | if (!ret) { |
63a0d9ab SS |
2917 | xhci_cleanup_stalled_ring(xhci, udev, ep_index); |
2918 | kfree(virt_ep->stopped_td); | |
a1587d97 SS |
2919 | xhci_ring_cmd_db(xhci); |
2920 | } | |
1624ae1c SS |
2921 | virt_ep->stopped_td = NULL; |
2922 | virt_ep->stopped_trb = NULL; | |
5e5cf6fc | 2923 | virt_ep->stopped_stream = 0; |
a1587d97 SS |
2924 | spin_unlock_irqrestore(&xhci->lock, flags); |
2925 | ||
2926 | if (ret) | |
2927 | xhci_warn(xhci, "FIXME allocate a new ring segment\n"); | |
2928 | } | |
2929 | ||
8df75f42 SS |
2930 | static int xhci_check_streams_endpoint(struct xhci_hcd *xhci, |
2931 | struct usb_device *udev, struct usb_host_endpoint *ep, | |
2932 | unsigned int slot_id) | |
2933 | { | |
2934 | int ret; | |
2935 | unsigned int ep_index; | |
2936 | unsigned int ep_state; | |
2937 | ||
2938 | if (!ep) | |
2939 | return -EINVAL; | |
64927730 | 2940 | ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__); |
8df75f42 SS |
2941 | if (ret <= 0) |
2942 | return -EINVAL; | |
842f1690 | 2943 | if (ep->ss_ep_comp.bmAttributes == 0) { |
8df75f42 SS |
2944 | xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion" |
2945 | " descriptor for ep 0x%x does not support streams\n", | |
2946 | ep->desc.bEndpointAddress); | |
2947 | return -EINVAL; | |
2948 | } | |
2949 | ||
2950 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
2951 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
2952 | if (ep_state & EP_HAS_STREAMS || | |
2953 | ep_state & EP_GETTING_STREAMS) { | |
2954 | xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x " | |
2955 | "already has streams set up.\n", | |
2956 | ep->desc.bEndpointAddress); | |
2957 | xhci_warn(xhci, "Send email to xHCI maintainer and ask for " | |
2958 | "dynamic stream context array reallocation.\n"); | |
2959 | return -EINVAL; | |
2960 | } | |
2961 | if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) { | |
2962 | xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk " | |
2963 | "endpoint 0x%x; URBs are pending.\n", | |
2964 | ep->desc.bEndpointAddress); | |
2965 | return -EINVAL; | |
2966 | } | |
2967 | return 0; | |
2968 | } | |
2969 | ||
2970 | static void xhci_calculate_streams_entries(struct xhci_hcd *xhci, | |
2971 | unsigned int *num_streams, unsigned int *num_stream_ctxs) | |
2972 | { | |
2973 | unsigned int max_streams; | |
2974 | ||
2975 | /* The stream context array size must be a power of two */ | |
2976 | *num_stream_ctxs = roundup_pow_of_two(*num_streams); | |
2977 | /* | |
2978 | * Find out how many primary stream array entries the host controller | |
2979 | * supports. Later we may use secondary stream arrays (similar to 2nd | |
2980 | * level page entries), but that's an optional feature for xHCI host | |
2981 | * controllers. xHCs must support at least 4 stream IDs. | |
2982 | */ | |
2983 | max_streams = HCC_MAX_PSA(xhci->hcc_params); | |
2984 | if (*num_stream_ctxs > max_streams) { | |
2985 | xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n", | |
2986 | max_streams); | |
2987 | *num_stream_ctxs = max_streams; | |
2988 | *num_streams = max_streams; | |
2989 | } | |
2990 | } | |
2991 | ||
2992 | /* Returns an error code if one of the endpoint already has streams. | |
2993 | * This does not change any data structures, it only checks and gathers | |
2994 | * information. | |
2995 | */ | |
2996 | static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci, | |
2997 | struct usb_device *udev, | |
2998 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
2999 | unsigned int *num_streams, u32 *changed_ep_bitmask) | |
3000 | { | |
8df75f42 SS |
3001 | unsigned int max_streams; |
3002 | unsigned int endpoint_flag; | |
3003 | int i; | |
3004 | int ret; | |
3005 | ||
3006 | for (i = 0; i < num_eps; i++) { | |
3007 | ret = xhci_check_streams_endpoint(xhci, udev, | |
3008 | eps[i], udev->slot_id); | |
3009 | if (ret < 0) | |
3010 | return ret; | |
3011 | ||
18b7ede5 | 3012 | max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp); |
8df75f42 SS |
3013 | if (max_streams < (*num_streams - 1)) { |
3014 | xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n", | |
3015 | eps[i]->desc.bEndpointAddress, | |
3016 | max_streams); | |
3017 | *num_streams = max_streams+1; | |
3018 | } | |
3019 | ||
3020 | endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc); | |
3021 | if (*changed_ep_bitmask & endpoint_flag) | |
3022 | return -EINVAL; | |
3023 | *changed_ep_bitmask |= endpoint_flag; | |
3024 | } | |
3025 | return 0; | |
3026 | } | |
3027 | ||
3028 | static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci, | |
3029 | struct usb_device *udev, | |
3030 | struct usb_host_endpoint **eps, unsigned int num_eps) | |
3031 | { | |
3032 | u32 changed_ep_bitmask = 0; | |
3033 | unsigned int slot_id; | |
3034 | unsigned int ep_index; | |
3035 | unsigned int ep_state; | |
3036 | int i; | |
3037 | ||
3038 | slot_id = udev->slot_id; | |
3039 | if (!xhci->devs[slot_id]) | |
3040 | return 0; | |
3041 | ||
3042 | for (i = 0; i < num_eps; i++) { | |
3043 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3044 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
3045 | /* Are streams already being freed for the endpoint? */ | |
3046 | if (ep_state & EP_GETTING_NO_STREAMS) { | |
3047 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3048 | "endpoint 0x%x, " |
3049 | "streams are being disabled already\n", | |
8df75f42 SS |
3050 | eps[i]->desc.bEndpointAddress); |
3051 | return 0; | |
3052 | } | |
3053 | /* Are there actually any streams to free? */ | |
3054 | if (!(ep_state & EP_HAS_STREAMS) && | |
3055 | !(ep_state & EP_GETTING_STREAMS)) { | |
3056 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3057 | "endpoint 0x%x, " |
3058 | "streams are already disabled!\n", | |
8df75f42 SS |
3059 | eps[i]->desc.bEndpointAddress); |
3060 | xhci_warn(xhci, "WARN xhci_free_streams() called " | |
3061 | "with non-streams endpoint\n"); | |
3062 | return 0; | |
3063 | } | |
3064 | changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc); | |
3065 | } | |
3066 | return changed_ep_bitmask; | |
3067 | } | |
3068 | ||
3069 | /* | |
3070 | * The USB device drivers use this function (though the HCD interface in USB | |
3071 | * core) to prepare a set of bulk endpoints to use streams. Streams are used to | |
3072 | * coordinate mass storage command queueing across multiple endpoints (basically | |
3073 | * a stream ID == a task ID). | |
3074 | * | |
3075 | * Setting up streams involves allocating the same size stream context array | |
3076 | * for each endpoint and issuing a configure endpoint command for all endpoints. | |
3077 | * | |
3078 | * Don't allow the call to succeed if one endpoint only supports one stream | |
3079 | * (which means it doesn't support streams at all). | |
3080 | * | |
3081 | * Drivers may get less stream IDs than they asked for, if the host controller | |
3082 | * hardware or endpoints claim they can't support the number of requested | |
3083 | * stream IDs. | |
3084 | */ | |
3085 | int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, | |
3086 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3087 | unsigned int num_streams, gfp_t mem_flags) | |
3088 | { | |
3089 | int i, ret; | |
3090 | struct xhci_hcd *xhci; | |
3091 | struct xhci_virt_device *vdev; | |
3092 | struct xhci_command *config_cmd; | |
92f8e767 | 3093 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3094 | unsigned int ep_index; |
3095 | unsigned int num_stream_ctxs; | |
3096 | unsigned long flags; | |
3097 | u32 changed_ep_bitmask = 0; | |
3098 | ||
3099 | if (!eps) | |
3100 | return -EINVAL; | |
3101 | ||
3102 | /* Add one to the number of streams requested to account for | |
3103 | * stream 0 that is reserved for xHCI usage. | |
3104 | */ | |
3105 | num_streams += 1; | |
3106 | xhci = hcd_to_xhci(hcd); | |
3107 | xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n", | |
3108 | num_streams); | |
3109 | ||
3110 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); | |
3111 | if (!config_cmd) { | |
3112 | xhci_dbg(xhci, "Could not allocate xHCI command structure.\n"); | |
3113 | return -ENOMEM; | |
3114 | } | |
92f8e767 SS |
3115 | ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx); |
3116 | if (!ctrl_ctx) { | |
3117 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3118 | __func__); | |
3119 | xhci_free_command(xhci, config_cmd); | |
3120 | return -ENOMEM; | |
3121 | } | |
8df75f42 SS |
3122 | |
3123 | /* Check to make sure all endpoints are not already configured for | |
3124 | * streams. While we're at it, find the maximum number of streams that | |
3125 | * all the endpoints will support and check for duplicate endpoints. | |
3126 | */ | |
3127 | spin_lock_irqsave(&xhci->lock, flags); | |
3128 | ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps, | |
3129 | num_eps, &num_streams, &changed_ep_bitmask); | |
3130 | if (ret < 0) { | |
3131 | xhci_free_command(xhci, config_cmd); | |
3132 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3133 | return ret; | |
3134 | } | |
3135 | if (num_streams <= 1) { | |
3136 | xhci_warn(xhci, "WARN: endpoints can't handle " | |
3137 | "more than one stream.\n"); | |
3138 | xhci_free_command(xhci, config_cmd); | |
3139 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3140 | return -EINVAL; | |
3141 | } | |
3142 | vdev = xhci->devs[udev->slot_id]; | |
25985edc | 3143 | /* Mark each endpoint as being in transition, so |
8df75f42 SS |
3144 | * xhci_urb_enqueue() will reject all URBs. |
3145 | */ | |
3146 | for (i = 0; i < num_eps; i++) { | |
3147 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3148 | vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS; | |
3149 | } | |
3150 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3151 | ||
3152 | /* Setup internal data structures and allocate HW data structures for | |
3153 | * streams (but don't install the HW structures in the input context | |
3154 | * until we're sure all memory allocation succeeded). | |
3155 | */ | |
3156 | xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs); | |
3157 | xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n", | |
3158 | num_stream_ctxs, num_streams); | |
3159 | ||
3160 | for (i = 0; i < num_eps; i++) { | |
3161 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3162 | vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci, | |
3163 | num_stream_ctxs, | |
3164 | num_streams, mem_flags); | |
3165 | if (!vdev->eps[ep_index].stream_info) | |
3166 | goto cleanup; | |
3167 | /* Set maxPstreams in endpoint context and update deq ptr to | |
3168 | * point to stream context array. FIXME | |
3169 | */ | |
3170 | } | |
3171 | ||
3172 | /* Set up the input context for a configure endpoint command. */ | |
3173 | for (i = 0; i < num_eps; i++) { | |
3174 | struct xhci_ep_ctx *ep_ctx; | |
3175 | ||
3176 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3177 | ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index); | |
3178 | ||
3179 | xhci_endpoint_copy(xhci, config_cmd->in_ctx, | |
3180 | vdev->out_ctx, ep_index); | |
3181 | xhci_setup_streams_ep_input_ctx(xhci, ep_ctx, | |
3182 | vdev->eps[ep_index].stream_info); | |
3183 | } | |
3184 | /* Tell the HW to drop its old copy of the endpoint context info | |
3185 | * and add the updated copy from the input context. | |
3186 | */ | |
3187 | xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx, | |
92f8e767 SS |
3188 | vdev->out_ctx, ctrl_ctx, |
3189 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3190 | |
3191 | /* Issue and wait for the configure endpoint command */ | |
3192 | ret = xhci_configure_endpoint(xhci, udev, config_cmd, | |
3193 | false, false); | |
3194 | ||
3195 | /* xHC rejected the configure endpoint command for some reason, so we | |
3196 | * leave the old ring intact and free our internal streams data | |
3197 | * structure. | |
3198 | */ | |
3199 | if (ret < 0) | |
3200 | goto cleanup; | |
3201 | ||
3202 | spin_lock_irqsave(&xhci->lock, flags); | |
3203 | for (i = 0; i < num_eps; i++) { | |
3204 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3205 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3206 | xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n", | |
3207 | udev->slot_id, ep_index); | |
3208 | vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS; | |
3209 | } | |
3210 | xhci_free_command(xhci, config_cmd); | |
3211 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3212 | ||
3213 | /* Subtract 1 for stream 0, which drivers can't use */ | |
3214 | return num_streams - 1; | |
3215 | ||
3216 | cleanup: | |
3217 | /* If it didn't work, free the streams! */ | |
3218 | for (i = 0; i < num_eps; i++) { | |
3219 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3220 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3221 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3222 | /* FIXME Unset maxPstreams in endpoint context and |
3223 | * update deq ptr to point to normal string ring. | |
3224 | */ | |
3225 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3226 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3227 | xhci_endpoint_zero(xhci, vdev, eps[i]); | |
3228 | } | |
3229 | xhci_free_command(xhci, config_cmd); | |
3230 | return -ENOMEM; | |
3231 | } | |
3232 | ||
3233 | /* Transition the endpoint from using streams to being a "normal" endpoint | |
3234 | * without streams. | |
3235 | * | |
3236 | * Modify the endpoint context state, submit a configure endpoint command, | |
3237 | * and free all endpoint rings for streams if that completes successfully. | |
3238 | */ | |
3239 | int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, | |
3240 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3241 | gfp_t mem_flags) | |
3242 | { | |
3243 | int i, ret; | |
3244 | struct xhci_hcd *xhci; | |
3245 | struct xhci_virt_device *vdev; | |
3246 | struct xhci_command *command; | |
92f8e767 | 3247 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3248 | unsigned int ep_index; |
3249 | unsigned long flags; | |
3250 | u32 changed_ep_bitmask; | |
3251 | ||
3252 | xhci = hcd_to_xhci(hcd); | |
3253 | vdev = xhci->devs[udev->slot_id]; | |
3254 | ||
3255 | /* Set up a configure endpoint command to remove the streams rings */ | |
3256 | spin_lock_irqsave(&xhci->lock, flags); | |
3257 | changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci, | |
3258 | udev, eps, num_eps); | |
3259 | if (changed_ep_bitmask == 0) { | |
3260 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3261 | return -EINVAL; | |
3262 | } | |
3263 | ||
3264 | /* Use the xhci_command structure from the first endpoint. We may have | |
3265 | * allocated too many, but the driver may call xhci_free_streams() for | |
3266 | * each endpoint it grouped into one call to xhci_alloc_streams(). | |
3267 | */ | |
3268 | ep_index = xhci_get_endpoint_index(&eps[0]->desc); | |
3269 | command = vdev->eps[ep_index].stream_info->free_streams_command; | |
92f8e767 SS |
3270 | ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx); |
3271 | if (!ctrl_ctx) { | |
1f21569c | 3272 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
3273 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
3274 | __func__); | |
3275 | return -EINVAL; | |
3276 | } | |
3277 | ||
8df75f42 SS |
3278 | for (i = 0; i < num_eps; i++) { |
3279 | struct xhci_ep_ctx *ep_ctx; | |
3280 | ||
3281 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3282 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); | |
3283 | xhci->devs[udev->slot_id]->eps[ep_index].ep_state |= | |
3284 | EP_GETTING_NO_STREAMS; | |
3285 | ||
3286 | xhci_endpoint_copy(xhci, command->in_ctx, | |
3287 | vdev->out_ctx, ep_index); | |
3288 | xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx, | |
3289 | &vdev->eps[ep_index]); | |
3290 | } | |
3291 | xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx, | |
92f8e767 SS |
3292 | vdev->out_ctx, ctrl_ctx, |
3293 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3294 | spin_unlock_irqrestore(&xhci->lock, flags); |
3295 | ||
3296 | /* Issue and wait for the configure endpoint command, | |
3297 | * which must succeed. | |
3298 | */ | |
3299 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3300 | false, true); | |
3301 | ||
3302 | /* xHC rejected the configure endpoint command for some reason, so we | |
3303 | * leave the streams rings intact. | |
3304 | */ | |
3305 | if (ret < 0) | |
3306 | return ret; | |
3307 | ||
3308 | spin_lock_irqsave(&xhci->lock, flags); | |
3309 | for (i = 0; i < num_eps; i++) { | |
3310 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3311 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3312 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3313 | /* FIXME Unset maxPstreams in endpoint context and |
3314 | * update deq ptr to point to normal string ring. | |
3315 | */ | |
3316 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS; | |
3317 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3318 | } | |
3319 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3320 | ||
3321 | return 0; | |
3322 | } | |
3323 | ||
2cf95c18 SS |
3324 | /* |
3325 | * Deletes endpoint resources for endpoints that were active before a Reset | |
3326 | * Device command, or a Disable Slot command. The Reset Device command leaves | |
3327 | * the control endpoint intact, whereas the Disable Slot command deletes it. | |
3328 | * | |
3329 | * Must be called with xhci->lock held. | |
3330 | */ | |
3331 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, | |
3332 | struct xhci_virt_device *virt_dev, bool drop_control_ep) | |
3333 | { | |
3334 | int i; | |
3335 | unsigned int num_dropped_eps = 0; | |
3336 | unsigned int drop_flags = 0; | |
3337 | ||
3338 | for (i = (drop_control_ep ? 0 : 1); i < 31; i++) { | |
3339 | if (virt_dev->eps[i].ring) { | |
3340 | drop_flags |= 1 << i; | |
3341 | num_dropped_eps++; | |
3342 | } | |
3343 | } | |
3344 | xhci->num_active_eps -= num_dropped_eps; | |
3345 | if (num_dropped_eps) | |
4bdfe4c3 XR |
3346 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3347 | "Dropped %u ep ctxs, flags = 0x%x, " | |
3348 | "%u now active.", | |
2cf95c18 SS |
3349 | num_dropped_eps, drop_flags, |
3350 | xhci->num_active_eps); | |
3351 | } | |
3352 | ||
2a8f82c4 SS |
3353 | /* |
3354 | * This submits a Reset Device Command, which will set the device state to 0, | |
3355 | * set the device address to 0, and disable all the endpoints except the default | |
3356 | * control endpoint. The USB core should come back and call | |
3357 | * xhci_address_device(), and then re-set up the configuration. If this is | |
3358 | * called because of a usb_reset_and_verify_device(), then the old alternate | |
3359 | * settings will be re-installed through the normal bandwidth allocation | |
3360 | * functions. | |
3361 | * | |
3362 | * Wait for the Reset Device command to finish. Remove all structures | |
3363 | * associated with the endpoints that were disabled. Clear the input device | |
3364 | * structure? Cache the rings? Reset the control endpoint 0 max packet size? | |
f0615c45 AX |
3365 | * |
3366 | * If the virt_dev to be reset does not exist or does not match the udev, | |
3367 | * it means the device is lost, possibly due to the xHC restore error and | |
3368 | * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to | |
3369 | * re-allocate the device. | |
2a8f82c4 | 3370 | */ |
f0615c45 | 3371 | int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev) |
2a8f82c4 SS |
3372 | { |
3373 | int ret, i; | |
3374 | unsigned long flags; | |
3375 | struct xhci_hcd *xhci; | |
3376 | unsigned int slot_id; | |
3377 | struct xhci_virt_device *virt_dev; | |
3378 | struct xhci_command *reset_device_cmd; | |
3379 | int timeleft; | |
3380 | int last_freed_endpoint; | |
001fd382 | 3381 | struct xhci_slot_ctx *slot_ctx; |
2e27980e | 3382 | int old_active_eps = 0; |
2a8f82c4 | 3383 | |
f0615c45 | 3384 | ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__); |
2a8f82c4 SS |
3385 | if (ret <= 0) |
3386 | return ret; | |
3387 | xhci = hcd_to_xhci(hcd); | |
3388 | slot_id = udev->slot_id; | |
3389 | virt_dev = xhci->devs[slot_id]; | |
f0615c45 AX |
3390 | if (!virt_dev) { |
3391 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3392 | "not exist. Re-allocate the device\n", slot_id); | |
3393 | ret = xhci_alloc_dev(hcd, udev); | |
3394 | if (ret == 1) | |
3395 | return 0; | |
3396 | else | |
3397 | return -EINVAL; | |
3398 | } | |
3399 | ||
3400 | if (virt_dev->udev != udev) { | |
3401 | /* If the virt_dev and the udev does not match, this virt_dev | |
3402 | * may belong to another udev. | |
3403 | * Re-allocate the device. | |
3404 | */ | |
3405 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3406 | "not match the udev. Re-allocate the device\n", | |
3407 | slot_id); | |
3408 | ret = xhci_alloc_dev(hcd, udev); | |
3409 | if (ret == 1) | |
3410 | return 0; | |
3411 | else | |
3412 | return -EINVAL; | |
3413 | } | |
2a8f82c4 | 3414 | |
001fd382 ML |
3415 | /* If device is not setup, there is no point in resetting it */ |
3416 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
3417 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == | |
3418 | SLOT_STATE_DISABLED) | |
3419 | return 0; | |
3420 | ||
2a8f82c4 SS |
3421 | xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id); |
3422 | /* Allocate the command structure that holds the struct completion. | |
3423 | * Assume we're in process context, since the normal device reset | |
3424 | * process has to wait for the device anyway. Storage devices are | |
3425 | * reset as part of error handling, so use GFP_NOIO instead of | |
3426 | * GFP_KERNEL. | |
3427 | */ | |
3428 | reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); | |
3429 | if (!reset_device_cmd) { | |
3430 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | |
3431 | return -ENOMEM; | |
3432 | } | |
3433 | ||
3434 | /* Attempt to submit the Reset Device command to the command ring */ | |
3435 | spin_lock_irqsave(&xhci->lock, flags); | |
3436 | reset_device_cmd->command_trb = xhci->cmd_ring->enqueue; | |
7a3783ef PZ |
3437 | |
3438 | /* Enqueue pointer can be left pointing to the link TRB, | |
3439 | * we must handle that | |
3440 | */ | |
f5960b69 | 3441 | if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control)) |
7a3783ef PZ |
3442 | reset_device_cmd->command_trb = |
3443 | xhci->cmd_ring->enq_seg->next->trbs; | |
3444 | ||
2a8f82c4 SS |
3445 | list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list); |
3446 | ret = xhci_queue_reset_device(xhci, slot_id); | |
3447 | if (ret) { | |
3448 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
3449 | list_del(&reset_device_cmd->cmd_list); | |
3450 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3451 | goto command_cleanup; | |
3452 | } | |
3453 | xhci_ring_cmd_db(xhci); | |
3454 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3455 | ||
3456 | /* Wait for the Reset Device command to finish */ | |
3457 | timeleft = wait_for_completion_interruptible_timeout( | |
3458 | reset_device_cmd->completion, | |
3459 | USB_CTRL_SET_TIMEOUT); | |
3460 | if (timeleft <= 0) { | |
3461 | xhci_warn(xhci, "%s while waiting for reset device command\n", | |
3462 | timeleft == 0 ? "Timeout" : "Signal"); | |
3463 | spin_lock_irqsave(&xhci->lock, flags); | |
3464 | /* The timeout might have raced with the event ring handler, so | |
3465 | * only delete from the list if the item isn't poisoned. | |
3466 | */ | |
3467 | if (reset_device_cmd->cmd_list.next != LIST_POISON1) | |
3468 | list_del(&reset_device_cmd->cmd_list); | |
3469 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3470 | ret = -ETIME; | |
3471 | goto command_cleanup; | |
3472 | } | |
3473 | ||
3474 | /* The Reset Device command can't fail, according to the 0.95/0.96 spec, | |
3475 | * unless we tried to reset a slot ID that wasn't enabled, | |
3476 | * or the device wasn't in the addressed or configured state. | |
3477 | */ | |
3478 | ret = reset_device_cmd->status; | |
3479 | switch (ret) { | |
3480 | case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */ | |
3481 | case COMP_CTX_STATE: /* 0.96 completion code for same thing */ | |
38a532a6 | 3482 | xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n", |
2a8f82c4 SS |
3483 | slot_id, |
3484 | xhci_get_slot_state(xhci, virt_dev->out_ctx)); | |
38a532a6 | 3485 | xhci_dbg(xhci, "Not freeing device rings.\n"); |
2a8f82c4 SS |
3486 | /* Don't treat this as an error. May change my mind later. */ |
3487 | ret = 0; | |
3488 | goto command_cleanup; | |
3489 | case COMP_SUCCESS: | |
3490 | xhci_dbg(xhci, "Successful reset device command.\n"); | |
3491 | break; | |
3492 | default: | |
3493 | if (xhci_is_vendor_info_code(xhci, ret)) | |
3494 | break; | |
3495 | xhci_warn(xhci, "Unknown completion code %u for " | |
3496 | "reset device command.\n", ret); | |
3497 | ret = -EINVAL; | |
3498 | goto command_cleanup; | |
3499 | } | |
3500 | ||
2cf95c18 SS |
3501 | /* Free up host controller endpoint resources */ |
3502 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3503 | spin_lock_irqsave(&xhci->lock, flags); | |
3504 | /* Don't delete the default control endpoint resources */ | |
3505 | xhci_free_device_endpoint_resources(xhci, virt_dev, false); | |
3506 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3507 | } | |
3508 | ||
2a8f82c4 SS |
3509 | /* Everything but endpoint 0 is disabled, so free or cache the rings. */ |
3510 | last_freed_endpoint = 1; | |
3511 | for (i = 1; i < 31; ++i) { | |
2dea75d9 DT |
3512 | struct xhci_virt_ep *ep = &virt_dev->eps[i]; |
3513 | ||
3514 | if (ep->ep_state & EP_HAS_STREAMS) { | |
3515 | xhci_free_stream_info(xhci, ep->stream_info); | |
3516 | ep->stream_info = NULL; | |
3517 | ep->ep_state &= ~EP_HAS_STREAMS; | |
3518 | } | |
3519 | ||
3520 | if (ep->ring) { | |
3521 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); | |
3522 | last_freed_endpoint = i; | |
3523 | } | |
2e27980e SS |
3524 | if (!list_empty(&virt_dev->eps[i].bw_endpoint_list)) |
3525 | xhci_drop_ep_from_interval_table(xhci, | |
3526 | &virt_dev->eps[i].bw_info, | |
3527 | virt_dev->bw_table, | |
3528 | udev, | |
3529 | &virt_dev->eps[i], | |
3530 | virt_dev->tt_info); | |
9af5d71d | 3531 | xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info); |
2a8f82c4 | 3532 | } |
2e27980e SS |
3533 | /* If necessary, update the number of active TTs on this root port */ |
3534 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
3535 | ||
2a8f82c4 SS |
3536 | xhci_dbg(xhci, "Output context after successful reset device cmd:\n"); |
3537 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint); | |
3538 | ret = 0; | |
3539 | ||
3540 | command_cleanup: | |
3541 | xhci_free_command(xhci, reset_device_cmd); | |
3542 | return ret; | |
3543 | } | |
3544 | ||
3ffbba95 SS |
3545 | /* |
3546 | * At this point, the struct usb_device is about to go away, the device has | |
3547 | * disconnected, and all traffic has been stopped and the endpoints have been | |
3548 | * disabled. Free any HC data structures associated with that device. | |
3549 | */ | |
3550 | void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3551 | { | |
3552 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
6f5165cf | 3553 | struct xhci_virt_device *virt_dev; |
3ffbba95 | 3554 | unsigned long flags; |
c526d0d4 | 3555 | u32 state; |
64927730 | 3556 | int i, ret; |
3ffbba95 | 3557 | |
64927730 | 3558 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
7bd89b40 SS |
3559 | /* If the host is halted due to driver unload, we still need to free the |
3560 | * device. | |
3561 | */ | |
3562 | if (ret <= 0 && ret != -ENODEV) | |
3ffbba95 | 3563 | return; |
64927730 | 3564 | |
6f5165cf | 3565 | virt_dev = xhci->devs[udev->slot_id]; |
6f5165cf SS |
3566 | |
3567 | /* Stop any wayward timer functions (which may grab the lock) */ | |
3568 | for (i = 0; i < 31; ++i) { | |
3569 | virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING; | |
3570 | del_timer_sync(&virt_dev->eps[i].stop_cmd_timer); | |
3571 | } | |
3ffbba95 | 3572 | |
65580b43 AX |
3573 | if (udev->usb2_hw_lpm_enabled) { |
3574 | xhci_set_usb2_hardware_lpm(hcd, udev, 0); | |
3575 | udev->usb2_hw_lpm_enabled = 0; | |
3576 | } | |
3577 | ||
3ffbba95 | 3578 | spin_lock_irqsave(&xhci->lock, flags); |
c526d0d4 SS |
3579 | /* Don't disable the slot if the host controller is dead. */ |
3580 | state = xhci_readl(xhci, &xhci->op_regs->status); | |
7bd89b40 SS |
3581 | if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) || |
3582 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
c526d0d4 SS |
3583 | xhci_free_virt_device(xhci, udev->slot_id); |
3584 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3585 | return; | |
3586 | } | |
3587 | ||
23e3be11 | 3588 | if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) { |
3ffbba95 SS |
3589 | spin_unlock_irqrestore(&xhci->lock, flags); |
3590 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
3591 | return; | |
3592 | } | |
23e3be11 | 3593 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3594 | spin_unlock_irqrestore(&xhci->lock, flags); |
3595 | /* | |
3596 | * Event command completion handler will free any data structures | |
f88ba78d | 3597 | * associated with the slot. XXX Can free sleep? |
3ffbba95 SS |
3598 | */ |
3599 | } | |
3600 | ||
2cf95c18 SS |
3601 | /* |
3602 | * Checks if we have enough host controller resources for the default control | |
3603 | * endpoint. | |
3604 | * | |
3605 | * Must be called with xhci->lock held. | |
3606 | */ | |
3607 | static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci) | |
3608 | { | |
3609 | if (xhci->num_active_eps + 1 > xhci->limit_active_eps) { | |
4bdfe4c3 XR |
3610 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3611 | "Not enough ep ctxs: " | |
3612 | "%u active, need to add 1, limit is %u.", | |
2cf95c18 SS |
3613 | xhci->num_active_eps, xhci->limit_active_eps); |
3614 | return -ENOMEM; | |
3615 | } | |
3616 | xhci->num_active_eps += 1; | |
4bdfe4c3 XR |
3617 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3618 | "Adding 1 ep ctx, %u now active.", | |
2cf95c18 SS |
3619 | xhci->num_active_eps); |
3620 | return 0; | |
3621 | } | |
3622 | ||
3623 | ||
3ffbba95 SS |
3624 | /* |
3625 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command | |
3626 | * timed out, or allocating memory failed. Returns 1 on success. | |
3627 | */ | |
3628 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3629 | { | |
3630 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
3631 | unsigned long flags; | |
3632 | int timeleft; | |
3633 | int ret; | |
6e4468b9 | 3634 | union xhci_trb *cmd_trb; |
3ffbba95 SS |
3635 | |
3636 | spin_lock_irqsave(&xhci->lock, flags); | |
6e4468b9 | 3637 | cmd_trb = xhci->cmd_ring->dequeue; |
23e3be11 | 3638 | ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0); |
3ffbba95 SS |
3639 | if (ret) { |
3640 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3641 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
3642 | return 0; | |
3643 | } | |
23e3be11 | 3644 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3645 | spin_unlock_irqrestore(&xhci->lock, flags); |
3646 | ||
3647 | /* XXX: how much time for xHC slot assignment? */ | |
3648 | timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev, | |
6e4468b9 | 3649 | XHCI_CMD_DEFAULT_TIMEOUT); |
3ffbba95 SS |
3650 | if (timeleft <= 0) { |
3651 | xhci_warn(xhci, "%s while waiting for a slot\n", | |
3652 | timeleft == 0 ? "Timeout" : "Signal"); | |
6e4468b9 EF |
3653 | /* cancel the enable slot request */ |
3654 | return xhci_cancel_cmd(xhci, NULL, cmd_trb); | |
3ffbba95 SS |
3655 | } |
3656 | ||
3ffbba95 SS |
3657 | if (!xhci->slot_id) { |
3658 | xhci_err(xhci, "Error while assigning device slot ID\n"); | |
3ffbba95 SS |
3659 | return 0; |
3660 | } | |
2cf95c18 SS |
3661 | |
3662 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3663 | spin_lock_irqsave(&xhci->lock, flags); | |
3664 | ret = xhci_reserve_host_control_ep_resources(xhci); | |
3665 | if (ret) { | |
3666 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3667 | xhci_warn(xhci, "Not enough host resources, " | |
3668 | "active endpoint contexts = %u\n", | |
3669 | xhci->num_active_eps); | |
3670 | goto disable_slot; | |
3671 | } | |
3672 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3673 | } | |
3674 | /* Use GFP_NOIO, since this function can be called from | |
a6d940dd SS |
3675 | * xhci_discover_or_reset_device(), which may be called as part of |
3676 | * mass storage driver error handling. | |
3677 | */ | |
3678 | if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) { | |
3ffbba95 | 3679 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); |
2cf95c18 | 3680 | goto disable_slot; |
3ffbba95 SS |
3681 | } |
3682 | udev->slot_id = xhci->slot_id; | |
3683 | /* Is this a LS or FS device under a HS hub? */ | |
3684 | /* Hub or peripherial? */ | |
3ffbba95 | 3685 | return 1; |
2cf95c18 SS |
3686 | |
3687 | disable_slot: | |
3688 | /* Disable slot, if we can do it without mem alloc */ | |
3689 | spin_lock_irqsave(&xhci->lock, flags); | |
3690 | if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) | |
3691 | xhci_ring_cmd_db(xhci); | |
3692 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3693 | return 0; | |
3ffbba95 SS |
3694 | } |
3695 | ||
3696 | /* | |
3697 | * Issue an Address Device command (which will issue a SetAddress request to | |
3698 | * the device). | |
3699 | * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so | |
3700 | * we should only issue and wait on one address command at the same time. | |
3701 | * | |
3702 | * We add one to the device address issued by the hardware because the USB core | |
3703 | * uses address 1 for the root hubs (even though they're not really devices). | |
3704 | */ | |
3705 | int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) | |
3706 | { | |
3707 | unsigned long flags; | |
3708 | int timeleft; | |
3709 | struct xhci_virt_device *virt_dev; | |
3710 | int ret = 0; | |
3711 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
d115b048 JY |
3712 | struct xhci_slot_ctx *slot_ctx; |
3713 | struct xhci_input_control_ctx *ctrl_ctx; | |
8e595a5d | 3714 | u64 temp_64; |
6e4468b9 | 3715 | union xhci_trb *cmd_trb; |
3ffbba95 SS |
3716 | |
3717 | if (!udev->slot_id) { | |
84a99f6f XR |
3718 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3719 | "Bad Slot ID %d", udev->slot_id); | |
3ffbba95 SS |
3720 | return -EINVAL; |
3721 | } | |
3722 | ||
3ffbba95 SS |
3723 | virt_dev = xhci->devs[udev->slot_id]; |
3724 | ||
7ed603ec ME |
3725 | if (WARN_ON(!virt_dev)) { |
3726 | /* | |
3727 | * In plug/unplug torture test with an NEC controller, | |
3728 | * a zero-dereference was observed once due to virt_dev = 0. | |
3729 | * Print useful debug rather than crash if it is observed again! | |
3730 | */ | |
3731 | xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n", | |
3732 | udev->slot_id); | |
3733 | return -EINVAL; | |
3734 | } | |
3735 | ||
f0615c45 | 3736 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
92f8e767 SS |
3737 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
3738 | if (!ctrl_ctx) { | |
3739 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3740 | __func__); | |
3741 | return -EINVAL; | |
3742 | } | |
f0615c45 AX |
3743 | /* |
3744 | * If this is the first Set Address since device plug-in or | |
3745 | * virt_device realloaction after a resume with an xHCI power loss, | |
3746 | * then set up the slot context. | |
3747 | */ | |
3748 | if (!slot_ctx->dev_info) | |
3ffbba95 | 3749 | xhci_setup_addressable_virt_dev(xhci, udev); |
f0615c45 | 3750 | /* Otherwise, update the control endpoint ring enqueue pointer. */ |
2d1ee590 SS |
3751 | else |
3752 | xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev); | |
d31c285b SS |
3753 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); |
3754 | ctrl_ctx->drop_flags = 0; | |
3755 | ||
66e49d87 | 3756 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
d115b048 | 3757 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
1d27fabe XR |
3758 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
3759 | slot_ctx->dev_info >> 27); | |
3ffbba95 | 3760 | |
f88ba78d | 3761 | spin_lock_irqsave(&xhci->lock, flags); |
6e4468b9 | 3762 | cmd_trb = xhci->cmd_ring->dequeue; |
d115b048 JY |
3763 | ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma, |
3764 | udev->slot_id); | |
3ffbba95 SS |
3765 | if (ret) { |
3766 | spin_unlock_irqrestore(&xhci->lock, flags); | |
84a99f6f XR |
3767 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3768 | "FIXME: allocate a command ring segment"); | |
3ffbba95 SS |
3769 | return ret; |
3770 | } | |
23e3be11 | 3771 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3772 | spin_unlock_irqrestore(&xhci->lock, flags); |
3773 | ||
3774 | /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */ | |
3775 | timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev, | |
6e4468b9 | 3776 | XHCI_CMD_DEFAULT_TIMEOUT); |
3ffbba95 SS |
3777 | /* FIXME: From section 4.3.4: "Software shall be responsible for timing |
3778 | * the SetAddress() "recovery interval" required by USB and aborting the | |
3779 | * command on a timeout. | |
3780 | */ | |
3781 | if (timeleft <= 0) { | |
cd68176a | 3782 | xhci_warn(xhci, "%s while waiting for address device command\n", |
3ffbba95 | 3783 | timeleft == 0 ? "Timeout" : "Signal"); |
6e4468b9 EF |
3784 | /* cancel the address device command */ |
3785 | ret = xhci_cancel_cmd(xhci, NULL, cmd_trb); | |
3786 | if (ret < 0) | |
3787 | return ret; | |
3ffbba95 SS |
3788 | return -ETIME; |
3789 | } | |
3790 | ||
3ffbba95 SS |
3791 | switch (virt_dev->cmd_status) { |
3792 | case COMP_CTX_STATE: | |
3793 | case COMP_EBADSLT: | |
3794 | xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n", | |
3795 | udev->slot_id); | |
3796 | ret = -EINVAL; | |
3797 | break; | |
3798 | case COMP_TX_ERR: | |
3799 | dev_warn(&udev->dev, "Device not responding to set address.\n"); | |
3800 | ret = -EPROTO; | |
3801 | break; | |
f6ba6fe2 AH |
3802 | case COMP_DEV_ERR: |
3803 | dev_warn(&udev->dev, "ERROR: Incompatible device for address " | |
3804 | "device command.\n"); | |
3805 | ret = -ENODEV; | |
3806 | break; | |
3ffbba95 | 3807 | case COMP_SUCCESS: |
84a99f6f XR |
3808 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3809 | "Successful Address Device command"); | |
3ffbba95 SS |
3810 | break; |
3811 | default: | |
3812 | xhci_err(xhci, "ERROR: unexpected command completion " | |
3813 | "code 0x%x.\n", virt_dev->cmd_status); | |
66e49d87 | 3814 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
d115b048 | 3815 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); |
1d27fabe | 3816 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1); |
3ffbba95 SS |
3817 | ret = -EINVAL; |
3818 | break; | |
3819 | } | |
3820 | if (ret) { | |
3ffbba95 SS |
3821 | return ret; |
3822 | } | |
8e595a5d | 3823 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
84a99f6f XR |
3824 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3825 | "Op regs DCBAA ptr = %#016llx", temp_64); | |
3826 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3827 | "Slot ID %d dcbaa entry @%p = %#016llx", | |
3828 | udev->slot_id, | |
3829 | &xhci->dcbaa->dev_context_ptrs[udev->slot_id], | |
3830 | (unsigned long long) | |
3831 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id])); | |
3832 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3833 | "Output Context DMA address = %#08llx", | |
d115b048 | 3834 | (unsigned long long)virt_dev->out_ctx->dma); |
3ffbba95 | 3835 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
d115b048 | 3836 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
1d27fabe XR |
3837 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
3838 | slot_ctx->dev_info >> 27); | |
3ffbba95 | 3839 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
d115b048 | 3840 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); |
3ffbba95 SS |
3841 | /* |
3842 | * USB core uses address 1 for the roothubs, so we add one to the | |
3843 | * address given back to us by the HC. | |
3844 | */ | |
d115b048 | 3845 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
1d27fabe XR |
3846 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, |
3847 | slot_ctx->dev_info >> 27); | |
c8d4af8e AX |
3848 | /* Use kernel assigned address for devices; store xHC assigned |
3849 | * address locally. */ | |
28ccd296 ME |
3850 | virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK) |
3851 | + 1; | |
f94e0186 | 3852 | /* Zero the input context control for later use */ |
d115b048 JY |
3853 | ctrl_ctx->add_flags = 0; |
3854 | ctrl_ctx->drop_flags = 0; | |
3ffbba95 | 3855 | |
84a99f6f XR |
3856 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3857 | "Internal device address = %d", virt_dev->address); | |
3ffbba95 SS |
3858 | |
3859 | return 0; | |
3860 | } | |
3861 | ||
3f5eb141 LT |
3862 | /* |
3863 | * Transfer the port index into real index in the HW port status | |
3864 | * registers. Caculate offset between the port's PORTSC register | |
3865 | * and port status base. Divide the number of per port register | |
3866 | * to get the real index. The raw port number bases 1. | |
3867 | */ | |
3868 | int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1) | |
3869 | { | |
3870 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
3871 | __le32 __iomem *base_addr = &xhci->op_regs->port_status_base; | |
3872 | __le32 __iomem *addr; | |
3873 | int raw_port; | |
3874 | ||
3875 | if (hcd->speed != HCD_USB3) | |
3876 | addr = xhci->usb2_ports[port1 - 1]; | |
3877 | else | |
3878 | addr = xhci->usb3_ports[port1 - 1]; | |
3879 | ||
3880 | raw_port = (addr - base_addr)/NUM_PORT_REGS + 1; | |
3881 | return raw_port; | |
3882 | } | |
3883 | ||
a558ccdc MN |
3884 | /* |
3885 | * Issue an Evaluate Context command to change the Maximum Exit Latency in the | |
3886 | * slot context. If that succeeds, store the new MEL in the xhci_virt_device. | |
3887 | */ | |
d5c82feb | 3888 | static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, |
a558ccdc MN |
3889 | struct usb_device *udev, u16 max_exit_latency) |
3890 | { | |
3891 | struct xhci_virt_device *virt_dev; | |
3892 | struct xhci_command *command; | |
3893 | struct xhci_input_control_ctx *ctrl_ctx; | |
3894 | struct xhci_slot_ctx *slot_ctx; | |
3895 | unsigned long flags; | |
3896 | int ret; | |
3897 | ||
3898 | spin_lock_irqsave(&xhci->lock, flags); | |
3899 | if (max_exit_latency == xhci->devs[udev->slot_id]->current_mel) { | |
3900 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3901 | return 0; | |
3902 | } | |
3903 | ||
3904 | /* Attempt to issue an Evaluate Context command to change the MEL. */ | |
3905 | virt_dev = xhci->devs[udev->slot_id]; | |
3906 | command = xhci->lpm_command; | |
92f8e767 SS |
3907 | ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx); |
3908 | if (!ctrl_ctx) { | |
3909 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3910 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3911 | __func__); | |
3912 | return -ENOMEM; | |
3913 | } | |
3914 | ||
a558ccdc MN |
3915 | xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx); |
3916 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3917 | ||
a558ccdc MN |
3918 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
3919 | slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx); | |
3920 | slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT)); | |
3921 | slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency); | |
3922 | ||
3a7fa5be XR |
3923 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
3924 | "Set up evaluate context for LPM MEL change."); | |
a558ccdc MN |
3925 | xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id); |
3926 | xhci_dbg_ctx(xhci, command->in_ctx, 0); | |
3927 | ||
3928 | /* Issue and wait for the evaluate context command. */ | |
3929 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3930 | true, true); | |
3931 | xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id); | |
3932 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0); | |
3933 | ||
3934 | if (!ret) { | |
3935 | spin_lock_irqsave(&xhci->lock, flags); | |
3936 | virt_dev->current_mel = max_exit_latency; | |
3937 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3938 | } | |
3939 | return ret; | |
3940 | } | |
3941 | ||
84ebc102 | 3942 | #ifdef CONFIG_PM_RUNTIME |
9574323c AX |
3943 | |
3944 | /* BESL to HIRD Encoding array for USB2 LPM */ | |
3945 | static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000, | |
3946 | 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000}; | |
3947 | ||
3948 | /* Calculate HIRD/BESL for USB2 PORTPMSC*/ | |
f99298bf AX |
3949 | static int xhci_calculate_hird_besl(struct xhci_hcd *xhci, |
3950 | struct usb_device *udev) | |
9574323c | 3951 | { |
f99298bf AX |
3952 | int u2del, besl, besl_host; |
3953 | int besl_device = 0; | |
3954 | u32 field; | |
3955 | ||
3956 | u2del = HCS_U2_LATENCY(xhci->hcs_params3); | |
3957 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
9574323c | 3958 | |
f99298bf AX |
3959 | if (field & USB_BESL_SUPPORT) { |
3960 | for (besl_host = 0; besl_host < 16; besl_host++) { | |
3961 | if (xhci_besl_encoding[besl_host] >= u2del) | |
9574323c AX |
3962 | break; |
3963 | } | |
f99298bf AX |
3964 | /* Use baseline BESL value as default */ |
3965 | if (field & USB_BESL_BASELINE_VALID) | |
3966 | besl_device = USB_GET_BESL_BASELINE(field); | |
3967 | else if (field & USB_BESL_DEEP_VALID) | |
3968 | besl_device = USB_GET_BESL_DEEP(field); | |
9574323c AX |
3969 | } else { |
3970 | if (u2del <= 50) | |
f99298bf | 3971 | besl_host = 0; |
9574323c | 3972 | else |
f99298bf | 3973 | besl_host = (u2del - 51) / 75 + 1; |
9574323c AX |
3974 | } |
3975 | ||
f99298bf AX |
3976 | besl = besl_host + besl_device; |
3977 | if (besl > 15) | |
3978 | besl = 15; | |
3979 | ||
3980 | return besl; | |
9574323c AX |
3981 | } |
3982 | ||
a558ccdc MN |
3983 | /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */ |
3984 | static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev) | |
3985 | { | |
3986 | u32 field; | |
3987 | int l1; | |
3988 | int besld = 0; | |
3989 | int hirdm = 0; | |
3990 | ||
3991 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
3992 | ||
3993 | /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */ | |
17f34867 | 3994 | l1 = udev->l1_params.timeout / 256; |
a558ccdc MN |
3995 | |
3996 | /* device has preferred BESLD */ | |
3997 | if (field & USB_BESL_DEEP_VALID) { | |
3998 | besld = USB_GET_BESL_DEEP(field); | |
3999 | hirdm = 1; | |
4000 | } | |
4001 | ||
4002 | return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm); | |
4003 | } | |
4004 | ||
9574323c AX |
4005 | static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd, |
4006 | struct usb_device *udev) | |
4007 | { | |
4008 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4009 | struct dev_info *dev_info; | |
4010 | __le32 __iomem **port_array; | |
4011 | __le32 __iomem *addr, *pm_addr; | |
4012 | u32 temp, dev_id; | |
4013 | unsigned int port_num; | |
4014 | unsigned long flags; | |
f99298bf | 4015 | int hird; |
9574323c AX |
4016 | int ret; |
4017 | ||
4018 | if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support || | |
4019 | !udev->lpm_capable) | |
4020 | return -EINVAL; | |
4021 | ||
4022 | /* we only support lpm for non-hub device connected to root hub yet */ | |
4023 | if (!udev->parent || udev->parent->parent || | |
4024 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4025 | return -EINVAL; | |
4026 | ||
4027 | spin_lock_irqsave(&xhci->lock, flags); | |
4028 | ||
4029 | /* Look for devices in lpm_failed_devs list */ | |
4030 | dev_id = le16_to_cpu(udev->descriptor.idVendor) << 16 | | |
4031 | le16_to_cpu(udev->descriptor.idProduct); | |
4032 | list_for_each_entry(dev_info, &xhci->lpm_failed_devs, list) { | |
4033 | if (dev_info->dev_id == dev_id) { | |
4034 | ret = -EINVAL; | |
4035 | goto finish; | |
4036 | } | |
4037 | } | |
4038 | ||
4039 | port_array = xhci->usb2_ports; | |
4040 | port_num = udev->portnum - 1; | |
4041 | ||
4042 | if (port_num > HCS_MAX_PORTS(xhci->hcs_params1)) { | |
4043 | xhci_dbg(xhci, "invalid port number %d\n", udev->portnum); | |
4044 | ret = -EINVAL; | |
4045 | goto finish; | |
4046 | } | |
4047 | ||
4048 | /* | |
4049 | * Test USB 2.0 software LPM. | |
4050 | * FIXME: some xHCI 1.0 hosts may implement a new register to set up | |
4051 | * hardware-controlled USB 2.0 LPM. See section 5.4.11 and 4.23.5.1.1.1 | |
4052 | * in the June 2011 errata release. | |
4053 | */ | |
4054 | xhci_dbg(xhci, "test port %d software LPM\n", port_num); | |
4055 | /* | |
4056 | * Set L1 Device Slot and HIRD/BESL. | |
4057 | * Check device's USB 2.0 extension descriptor to determine whether | |
4058 | * HIRD or BESL shoule be used. See USB2.0 LPM errata. | |
4059 | */ | |
b6e76371 | 4060 | pm_addr = port_array[port_num] + PORTPMSC; |
f99298bf | 4061 | hird = xhci_calculate_hird_besl(xhci, udev); |
9574323c AX |
4062 | temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird); |
4063 | xhci_writel(xhci, temp, pm_addr); | |
4064 | ||
4065 | /* Set port link state to U2(L1) */ | |
4066 | addr = port_array[port_num]; | |
4067 | xhci_set_link_state(xhci, port_array, port_num, XDEV_U2); | |
4068 | ||
4069 | /* wait for ACK */ | |
4070 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4071 | msleep(10); | |
4072 | spin_lock_irqsave(&xhci->lock, flags); | |
4073 | ||
4074 | /* Check L1 Status */ | |
2611bd18 SS |
4075 | ret = xhci_handshake(xhci, pm_addr, |
4076 | PORT_L1S_MASK, PORT_L1S_SUCCESS, 125); | |
9574323c AX |
4077 | if (ret != -ETIMEDOUT) { |
4078 | /* enter L1 successfully */ | |
4079 | temp = xhci_readl(xhci, addr); | |
4080 | xhci_dbg(xhci, "port %d entered L1 state, port status 0x%x\n", | |
4081 | port_num, temp); | |
4082 | ret = 0; | |
4083 | } else { | |
4084 | temp = xhci_readl(xhci, pm_addr); | |
4085 | xhci_dbg(xhci, "port %d software lpm failed, L1 status %d\n", | |
4086 | port_num, temp & PORT_L1S_MASK); | |
4087 | ret = -EINVAL; | |
4088 | } | |
4089 | ||
4090 | /* Resume the port */ | |
4091 | xhci_set_link_state(xhci, port_array, port_num, XDEV_U0); | |
4092 | ||
4093 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4094 | msleep(10); | |
4095 | spin_lock_irqsave(&xhci->lock, flags); | |
4096 | ||
4097 | /* Clear PLC */ | |
4098 | xhci_test_and_clear_bit(xhci, port_array, port_num, PORT_PLC); | |
4099 | ||
4100 | /* Check PORTSC to make sure the device is in the right state */ | |
4101 | if (!ret) { | |
4102 | temp = xhci_readl(xhci, addr); | |
4103 | xhci_dbg(xhci, "resumed port %d status 0x%x\n", port_num, temp); | |
4104 | if (!(temp & PORT_CONNECT) || !(temp & PORT_PE) || | |
4105 | (temp & PORT_PLS_MASK) != XDEV_U0) { | |
4106 | xhci_dbg(xhci, "port L1 resume fail\n"); | |
4107 | ret = -EINVAL; | |
4108 | } | |
4109 | } | |
4110 | ||
4111 | if (ret) { | |
4112 | /* Insert dev to lpm_failed_devs list */ | |
4113 | xhci_warn(xhci, "device LPM test failed, may disconnect and " | |
4114 | "re-enumerate\n"); | |
4115 | dev_info = kzalloc(sizeof(struct dev_info), GFP_ATOMIC); | |
4116 | if (!dev_info) { | |
4117 | ret = -ENOMEM; | |
4118 | goto finish; | |
4119 | } | |
4120 | dev_info->dev_id = dev_id; | |
4121 | INIT_LIST_HEAD(&dev_info->list); | |
4122 | list_add(&dev_info->list, &xhci->lpm_failed_devs); | |
4123 | } else { | |
4124 | xhci_ring_device(xhci, udev->slot_id); | |
4125 | } | |
4126 | ||
4127 | finish: | |
4128 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4129 | return ret; | |
4130 | } | |
4131 | ||
65580b43 AX |
4132 | int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
4133 | struct usb_device *udev, int enable) | |
4134 | { | |
4135 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4136 | __le32 __iomem **port_array; | |
a558ccdc MN |
4137 | __le32 __iomem *pm_addr, *hlpm_addr; |
4138 | u32 pm_val, hlpm_val, field; | |
65580b43 AX |
4139 | unsigned int port_num; |
4140 | unsigned long flags; | |
a558ccdc MN |
4141 | int hird, exit_latency; |
4142 | int ret; | |
65580b43 AX |
4143 | |
4144 | if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support || | |
4145 | !udev->lpm_capable) | |
4146 | return -EPERM; | |
4147 | ||
4148 | if (!udev->parent || udev->parent->parent || | |
4149 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4150 | return -EPERM; | |
4151 | ||
4152 | if (udev->usb2_hw_lpm_capable != 1) | |
4153 | return -EPERM; | |
4154 | ||
4155 | spin_lock_irqsave(&xhci->lock, flags); | |
4156 | ||
4157 | port_array = xhci->usb2_ports; | |
4158 | port_num = udev->portnum - 1; | |
b6e76371 | 4159 | pm_addr = port_array[port_num] + PORTPMSC; |
a558ccdc MN |
4160 | pm_val = xhci_readl(xhci, pm_addr); |
4161 | hlpm_addr = port_array[port_num] + PORTHLPMC; | |
4162 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
65580b43 AX |
4163 | |
4164 | xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n", | |
4165 | enable ? "enable" : "disable", port_num); | |
4166 | ||
65580b43 | 4167 | if (enable) { |
a558ccdc MN |
4168 | /* Host supports BESL timeout instead of HIRD */ |
4169 | if (udev->usb2_hw_lpm_besl_capable) { | |
4170 | /* if device doesn't have a preferred BESL value use a | |
4171 | * default one which works with mixed HIRD and BESL | |
4172 | * systems. See XHCI_DEFAULT_BESL definition in xhci.h | |
4173 | */ | |
4174 | if ((field & USB_BESL_SUPPORT) && | |
4175 | (field & USB_BESL_BASELINE_VALID)) | |
4176 | hird = USB_GET_BESL_BASELINE(field); | |
4177 | else | |
17f34867 | 4178 | hird = udev->l1_params.besl; |
a558ccdc MN |
4179 | |
4180 | exit_latency = xhci_besl_encoding[hird]; | |
4181 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4182 | ||
4183 | /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx | |
4184 | * input context for link powermanagement evaluate | |
4185 | * context commands. It is protected by hcd->bandwidth | |
4186 | * mutex and is shared by all devices. We need to set | |
4187 | * the max ext latency in USB 2 BESL LPM as well, so | |
4188 | * use the same mutex and xhci_change_max_exit_latency() | |
4189 | */ | |
4190 | mutex_lock(hcd->bandwidth_mutex); | |
4191 | ret = xhci_change_max_exit_latency(xhci, udev, | |
4192 | exit_latency); | |
4193 | mutex_unlock(hcd->bandwidth_mutex); | |
4194 | ||
4195 | if (ret < 0) | |
4196 | return ret; | |
4197 | spin_lock_irqsave(&xhci->lock, flags); | |
4198 | ||
4199 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); | |
4200 | xhci_writel(xhci, hlpm_val, hlpm_addr); | |
4201 | /* flush write */ | |
4202 | xhci_readl(xhci, hlpm_addr); | |
4203 | } else { | |
4204 | hird = xhci_calculate_hird_besl(xhci, udev); | |
4205 | } | |
4206 | ||
4207 | pm_val &= ~PORT_HIRD_MASK; | |
4208 | pm_val |= PORT_HIRD(hird) | PORT_RWE; | |
4209 | xhci_writel(xhci, pm_val, pm_addr); | |
4210 | pm_val = xhci_readl(xhci, pm_addr); | |
4211 | pm_val |= PORT_HLE; | |
4212 | xhci_writel(xhci, pm_val, pm_addr); | |
4213 | /* flush write */ | |
4214 | xhci_readl(xhci, pm_addr); | |
65580b43 | 4215 | } else { |
a558ccdc MN |
4216 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK); |
4217 | xhci_writel(xhci, pm_val, pm_addr); | |
4218 | /* flush write */ | |
4219 | xhci_readl(xhci, pm_addr); | |
4220 | if (udev->usb2_hw_lpm_besl_capable) { | |
4221 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4222 | mutex_lock(hcd->bandwidth_mutex); | |
4223 | xhci_change_max_exit_latency(xhci, udev, 0); | |
4224 | mutex_unlock(hcd->bandwidth_mutex); | |
4225 | return 0; | |
4226 | } | |
65580b43 AX |
4227 | } |
4228 | ||
4229 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4230 | return 0; | |
4231 | } | |
4232 | ||
b630d4b9 MN |
4233 | /* check if a usb2 port supports a given extened capability protocol |
4234 | * only USB2 ports extended protocol capability values are cached. | |
4235 | * Return 1 if capability is supported | |
4236 | */ | |
4237 | static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port, | |
4238 | unsigned capability) | |
4239 | { | |
4240 | u32 port_offset, port_count; | |
4241 | int i; | |
4242 | ||
4243 | for (i = 0; i < xhci->num_ext_caps; i++) { | |
4244 | if (xhci->ext_caps[i] & capability) { | |
4245 | /* port offsets starts at 1 */ | |
4246 | port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1; | |
4247 | port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]); | |
4248 | if (port >= port_offset && | |
4249 | port < port_offset + port_count) | |
4250 | return 1; | |
4251 | } | |
4252 | } | |
4253 | return 0; | |
4254 | } | |
4255 | ||
b01bcbf7 SS |
4256 | int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
4257 | { | |
4258 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4259 | int ret; | |
b630d4b9 | 4260 | int portnum = udev->portnum - 1; |
b01bcbf7 SS |
4261 | |
4262 | ret = xhci_usb2_software_lpm_test(hcd, udev); | |
4263 | if (!ret) { | |
4264 | xhci_dbg(xhci, "software LPM test succeed\n"); | |
b630d4b9 MN |
4265 | if (xhci->hw_lpm_support == 1 && |
4266 | xhci_check_usb2_port_capability(xhci, portnum, XHCI_HLC)) { | |
b01bcbf7 | 4267 | udev->usb2_hw_lpm_capable = 1; |
17f34867 MN |
4268 | udev->l1_params.timeout = XHCI_L1_TIMEOUT; |
4269 | udev->l1_params.besl = XHCI_DEFAULT_BESL; | |
a558ccdc MN |
4270 | if (xhci_check_usb2_port_capability(xhci, portnum, |
4271 | XHCI_BLC)) | |
4272 | udev->usb2_hw_lpm_besl_capable = 1; | |
b01bcbf7 SS |
4273 | ret = xhci_set_usb2_hardware_lpm(hcd, udev, 1); |
4274 | if (!ret) | |
4275 | udev->usb2_hw_lpm_enabled = 1; | |
4276 | } | |
4277 | } | |
4278 | ||
4279 | return 0; | |
4280 | } | |
4281 | ||
4282 | #else | |
4283 | ||
4284 | int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, | |
4285 | struct usb_device *udev, int enable) | |
4286 | { | |
4287 | return 0; | |
4288 | } | |
4289 | ||
4290 | int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) | |
4291 | { | |
4292 | return 0; | |
4293 | } | |
4294 | ||
84ebc102 | 4295 | #endif /* CONFIG_PM_RUNTIME */ |
b01bcbf7 | 4296 | |
3b3db026 SS |
4297 | /*---------------------- USB 3.0 Link PM functions ------------------------*/ |
4298 | ||
b01bcbf7 | 4299 | #ifdef CONFIG_PM |
e3567d2c SS |
4300 | /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */ |
4301 | static unsigned long long xhci_service_interval_to_ns( | |
4302 | struct usb_endpoint_descriptor *desc) | |
4303 | { | |
16b45fdf | 4304 | return (1ULL << (desc->bInterval - 1)) * 125 * 1000; |
e3567d2c SS |
4305 | } |
4306 | ||
3b3db026 SS |
4307 | static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev, |
4308 | enum usb3_link_state state) | |
4309 | { | |
4310 | unsigned long long sel; | |
4311 | unsigned long long pel; | |
4312 | unsigned int max_sel_pel; | |
4313 | char *state_name; | |
4314 | ||
4315 | switch (state) { | |
4316 | case USB3_LPM_U1: | |
4317 | /* Convert SEL and PEL stored in nanoseconds to microseconds */ | |
4318 | sel = DIV_ROUND_UP(udev->u1_params.sel, 1000); | |
4319 | pel = DIV_ROUND_UP(udev->u1_params.pel, 1000); | |
4320 | max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL; | |
4321 | state_name = "U1"; | |
4322 | break; | |
4323 | case USB3_LPM_U2: | |
4324 | sel = DIV_ROUND_UP(udev->u2_params.sel, 1000); | |
4325 | pel = DIV_ROUND_UP(udev->u2_params.pel, 1000); | |
4326 | max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL; | |
4327 | state_name = "U2"; | |
4328 | break; | |
4329 | default: | |
4330 | dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n", | |
4331 | __func__); | |
e25e62ae | 4332 | return USB3_LPM_DISABLED; |
3b3db026 SS |
4333 | } |
4334 | ||
4335 | if (sel <= max_sel_pel && pel <= max_sel_pel) | |
4336 | return USB3_LPM_DEVICE_INITIATED; | |
4337 | ||
4338 | if (sel > max_sel_pel) | |
4339 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
4340 | "due to long SEL %llu ms\n", | |
4341 | state_name, sel); | |
4342 | else | |
4343 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
03e64e96 | 4344 | "due to long PEL %llu ms\n", |
3b3db026 SS |
4345 | state_name, pel); |
4346 | return USB3_LPM_DISABLED; | |
4347 | } | |
4348 | ||
e3567d2c SS |
4349 | /* Returns the hub-encoded U1 timeout value. |
4350 | * The U1 timeout should be the maximum of the following values: | |
4351 | * - For control endpoints, U1 system exit latency (SEL) * 3 | |
4352 | * - For bulk endpoints, U1 SEL * 5 | |
4353 | * - For interrupt endpoints: | |
4354 | * - Notification EPs, U1 SEL * 3 | |
4355 | * - Periodic EPs, max(105% of bInterval, U1 SEL * 2) | |
4356 | * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2) | |
4357 | */ | |
4358 | static u16 xhci_calculate_intel_u1_timeout(struct usb_device *udev, | |
4359 | struct usb_endpoint_descriptor *desc) | |
4360 | { | |
4361 | unsigned long long timeout_ns; | |
4362 | int ep_type; | |
4363 | int intr_type; | |
4364 | ||
4365 | ep_type = usb_endpoint_type(desc); | |
4366 | switch (ep_type) { | |
4367 | case USB_ENDPOINT_XFER_CONTROL: | |
4368 | timeout_ns = udev->u1_params.sel * 3; | |
4369 | break; | |
4370 | case USB_ENDPOINT_XFER_BULK: | |
4371 | timeout_ns = udev->u1_params.sel * 5; | |
4372 | break; | |
4373 | case USB_ENDPOINT_XFER_INT: | |
4374 | intr_type = usb_endpoint_interrupt_type(desc); | |
4375 | if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) { | |
4376 | timeout_ns = udev->u1_params.sel * 3; | |
4377 | break; | |
4378 | } | |
4379 | /* Otherwise the calculation is the same as isoc eps */ | |
4380 | case USB_ENDPOINT_XFER_ISOC: | |
4381 | timeout_ns = xhci_service_interval_to_ns(desc); | |
c88db160 | 4382 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100); |
e3567d2c SS |
4383 | if (timeout_ns < udev->u1_params.sel * 2) |
4384 | timeout_ns = udev->u1_params.sel * 2; | |
4385 | break; | |
4386 | default: | |
4387 | return 0; | |
4388 | } | |
4389 | ||
4390 | /* The U1 timeout is encoded in 1us intervals. */ | |
c88db160 | 4391 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000); |
e3567d2c SS |
4392 | /* Don't return a timeout of zero, because that's USB3_LPM_DISABLED. */ |
4393 | if (timeout_ns == USB3_LPM_DISABLED) | |
4394 | timeout_ns++; | |
4395 | ||
4396 | /* If the necessary timeout value is bigger than what we can set in the | |
4397 | * USB 3.0 hub, we have to disable hub-initiated U1. | |
4398 | */ | |
4399 | if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT) | |
4400 | return timeout_ns; | |
4401 | dev_dbg(&udev->dev, "Hub-initiated U1 disabled " | |
4402 | "due to long timeout %llu ms\n", timeout_ns); | |
4403 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1); | |
4404 | } | |
4405 | ||
4406 | /* Returns the hub-encoded U2 timeout value. | |
4407 | * The U2 timeout should be the maximum of: | |
4408 | * - 10 ms (to avoid the bandwidth impact on the scheduler) | |
4409 | * - largest bInterval of any active periodic endpoint (to avoid going | |
4410 | * into lower power link states between intervals). | |
4411 | * - the U2 Exit Latency of the device | |
4412 | */ | |
4413 | static u16 xhci_calculate_intel_u2_timeout(struct usb_device *udev, | |
4414 | struct usb_endpoint_descriptor *desc) | |
4415 | { | |
4416 | unsigned long long timeout_ns; | |
4417 | unsigned long long u2_del_ns; | |
4418 | ||
4419 | timeout_ns = 10 * 1000 * 1000; | |
4420 | ||
4421 | if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) && | |
4422 | (xhci_service_interval_to_ns(desc) > timeout_ns)) | |
4423 | timeout_ns = xhci_service_interval_to_ns(desc); | |
4424 | ||
966e7a85 | 4425 | u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL; |
e3567d2c SS |
4426 | if (u2_del_ns > timeout_ns) |
4427 | timeout_ns = u2_del_ns; | |
4428 | ||
4429 | /* The U2 timeout is encoded in 256us intervals */ | |
c88db160 | 4430 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000); |
e3567d2c SS |
4431 | /* If the necessary timeout value is bigger than what we can set in the |
4432 | * USB 3.0 hub, we have to disable hub-initiated U2. | |
4433 | */ | |
4434 | if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT) | |
4435 | return timeout_ns; | |
4436 | dev_dbg(&udev->dev, "Hub-initiated U2 disabled " | |
4437 | "due to long timeout %llu ms\n", timeout_ns); | |
4438 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2); | |
4439 | } | |
4440 | ||
3b3db026 SS |
4441 | static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci, |
4442 | struct usb_device *udev, | |
4443 | struct usb_endpoint_descriptor *desc, | |
4444 | enum usb3_link_state state, | |
4445 | u16 *timeout) | |
4446 | { | |
e3567d2c SS |
4447 | if (state == USB3_LPM_U1) { |
4448 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4449 | return xhci_calculate_intel_u1_timeout(udev, desc); | |
4450 | } else { | |
4451 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4452 | return xhci_calculate_intel_u2_timeout(udev, desc); | |
4453 | } | |
4454 | ||
3b3db026 SS |
4455 | return USB3_LPM_DISABLED; |
4456 | } | |
4457 | ||
4458 | static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci, | |
4459 | struct usb_device *udev, | |
4460 | struct usb_endpoint_descriptor *desc, | |
4461 | enum usb3_link_state state, | |
4462 | u16 *timeout) | |
4463 | { | |
4464 | u16 alt_timeout; | |
4465 | ||
4466 | alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev, | |
4467 | desc, state, timeout); | |
4468 | ||
4469 | /* If we found we can't enable hub-initiated LPM, or | |
4470 | * the U1 or U2 exit latency was too high to allow | |
4471 | * device-initiated LPM as well, just stop searching. | |
4472 | */ | |
4473 | if (alt_timeout == USB3_LPM_DISABLED || | |
4474 | alt_timeout == USB3_LPM_DEVICE_INITIATED) { | |
4475 | *timeout = alt_timeout; | |
4476 | return -E2BIG; | |
4477 | } | |
4478 | if (alt_timeout > *timeout) | |
4479 | *timeout = alt_timeout; | |
4480 | return 0; | |
4481 | } | |
4482 | ||
4483 | static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci, | |
4484 | struct usb_device *udev, | |
4485 | struct usb_host_interface *alt, | |
4486 | enum usb3_link_state state, | |
4487 | u16 *timeout) | |
4488 | { | |
4489 | int j; | |
4490 | ||
4491 | for (j = 0; j < alt->desc.bNumEndpoints; j++) { | |
4492 | if (xhci_update_timeout_for_endpoint(xhci, udev, | |
4493 | &alt->endpoint[j].desc, state, timeout)) | |
4494 | return -E2BIG; | |
4495 | continue; | |
4496 | } | |
4497 | return 0; | |
4498 | } | |
4499 | ||
e3567d2c SS |
4500 | static int xhci_check_intel_tier_policy(struct usb_device *udev, |
4501 | enum usb3_link_state state) | |
4502 | { | |
4503 | struct usb_device *parent; | |
4504 | unsigned int num_hubs; | |
4505 | ||
4506 | if (state == USB3_LPM_U2) | |
4507 | return 0; | |
4508 | ||
4509 | /* Don't enable U1 if the device is on a 2nd tier hub or lower. */ | |
4510 | for (parent = udev->parent, num_hubs = 0; parent->parent; | |
4511 | parent = parent->parent) | |
4512 | num_hubs++; | |
4513 | ||
4514 | if (num_hubs < 2) | |
4515 | return 0; | |
4516 | ||
4517 | dev_dbg(&udev->dev, "Disabling U1 link state for device" | |
4518 | " below second-tier hub.\n"); | |
4519 | dev_dbg(&udev->dev, "Plug device into first-tier hub " | |
4520 | "to decrease power consumption.\n"); | |
4521 | return -E2BIG; | |
4522 | } | |
4523 | ||
3b3db026 SS |
4524 | static int xhci_check_tier_policy(struct xhci_hcd *xhci, |
4525 | struct usb_device *udev, | |
4526 | enum usb3_link_state state) | |
4527 | { | |
e3567d2c SS |
4528 | if (xhci->quirks & XHCI_INTEL_HOST) |
4529 | return xhci_check_intel_tier_policy(udev, state); | |
3b3db026 SS |
4530 | return -EINVAL; |
4531 | } | |
4532 | ||
4533 | /* Returns the U1 or U2 timeout that should be enabled. | |
4534 | * If the tier check or timeout setting functions return with a non-zero exit | |
4535 | * code, that means the timeout value has been finalized and we shouldn't look | |
4536 | * at any more endpoints. | |
4537 | */ | |
4538 | static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd, | |
4539 | struct usb_device *udev, enum usb3_link_state state) | |
4540 | { | |
4541 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4542 | struct usb_host_config *config; | |
4543 | char *state_name; | |
4544 | int i; | |
4545 | u16 timeout = USB3_LPM_DISABLED; | |
4546 | ||
4547 | if (state == USB3_LPM_U1) | |
4548 | state_name = "U1"; | |
4549 | else if (state == USB3_LPM_U2) | |
4550 | state_name = "U2"; | |
4551 | else { | |
4552 | dev_warn(&udev->dev, "Can't enable unknown link state %i\n", | |
4553 | state); | |
4554 | return timeout; | |
4555 | } | |
4556 | ||
4557 | if (xhci_check_tier_policy(xhci, udev, state) < 0) | |
4558 | return timeout; | |
4559 | ||
4560 | /* Gather some information about the currently installed configuration | |
4561 | * and alternate interface settings. | |
4562 | */ | |
4563 | if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc, | |
4564 | state, &timeout)) | |
4565 | return timeout; | |
4566 | ||
4567 | config = udev->actconfig; | |
4568 | if (!config) | |
4569 | return timeout; | |
4570 | ||
4571 | for (i = 0; i < USB_MAXINTERFACES; i++) { | |
4572 | struct usb_driver *driver; | |
4573 | struct usb_interface *intf = config->interface[i]; | |
4574 | ||
4575 | if (!intf) | |
4576 | continue; | |
4577 | ||
4578 | /* Check if any currently bound drivers want hub-initiated LPM | |
4579 | * disabled. | |
4580 | */ | |
4581 | if (intf->dev.driver) { | |
4582 | driver = to_usb_driver(intf->dev.driver); | |
4583 | if (driver && driver->disable_hub_initiated_lpm) { | |
4584 | dev_dbg(&udev->dev, "Hub-initiated %s disabled " | |
4585 | "at request of driver %s\n", | |
4586 | state_name, driver->name); | |
4587 | return xhci_get_timeout_no_hub_lpm(udev, state); | |
4588 | } | |
4589 | } | |
4590 | ||
4591 | /* Not sure how this could happen... */ | |
4592 | if (!intf->cur_altsetting) | |
4593 | continue; | |
4594 | ||
4595 | if (xhci_update_timeout_for_interface(xhci, udev, | |
4596 | intf->cur_altsetting, | |
4597 | state, &timeout)) | |
4598 | return timeout; | |
4599 | } | |
4600 | return timeout; | |
4601 | } | |
4602 | ||
3b3db026 SS |
4603 | static int calculate_max_exit_latency(struct usb_device *udev, |
4604 | enum usb3_link_state state_changed, | |
4605 | u16 hub_encoded_timeout) | |
4606 | { | |
4607 | unsigned long long u1_mel_us = 0; | |
4608 | unsigned long long u2_mel_us = 0; | |
4609 | unsigned long long mel_us = 0; | |
4610 | bool disabling_u1; | |
4611 | bool disabling_u2; | |
4612 | bool enabling_u1; | |
4613 | bool enabling_u2; | |
4614 | ||
4615 | disabling_u1 = (state_changed == USB3_LPM_U1 && | |
4616 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4617 | disabling_u2 = (state_changed == USB3_LPM_U2 && | |
4618 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4619 | ||
4620 | enabling_u1 = (state_changed == USB3_LPM_U1 && | |
4621 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4622 | enabling_u2 = (state_changed == USB3_LPM_U2 && | |
4623 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4624 | ||
4625 | /* If U1 was already enabled and we're not disabling it, | |
4626 | * or we're going to enable U1, account for the U1 max exit latency. | |
4627 | */ | |
4628 | if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) || | |
4629 | enabling_u1) | |
4630 | u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000); | |
4631 | if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) || | |
4632 | enabling_u2) | |
4633 | u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000); | |
4634 | ||
4635 | if (u1_mel_us > u2_mel_us) | |
4636 | mel_us = u1_mel_us; | |
4637 | else | |
4638 | mel_us = u2_mel_us; | |
4639 | /* xHCI host controller max exit latency field is only 16 bits wide. */ | |
4640 | if (mel_us > MAX_EXIT) { | |
4641 | dev_warn(&udev->dev, "Link PM max exit latency of %lluus " | |
4642 | "is too big.\n", mel_us); | |
4643 | return -E2BIG; | |
4644 | } | |
4645 | return mel_us; | |
4646 | } | |
4647 | ||
4648 | /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */ | |
4649 | int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, | |
4650 | struct usb_device *udev, enum usb3_link_state state) | |
4651 | { | |
4652 | struct xhci_hcd *xhci; | |
4653 | u16 hub_encoded_timeout; | |
4654 | int mel; | |
4655 | int ret; | |
4656 | ||
4657 | xhci = hcd_to_xhci(hcd); | |
4658 | /* The LPM timeout values are pretty host-controller specific, so don't | |
4659 | * enable hub-initiated timeouts unless the vendor has provided | |
4660 | * information about their timeout algorithm. | |
4661 | */ | |
4662 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4663 | !xhci->devs[udev->slot_id]) | |
4664 | return USB3_LPM_DISABLED; | |
4665 | ||
4666 | hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state); | |
4667 | mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout); | |
4668 | if (mel < 0) { | |
4669 | /* Max Exit Latency is too big, disable LPM. */ | |
4670 | hub_encoded_timeout = USB3_LPM_DISABLED; | |
4671 | mel = 0; | |
4672 | } | |
4673 | ||
4674 | ret = xhci_change_max_exit_latency(xhci, udev, mel); | |
4675 | if (ret) | |
4676 | return ret; | |
4677 | return hub_encoded_timeout; | |
4678 | } | |
4679 | ||
4680 | int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, | |
4681 | struct usb_device *udev, enum usb3_link_state state) | |
4682 | { | |
4683 | struct xhci_hcd *xhci; | |
4684 | u16 mel; | |
4685 | int ret; | |
4686 | ||
4687 | xhci = hcd_to_xhci(hcd); | |
4688 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4689 | !xhci->devs[udev->slot_id]) | |
4690 | return 0; | |
4691 | ||
4692 | mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED); | |
4693 | ret = xhci_change_max_exit_latency(xhci, udev, mel); | |
4694 | if (ret) | |
4695 | return ret; | |
4696 | return 0; | |
4697 | } | |
b01bcbf7 | 4698 | #else /* CONFIG_PM */ |
9574323c | 4699 | |
b01bcbf7 SS |
4700 | int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
4701 | struct usb_device *udev, enum usb3_link_state state) | |
65580b43 | 4702 | { |
b01bcbf7 | 4703 | return USB3_LPM_DISABLED; |
65580b43 AX |
4704 | } |
4705 | ||
b01bcbf7 SS |
4706 | int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, |
4707 | struct usb_device *udev, enum usb3_link_state state) | |
9574323c AX |
4708 | { |
4709 | return 0; | |
4710 | } | |
b01bcbf7 | 4711 | #endif /* CONFIG_PM */ |
9574323c | 4712 | |
b01bcbf7 | 4713 | /*-------------------------------------------------------------------------*/ |
9574323c | 4714 | |
ac1c1b7f SS |
4715 | /* Once a hub descriptor is fetched for a device, we need to update the xHC's |
4716 | * internal data structures for the device. | |
4717 | */ | |
4718 | int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, | |
4719 | struct usb_tt *tt, gfp_t mem_flags) | |
4720 | { | |
4721 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4722 | struct xhci_virt_device *vdev; | |
4723 | struct xhci_command *config_cmd; | |
4724 | struct xhci_input_control_ctx *ctrl_ctx; | |
4725 | struct xhci_slot_ctx *slot_ctx; | |
4726 | unsigned long flags; | |
4727 | unsigned think_time; | |
4728 | int ret; | |
4729 | ||
4730 | /* Ignore root hubs */ | |
4731 | if (!hdev->parent) | |
4732 | return 0; | |
4733 | ||
4734 | vdev = xhci->devs[hdev->slot_id]; | |
4735 | if (!vdev) { | |
4736 | xhci_warn(xhci, "Cannot update hub desc for unknown device.\n"); | |
4737 | return -EINVAL; | |
4738 | } | |
a1d78c16 | 4739 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); |
ac1c1b7f SS |
4740 | if (!config_cmd) { |
4741 | xhci_dbg(xhci, "Could not allocate xHCI command structure.\n"); | |
4742 | return -ENOMEM; | |
4743 | } | |
92f8e767 SS |
4744 | ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx); |
4745 | if (!ctrl_ctx) { | |
4746 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
4747 | __func__); | |
4748 | xhci_free_command(xhci, config_cmd); | |
4749 | return -ENOMEM; | |
4750 | } | |
ac1c1b7f SS |
4751 | |
4752 | spin_lock_irqsave(&xhci->lock, flags); | |
839c817c SS |
4753 | if (hdev->speed == USB_SPEED_HIGH && |
4754 | xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) { | |
4755 | xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n"); | |
4756 | xhci_free_command(xhci, config_cmd); | |
4757 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4758 | return -ENOMEM; | |
4759 | } | |
4760 | ||
ac1c1b7f | 4761 | xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx); |
28ccd296 | 4762 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
ac1c1b7f | 4763 | slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx); |
28ccd296 | 4764 | slot_ctx->dev_info |= cpu_to_le32(DEV_HUB); |
ac1c1b7f | 4765 | if (tt->multi) |
28ccd296 | 4766 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
ac1c1b7f SS |
4767 | if (xhci->hci_version > 0x95) { |
4768 | xhci_dbg(xhci, "xHCI version %x needs hub " | |
4769 | "TT think time and number of ports\n", | |
4770 | (unsigned int) xhci->hci_version); | |
28ccd296 | 4771 | slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild)); |
ac1c1b7f SS |
4772 | /* Set TT think time - convert from ns to FS bit times. |
4773 | * 0 = 8 FS bit times, 1 = 16 FS bit times, | |
4774 | * 2 = 24 FS bit times, 3 = 32 FS bit times. | |
700b4173 AX |
4775 | * |
4776 | * xHCI 1.0: this field shall be 0 if the device is not a | |
4777 | * High-spped hub. | |
ac1c1b7f SS |
4778 | */ |
4779 | think_time = tt->think_time; | |
4780 | if (think_time != 0) | |
4781 | think_time = (think_time / 666) - 1; | |
700b4173 AX |
4782 | if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH) |
4783 | slot_ctx->tt_info |= | |
4784 | cpu_to_le32(TT_THINK_TIME(think_time)); | |
ac1c1b7f SS |
4785 | } else { |
4786 | xhci_dbg(xhci, "xHCI version %x doesn't need hub " | |
4787 | "TT think time or number of ports\n", | |
4788 | (unsigned int) xhci->hci_version); | |
4789 | } | |
4790 | slot_ctx->dev_state = 0; | |
4791 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4792 | ||
4793 | xhci_dbg(xhci, "Set up %s for hub device.\n", | |
4794 | (xhci->hci_version > 0x95) ? | |
4795 | "configure endpoint" : "evaluate context"); | |
4796 | xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id); | |
4797 | xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0); | |
4798 | ||
4799 | /* Issue and wait for the configure endpoint or | |
4800 | * evaluate context command. | |
4801 | */ | |
4802 | if (xhci->hci_version > 0x95) | |
4803 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4804 | false, false); | |
4805 | else | |
4806 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4807 | true, false); | |
4808 | ||
4809 | xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id); | |
4810 | xhci_dbg_ctx(xhci, vdev->out_ctx, 0); | |
4811 | ||
4812 | xhci_free_command(xhci, config_cmd); | |
4813 | return ret; | |
4814 | } | |
4815 | ||
66d4eadd SS |
4816 | int xhci_get_frame(struct usb_hcd *hcd) |
4817 | { | |
4818 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4819 | /* EHCI mods by the periodic size. Why? */ | |
4820 | return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3; | |
4821 | } | |
4822 | ||
552e0c4f SAS |
4823 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) |
4824 | { | |
4825 | struct xhci_hcd *xhci; | |
4826 | struct device *dev = hcd->self.controller; | |
4827 | int retval; | |
4828 | u32 temp; | |
4829 | ||
fdaf8b31 AX |
4830 | /* Accept arbitrarily long scatter-gather lists */ |
4831 | hcd->self.sg_tablesize = ~0; | |
19181bc5 HG |
4832 | /* XHCI controllers don't stop the ep queue on short packets :| */ |
4833 | hcd->self.no_stop_on_short = 1; | |
552e0c4f SAS |
4834 | |
4835 | if (usb_hcd_is_primary_hcd(hcd)) { | |
4836 | xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL); | |
4837 | if (!xhci) | |
4838 | return -ENOMEM; | |
4839 | *((struct xhci_hcd **) hcd->hcd_priv) = xhci; | |
4840 | xhci->main_hcd = hcd; | |
4841 | /* Mark the first roothub as being USB 2.0. | |
4842 | * The xHCI driver will register the USB 3.0 roothub. | |
4843 | */ | |
4844 | hcd->speed = HCD_USB2; | |
4845 | hcd->self.root_hub->speed = USB_SPEED_HIGH; | |
4846 | /* | |
4847 | * USB 2.0 roothub under xHCI has an integrated TT, | |
4848 | * (rate matching hub) as opposed to having an OHCI/UHCI | |
4849 | * companion controller. | |
4850 | */ | |
4851 | hcd->has_tt = 1; | |
4852 | } else { | |
4853 | /* xHCI private pointer was set in xhci_pci_probe for the second | |
4854 | * registered roothub. | |
4855 | */ | |
4856 | xhci = hcd_to_xhci(hcd); | |
4857 | temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); | |
4858 | if (HCC_64BIT_ADDR(temp)) { | |
4859 | xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); | |
4860 | dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)); | |
4861 | } else { | |
4862 | dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32)); | |
4863 | } | |
4864 | return 0; | |
4865 | } | |
4866 | ||
4867 | xhci->cap_regs = hcd->regs; | |
4868 | xhci->op_regs = hcd->regs + | |
4869 | HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase)); | |
4870 | xhci->run_regs = hcd->regs + | |
4871 | (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK); | |
4872 | /* Cache read-only capability registers */ | |
4873 | xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1); | |
4874 | xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2); | |
4875 | xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); | |
4876 | xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); | |
4877 | xhci->hci_version = HC_VERSION(xhci->hcc_params); | |
4878 | xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params); | |
4879 | xhci_print_registers(xhci); | |
4880 | ||
4881 | get_quirks(dev, xhci); | |
4882 | ||
07f3cb7c GC |
4883 | /* In xhci controllers which follow xhci 1.0 spec gives a spurious |
4884 | * success event after a short transfer. This quirk will ignore such | |
4885 | * spurious event. | |
4886 | */ | |
4887 | if (xhci->hci_version > 0x96) | |
4888 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; | |
4889 | ||
552e0c4f SAS |
4890 | /* Make sure the HC is halted. */ |
4891 | retval = xhci_halt(xhci); | |
4892 | if (retval) | |
4893 | goto error; | |
4894 | ||
4895 | xhci_dbg(xhci, "Resetting HCD\n"); | |
4896 | /* Reset the internal HC memory state and registers. */ | |
4897 | retval = xhci_reset(xhci); | |
4898 | if (retval) | |
4899 | goto error; | |
4900 | xhci_dbg(xhci, "Reset complete\n"); | |
4901 | ||
4902 | temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); | |
4903 | if (HCC_64BIT_ADDR(temp)) { | |
4904 | xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); | |
4905 | dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)); | |
4906 | } else { | |
4907 | dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32)); | |
4908 | } | |
4909 | ||
4910 | xhci_dbg(xhci, "Calling HCD init\n"); | |
4911 | /* Initialize HCD and host controller data structures. */ | |
4912 | retval = xhci_init(hcd); | |
4913 | if (retval) | |
4914 | goto error; | |
4915 | xhci_dbg(xhci, "Called HCD init\n"); | |
4916 | return 0; | |
4917 | error: | |
4918 | kfree(xhci); | |
4919 | return retval; | |
4920 | } | |
4921 | ||
66d4eadd SS |
4922 | MODULE_DESCRIPTION(DRIVER_DESC); |
4923 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
4924 | MODULE_LICENSE("GPL"); | |
4925 | ||
4926 | static int __init xhci_hcd_init(void) | |
4927 | { | |
0cc47d54 | 4928 | int retval; |
66d4eadd SS |
4929 | |
4930 | retval = xhci_register_pci(); | |
66d4eadd | 4931 | if (retval < 0) { |
5c1127d3 | 4932 | pr_debug("Problem registering PCI driver.\n"); |
66d4eadd SS |
4933 | return retval; |
4934 | } | |
3429e91a SAS |
4935 | retval = xhci_register_plat(); |
4936 | if (retval < 0) { | |
5c1127d3 | 4937 | pr_debug("Problem registering platform driver.\n"); |
3429e91a SAS |
4938 | goto unreg_pci; |
4939 | } | |
98441973 SS |
4940 | /* |
4941 | * Check the compiler generated sizes of structures that must be laid | |
4942 | * out in specific ways for hardware access. | |
4943 | */ | |
4944 | BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8); | |
4945 | BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8); | |
4946 | BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8); | |
4947 | /* xhci_device_control has eight fields, and also | |
4948 | * embeds one xhci_slot_ctx and 31 xhci_ep_ctx | |
4949 | */ | |
98441973 SS |
4950 | BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8); |
4951 | BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8); | |
4952 | BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8); | |
4953 | BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8); | |
4954 | BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8); | |
4955 | /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */ | |
4956 | BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8); | |
66d4eadd | 4957 | return 0; |
3429e91a SAS |
4958 | unreg_pci: |
4959 | xhci_unregister_pci(); | |
4960 | return retval; | |
66d4eadd SS |
4961 | } |
4962 | module_init(xhci_hcd_init); | |
4963 | ||
4964 | static void __exit xhci_hcd_cleanup(void) | |
4965 | { | |
66d4eadd | 4966 | xhci_unregister_pci(); |
3429e91a | 4967 | xhci_unregister_plat(); |
66d4eadd SS |
4968 | } |
4969 | module_exit(xhci_hcd_cleanup); |