Commit | Line | Data |
---|---|---|
66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
43b86af8 | 23 | #include <linux/pci.h> |
66d4eadd | 24 | #include <linux/irq.h> |
8df75f42 | 25 | #include <linux/log2.h> |
66d4eadd | 26 | #include <linux/module.h> |
b0567b3f | 27 | #include <linux/moduleparam.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
71c731a2 | 29 | #include <linux/dmi.h> |
008eb957 | 30 | #include <linux/dma-mapping.h> |
66d4eadd SS |
31 | |
32 | #include "xhci.h" | |
84a99f6f | 33 | #include "xhci-trace.h" |
66d4eadd SS |
34 | |
35 | #define DRIVER_AUTHOR "Sarah Sharp" | |
36 | #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" | |
37 | ||
b0567b3f SS |
38 | /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */ |
39 | static int link_quirk; | |
40 | module_param(link_quirk, int, S_IRUGO | S_IWUSR); | |
41 | MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); | |
42 | ||
4e6a1ee7 TI |
43 | static unsigned int quirks; |
44 | module_param(quirks, uint, S_IRUGO); | |
45 | MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default"); | |
46 | ||
66d4eadd SS |
47 | /* TODO: copied from ehci-hcd.c - can this be refactored? */ |
48 | /* | |
2611bd18 | 49 | * xhci_handshake - spin reading hc until handshake completes or fails |
66d4eadd SS |
50 | * @ptr: address of hc register to be read |
51 | * @mask: bits to look at in result of read | |
52 | * @done: value of those bits when handshake succeeds | |
53 | * @usec: timeout in microseconds | |
54 | * | |
55 | * Returns negative errno, or zero on success | |
56 | * | |
57 | * Success happens when the "mask" bits have the specified value (hardware | |
58 | * handshake done). There are two failure modes: "usec" have passed (major | |
59 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
60 | */ | |
2611bd18 | 61 | int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr, |
66d4eadd SS |
62 | u32 mask, u32 done, int usec) |
63 | { | |
64 | u32 result; | |
65 | ||
66 | do { | |
b0ba9720 | 67 | result = readl(ptr); |
66d4eadd SS |
68 | if (result == ~(u32)0) /* card removed */ |
69 | return -ENODEV; | |
70 | result &= mask; | |
71 | if (result == done) | |
72 | return 0; | |
73 | udelay(1); | |
74 | usec--; | |
75 | } while (usec > 0); | |
76 | return -ETIMEDOUT; | |
77 | } | |
78 | ||
79 | /* | |
4f0f0bae | 80 | * Disable interrupts and begin the xHCI halting process. |
66d4eadd | 81 | */ |
4f0f0bae | 82 | void xhci_quiesce(struct xhci_hcd *xhci) |
66d4eadd SS |
83 | { |
84 | u32 halted; | |
85 | u32 cmd; | |
86 | u32 mask; | |
87 | ||
66d4eadd | 88 | mask = ~(XHCI_IRQS); |
b0ba9720 | 89 | halted = readl(&xhci->op_regs->status) & STS_HALT; |
66d4eadd SS |
90 | if (!halted) |
91 | mask &= ~CMD_RUN; | |
92 | ||
b0ba9720 | 93 | cmd = readl(&xhci->op_regs->command); |
66d4eadd | 94 | cmd &= mask; |
204b7793 | 95 | writel(cmd, &xhci->op_regs->command); |
4f0f0bae SS |
96 | } |
97 | ||
98 | /* | |
99 | * Force HC into halt state. | |
100 | * | |
101 | * Disable any IRQs and clear the run/stop bit. | |
102 | * HC will complete any current and actively pipelined transactions, and | |
bdfca502 | 103 | * should halt within 16 ms of the run/stop bit being cleared. |
4f0f0bae | 104 | * Read HC Halted bit in the status register to see when the HC is finished. |
4f0f0bae SS |
105 | */ |
106 | int xhci_halt(struct xhci_hcd *xhci) | |
107 | { | |
c6cc27c7 | 108 | int ret; |
d195fcff | 109 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC"); |
4f0f0bae | 110 | xhci_quiesce(xhci); |
66d4eadd | 111 | |
2611bd18 | 112 | ret = xhci_handshake(xhci, &xhci->op_regs->status, |
66d4eadd | 113 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); |
c181bc5b | 114 | if (!ret) { |
c6cc27c7 | 115 | xhci->xhc_state |= XHCI_STATE_HALTED; |
c181bc5b EF |
116 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; |
117 | } else | |
5af98bb0 SS |
118 | xhci_warn(xhci, "Host not halted after %u microseconds.\n", |
119 | XHCI_MAX_HALT_USEC); | |
c6cc27c7 | 120 | return ret; |
66d4eadd SS |
121 | } |
122 | ||
ed07453f SS |
123 | /* |
124 | * Set the run bit and wait for the host to be running. | |
125 | */ | |
8212a49d | 126 | static int xhci_start(struct xhci_hcd *xhci) |
ed07453f SS |
127 | { |
128 | u32 temp; | |
129 | int ret; | |
130 | ||
b0ba9720 | 131 | temp = readl(&xhci->op_regs->command); |
ed07453f | 132 | temp |= (CMD_RUN); |
d195fcff | 133 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", |
ed07453f | 134 | temp); |
204b7793 | 135 | writel(temp, &xhci->op_regs->command); |
ed07453f SS |
136 | |
137 | /* | |
138 | * Wait for the HCHalted Status bit to be 0 to indicate the host is | |
139 | * running. | |
140 | */ | |
2611bd18 | 141 | ret = xhci_handshake(xhci, &xhci->op_regs->status, |
ed07453f SS |
142 | STS_HALT, 0, XHCI_MAX_HALT_USEC); |
143 | if (ret == -ETIMEDOUT) | |
144 | xhci_err(xhci, "Host took too long to start, " | |
145 | "waited %u microseconds.\n", | |
146 | XHCI_MAX_HALT_USEC); | |
c6cc27c7 SS |
147 | if (!ret) |
148 | xhci->xhc_state &= ~XHCI_STATE_HALTED; | |
ed07453f SS |
149 | return ret; |
150 | } | |
151 | ||
66d4eadd | 152 | /* |
ac04e6ff | 153 | * Reset a halted HC. |
66d4eadd SS |
154 | * |
155 | * This resets pipelines, timers, counters, state machines, etc. | |
156 | * Transactions will be terminated immediately, and operational registers | |
157 | * will be set to their defaults. | |
158 | */ | |
159 | int xhci_reset(struct xhci_hcd *xhci) | |
160 | { | |
161 | u32 command; | |
162 | u32 state; | |
f370b996 | 163 | int ret, i; |
66d4eadd | 164 | |
b0ba9720 | 165 | state = readl(&xhci->op_regs->status); |
d3512f63 SS |
166 | if ((state & STS_HALT) == 0) { |
167 | xhci_warn(xhci, "Host controller not halted, aborting reset.\n"); | |
168 | return 0; | |
169 | } | |
66d4eadd | 170 | |
d195fcff | 171 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); |
b0ba9720 | 172 | command = readl(&xhci->op_regs->command); |
66d4eadd | 173 | command |= CMD_RESET; |
204b7793 | 174 | writel(command, &xhci->op_regs->command); |
66d4eadd | 175 | |
2611bd18 | 176 | ret = xhci_handshake(xhci, &xhci->op_regs->command, |
22ceac19 | 177 | CMD_RESET, 0, 10 * 1000 * 1000); |
2d62f3ee SS |
178 | if (ret) |
179 | return ret; | |
180 | ||
d195fcff XR |
181 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
182 | "Wait for controller to be ready for doorbell rings"); | |
2d62f3ee SS |
183 | /* |
184 | * xHCI cannot write to any doorbells or operational registers other | |
185 | * than status until the "Controller Not Ready" flag is cleared. | |
186 | */ | |
2611bd18 | 187 | ret = xhci_handshake(xhci, &xhci->op_regs->status, |
22ceac19 | 188 | STS_CNR, 0, 10 * 1000 * 1000); |
f370b996 AX |
189 | |
190 | for (i = 0; i < 2; ++i) { | |
191 | xhci->bus_state[i].port_c_suspend = 0; | |
192 | xhci->bus_state[i].suspended_ports = 0; | |
193 | xhci->bus_state[i].resuming_ports = 0; | |
194 | } | |
195 | ||
196 | return ret; | |
66d4eadd SS |
197 | } |
198 | ||
421aa841 SAS |
199 | #ifdef CONFIG_PCI |
200 | static int xhci_free_msi(struct xhci_hcd *xhci) | |
43b86af8 DN |
201 | { |
202 | int i; | |
43b86af8 | 203 | |
421aa841 SAS |
204 | if (!xhci->msix_entries) |
205 | return -EINVAL; | |
43b86af8 | 206 | |
421aa841 SAS |
207 | for (i = 0; i < xhci->msix_count; i++) |
208 | if (xhci->msix_entries[i].vector) | |
209 | free_irq(xhci->msix_entries[i].vector, | |
210 | xhci_to_hcd(xhci)); | |
211 | return 0; | |
43b86af8 DN |
212 | } |
213 | ||
214 | /* | |
215 | * Set up MSI | |
216 | */ | |
217 | static int xhci_setup_msi(struct xhci_hcd *xhci) | |
66d4eadd SS |
218 | { |
219 | int ret; | |
43b86af8 DN |
220 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
221 | ||
222 | ret = pci_enable_msi(pdev); | |
223 | if (ret) { | |
d195fcff XR |
224 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
225 | "failed to allocate MSI entry"); | |
43b86af8 DN |
226 | return ret; |
227 | } | |
228 | ||
851ec164 | 229 | ret = request_irq(pdev->irq, xhci_msi_irq, |
43b86af8 DN |
230 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
231 | if (ret) { | |
d195fcff XR |
232 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
233 | "disable MSI interrupt"); | |
43b86af8 DN |
234 | pci_disable_msi(pdev); |
235 | } | |
236 | ||
237 | return ret; | |
238 | } | |
239 | ||
421aa841 SAS |
240 | /* |
241 | * Free IRQs | |
242 | * free all IRQs request | |
243 | */ | |
244 | static void xhci_free_irq(struct xhci_hcd *xhci) | |
245 | { | |
246 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
247 | int ret; | |
248 | ||
249 | /* return if using legacy interrupt */ | |
cd70469d | 250 | if (xhci_to_hcd(xhci)->irq > 0) |
421aa841 SAS |
251 | return; |
252 | ||
253 | ret = xhci_free_msi(xhci); | |
254 | if (!ret) | |
255 | return; | |
cd70469d | 256 | if (pdev->irq > 0) |
421aa841 SAS |
257 | free_irq(pdev->irq, xhci_to_hcd(xhci)); |
258 | ||
259 | return; | |
260 | } | |
261 | ||
43b86af8 DN |
262 | /* |
263 | * Set up MSI-X | |
264 | */ | |
265 | static int xhci_setup_msix(struct xhci_hcd *xhci) | |
266 | { | |
267 | int i, ret = 0; | |
0029227f AX |
268 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
269 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 270 | |
43b86af8 DN |
271 | /* |
272 | * calculate number of msi-x vectors supported. | |
273 | * - HCS_MAX_INTRS: the max number of interrupts the host can handle, | |
274 | * with max number of interrupters based on the xhci HCSPARAMS1. | |
275 | * - num_online_cpus: maximum msi-x vectors per CPUs core. | |
276 | * Add additional 1 vector to ensure always available interrupt. | |
277 | */ | |
278 | xhci->msix_count = min(num_online_cpus() + 1, | |
279 | HCS_MAX_INTRS(xhci->hcs_params1)); | |
280 | ||
281 | xhci->msix_entries = | |
282 | kmalloc((sizeof(struct msix_entry))*xhci->msix_count, | |
86871975 | 283 | GFP_KERNEL); |
66d4eadd SS |
284 | if (!xhci->msix_entries) { |
285 | xhci_err(xhci, "Failed to allocate MSI-X entries\n"); | |
286 | return -ENOMEM; | |
287 | } | |
43b86af8 DN |
288 | |
289 | for (i = 0; i < xhci->msix_count; i++) { | |
290 | xhci->msix_entries[i].entry = i; | |
291 | xhci->msix_entries[i].vector = 0; | |
292 | } | |
66d4eadd | 293 | |
a62445ae | 294 | ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count); |
66d4eadd | 295 | if (ret) { |
d195fcff XR |
296 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
297 | "Failed to enable MSI-X"); | |
66d4eadd SS |
298 | goto free_entries; |
299 | } | |
300 | ||
43b86af8 DN |
301 | for (i = 0; i < xhci->msix_count; i++) { |
302 | ret = request_irq(xhci->msix_entries[i].vector, | |
851ec164 | 303 | xhci_msi_irq, |
43b86af8 DN |
304 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
305 | if (ret) | |
306 | goto disable_msix; | |
66d4eadd | 307 | } |
43b86af8 | 308 | |
0029227f | 309 | hcd->msix_enabled = 1; |
43b86af8 | 310 | return ret; |
66d4eadd SS |
311 | |
312 | disable_msix: | |
d195fcff | 313 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); |
43b86af8 | 314 | xhci_free_irq(xhci); |
66d4eadd SS |
315 | pci_disable_msix(pdev); |
316 | free_entries: | |
317 | kfree(xhci->msix_entries); | |
318 | xhci->msix_entries = NULL; | |
319 | return ret; | |
320 | } | |
321 | ||
66d4eadd SS |
322 | /* Free any IRQs and disable MSI-X */ |
323 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |
324 | { | |
0029227f AX |
325 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
326 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 327 | |
9005355a JP |
328 | if (xhci->quirks & XHCI_PLAT) |
329 | return; | |
330 | ||
43b86af8 DN |
331 | xhci_free_irq(xhci); |
332 | ||
333 | if (xhci->msix_entries) { | |
334 | pci_disable_msix(pdev); | |
335 | kfree(xhci->msix_entries); | |
336 | xhci->msix_entries = NULL; | |
337 | } else { | |
338 | pci_disable_msi(pdev); | |
339 | } | |
340 | ||
0029227f | 341 | hcd->msix_enabled = 0; |
43b86af8 | 342 | return; |
66d4eadd | 343 | } |
66d4eadd | 344 | |
d5c82feb | 345 | static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 SAS |
346 | { |
347 | int i; | |
348 | ||
349 | if (xhci->msix_entries) { | |
350 | for (i = 0; i < xhci->msix_count; i++) | |
351 | synchronize_irq(xhci->msix_entries[i].vector); | |
352 | } | |
353 | } | |
354 | ||
355 | static int xhci_try_enable_msi(struct usb_hcd *hcd) | |
356 | { | |
357 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
52fb6125 | 358 | struct pci_dev *pdev; |
421aa841 SAS |
359 | int ret; |
360 | ||
52fb6125 SS |
361 | /* The xhci platform device has set up IRQs through usb_add_hcd. */ |
362 | if (xhci->quirks & XHCI_PLAT) | |
363 | return 0; | |
364 | ||
365 | pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
421aa841 SAS |
366 | /* |
367 | * Some Fresco Logic host controllers advertise MSI, but fail to | |
368 | * generate interrupts. Don't even try to enable MSI. | |
369 | */ | |
370 | if (xhci->quirks & XHCI_BROKEN_MSI) | |
00eed9c8 | 371 | goto legacy_irq; |
421aa841 SAS |
372 | |
373 | /* unregister the legacy interrupt */ | |
374 | if (hcd->irq) | |
375 | free_irq(hcd->irq, hcd); | |
cd70469d | 376 | hcd->irq = 0; |
421aa841 SAS |
377 | |
378 | ret = xhci_setup_msix(xhci); | |
379 | if (ret) | |
380 | /* fall back to msi*/ | |
381 | ret = xhci_setup_msi(xhci); | |
382 | ||
383 | if (!ret) | |
cd70469d | 384 | /* hcd->irq is 0, we have MSI */ |
421aa841 SAS |
385 | return 0; |
386 | ||
68d07f64 SS |
387 | if (!pdev->irq) { |
388 | xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); | |
389 | return -EINVAL; | |
390 | } | |
391 | ||
00eed9c8 | 392 | legacy_irq: |
79699437 AH |
393 | if (!strlen(hcd->irq_descr)) |
394 | snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", | |
395 | hcd->driver->description, hcd->self.busnum); | |
396 | ||
421aa841 SAS |
397 | /* fall back to legacy interrupt*/ |
398 | ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, | |
399 | hcd->irq_descr, hcd); | |
400 | if (ret) { | |
401 | xhci_err(xhci, "request interrupt %d failed\n", | |
402 | pdev->irq); | |
403 | return ret; | |
404 | } | |
405 | hcd->irq = pdev->irq; | |
406 | return 0; | |
407 | } | |
408 | ||
409 | #else | |
410 | ||
01bb59eb | 411 | static inline int xhci_try_enable_msi(struct usb_hcd *hcd) |
421aa841 SAS |
412 | { |
413 | return 0; | |
414 | } | |
415 | ||
01bb59eb | 416 | static inline void xhci_cleanup_msix(struct xhci_hcd *xhci) |
421aa841 SAS |
417 | { |
418 | } | |
419 | ||
01bb59eb | 420 | static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 SAS |
421 | { |
422 | } | |
423 | ||
424 | #endif | |
425 | ||
71c731a2 AC |
426 | static void compliance_mode_recovery(unsigned long arg) |
427 | { | |
428 | struct xhci_hcd *xhci; | |
429 | struct usb_hcd *hcd; | |
430 | u32 temp; | |
431 | int i; | |
432 | ||
433 | xhci = (struct xhci_hcd *)arg; | |
434 | ||
435 | for (i = 0; i < xhci->num_usb3_ports; i++) { | |
b0ba9720 | 436 | temp = readl(xhci->usb3_ports[i]); |
71c731a2 AC |
437 | if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) { |
438 | /* | |
439 | * Compliance Mode Detected. Letting USB Core | |
440 | * handle the Warm Reset | |
441 | */ | |
4bdfe4c3 XR |
442 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
443 | "Compliance mode detected->port %d", | |
71c731a2 | 444 | i + 1); |
4bdfe4c3 XR |
445 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
446 | "Attempting compliance mode recovery"); | |
71c731a2 AC |
447 | hcd = xhci->shared_hcd; |
448 | ||
449 | if (hcd->state == HC_STATE_SUSPENDED) | |
450 | usb_hcd_resume_root_hub(hcd); | |
451 | ||
452 | usb_hcd_poll_rh_status(hcd); | |
453 | } | |
454 | } | |
455 | ||
456 | if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1)) | |
457 | mod_timer(&xhci->comp_mode_recovery_timer, | |
458 | jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS)); | |
459 | } | |
460 | ||
461 | /* | |
462 | * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver | |
463 | * that causes ports behind that hardware to enter compliance mode sometimes. | |
464 | * The quirk creates a timer that polls every 2 seconds the link state of | |
465 | * each host controller's port and recovers it by issuing a Warm reset | |
466 | * if Compliance mode is detected, otherwise the port will become "dead" (no | |
467 | * device connections or disconnections will be detected anymore). Becasue no | |
468 | * status event is generated when entering compliance mode (per xhci spec), | |
469 | * this quirk is needed on systems that have the failing hardware installed. | |
470 | */ | |
471 | static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci) | |
472 | { | |
473 | xhci->port_status_u0 = 0; | |
474 | init_timer(&xhci->comp_mode_recovery_timer); | |
475 | ||
476 | xhci->comp_mode_recovery_timer.data = (unsigned long) xhci; | |
477 | xhci->comp_mode_recovery_timer.function = compliance_mode_recovery; | |
478 | xhci->comp_mode_recovery_timer.expires = jiffies + | |
479 | msecs_to_jiffies(COMP_MODE_RCVRY_MSECS); | |
480 | ||
481 | set_timer_slack(&xhci->comp_mode_recovery_timer, | |
482 | msecs_to_jiffies(COMP_MODE_RCVRY_MSECS)); | |
483 | add_timer(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
484 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
485 | "Compliance mode recovery timer initialized"); | |
71c731a2 AC |
486 | } |
487 | ||
488 | /* | |
489 | * This function identifies the systems that have installed the SN65LVPE502CP | |
490 | * USB3.0 re-driver and that need the Compliance Mode Quirk. | |
491 | * Systems: | |
492 | * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820 | |
493 | */ | |
c3897aa5 | 494 | bool xhci_compliance_mode_recovery_timer_quirk_check(void) |
71c731a2 AC |
495 | { |
496 | const char *dmi_product_name, *dmi_sys_vendor; | |
497 | ||
498 | dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); | |
499 | dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR); | |
457a73d3 VG |
500 | if (!dmi_product_name || !dmi_sys_vendor) |
501 | return false; | |
71c731a2 AC |
502 | |
503 | if (!(strstr(dmi_sys_vendor, "Hewlett-Packard"))) | |
504 | return false; | |
505 | ||
506 | if (strstr(dmi_product_name, "Z420") || | |
507 | strstr(dmi_product_name, "Z620") || | |
47080974 | 508 | strstr(dmi_product_name, "Z820") || |
b0e4e606 | 509 | strstr(dmi_product_name, "Z1 Workstation")) |
71c731a2 AC |
510 | return true; |
511 | ||
512 | return false; | |
513 | } | |
514 | ||
515 | static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci) | |
516 | { | |
517 | return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1)); | |
518 | } | |
519 | ||
520 | ||
66d4eadd SS |
521 | /* |
522 | * Initialize memory for HCD and xHC (one-time init). | |
523 | * | |
524 | * Program the PAGESIZE register, initialize the device context array, create | |
525 | * device contexts (?), set up a command ring segment (or two?), create event | |
526 | * ring (one for now). | |
527 | */ | |
528 | int xhci_init(struct usb_hcd *hcd) | |
529 | { | |
530 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
531 | int retval = 0; | |
532 | ||
d195fcff | 533 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init"); |
66d4eadd | 534 | spin_lock_init(&xhci->lock); |
d7826599 | 535 | if (xhci->hci_version == 0x95 && link_quirk) { |
4bdfe4c3 XR |
536 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
537 | "QUIRK: Not clearing Link TRB chain bits."); | |
b0567b3f SS |
538 | xhci->quirks |= XHCI_LINK_TRB_QUIRK; |
539 | } else { | |
d195fcff XR |
540 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
541 | "xHCI doesn't need link TRB QUIRK"); | |
b0567b3f | 542 | } |
66d4eadd | 543 | retval = xhci_mem_init(xhci, GFP_KERNEL); |
d195fcff | 544 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init"); |
66d4eadd | 545 | |
71c731a2 | 546 | /* Initializing Compliance Mode Recovery Data If Needed */ |
c3897aa5 | 547 | if (xhci_compliance_mode_recovery_timer_quirk_check()) { |
71c731a2 AC |
548 | xhci->quirks |= XHCI_COMP_MODE_QUIRK; |
549 | compliance_mode_recovery_timer_init(xhci); | |
550 | } | |
551 | ||
66d4eadd SS |
552 | return retval; |
553 | } | |
554 | ||
7f84eef0 SS |
555 | /*-------------------------------------------------------------------------*/ |
556 | ||
7f84eef0 | 557 | |
f6ff0ac8 SS |
558 | static int xhci_run_finished(struct xhci_hcd *xhci) |
559 | { | |
560 | if (xhci_start(xhci)) { | |
561 | xhci_halt(xhci); | |
562 | return -ENODEV; | |
563 | } | |
564 | xhci->shared_hcd->state = HC_STATE_RUNNING; | |
c181bc5b | 565 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; |
f6ff0ac8 SS |
566 | |
567 | if (xhci->quirks & XHCI_NEC_HOST) | |
568 | xhci_ring_cmd_db(xhci); | |
569 | ||
d195fcff XR |
570 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
571 | "Finished xhci_run for USB3 roothub"); | |
f6ff0ac8 SS |
572 | return 0; |
573 | } | |
574 | ||
66d4eadd SS |
575 | /* |
576 | * Start the HC after it was halted. | |
577 | * | |
578 | * This function is called by the USB core when the HC driver is added. | |
579 | * Its opposite is xhci_stop(). | |
580 | * | |
581 | * xhci_init() must be called once before this function can be called. | |
582 | * Reset the HC, enable device slot contexts, program DCBAAP, and | |
583 | * set command ring pointer and event ring pointer. | |
584 | * | |
585 | * Setup MSI-X vectors and enable interrupts. | |
586 | */ | |
587 | int xhci_run(struct usb_hcd *hcd) | |
588 | { | |
589 | u32 temp; | |
8e595a5d | 590 | u64 temp_64; |
3fd1ec58 | 591 | int ret; |
66d4eadd | 592 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
66d4eadd | 593 | |
f6ff0ac8 SS |
594 | /* Start the xHCI host controller running only after the USB 2.0 roothub |
595 | * is setup. | |
596 | */ | |
66d4eadd | 597 | |
0f2a7930 | 598 | hcd->uses_new_polling = 1; |
f6ff0ac8 SS |
599 | if (!usb_hcd_is_primary_hcd(hcd)) |
600 | return xhci_run_finished(xhci); | |
0f2a7930 | 601 | |
d195fcff | 602 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run"); |
43b86af8 | 603 | |
3fd1ec58 | 604 | ret = xhci_try_enable_msi(hcd); |
43b86af8 | 605 | if (ret) |
3fd1ec58 | 606 | return ret; |
66d4eadd | 607 | |
66e49d87 SS |
608 | xhci_dbg(xhci, "Command ring memory map follows:\n"); |
609 | xhci_debug_ring(xhci, xhci->cmd_ring); | |
610 | xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); | |
611 | xhci_dbg_cmd_ptrs(xhci); | |
612 | ||
613 | xhci_dbg(xhci, "ERST memory map follows:\n"); | |
614 | xhci_dbg_erst(xhci, &xhci->erst); | |
615 | xhci_dbg(xhci, "Event ring:\n"); | |
616 | xhci_debug_ring(xhci, xhci->event_ring); | |
617 | xhci_dbg_ring_ptrs(xhci, xhci->event_ring); | |
f7b2e403 | 618 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
66e49d87 | 619 | temp_64 &= ~ERST_PTR_MASK; |
d195fcff XR |
620 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
621 | "ERST deq = 64'h%0lx", (long unsigned int) temp_64); | |
66e49d87 | 622 | |
d195fcff XR |
623 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
624 | "// Set the interrupt modulation register"); | |
b0ba9720 | 625 | temp = readl(&xhci->ir_set->irq_control); |
a4d88302 | 626 | temp &= ~ER_IRQ_INTERVAL_MASK; |
66d4eadd | 627 | temp |= (u32) 160; |
204b7793 | 628 | writel(temp, &xhci->ir_set->irq_control); |
66d4eadd SS |
629 | |
630 | /* Set the HCD state before we enable the irqs */ | |
b0ba9720 | 631 | temp = readl(&xhci->op_regs->command); |
66d4eadd | 632 | temp |= (CMD_EIE); |
d195fcff XR |
633 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
634 | "// Enable interrupts, cmd = 0x%x.", temp); | |
204b7793 | 635 | writel(temp, &xhci->op_regs->command); |
66d4eadd | 636 | |
b0ba9720 | 637 | temp = readl(&xhci->ir_set->irq_pending); |
d195fcff XR |
638 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
639 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", | |
700e2052 | 640 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); |
204b7793 | 641 | writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 642 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 643 | |
ddba5cd0 MN |
644 | if (xhci->quirks & XHCI_NEC_HOST) { |
645 | struct xhci_command *command; | |
646 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); | |
647 | if (!command) | |
648 | return -ENOMEM; | |
649 | xhci_queue_vendor_command(xhci, command, 0, 0, 0, | |
0238634d | 650 | TRB_TYPE(TRB_NEC_GET_FW)); |
ddba5cd0 | 651 | } |
d195fcff XR |
652 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
653 | "Finished xhci_run for USB2 roothub"); | |
f6ff0ac8 SS |
654 | return 0; |
655 | } | |
ed07453f | 656 | |
f6ff0ac8 SS |
657 | static void xhci_only_stop_hcd(struct usb_hcd *hcd) |
658 | { | |
659 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
66d4eadd | 660 | |
f6ff0ac8 SS |
661 | spin_lock_irq(&xhci->lock); |
662 | xhci_halt(xhci); | |
663 | ||
664 | /* The shared_hcd is going to be deallocated shortly (the USB core only | |
665 | * calls this function when allocation fails in usb_add_hcd(), or | |
666 | * usb_remove_hcd() is called). So we need to unset xHCI's pointer. | |
667 | */ | |
668 | xhci->shared_hcd = NULL; | |
669 | spin_unlock_irq(&xhci->lock); | |
66d4eadd SS |
670 | } |
671 | ||
672 | /* | |
673 | * Stop xHCI driver. | |
674 | * | |
675 | * This function is called by the USB core when the HC driver is removed. | |
676 | * Its opposite is xhci_run(). | |
677 | * | |
678 | * Disable device contexts, disable IRQs, and quiesce the HC. | |
679 | * Reset the HC, finish any completed transactions, and cleanup memory. | |
680 | */ | |
681 | void xhci_stop(struct usb_hcd *hcd) | |
682 | { | |
683 | u32 temp; | |
684 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
685 | ||
f6ff0ac8 SS |
686 | if (!usb_hcd_is_primary_hcd(hcd)) { |
687 | xhci_only_stop_hcd(xhci->shared_hcd); | |
688 | return; | |
689 | } | |
690 | ||
66d4eadd | 691 | spin_lock_irq(&xhci->lock); |
f6ff0ac8 SS |
692 | /* Make sure the xHC is halted for a USB3 roothub |
693 | * (xhci_stop() could be called as part of failed init). | |
694 | */ | |
66d4eadd SS |
695 | xhci_halt(xhci); |
696 | xhci_reset(xhci); | |
697 | spin_unlock_irq(&xhci->lock); | |
698 | ||
40a9fb17 ZR |
699 | xhci_cleanup_msix(xhci); |
700 | ||
71c731a2 AC |
701 | /* Deleting Compliance Mode Recovery Timer */ |
702 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
58b1d799 | 703 | (!(xhci_all_ports_seen_u0(xhci)))) { |
71c731a2 | 704 | del_timer_sync(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
705 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
706 | "%s: compliance mode recovery timer deleted", | |
58b1d799 TC |
707 | __func__); |
708 | } | |
71c731a2 | 709 | |
c41136b0 AX |
710 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
711 | usb_amd_dev_put(); | |
712 | ||
d195fcff XR |
713 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
714 | "// Disabling event ring interrupts"); | |
b0ba9720 | 715 | temp = readl(&xhci->op_regs->status); |
204b7793 | 716 | writel(temp & ~STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 717 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 718 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 719 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 720 | |
d195fcff | 721 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); |
66d4eadd | 722 | xhci_mem_cleanup(xhci); |
d195fcff XR |
723 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
724 | "xhci_stop completed - status = %x", | |
b0ba9720 | 725 | readl(&xhci->op_regs->status)); |
66d4eadd SS |
726 | } |
727 | ||
728 | /* | |
729 | * Shutdown HC (not bus-specific) | |
730 | * | |
731 | * This is called when the machine is rebooting or halting. We assume that the | |
732 | * machine will be powered off, and the HC's internal state will be reset. | |
733 | * Don't bother to free memory. | |
f6ff0ac8 SS |
734 | * |
735 | * This will only ever be called with the main usb_hcd (the USB3 roothub). | |
66d4eadd SS |
736 | */ |
737 | void xhci_shutdown(struct usb_hcd *hcd) | |
738 | { | |
739 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
740 | ||
052c7f9f | 741 | if (xhci->quirks & XHCI_SPURIOUS_REBOOT) |
e95829f4 SS |
742 | usb_disable_xhci_ports(to_pci_dev(hcd->self.controller)); |
743 | ||
66d4eadd SS |
744 | spin_lock_irq(&xhci->lock); |
745 | xhci_halt(xhci); | |
638298dc TI |
746 | /* Workaround for spurious wakeups at shutdown with HSW */ |
747 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
748 | xhci_reset(xhci); | |
43b86af8 | 749 | spin_unlock_irq(&xhci->lock); |
66d4eadd | 750 | |
40a9fb17 ZR |
751 | xhci_cleanup_msix(xhci); |
752 | ||
d195fcff XR |
753 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
754 | "xhci_shutdown completed - status = %x", | |
b0ba9720 | 755 | readl(&xhci->op_regs->status)); |
638298dc TI |
756 | |
757 | /* Yet another workaround for spurious wakeups at shutdown with HSW */ | |
758 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
759 | pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot); | |
66d4eadd SS |
760 | } |
761 | ||
b5b5c3ac | 762 | #ifdef CONFIG_PM |
5535b1d5 AX |
763 | static void xhci_save_registers(struct xhci_hcd *xhci) |
764 | { | |
b0ba9720 XR |
765 | xhci->s3.command = readl(&xhci->op_regs->command); |
766 | xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification); | |
f7b2e403 | 767 | xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
b0ba9720 XR |
768 | xhci->s3.config_reg = readl(&xhci->op_regs->config_reg); |
769 | xhci->s3.erst_size = readl(&xhci->ir_set->erst_size); | |
f7b2e403 SS |
770 | xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
771 | xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
b0ba9720 XR |
772 | xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending); |
773 | xhci->s3.irq_control = readl(&xhci->ir_set->irq_control); | |
5535b1d5 AX |
774 | } |
775 | ||
776 | static void xhci_restore_registers(struct xhci_hcd *xhci) | |
777 | { | |
204b7793 XR |
778 | writel(xhci->s3.command, &xhci->op_regs->command); |
779 | writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification); | |
477632df | 780 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); |
204b7793 XR |
781 | writel(xhci->s3.config_reg, &xhci->op_regs->config_reg); |
782 | writel(xhci->s3.erst_size, &xhci->ir_set->erst_size); | |
477632df SS |
783 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); |
784 | xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); | |
204b7793 XR |
785 | writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending); |
786 | writel(xhci->s3.irq_control, &xhci->ir_set->irq_control); | |
5535b1d5 AX |
787 | } |
788 | ||
89821320 SS |
789 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) |
790 | { | |
791 | u64 val_64; | |
792 | ||
793 | /* step 2: initialize command ring buffer */ | |
f7b2e403 | 794 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
89821320 SS |
795 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
796 | (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | |
797 | xhci->cmd_ring->dequeue) & | |
798 | (u64) ~CMD_RING_RSVD_BITS) | | |
799 | xhci->cmd_ring->cycle_state; | |
d195fcff XR |
800 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
801 | "// Setting command ring address to 0x%llx", | |
89821320 | 802 | (long unsigned long) val_64); |
477632df | 803 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); |
89821320 SS |
804 | } |
805 | ||
806 | /* | |
807 | * The whole command ring must be cleared to zero when we suspend the host. | |
808 | * | |
809 | * The host doesn't save the command ring pointer in the suspend well, so we | |
810 | * need to re-program it on resume. Unfortunately, the pointer must be 64-byte | |
811 | * aligned, because of the reserved bits in the command ring dequeue pointer | |
812 | * register. Therefore, we can't just set the dequeue pointer back in the | |
813 | * middle of the ring (TRBs are 16-byte aligned). | |
814 | */ | |
815 | static void xhci_clear_command_ring(struct xhci_hcd *xhci) | |
816 | { | |
817 | struct xhci_ring *ring; | |
818 | struct xhci_segment *seg; | |
819 | ||
820 | ring = xhci->cmd_ring; | |
821 | seg = ring->deq_seg; | |
822 | do { | |
158886cd AX |
823 | memset(seg->trbs, 0, |
824 | sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1)); | |
825 | seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= | |
826 | cpu_to_le32(~TRB_CYCLE); | |
89821320 SS |
827 | seg = seg->next; |
828 | } while (seg != ring->deq_seg); | |
829 | ||
830 | /* Reset the software enqueue and dequeue pointers */ | |
831 | ring->deq_seg = ring->first_seg; | |
832 | ring->dequeue = ring->first_seg->trbs; | |
833 | ring->enq_seg = ring->deq_seg; | |
834 | ring->enqueue = ring->dequeue; | |
835 | ||
b008df60 | 836 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; |
89821320 SS |
837 | /* |
838 | * Ring is now zeroed, so the HW should look for change of ownership | |
839 | * when the cycle bit is set to 1. | |
840 | */ | |
841 | ring->cycle_state = 1; | |
842 | ||
843 | /* | |
844 | * Reset the hardware dequeue pointer. | |
845 | * Yes, this will need to be re-written after resume, but we're paranoid | |
846 | * and want to make sure the hardware doesn't access bogus memory | |
847 | * because, say, the BIOS or an SMI started the host without changing | |
848 | * the command ring pointers. | |
849 | */ | |
850 | xhci_set_cmd_ring_deq(xhci); | |
851 | } | |
852 | ||
5535b1d5 AX |
853 | /* |
854 | * Stop HC (not bus-specific) | |
855 | * | |
856 | * This is called when the machine transition into S3/S4 mode. | |
857 | * | |
858 | */ | |
859 | int xhci_suspend(struct xhci_hcd *xhci) | |
860 | { | |
861 | int rc = 0; | |
455f5892 | 862 | unsigned int delay = XHCI_MAX_HALT_USEC; |
5535b1d5 AX |
863 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
864 | u32 command; | |
865 | ||
77b84767 FB |
866 | if (hcd->state != HC_STATE_SUSPENDED || |
867 | xhci->shared_hcd->state != HC_STATE_SUSPENDED) | |
868 | return -EINVAL; | |
869 | ||
c52804a4 SS |
870 | /* Don't poll the roothubs on bus suspend. */ |
871 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
872 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
873 | del_timer_sync(&hcd->rh_timer); | |
874 | ||
5535b1d5 AX |
875 | spin_lock_irq(&xhci->lock); |
876 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
b3209379 | 877 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); |
5535b1d5 AX |
878 | /* step 1: stop endpoint */ |
879 | /* skipped assuming that port suspend has done */ | |
880 | ||
881 | /* step 2: clear Run/Stop bit */ | |
b0ba9720 | 882 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 883 | command &= ~CMD_RUN; |
204b7793 | 884 | writel(command, &xhci->op_regs->command); |
455f5892 ON |
885 | |
886 | /* Some chips from Fresco Logic need an extraordinary delay */ | |
887 | delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; | |
888 | ||
2611bd18 | 889 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
455f5892 | 890 | STS_HALT, STS_HALT, delay)) { |
5535b1d5 AX |
891 | xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n"); |
892 | spin_unlock_irq(&xhci->lock); | |
893 | return -ETIMEDOUT; | |
894 | } | |
89821320 | 895 | xhci_clear_command_ring(xhci); |
5535b1d5 AX |
896 | |
897 | /* step 3: save registers */ | |
898 | xhci_save_registers(xhci); | |
899 | ||
900 | /* step 4: set CSS flag */ | |
b0ba9720 | 901 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 902 | command |= CMD_CSS; |
204b7793 | 903 | writel(command, &xhci->op_regs->command); |
2611bd18 SS |
904 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
905 | STS_SAVE, 0, 10 * 1000)) { | |
622eb783 | 906 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); |
5535b1d5 AX |
907 | spin_unlock_irq(&xhci->lock); |
908 | return -ETIMEDOUT; | |
909 | } | |
5535b1d5 AX |
910 | spin_unlock_irq(&xhci->lock); |
911 | ||
71c731a2 AC |
912 | /* |
913 | * Deleting Compliance Mode Recovery Timer because the xHCI Host | |
914 | * is about to be suspended. | |
915 | */ | |
916 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
917 | (!(xhci_all_ports_seen_u0(xhci)))) { | |
918 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
919 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
920 | "%s: compliance mode recovery timer deleted", | |
58b1d799 | 921 | __func__); |
71c731a2 AC |
922 | } |
923 | ||
0029227f AX |
924 | /* step 5: remove core well power */ |
925 | /* synchronize irq when using MSI-X */ | |
421aa841 | 926 | xhci_msix_sync_irqs(xhci); |
0029227f | 927 | |
5535b1d5 AX |
928 | return rc; |
929 | } | |
930 | ||
931 | /* | |
932 | * start xHC (not bus-specific) | |
933 | * | |
934 | * This is called when the machine transition from S3/S4 mode. | |
935 | * | |
936 | */ | |
937 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |
938 | { | |
d6236f6d | 939 | u32 command, temp = 0, status; |
5535b1d5 | 940 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
65b22f93 | 941 | struct usb_hcd *secondary_hcd; |
f69e3120 | 942 | int retval = 0; |
77df9e0b | 943 | bool comp_timer_running = false; |
5535b1d5 | 944 | |
f6ff0ac8 | 945 | /* Wait a bit if either of the roothubs need to settle from the |
25985edc | 946 | * transition into bus suspend. |
20b67cf5 | 947 | */ |
f6ff0ac8 SS |
948 | if (time_before(jiffies, xhci->bus_state[0].next_statechange) || |
949 | time_before(jiffies, | |
950 | xhci->bus_state[1].next_statechange)) | |
5535b1d5 AX |
951 | msleep(100); |
952 | ||
f69e3120 AS |
953 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
954 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); | |
955 | ||
5535b1d5 | 956 | spin_lock_irq(&xhci->lock); |
c877b3b2 ML |
957 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
958 | hibernated = true; | |
5535b1d5 AX |
959 | |
960 | if (!hibernated) { | |
961 | /* step 1: restore register */ | |
962 | xhci_restore_registers(xhci); | |
963 | /* step 2: initialize command ring buffer */ | |
89821320 | 964 | xhci_set_cmd_ring_deq(xhci); |
5535b1d5 AX |
965 | /* step 3: restore state and start state*/ |
966 | /* step 3: set CRS flag */ | |
b0ba9720 | 967 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 968 | command |= CMD_CRS; |
204b7793 | 969 | writel(command, &xhci->op_regs->command); |
2611bd18 | 970 | if (xhci_handshake(xhci, &xhci->op_regs->status, |
622eb783 AX |
971 | STS_RESTORE, 0, 10 * 1000)) { |
972 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); | |
5535b1d5 AX |
973 | spin_unlock_irq(&xhci->lock); |
974 | return -ETIMEDOUT; | |
975 | } | |
b0ba9720 | 976 | temp = readl(&xhci->op_regs->status); |
5535b1d5 AX |
977 | } |
978 | ||
979 | /* If restore operation fails, re-initialize the HC during resume */ | |
980 | if ((temp & STS_SRE) || hibernated) { | |
77df9e0b TC |
981 | |
982 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
983 | !(xhci_all_ports_seen_u0(xhci))) { | |
984 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
985 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
986 | "Compliance Mode Recovery Timer deleted!"); | |
77df9e0b TC |
987 | } |
988 | ||
fedd383e SS |
989 | /* Let the USB core know _both_ roothubs lost power. */ |
990 | usb_root_hub_lost_power(xhci->main_hcd->self.root_hub); | |
991 | usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub); | |
5535b1d5 AX |
992 | |
993 | xhci_dbg(xhci, "Stop HCD\n"); | |
994 | xhci_halt(xhci); | |
995 | xhci_reset(xhci); | |
5535b1d5 | 996 | spin_unlock_irq(&xhci->lock); |
0029227f | 997 | xhci_cleanup_msix(xhci); |
5535b1d5 | 998 | |
5535b1d5 | 999 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
b0ba9720 | 1000 | temp = readl(&xhci->op_regs->status); |
204b7793 | 1001 | writel(temp & ~STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 1002 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 1003 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 1004 | xhci_print_ir_set(xhci, 0); |
5535b1d5 AX |
1005 | |
1006 | xhci_dbg(xhci, "cleaning up memory\n"); | |
1007 | xhci_mem_cleanup(xhci); | |
1008 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", | |
b0ba9720 | 1009 | readl(&xhci->op_regs->status)); |
5535b1d5 | 1010 | |
65b22f93 SS |
1011 | /* USB core calls the PCI reinit and start functions twice: |
1012 | * first with the primary HCD, and then with the secondary HCD. | |
1013 | * If we don't do the same, the host will never be started. | |
1014 | */ | |
1015 | if (!usb_hcd_is_primary_hcd(hcd)) | |
1016 | secondary_hcd = hcd; | |
1017 | else | |
1018 | secondary_hcd = xhci->shared_hcd; | |
1019 | ||
1020 | xhci_dbg(xhci, "Initialize the xhci_hcd\n"); | |
1021 | retval = xhci_init(hcd->primary_hcd); | |
5535b1d5 AX |
1022 | if (retval) |
1023 | return retval; | |
77df9e0b TC |
1024 | comp_timer_running = true; |
1025 | ||
65b22f93 SS |
1026 | xhci_dbg(xhci, "Start the primary HCD\n"); |
1027 | retval = xhci_run(hcd->primary_hcd); | |
b3209379 | 1028 | if (!retval) { |
f69e3120 AS |
1029 | xhci_dbg(xhci, "Start the secondary HCD\n"); |
1030 | retval = xhci_run(secondary_hcd); | |
b3209379 | 1031 | } |
5535b1d5 | 1032 | hcd->state = HC_STATE_SUSPENDED; |
b3209379 | 1033 | xhci->shared_hcd->state = HC_STATE_SUSPENDED; |
f69e3120 | 1034 | goto done; |
5535b1d5 AX |
1035 | } |
1036 | ||
5535b1d5 | 1037 | /* step 4: set Run/Stop bit */ |
b0ba9720 | 1038 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1039 | command |= CMD_RUN; |
204b7793 | 1040 | writel(command, &xhci->op_regs->command); |
2611bd18 | 1041 | xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT, |
5535b1d5 AX |
1042 | 0, 250 * 1000); |
1043 | ||
1044 | /* step 5: walk topology and initialize portsc, | |
1045 | * portpmsc and portli | |
1046 | */ | |
1047 | /* this is done in bus_resume */ | |
1048 | ||
1049 | /* step 6: restart each of the previously | |
1050 | * Running endpoints by ringing their doorbells | |
1051 | */ | |
1052 | ||
5535b1d5 | 1053 | spin_unlock_irq(&xhci->lock); |
f69e3120 AS |
1054 | |
1055 | done: | |
1056 | if (retval == 0) { | |
d6236f6d WY |
1057 | /* Resume root hubs only when have pending events. */ |
1058 | status = readl(&xhci->op_regs->status); | |
1059 | if (status & STS_EINT) { | |
1060 | usb_hcd_resume_root_hub(hcd); | |
1061 | usb_hcd_resume_root_hub(xhci->shared_hcd); | |
1062 | } | |
f69e3120 | 1063 | } |
71c731a2 AC |
1064 | |
1065 | /* | |
1066 | * If system is subject to the Quirk, Compliance Mode Timer needs to | |
1067 | * be re-initialized Always after a system resume. Ports are subject | |
1068 | * to suffer the Compliance Mode issue again. It doesn't matter if | |
1069 | * ports have entered previously to U0 before system's suspension. | |
1070 | */ | |
77df9e0b | 1071 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running) |
71c731a2 AC |
1072 | compliance_mode_recovery_timer_init(xhci); |
1073 | ||
c52804a4 SS |
1074 | /* Re-enable port polling. */ |
1075 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1076 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
1077 | usb_hcd_poll_rh_status(hcd); | |
1078 | ||
f69e3120 | 1079 | return retval; |
5535b1d5 | 1080 | } |
b5b5c3ac SS |
1081 | #endif /* CONFIG_PM */ |
1082 | ||
7f84eef0 SS |
1083 | /*-------------------------------------------------------------------------*/ |
1084 | ||
d0e96f5a SS |
1085 | /** |
1086 | * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and | |
1087 | * HCDs. Find the index for an endpoint given its descriptor. Use the return | |
1088 | * value to right shift 1 for the bitmask. | |
1089 | * | |
1090 | * Index = (epnum * 2) + direction - 1, | |
1091 | * where direction = 0 for OUT, 1 for IN. | |
1092 | * For control endpoints, the IN index is used (OUT index is unused), so | |
1093 | * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) | |
1094 | */ | |
1095 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc) | |
1096 | { | |
1097 | unsigned int index; | |
1098 | if (usb_endpoint_xfer_control(desc)) | |
1099 | index = (unsigned int) (usb_endpoint_num(desc)*2); | |
1100 | else | |
1101 | index = (unsigned int) (usb_endpoint_num(desc)*2) + | |
1102 | (usb_endpoint_dir_in(desc) ? 1 : 0) - 1; | |
1103 | return index; | |
1104 | } | |
1105 | ||
01c5f447 JW |
1106 | /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint |
1107 | * address from the XHCI endpoint index. | |
1108 | */ | |
1109 | unsigned int xhci_get_endpoint_address(unsigned int ep_index) | |
1110 | { | |
1111 | unsigned int number = DIV_ROUND_UP(ep_index, 2); | |
1112 | unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN; | |
1113 | return direction | number; | |
1114 | } | |
1115 | ||
f94e0186 SS |
1116 | /* Find the flag for this endpoint (for use in the control context). Use the |
1117 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1118 | * bit 1, etc. | |
1119 | */ | |
1120 | unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc) | |
1121 | { | |
1122 | return 1 << (xhci_get_endpoint_index(desc) + 1); | |
1123 | } | |
1124 | ||
ac9d8fe7 SS |
1125 | /* Find the flag for this endpoint (for use in the control context). Use the |
1126 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1127 | * bit 1, etc. | |
1128 | */ | |
1129 | unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index) | |
1130 | { | |
1131 | return 1 << (ep_index + 1); | |
1132 | } | |
1133 | ||
f94e0186 SS |
1134 | /* Compute the last valid endpoint context index. Basically, this is the |
1135 | * endpoint index plus one. For slot contexts with more than valid endpoint, | |
1136 | * we find the most significant bit set in the added contexts flags. | |
1137 | * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000 | |
1138 | * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one. | |
1139 | */ | |
ac9d8fe7 | 1140 | unsigned int xhci_last_valid_endpoint(u32 added_ctxs) |
f94e0186 SS |
1141 | { |
1142 | return fls(added_ctxs) - 1; | |
1143 | } | |
1144 | ||
d0e96f5a SS |
1145 | /* Returns 1 if the arguments are OK; |
1146 | * returns 0 this is a root hub; returns -EINVAL for NULL pointers. | |
1147 | */ | |
8212a49d | 1148 | static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, |
64927730 AX |
1149 | struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev, |
1150 | const char *func) { | |
1151 | struct xhci_hcd *xhci; | |
1152 | struct xhci_virt_device *virt_dev; | |
1153 | ||
d0e96f5a | 1154 | if (!hcd || (check_ep && !ep) || !udev) { |
5c1127d3 | 1155 | pr_debug("xHCI %s called with invalid args\n", func); |
d0e96f5a SS |
1156 | return -EINVAL; |
1157 | } | |
1158 | if (!udev->parent) { | |
5c1127d3 | 1159 | pr_debug("xHCI %s called for root hub\n", func); |
d0e96f5a SS |
1160 | return 0; |
1161 | } | |
64927730 | 1162 | |
7bd89b40 | 1163 | xhci = hcd_to_xhci(hcd); |
64927730 | 1164 | if (check_virt_dev) { |
73ddc247 | 1165 | if (!udev->slot_id || !xhci->devs[udev->slot_id]) { |
5c1127d3 XR |
1166 | xhci_dbg(xhci, "xHCI %s called with unaddressed device\n", |
1167 | func); | |
64927730 AX |
1168 | return -EINVAL; |
1169 | } | |
1170 | ||
1171 | virt_dev = xhci->devs[udev->slot_id]; | |
1172 | if (virt_dev->udev != udev) { | |
5c1127d3 | 1173 | xhci_dbg(xhci, "xHCI %s called with udev and " |
64927730 AX |
1174 | "virt_dev does not match\n", func); |
1175 | return -EINVAL; | |
1176 | } | |
d0e96f5a | 1177 | } |
64927730 | 1178 | |
203a8661 SS |
1179 | if (xhci->xhc_state & XHCI_STATE_HALTED) |
1180 | return -ENODEV; | |
1181 | ||
d0e96f5a SS |
1182 | return 1; |
1183 | } | |
1184 | ||
2d3f1fac | 1185 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, |
913a8a34 SS |
1186 | struct usb_device *udev, struct xhci_command *command, |
1187 | bool ctx_change, bool must_succeed); | |
2d3f1fac SS |
1188 | |
1189 | /* | |
1190 | * Full speed devices may have a max packet size greater than 8 bytes, but the | |
1191 | * USB core doesn't know that until it reads the first 8 bytes of the | |
1192 | * descriptor. If the usb_device's max packet size changes after that point, | |
1193 | * we need to issue an evaluate context command and wait on it. | |
1194 | */ | |
1195 | static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, | |
1196 | unsigned int ep_index, struct urb *urb) | |
1197 | { | |
2d3f1fac SS |
1198 | struct xhci_container_ctx *out_ctx; |
1199 | struct xhci_input_control_ctx *ctrl_ctx; | |
1200 | struct xhci_ep_ctx *ep_ctx; | |
ddba5cd0 | 1201 | struct xhci_command *command; |
2d3f1fac SS |
1202 | int max_packet_size; |
1203 | int hw_max_packet_size; | |
1204 | int ret = 0; | |
1205 | ||
1206 | out_ctx = xhci->devs[slot_id]->out_ctx; | |
1207 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); | |
28ccd296 | 1208 | hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); |
29cc8897 | 1209 | max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc); |
2d3f1fac | 1210 | if (hw_max_packet_size != max_packet_size) { |
3a7fa5be XR |
1211 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1212 | "Max Packet Size for ep 0 changed."); | |
1213 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, | |
1214 | "Max packet size in usb_device = %d", | |
2d3f1fac | 1215 | max_packet_size); |
3a7fa5be XR |
1216 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1217 | "Max packet size in xHCI HW = %d", | |
2d3f1fac | 1218 | hw_max_packet_size); |
3a7fa5be XR |
1219 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1220 | "Issuing evaluate context command."); | |
2d3f1fac | 1221 | |
92f8e767 SS |
1222 | /* Set up the input context flags for the command */ |
1223 | /* FIXME: This won't work if a non-default control endpoint | |
1224 | * changes max packet sizes. | |
1225 | */ | |
ddba5cd0 MN |
1226 | |
1227 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); | |
1228 | if (!command) | |
1229 | return -ENOMEM; | |
1230 | ||
1231 | command->in_ctx = xhci->devs[slot_id]->in_ctx; | |
1232 | ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx); | |
92f8e767 SS |
1233 | if (!ctrl_ctx) { |
1234 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1235 | __func__); | |
ddba5cd0 MN |
1236 | ret = -ENOMEM; |
1237 | goto command_cleanup; | |
92f8e767 | 1238 | } |
2d3f1fac | 1239 | /* Set up the modified control endpoint 0 */ |
913a8a34 SS |
1240 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
1241 | xhci->devs[slot_id]->out_ctx, ep_index); | |
92f8e767 | 1242 | |
ddba5cd0 | 1243 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); |
28ccd296 ME |
1244 | ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK); |
1245 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); | |
2d3f1fac | 1246 | |
28ccd296 | 1247 | ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); |
2d3f1fac SS |
1248 | ctrl_ctx->drop_flags = 0; |
1249 | ||
1250 | xhci_dbg(xhci, "Slot %d input context\n", slot_id); | |
ddba5cd0 | 1251 | xhci_dbg_ctx(xhci, command->in_ctx, ep_index); |
2d3f1fac SS |
1252 | xhci_dbg(xhci, "Slot %d output context\n", slot_id); |
1253 | xhci_dbg_ctx(xhci, out_ctx, ep_index); | |
1254 | ||
ddba5cd0 | 1255 | ret = xhci_configure_endpoint(xhci, urb->dev, command, |
913a8a34 | 1256 | true, false); |
2d3f1fac SS |
1257 | |
1258 | /* Clean up the input context for later use by bandwidth | |
1259 | * functions. | |
1260 | */ | |
28ccd296 | 1261 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); |
ddba5cd0 MN |
1262 | command_cleanup: |
1263 | kfree(command->completion); | |
1264 | kfree(command); | |
2d3f1fac SS |
1265 | } |
1266 | return ret; | |
1267 | } | |
1268 | ||
d0e96f5a SS |
1269 | /* |
1270 | * non-error returns are a promise to giveback() the urb later | |
1271 | * we drop ownership so next owner (or urb unlink) can get it | |
1272 | */ | |
1273 | int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) | |
1274 | { | |
1275 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
2ffdea25 | 1276 | struct xhci_td *buffer; |
d0e96f5a SS |
1277 | unsigned long flags; |
1278 | int ret = 0; | |
1279 | unsigned int slot_id, ep_index; | |
8e51adcc AX |
1280 | struct urb_priv *urb_priv; |
1281 | int size, i; | |
2d3f1fac | 1282 | |
64927730 AX |
1283 | if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, |
1284 | true, true, __func__) <= 0) | |
d0e96f5a SS |
1285 | return -EINVAL; |
1286 | ||
1287 | slot_id = urb->dev->slot_id; | |
1288 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
d0e96f5a | 1289 | |
541c7d43 | 1290 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
d0e96f5a SS |
1291 | if (!in_interrupt()) |
1292 | xhci_dbg(xhci, "urb submitted during PCI suspend\n"); | |
1293 | ret = -ESHUTDOWN; | |
1294 | goto exit; | |
1295 | } | |
8e51adcc AX |
1296 | |
1297 | if (usb_endpoint_xfer_isoc(&urb->ep->desc)) | |
1298 | size = urb->number_of_packets; | |
1299 | else | |
1300 | size = 1; | |
1301 | ||
1302 | urb_priv = kzalloc(sizeof(struct urb_priv) + | |
1303 | size * sizeof(struct xhci_td *), mem_flags); | |
1304 | if (!urb_priv) | |
1305 | return -ENOMEM; | |
1306 | ||
2ffdea25 AX |
1307 | buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags); |
1308 | if (!buffer) { | |
1309 | kfree(urb_priv); | |
1310 | return -ENOMEM; | |
1311 | } | |
1312 | ||
8e51adcc | 1313 | for (i = 0; i < size; i++) { |
2ffdea25 AX |
1314 | urb_priv->td[i] = buffer; |
1315 | buffer++; | |
8e51adcc AX |
1316 | } |
1317 | ||
1318 | urb_priv->length = size; | |
1319 | urb_priv->td_cnt = 0; | |
1320 | urb->hcpriv = urb_priv; | |
1321 | ||
2d3f1fac SS |
1322 | if (usb_endpoint_xfer_control(&urb->ep->desc)) { |
1323 | /* Check to see if the max packet size for the default control | |
1324 | * endpoint changed during FS device enumeration | |
1325 | */ | |
1326 | if (urb->dev->speed == USB_SPEED_FULL) { | |
1327 | ret = xhci_check_maxpacket(xhci, slot_id, | |
1328 | ep_index, urb); | |
d13565c1 SS |
1329 | if (ret < 0) { |
1330 | xhci_urb_free_priv(xhci, urb_priv); | |
1331 | urb->hcpriv = NULL; | |
2d3f1fac | 1332 | return ret; |
d13565c1 | 1333 | } |
2d3f1fac SS |
1334 | } |
1335 | ||
b11069f5 SS |
1336 | /* We have a spinlock and interrupts disabled, so we must pass |
1337 | * atomic context to this function, which may allocate memory. | |
1338 | */ | |
2d3f1fac | 1339 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
1340 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1341 | goto dying; | |
b11069f5 | 1342 | ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb, |
23e3be11 | 1343 | slot_id, ep_index); |
d13565c1 SS |
1344 | if (ret) |
1345 | goto free_priv; | |
2d3f1fac SS |
1346 | spin_unlock_irqrestore(&xhci->lock, flags); |
1347 | } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) { | |
1348 | spin_lock_irqsave(&xhci->lock, flags); | |
6f5165cf SS |
1349 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1350 | goto dying; | |
8df75f42 SS |
1351 | if (xhci->devs[slot_id]->eps[ep_index].ep_state & |
1352 | EP_GETTING_STREAMS) { | |
1353 | xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep " | |
1354 | "is transitioning to using streams.\n"); | |
1355 | ret = -EINVAL; | |
1356 | } else if (xhci->devs[slot_id]->eps[ep_index].ep_state & | |
1357 | EP_GETTING_NO_STREAMS) { | |
1358 | xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep " | |
1359 | "is transitioning to " | |
1360 | "not having streams.\n"); | |
1361 | ret = -EINVAL; | |
1362 | } else { | |
1363 | ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, | |
1364 | slot_id, ep_index); | |
1365 | } | |
d13565c1 SS |
1366 | if (ret) |
1367 | goto free_priv; | |
2d3f1fac | 1368 | spin_unlock_irqrestore(&xhci->lock, flags); |
624defa1 SS |
1369 | } else if (usb_endpoint_xfer_int(&urb->ep->desc)) { |
1370 | spin_lock_irqsave(&xhci->lock, flags); | |
6f5165cf SS |
1371 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1372 | goto dying; | |
624defa1 SS |
1373 | ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb, |
1374 | slot_id, ep_index); | |
d13565c1 SS |
1375 | if (ret) |
1376 | goto free_priv; | |
624defa1 | 1377 | spin_unlock_irqrestore(&xhci->lock, flags); |
2d3f1fac | 1378 | } else { |
787f4e5a AX |
1379 | spin_lock_irqsave(&xhci->lock, flags); |
1380 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
1381 | goto dying; | |
1382 | ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb, | |
1383 | slot_id, ep_index); | |
d13565c1 SS |
1384 | if (ret) |
1385 | goto free_priv; | |
787f4e5a | 1386 | spin_unlock_irqrestore(&xhci->lock, flags); |
2d3f1fac | 1387 | } |
d0e96f5a | 1388 | exit: |
d0e96f5a | 1389 | return ret; |
6f5165cf SS |
1390 | dying: |
1391 | xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for " | |
1392 | "non-responsive xHCI host.\n", | |
1393 | urb->ep->desc.bEndpointAddress, urb); | |
d13565c1 SS |
1394 | ret = -ESHUTDOWN; |
1395 | free_priv: | |
1396 | xhci_urb_free_priv(xhci, urb_priv); | |
1397 | urb->hcpriv = NULL; | |
6f5165cf | 1398 | spin_unlock_irqrestore(&xhci->lock, flags); |
d13565c1 | 1399 | return ret; |
d0e96f5a SS |
1400 | } |
1401 | ||
021bff91 SS |
1402 | /* Get the right ring for the given URB. |
1403 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
1404 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
1405 | */ | |
1406 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |
1407 | struct urb *urb) | |
1408 | { | |
1409 | unsigned int slot_id; | |
1410 | unsigned int ep_index; | |
1411 | unsigned int stream_id; | |
1412 | struct xhci_virt_ep *ep; | |
1413 | ||
1414 | slot_id = urb->dev->slot_id; | |
1415 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
1416 | stream_id = urb->stream_id; | |
1417 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
1418 | /* Common case: no streams */ | |
1419 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
1420 | return ep->ring; | |
1421 | ||
1422 | if (stream_id == 0) { | |
1423 | xhci_warn(xhci, | |
1424 | "WARN: Slot ID %u, ep index %u has streams, " | |
1425 | "but URB has no stream ID.\n", | |
1426 | slot_id, ep_index); | |
1427 | return NULL; | |
1428 | } | |
1429 | ||
1430 | if (stream_id < ep->stream_info->num_streams) | |
1431 | return ep->stream_info->stream_rings[stream_id]; | |
1432 | ||
1433 | xhci_warn(xhci, | |
1434 | "WARN: Slot ID %u, ep index %u has " | |
1435 | "stream IDs 1 to %u allocated, " | |
1436 | "but stream ID %u is requested.\n", | |
1437 | slot_id, ep_index, | |
1438 | ep->stream_info->num_streams - 1, | |
1439 | stream_id); | |
1440 | return NULL; | |
1441 | } | |
1442 | ||
ae636747 SS |
1443 | /* |
1444 | * Remove the URB's TD from the endpoint ring. This may cause the HC to stop | |
1445 | * USB transfers, potentially stopping in the middle of a TRB buffer. The HC | |
1446 | * should pick up where it left off in the TD, unless a Set Transfer Ring | |
1447 | * Dequeue Pointer is issued. | |
1448 | * | |
1449 | * The TRBs that make up the buffers for the canceled URB will be "removed" from | |
1450 | * the ring. Since the ring is a contiguous structure, they can't be physically | |
1451 | * removed. Instead, there are two options: | |
1452 | * | |
1453 | * 1) If the HC is in the middle of processing the URB to be canceled, we | |
1454 | * simply move the ring's dequeue pointer past those TRBs using the Set | |
1455 | * Transfer Ring Dequeue Pointer command. This will be the common case, | |
1456 | * when drivers timeout on the last submitted URB and attempt to cancel. | |
1457 | * | |
1458 | * 2) If the HC is in the middle of a different TD, we turn the TRBs into a | |
1459 | * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The | |
1460 | * HC will need to invalidate the any TRBs it has cached after the stop | |
1461 | * endpoint command, as noted in the xHCI 0.95 errata. | |
1462 | * | |
1463 | * 3) The TD may have completed by the time the Stop Endpoint Command | |
1464 | * completes, so software needs to handle that case too. | |
1465 | * | |
1466 | * This function should protect against the TD enqueueing code ringing the | |
1467 | * doorbell while this code is waiting for a Stop Endpoint command to complete. | |
1468 | * It also needs to account for multiple cancellations on happening at the same | |
1469 | * time for the same endpoint. | |
1470 | * | |
1471 | * Note that this function can be called in any context, or so says | |
1472 | * usb_hcd_unlink_urb() | |
d0e96f5a SS |
1473 | */ |
1474 | int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | |
1475 | { | |
ae636747 | 1476 | unsigned long flags; |
8e51adcc | 1477 | int ret, i; |
e34b2fbf | 1478 | u32 temp; |
ae636747 | 1479 | struct xhci_hcd *xhci; |
8e51adcc | 1480 | struct urb_priv *urb_priv; |
ae636747 SS |
1481 | struct xhci_td *td; |
1482 | unsigned int ep_index; | |
1483 | struct xhci_ring *ep_ring; | |
63a0d9ab | 1484 | struct xhci_virt_ep *ep; |
ddba5cd0 | 1485 | struct xhci_command *command; |
ae636747 SS |
1486 | |
1487 | xhci = hcd_to_xhci(hcd); | |
1488 | spin_lock_irqsave(&xhci->lock, flags); | |
1489 | /* Make sure the URB hasn't completed or been unlinked already */ | |
1490 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); | |
1491 | if (ret || !urb->hcpriv) | |
1492 | goto done; | |
b0ba9720 | 1493 | temp = readl(&xhci->op_regs->status); |
c6cc27c7 | 1494 | if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) { |
aa50b290 XR |
1495 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1496 | "HW died, freeing TD."); | |
8e51adcc | 1497 | urb_priv = urb->hcpriv; |
585df1d9 SS |
1498 | for (i = urb_priv->td_cnt; i < urb_priv->length; i++) { |
1499 | td = urb_priv->td[i]; | |
1500 | if (!list_empty(&td->td_list)) | |
1501 | list_del_init(&td->td_list); | |
1502 | if (!list_empty(&td->cancelled_td_list)) | |
1503 | list_del_init(&td->cancelled_td_list); | |
1504 | } | |
e34b2fbf SS |
1505 | |
1506 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
1507 | spin_unlock_irqrestore(&xhci->lock, flags); | |
214f76f7 | 1508 | usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN); |
8e51adcc | 1509 | xhci_urb_free_priv(xhci, urb_priv); |
e34b2fbf SS |
1510 | return ret; |
1511 | } | |
7bd89b40 SS |
1512 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
1513 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
aa50b290 XR |
1514 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1515 | "Ep 0x%x: URB %p to be canceled on " | |
1516 | "non-responsive xHCI host.", | |
6f5165cf SS |
1517 | urb->ep->desc.bEndpointAddress, urb); |
1518 | /* Let the stop endpoint command watchdog timer (which set this | |
1519 | * state) finish cleaning up the endpoint TD lists. We must | |
1520 | * have caught it in the middle of dropping a lock and giving | |
1521 | * back an URB. | |
1522 | */ | |
1523 | goto done; | |
1524 | } | |
ae636747 | 1525 | |
ae636747 | 1526 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); |
63a0d9ab | 1527 | ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index]; |
e9df17eb SS |
1528 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
1529 | if (!ep_ring) { | |
1530 | ret = -EINVAL; | |
1531 | goto done; | |
1532 | } | |
1533 | ||
8e51adcc | 1534 | urb_priv = urb->hcpriv; |
79688acf SS |
1535 | i = urb_priv->td_cnt; |
1536 | if (i < urb_priv->length) | |
aa50b290 XR |
1537 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1538 | "Cancel URB %p, dev %s, ep 0x%x, " | |
1539 | "starting at offset 0x%llx", | |
79688acf SS |
1540 | urb, urb->dev->devpath, |
1541 | urb->ep->desc.bEndpointAddress, | |
1542 | (unsigned long long) xhci_trb_virt_to_dma( | |
1543 | urb_priv->td[i]->start_seg, | |
1544 | urb_priv->td[i]->first_trb)); | |
1545 | ||
1546 | for (; i < urb_priv->length; i++) { | |
8e51adcc AX |
1547 | td = urb_priv->td[i]; |
1548 | list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); | |
1549 | } | |
1550 | ||
ae636747 SS |
1551 | /* Queue a stop endpoint command, but only if this is |
1552 | * the first cancellation to be handled. | |
1553 | */ | |
678539cf | 1554 | if (!(ep->ep_state & EP_HALT_PENDING)) { |
ddba5cd0 | 1555 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); |
678539cf | 1556 | ep->ep_state |= EP_HALT_PENDING; |
6f5165cf SS |
1557 | ep->stop_cmds_pending++; |
1558 | ep->stop_cmd_timer.expires = jiffies + | |
1559 | XHCI_STOP_EP_CMD_TIMEOUT * HZ; | |
1560 | add_timer(&ep->stop_cmd_timer); | |
ddba5cd0 MN |
1561 | xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id, |
1562 | ep_index, 0); | |
23e3be11 | 1563 | xhci_ring_cmd_db(xhci); |
ae636747 SS |
1564 | } |
1565 | done: | |
1566 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1567 | return ret; | |
d0e96f5a SS |
1568 | } |
1569 | ||
f94e0186 SS |
1570 | /* Drop an endpoint from a new bandwidth configuration for this device. |
1571 | * Only one call to this function is allowed per endpoint before | |
1572 | * check_bandwidth() or reset_bandwidth() must be called. | |
1573 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1574 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1575 | * different endpoint descriptor in usb_host_endpoint. | |
1576 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1577 | * not allowed. | |
f88ba78d SS |
1578 | * |
1579 | * The USB core will not allow URBs to be queued to an endpoint that is being | |
1580 | * disabled, so there's no need for mutual exclusion to protect | |
1581 | * the xhci->devs[slot_id] structure. | |
f94e0186 SS |
1582 | */ |
1583 | int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |
1584 | struct usb_host_endpoint *ep) | |
1585 | { | |
f94e0186 | 1586 | struct xhci_hcd *xhci; |
d115b048 JY |
1587 | struct xhci_container_ctx *in_ctx, *out_ctx; |
1588 | struct xhci_input_control_ctx *ctrl_ctx; | |
f94e0186 SS |
1589 | unsigned int ep_index; |
1590 | struct xhci_ep_ctx *ep_ctx; | |
1591 | u32 drop_flag; | |
d6759133 | 1592 | u32 new_add_flags, new_drop_flags; |
f94e0186 SS |
1593 | int ret; |
1594 | ||
64927730 | 1595 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
f94e0186 SS |
1596 | if (ret <= 0) |
1597 | return ret; | |
1598 | xhci = hcd_to_xhci(hcd); | |
fe6c6c13 SS |
1599 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1600 | return -ENODEV; | |
f94e0186 | 1601 | |
fe6c6c13 | 1602 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
1603 | drop_flag = xhci_get_endpoint_flag(&ep->desc); |
1604 | if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { | |
1605 | xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", | |
1606 | __func__, drop_flag); | |
1607 | return 0; | |
1608 | } | |
1609 | ||
f94e0186 | 1610 | in_ctx = xhci->devs[udev->slot_id]->in_ctx; |
d115b048 JY |
1611 | out_ctx = xhci->devs[udev->slot_id]->out_ctx; |
1612 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
92f8e767 SS |
1613 | if (!ctrl_ctx) { |
1614 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1615 | __func__); | |
1616 | return 0; | |
1617 | } | |
1618 | ||
f94e0186 | 1619 | ep_index = xhci_get_endpoint_index(&ep->desc); |
d115b048 | 1620 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
f94e0186 SS |
1621 | /* If the HC already knows the endpoint is disabled, |
1622 | * or the HCD has noted it is disabled, ignore this request | |
1623 | */ | |
f5960b69 ME |
1624 | if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
1625 | cpu_to_le32(EP_STATE_DISABLED)) || | |
28ccd296 ME |
1626 | le32_to_cpu(ctrl_ctx->drop_flags) & |
1627 | xhci_get_endpoint_flag(&ep->desc)) { | |
700e2052 GKH |
1628 | xhci_warn(xhci, "xHCI %s called with disabled ep %p\n", |
1629 | __func__, ep); | |
f94e0186 SS |
1630 | return 0; |
1631 | } | |
1632 | ||
28ccd296 ME |
1633 | ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag); |
1634 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
f94e0186 | 1635 | |
28ccd296 ME |
1636 | ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag); |
1637 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 | 1638 | |
f94e0186 SS |
1639 | xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); |
1640 | ||
d6759133 | 1641 | xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", |
f94e0186 SS |
1642 | (unsigned int) ep->desc.bEndpointAddress, |
1643 | udev->slot_id, | |
1644 | (unsigned int) new_drop_flags, | |
d6759133 | 1645 | (unsigned int) new_add_flags); |
f94e0186 SS |
1646 | return 0; |
1647 | } | |
1648 | ||
1649 | /* Add an endpoint to a new possible bandwidth configuration for this device. | |
1650 | * Only one call to this function is allowed per endpoint before | |
1651 | * check_bandwidth() or reset_bandwidth() must be called. | |
1652 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1653 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1654 | * different endpoint descriptor in usb_host_endpoint. | |
1655 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1656 | * not allowed. | |
f88ba78d SS |
1657 | * |
1658 | * The USB core will not allow URBs to be queued to an endpoint until the | |
1659 | * configuration or alt setting is installed in the device, so there's no need | |
1660 | * for mutual exclusion to protect the xhci->devs[slot_id] structure. | |
f94e0186 SS |
1661 | */ |
1662 | int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, | |
1663 | struct usb_host_endpoint *ep) | |
1664 | { | |
f94e0186 | 1665 | struct xhci_hcd *xhci; |
d115b048 | 1666 | struct xhci_container_ctx *in_ctx, *out_ctx; |
f94e0186 | 1667 | unsigned int ep_index; |
d115b048 | 1668 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1669 | u32 added_ctxs; |
d6759133 | 1670 | u32 new_add_flags, new_drop_flags; |
fa75ac37 | 1671 | struct xhci_virt_device *virt_dev; |
f94e0186 SS |
1672 | int ret = 0; |
1673 | ||
64927730 | 1674 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
a1587d97 SS |
1675 | if (ret <= 0) { |
1676 | /* So we won't queue a reset ep command for a root hub */ | |
1677 | ep->hcpriv = NULL; | |
f94e0186 | 1678 | return ret; |
a1587d97 | 1679 | } |
f94e0186 | 1680 | xhci = hcd_to_xhci(hcd); |
fe6c6c13 SS |
1681 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1682 | return -ENODEV; | |
f94e0186 SS |
1683 | |
1684 | added_ctxs = xhci_get_endpoint_flag(&ep->desc); | |
f94e0186 SS |
1685 | if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) { |
1686 | /* FIXME when we have to issue an evaluate endpoint command to | |
1687 | * deal with ep0 max packet size changing once we get the | |
1688 | * descriptors | |
1689 | */ | |
1690 | xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n", | |
1691 | __func__, added_ctxs); | |
1692 | return 0; | |
1693 | } | |
1694 | ||
fa75ac37 SS |
1695 | virt_dev = xhci->devs[udev->slot_id]; |
1696 | in_ctx = virt_dev->in_ctx; | |
1697 | out_ctx = virt_dev->out_ctx; | |
d115b048 | 1698 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); |
92f8e767 SS |
1699 | if (!ctrl_ctx) { |
1700 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1701 | __func__); | |
1702 | return 0; | |
1703 | } | |
fa75ac37 | 1704 | |
92f8e767 | 1705 | ep_index = xhci_get_endpoint_index(&ep->desc); |
fa75ac37 SS |
1706 | /* If this endpoint is already in use, and the upper layers are trying |
1707 | * to add it again without dropping it, reject the addition. | |
1708 | */ | |
1709 | if (virt_dev->eps[ep_index].ring && | |
1710 | !(le32_to_cpu(ctrl_ctx->drop_flags) & | |
1711 | xhci_get_endpoint_flag(&ep->desc))) { | |
1712 | xhci_warn(xhci, "Trying to add endpoint 0x%x " | |
1713 | "without dropping it.\n", | |
1714 | (unsigned int) ep->desc.bEndpointAddress); | |
1715 | return -EINVAL; | |
1716 | } | |
1717 | ||
f94e0186 SS |
1718 | /* If the HCD has already noted the endpoint is enabled, |
1719 | * ignore this request. | |
1720 | */ | |
28ccd296 ME |
1721 | if (le32_to_cpu(ctrl_ctx->add_flags) & |
1722 | xhci_get_endpoint_flag(&ep->desc)) { | |
700e2052 GKH |
1723 | xhci_warn(xhci, "xHCI %s called with enabled ep %p\n", |
1724 | __func__, ep); | |
f94e0186 SS |
1725 | return 0; |
1726 | } | |
1727 | ||
f88ba78d SS |
1728 | /* |
1729 | * Configuration and alternate setting changes must be done in | |
1730 | * process context, not interrupt context (or so documenation | |
1731 | * for usb_set_interface() and usb_set_configuration() claim). | |
1732 | */ | |
fa75ac37 | 1733 | if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) { |
f94e0186 SS |
1734 | dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n", |
1735 | __func__, ep->desc.bEndpointAddress); | |
f94e0186 SS |
1736 | return -ENOMEM; |
1737 | } | |
1738 | ||
28ccd296 ME |
1739 | ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs); |
1740 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 SS |
1741 | |
1742 | /* If xhci_endpoint_disable() was called for this endpoint, but the | |
1743 | * xHC hasn't been notified yet through the check_bandwidth() call, | |
1744 | * this re-adds a new state for the endpoint from the new endpoint | |
1745 | * descriptors. We must drop and re-add this endpoint, so we leave the | |
1746 | * drop flags alone. | |
1747 | */ | |
28ccd296 | 1748 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); |
f94e0186 | 1749 | |
a1587d97 SS |
1750 | /* Store the usb_device pointer for later use */ |
1751 | ep->hcpriv = udev; | |
1752 | ||
d6759133 | 1753 | xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", |
f94e0186 SS |
1754 | (unsigned int) ep->desc.bEndpointAddress, |
1755 | udev->slot_id, | |
1756 | (unsigned int) new_drop_flags, | |
d6759133 | 1757 | (unsigned int) new_add_flags); |
f94e0186 SS |
1758 | return 0; |
1759 | } | |
1760 | ||
d115b048 | 1761 | static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev) |
f94e0186 | 1762 | { |
d115b048 | 1763 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1764 | struct xhci_ep_ctx *ep_ctx; |
d115b048 | 1765 | struct xhci_slot_ctx *slot_ctx; |
f94e0186 SS |
1766 | int i; |
1767 | ||
92f8e767 SS |
1768 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
1769 | if (!ctrl_ctx) { | |
1770 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1771 | __func__); | |
1772 | return; | |
1773 | } | |
1774 | ||
f94e0186 SS |
1775 | /* When a device's add flag and drop flag are zero, any subsequent |
1776 | * configure endpoint command will leave that endpoint's state | |
1777 | * untouched. Make sure we don't leave any old state in the input | |
1778 | * endpoint contexts. | |
1779 | */ | |
d115b048 JY |
1780 | ctrl_ctx->drop_flags = 0; |
1781 | ctrl_ctx->add_flags = 0; | |
1782 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); | |
28ccd296 | 1783 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); |
f94e0186 | 1784 | /* Endpoint 0 is always valid */ |
28ccd296 | 1785 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); |
f94e0186 | 1786 | for (i = 1; i < 31; ++i) { |
d115b048 | 1787 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i); |
f94e0186 SS |
1788 | ep_ctx->ep_info = 0; |
1789 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1790 | ep_ctx->deq = 0; |
f94e0186 SS |
1791 | ep_ctx->tx_info = 0; |
1792 | } | |
1793 | } | |
1794 | ||
f2217e8e | 1795 | static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, |
00161f7d | 1796 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1797 | { |
1798 | int ret; | |
1799 | ||
913a8a34 | 1800 | switch (*cmd_status) { |
c311e391 MN |
1801 | case COMP_CMD_ABORT: |
1802 | case COMP_CMD_STOP: | |
1803 | xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n"); | |
1804 | ret = -ETIME; | |
1805 | break; | |
f2217e8e | 1806 | case COMP_ENOMEM: |
288c0f44 ON |
1807 | dev_warn(&udev->dev, |
1808 | "Not enough host controller resources for new device state.\n"); | |
f2217e8e SS |
1809 | ret = -ENOMEM; |
1810 | /* FIXME: can we allocate more resources for the HC? */ | |
1811 | break; | |
1812 | case COMP_BW_ERR: | |
71d85724 | 1813 | case COMP_2ND_BW_ERR: |
288c0f44 ON |
1814 | dev_warn(&udev->dev, |
1815 | "Not enough bandwidth for new device state.\n"); | |
f2217e8e SS |
1816 | ret = -ENOSPC; |
1817 | /* FIXME: can we go back to the old state? */ | |
1818 | break; | |
1819 | case COMP_TRB_ERR: | |
1820 | /* the HCD set up something wrong */ | |
1821 | dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, " | |
1822 | "add flag = 1, " | |
1823 | "and endpoint is not disabled.\n"); | |
1824 | ret = -EINVAL; | |
1825 | break; | |
f6ba6fe2 | 1826 | case COMP_DEV_ERR: |
288c0f44 ON |
1827 | dev_warn(&udev->dev, |
1828 | "ERROR: Incompatible device for endpoint configure command.\n"); | |
f6ba6fe2 AH |
1829 | ret = -ENODEV; |
1830 | break; | |
f2217e8e | 1831 | case COMP_SUCCESS: |
3a7fa5be XR |
1832 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1833 | "Successful Endpoint Configure command"); | |
f2217e8e SS |
1834 | ret = 0; |
1835 | break; | |
1836 | default: | |
288c0f44 ON |
1837 | xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n", |
1838 | *cmd_status); | |
f2217e8e SS |
1839 | ret = -EINVAL; |
1840 | break; | |
1841 | } | |
1842 | return ret; | |
1843 | } | |
1844 | ||
1845 | static int xhci_evaluate_context_result(struct xhci_hcd *xhci, | |
00161f7d | 1846 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1847 | { |
1848 | int ret; | |
913a8a34 | 1849 | struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id]; |
f2217e8e | 1850 | |
913a8a34 | 1851 | switch (*cmd_status) { |
c311e391 MN |
1852 | case COMP_CMD_ABORT: |
1853 | case COMP_CMD_STOP: | |
1854 | xhci_warn(xhci, "Timeout while waiting for evaluate context command\n"); | |
1855 | ret = -ETIME; | |
1856 | break; | |
f2217e8e | 1857 | case COMP_EINVAL: |
288c0f44 ON |
1858 | dev_warn(&udev->dev, |
1859 | "WARN: xHCI driver setup invalid evaluate context command.\n"); | |
f2217e8e SS |
1860 | ret = -EINVAL; |
1861 | break; | |
1862 | case COMP_EBADSLT: | |
288c0f44 ON |
1863 | dev_warn(&udev->dev, |
1864 | "WARN: slot not enabled for evaluate context command.\n"); | |
b8031342 SS |
1865 | ret = -EINVAL; |
1866 | break; | |
f2217e8e | 1867 | case COMP_CTX_STATE: |
288c0f44 ON |
1868 | dev_warn(&udev->dev, |
1869 | "WARN: invalid context state for evaluate context command.\n"); | |
f2217e8e SS |
1870 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1); |
1871 | ret = -EINVAL; | |
1872 | break; | |
f6ba6fe2 | 1873 | case COMP_DEV_ERR: |
288c0f44 ON |
1874 | dev_warn(&udev->dev, |
1875 | "ERROR: Incompatible device for evaluate context command.\n"); | |
f6ba6fe2 AH |
1876 | ret = -ENODEV; |
1877 | break; | |
1bb73a88 AH |
1878 | case COMP_MEL_ERR: |
1879 | /* Max Exit Latency too large error */ | |
1880 | dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n"); | |
1881 | ret = -EINVAL; | |
1882 | break; | |
f2217e8e | 1883 | case COMP_SUCCESS: |
3a7fa5be XR |
1884 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1885 | "Successful evaluate context command"); | |
f2217e8e SS |
1886 | ret = 0; |
1887 | break; | |
1888 | default: | |
288c0f44 ON |
1889 | xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n", |
1890 | *cmd_status); | |
f2217e8e SS |
1891 | ret = -EINVAL; |
1892 | break; | |
1893 | } | |
1894 | return ret; | |
1895 | } | |
1896 | ||
2cf95c18 | 1897 | static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci, |
92f8e767 | 1898 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1899 | { |
2cf95c18 SS |
1900 | u32 valid_add_flags; |
1901 | u32 valid_drop_flags; | |
1902 | ||
2cf95c18 SS |
1903 | /* Ignore the slot flag (bit 0), and the default control endpoint flag |
1904 | * (bit 1). The default control endpoint is added during the Address | |
1905 | * Device command and is never removed until the slot is disabled. | |
1906 | */ | |
ef73400c XR |
1907 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1908 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
1909 | |
1910 | /* Use hweight32 to count the number of ones in the add flags, or | |
1911 | * number of endpoints added. Don't count endpoints that are changed | |
1912 | * (both added and dropped). | |
1913 | */ | |
1914 | return hweight32(valid_add_flags) - | |
1915 | hweight32(valid_add_flags & valid_drop_flags); | |
1916 | } | |
1917 | ||
1918 | static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci, | |
92f8e767 | 1919 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1920 | { |
2cf95c18 SS |
1921 | u32 valid_add_flags; |
1922 | u32 valid_drop_flags; | |
1923 | ||
78d1ff02 XR |
1924 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1925 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
1926 | |
1927 | return hweight32(valid_drop_flags) - | |
1928 | hweight32(valid_add_flags & valid_drop_flags); | |
1929 | } | |
1930 | ||
1931 | /* | |
1932 | * We need to reserve the new number of endpoints before the configure endpoint | |
1933 | * command completes. We can't subtract the dropped endpoints from the number | |
1934 | * of active endpoints until the command completes because we can oversubscribe | |
1935 | * the host in this case: | |
1936 | * | |
1937 | * - the first configure endpoint command drops more endpoints than it adds | |
1938 | * - a second configure endpoint command that adds more endpoints is queued | |
1939 | * - the first configure endpoint command fails, so the config is unchanged | |
1940 | * - the second command may succeed, even though there isn't enough resources | |
1941 | * | |
1942 | * Must be called with xhci->lock held. | |
1943 | */ | |
1944 | static int xhci_reserve_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1945 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1946 | { |
1947 | u32 added_eps; | |
1948 | ||
92f8e767 | 1949 | added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1950 | if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) { |
4bdfe4c3 XR |
1951 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1952 | "Not enough ep ctxs: " | |
1953 | "%u active, need to add %u, limit is %u.", | |
2cf95c18 SS |
1954 | xhci->num_active_eps, added_eps, |
1955 | xhci->limit_active_eps); | |
1956 | return -ENOMEM; | |
1957 | } | |
1958 | xhci->num_active_eps += added_eps; | |
4bdfe4c3 XR |
1959 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1960 | "Adding %u ep ctxs, %u now active.", added_eps, | |
2cf95c18 SS |
1961 | xhci->num_active_eps); |
1962 | return 0; | |
1963 | } | |
1964 | ||
1965 | /* | |
1966 | * The configure endpoint was failed by the xHC for some other reason, so we | |
1967 | * need to revert the resources that failed configuration would have used. | |
1968 | * | |
1969 | * Must be called with xhci->lock held. | |
1970 | */ | |
1971 | static void xhci_free_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1972 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1973 | { |
1974 | u32 num_failed_eps; | |
1975 | ||
92f8e767 | 1976 | num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1977 | xhci->num_active_eps -= num_failed_eps; |
4bdfe4c3 XR |
1978 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1979 | "Removing %u failed ep ctxs, %u now active.", | |
2cf95c18 SS |
1980 | num_failed_eps, |
1981 | xhci->num_active_eps); | |
1982 | } | |
1983 | ||
1984 | /* | |
1985 | * Now that the command has completed, clean up the active endpoint count by | |
1986 | * subtracting out the endpoints that were dropped (but not changed). | |
1987 | * | |
1988 | * Must be called with xhci->lock held. | |
1989 | */ | |
1990 | static void xhci_finish_resource_reservation(struct xhci_hcd *xhci, | |
92f8e767 | 1991 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1992 | { |
1993 | u32 num_dropped_eps; | |
1994 | ||
92f8e767 | 1995 | num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx); |
2cf95c18 SS |
1996 | xhci->num_active_eps -= num_dropped_eps; |
1997 | if (num_dropped_eps) | |
4bdfe4c3 XR |
1998 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1999 | "Removing %u dropped ep ctxs, %u now active.", | |
2cf95c18 SS |
2000 | num_dropped_eps, |
2001 | xhci->num_active_eps); | |
2002 | } | |
2003 | ||
ed384bd3 | 2004 | static unsigned int xhci_get_block_size(struct usb_device *udev) |
c29eea62 SS |
2005 | { |
2006 | switch (udev->speed) { | |
2007 | case USB_SPEED_LOW: | |
2008 | case USB_SPEED_FULL: | |
2009 | return FS_BLOCK; | |
2010 | case USB_SPEED_HIGH: | |
2011 | return HS_BLOCK; | |
2012 | case USB_SPEED_SUPER: | |
2013 | return SS_BLOCK; | |
2014 | case USB_SPEED_UNKNOWN: | |
2015 | case USB_SPEED_WIRELESS: | |
2016 | default: | |
2017 | /* Should never happen */ | |
2018 | return 1; | |
2019 | } | |
2020 | } | |
2021 | ||
ed384bd3 FB |
2022 | static unsigned int |
2023 | xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw) | |
c29eea62 SS |
2024 | { |
2025 | if (interval_bw->overhead[LS_OVERHEAD_TYPE]) | |
2026 | return LS_OVERHEAD; | |
2027 | if (interval_bw->overhead[FS_OVERHEAD_TYPE]) | |
2028 | return FS_OVERHEAD; | |
2029 | return HS_OVERHEAD; | |
2030 | } | |
2031 | ||
2032 | /* If we are changing a LS/FS device under a HS hub, | |
2033 | * make sure (if we are activating a new TT) that the HS bus has enough | |
2034 | * bandwidth for this new TT. | |
2035 | */ | |
2036 | static int xhci_check_tt_bw_table(struct xhci_hcd *xhci, | |
2037 | struct xhci_virt_device *virt_dev, | |
2038 | int old_active_eps) | |
2039 | { | |
2040 | struct xhci_interval_bw_table *bw_table; | |
2041 | struct xhci_tt_bw_info *tt_info; | |
2042 | ||
2043 | /* Find the bandwidth table for the root port this TT is attached to. */ | |
2044 | bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table; | |
2045 | tt_info = virt_dev->tt_info; | |
2046 | /* If this TT already had active endpoints, the bandwidth for this TT | |
2047 | * has already been added. Removing all periodic endpoints (and thus | |
2048 | * making the TT enactive) will only decrease the bandwidth used. | |
2049 | */ | |
2050 | if (old_active_eps) | |
2051 | return 0; | |
2052 | if (old_active_eps == 0 && tt_info->active_eps != 0) { | |
2053 | if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT) | |
2054 | return -ENOMEM; | |
2055 | return 0; | |
2056 | } | |
2057 | /* Not sure why we would have no new active endpoints... | |
2058 | * | |
2059 | * Maybe because of an Evaluate Context change for a hub update or a | |
2060 | * control endpoint 0 max packet size change? | |
2061 | * FIXME: skip the bandwidth calculation in that case. | |
2062 | */ | |
2063 | return 0; | |
2064 | } | |
2065 | ||
2b698999 SS |
2066 | static int xhci_check_ss_bw(struct xhci_hcd *xhci, |
2067 | struct xhci_virt_device *virt_dev) | |
2068 | { | |
2069 | unsigned int bw_reserved; | |
2070 | ||
2071 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100); | |
2072 | if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved)) | |
2073 | return -ENOMEM; | |
2074 | ||
2075 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100); | |
2076 | if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved)) | |
2077 | return -ENOMEM; | |
2078 | ||
2079 | return 0; | |
2080 | } | |
2081 | ||
c29eea62 SS |
2082 | /* |
2083 | * This algorithm is a very conservative estimate of the worst-case scheduling | |
2084 | * scenario for any one interval. The hardware dynamically schedules the | |
2085 | * packets, so we can't tell which microframe could be the limiting factor in | |
2086 | * the bandwidth scheduling. This only takes into account periodic endpoints. | |
2087 | * | |
2088 | * Obviously, we can't solve an NP complete problem to find the minimum worst | |
2089 | * case scenario. Instead, we come up with an estimate that is no less than | |
2090 | * the worst case bandwidth used for any one microframe, but may be an | |
2091 | * over-estimate. | |
2092 | * | |
2093 | * We walk the requirements for each endpoint by interval, starting with the | |
2094 | * smallest interval, and place packets in the schedule where there is only one | |
2095 | * possible way to schedule packets for that interval. In order to simplify | |
2096 | * this algorithm, we record the largest max packet size for each interval, and | |
2097 | * assume all packets will be that size. | |
2098 | * | |
2099 | * For interval 0, we obviously must schedule all packets for each interval. | |
2100 | * The bandwidth for interval 0 is just the amount of data to be transmitted | |
2101 | * (the sum of all max ESIT payload sizes, plus any overhead per packet times | |
2102 | * the number of packets). | |
2103 | * | |
2104 | * For interval 1, we have two possible microframes to schedule those packets | |
2105 | * in. For this algorithm, if we can schedule the same number of packets for | |
2106 | * each possible scheduling opportunity (each microframe), we will do so. The | |
2107 | * remaining number of packets will be saved to be transmitted in the gaps in | |
2108 | * the next interval's scheduling sequence. | |
2109 | * | |
2110 | * As we move those remaining packets to be scheduled with interval 2 packets, | |
2111 | * we have to double the number of remaining packets to transmit. This is | |
2112 | * because the intervals are actually powers of 2, and we would be transmitting | |
2113 | * the previous interval's packets twice in this interval. We also have to be | |
2114 | * sure that when we look at the largest max packet size for this interval, we | |
2115 | * also look at the largest max packet size for the remaining packets and take | |
2116 | * the greater of the two. | |
2117 | * | |
2118 | * The algorithm continues to evenly distribute packets in each scheduling | |
2119 | * opportunity, and push the remaining packets out, until we get to the last | |
2120 | * interval. Then those packets and their associated overhead are just added | |
2121 | * to the bandwidth used. | |
2e27980e SS |
2122 | */ |
2123 | static int xhci_check_bw_table(struct xhci_hcd *xhci, | |
2124 | struct xhci_virt_device *virt_dev, | |
2125 | int old_active_eps) | |
2126 | { | |
c29eea62 SS |
2127 | unsigned int bw_reserved; |
2128 | unsigned int max_bandwidth; | |
2129 | unsigned int bw_used; | |
2130 | unsigned int block_size; | |
2131 | struct xhci_interval_bw_table *bw_table; | |
2132 | unsigned int packet_size = 0; | |
2133 | unsigned int overhead = 0; | |
2134 | unsigned int packets_transmitted = 0; | |
2135 | unsigned int packets_remaining = 0; | |
2136 | unsigned int i; | |
2137 | ||
2b698999 SS |
2138 | if (virt_dev->udev->speed == USB_SPEED_SUPER) |
2139 | return xhci_check_ss_bw(xhci, virt_dev); | |
2140 | ||
c29eea62 SS |
2141 | if (virt_dev->udev->speed == USB_SPEED_HIGH) { |
2142 | max_bandwidth = HS_BW_LIMIT; | |
2143 | /* Convert percent of bus BW reserved to blocks reserved */ | |
2144 | bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100); | |
2145 | } else { | |
2146 | max_bandwidth = FS_BW_LIMIT; | |
2147 | bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100); | |
2148 | } | |
2149 | ||
2150 | bw_table = virt_dev->bw_table; | |
2151 | /* We need to translate the max packet size and max ESIT payloads into | |
2152 | * the units the hardware uses. | |
2153 | */ | |
2154 | block_size = xhci_get_block_size(virt_dev->udev); | |
2155 | ||
2156 | /* If we are manipulating a LS/FS device under a HS hub, double check | |
2157 | * that the HS bus has enough bandwidth if we are activing a new TT. | |
2158 | */ | |
2159 | if (virt_dev->tt_info) { | |
4bdfe4c3 XR |
2160 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2161 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2162 | virt_dev->real_port); |
2163 | if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) { | |
2164 | xhci_warn(xhci, "Not enough bandwidth on HS bus for " | |
2165 | "newly activated TT.\n"); | |
2166 | return -ENOMEM; | |
2167 | } | |
4bdfe4c3 XR |
2168 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2169 | "Recalculating BW for TT slot %u port %u", | |
c29eea62 SS |
2170 | virt_dev->tt_info->slot_id, |
2171 | virt_dev->tt_info->ttport); | |
2172 | } else { | |
4bdfe4c3 XR |
2173 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2174 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2175 | virt_dev->real_port); |
2176 | } | |
2177 | ||
2178 | /* Add in how much bandwidth will be used for interval zero, or the | |
2179 | * rounded max ESIT payload + number of packets * largest overhead. | |
2180 | */ | |
2181 | bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) + | |
2182 | bw_table->interval_bw[0].num_packets * | |
2183 | xhci_get_largest_overhead(&bw_table->interval_bw[0]); | |
2184 | ||
2185 | for (i = 1; i < XHCI_MAX_INTERVAL; i++) { | |
2186 | unsigned int bw_added; | |
2187 | unsigned int largest_mps; | |
2188 | unsigned int interval_overhead; | |
2189 | ||
2190 | /* | |
2191 | * How many packets could we transmit in this interval? | |
2192 | * If packets didn't fit in the previous interval, we will need | |
2193 | * to transmit that many packets twice within this interval. | |
2194 | */ | |
2195 | packets_remaining = 2 * packets_remaining + | |
2196 | bw_table->interval_bw[i].num_packets; | |
2197 | ||
2198 | /* Find the largest max packet size of this or the previous | |
2199 | * interval. | |
2200 | */ | |
2201 | if (list_empty(&bw_table->interval_bw[i].endpoints)) | |
2202 | largest_mps = 0; | |
2203 | else { | |
2204 | struct xhci_virt_ep *virt_ep; | |
2205 | struct list_head *ep_entry; | |
2206 | ||
2207 | ep_entry = bw_table->interval_bw[i].endpoints.next; | |
2208 | virt_ep = list_entry(ep_entry, | |
2209 | struct xhci_virt_ep, bw_endpoint_list); | |
2210 | /* Convert to blocks, rounding up */ | |
2211 | largest_mps = DIV_ROUND_UP( | |
2212 | virt_ep->bw_info.max_packet_size, | |
2213 | block_size); | |
2214 | } | |
2215 | if (largest_mps > packet_size) | |
2216 | packet_size = largest_mps; | |
2217 | ||
2218 | /* Use the larger overhead of this or the previous interval. */ | |
2219 | interval_overhead = xhci_get_largest_overhead( | |
2220 | &bw_table->interval_bw[i]); | |
2221 | if (interval_overhead > overhead) | |
2222 | overhead = interval_overhead; | |
2223 | ||
2224 | /* How many packets can we evenly distribute across | |
2225 | * (1 << (i + 1)) possible scheduling opportunities? | |
2226 | */ | |
2227 | packets_transmitted = packets_remaining >> (i + 1); | |
2228 | ||
2229 | /* Add in the bandwidth used for those scheduled packets */ | |
2230 | bw_added = packets_transmitted * (overhead + packet_size); | |
2231 | ||
2232 | /* How many packets do we have remaining to transmit? */ | |
2233 | packets_remaining = packets_remaining % (1 << (i + 1)); | |
2234 | ||
2235 | /* What largest max packet size should those packets have? */ | |
2236 | /* If we've transmitted all packets, don't carry over the | |
2237 | * largest packet size. | |
2238 | */ | |
2239 | if (packets_remaining == 0) { | |
2240 | packet_size = 0; | |
2241 | overhead = 0; | |
2242 | } else if (packets_transmitted > 0) { | |
2243 | /* Otherwise if we do have remaining packets, and we've | |
2244 | * scheduled some packets in this interval, take the | |
2245 | * largest max packet size from endpoints with this | |
2246 | * interval. | |
2247 | */ | |
2248 | packet_size = largest_mps; | |
2249 | overhead = interval_overhead; | |
2250 | } | |
2251 | /* Otherwise carry over packet_size and overhead from the last | |
2252 | * time we had a remainder. | |
2253 | */ | |
2254 | bw_used += bw_added; | |
2255 | if (bw_used > max_bandwidth) { | |
2256 | xhci_warn(xhci, "Not enough bandwidth. " | |
2257 | "Proposed: %u, Max: %u\n", | |
2258 | bw_used, max_bandwidth); | |
2259 | return -ENOMEM; | |
2260 | } | |
2261 | } | |
2262 | /* | |
2263 | * Ok, we know we have some packets left over after even-handedly | |
2264 | * scheduling interval 15. We don't know which microframes they will | |
2265 | * fit into, so we over-schedule and say they will be scheduled every | |
2266 | * microframe. | |
2267 | */ | |
2268 | if (packets_remaining > 0) | |
2269 | bw_used += overhead + packet_size; | |
2270 | ||
2271 | if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) { | |
2272 | unsigned int port_index = virt_dev->real_port - 1; | |
2273 | ||
2274 | /* OK, we're manipulating a HS device attached to a | |
2275 | * root port bandwidth domain. Include the number of active TTs | |
2276 | * in the bandwidth used. | |
2277 | */ | |
2278 | bw_used += TT_HS_OVERHEAD * | |
2279 | xhci->rh_bw[port_index].num_active_tts; | |
2280 | } | |
2281 | ||
4bdfe4c3 XR |
2282 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2283 | "Final bandwidth: %u, Limit: %u, Reserved: %u, " | |
2284 | "Available: %u " "percent", | |
c29eea62 SS |
2285 | bw_used, max_bandwidth, bw_reserved, |
2286 | (max_bandwidth - bw_used - bw_reserved) * 100 / | |
2287 | max_bandwidth); | |
2288 | ||
2289 | bw_used += bw_reserved; | |
2290 | if (bw_used > max_bandwidth) { | |
2291 | xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n", | |
2292 | bw_used, max_bandwidth); | |
2293 | return -ENOMEM; | |
2294 | } | |
2295 | ||
2296 | bw_table->bw_used = bw_used; | |
2e27980e SS |
2297 | return 0; |
2298 | } | |
2299 | ||
2300 | static bool xhci_is_async_ep(unsigned int ep_type) | |
2301 | { | |
2302 | return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
2303 | ep_type != ISOC_IN_EP && | |
2304 | ep_type != INT_IN_EP); | |
2305 | } | |
2306 | ||
2b698999 SS |
2307 | static bool xhci_is_sync_in_ep(unsigned int ep_type) |
2308 | { | |
392a07ae | 2309 | return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP); |
2b698999 SS |
2310 | } |
2311 | ||
2312 | static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw) | |
2313 | { | |
2314 | unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK); | |
2315 | ||
2316 | if (ep_bw->ep_interval == 0) | |
2317 | return SS_OVERHEAD_BURST + | |
2318 | (ep_bw->mult * ep_bw->num_packets * | |
2319 | (SS_OVERHEAD + mps)); | |
2320 | return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets * | |
2321 | (SS_OVERHEAD + mps + SS_OVERHEAD_BURST), | |
2322 | 1 << ep_bw->ep_interval); | |
2323 | ||
2324 | } | |
2325 | ||
2e27980e SS |
2326 | void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, |
2327 | struct xhci_bw_info *ep_bw, | |
2328 | struct xhci_interval_bw_table *bw_table, | |
2329 | struct usb_device *udev, | |
2330 | struct xhci_virt_ep *virt_ep, | |
2331 | struct xhci_tt_bw_info *tt_info) | |
2332 | { | |
2333 | struct xhci_interval_bw *interval_bw; | |
2334 | int normalized_interval; | |
2335 | ||
2b698999 | 2336 | if (xhci_is_async_ep(ep_bw->type)) |
2e27980e SS |
2337 | return; |
2338 | ||
2b698999 SS |
2339 | if (udev->speed == USB_SPEED_SUPER) { |
2340 | if (xhci_is_sync_in_ep(ep_bw->type)) | |
2341 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in -= | |
2342 | xhci_get_ss_bw_consumed(ep_bw); | |
2343 | else | |
2344 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out -= | |
2345 | xhci_get_ss_bw_consumed(ep_bw); | |
2346 | return; | |
2347 | } | |
2348 | ||
2349 | /* SuperSpeed endpoints never get added to intervals in the table, so | |
2350 | * this check is only valid for HS/FS/LS devices. | |
2351 | */ | |
2352 | if (list_empty(&virt_ep->bw_endpoint_list)) | |
2353 | return; | |
2e27980e SS |
2354 | /* For LS/FS devices, we need to translate the interval expressed in |
2355 | * microframes to frames. | |
2356 | */ | |
2357 | if (udev->speed == USB_SPEED_HIGH) | |
2358 | normalized_interval = ep_bw->ep_interval; | |
2359 | else | |
2360 | normalized_interval = ep_bw->ep_interval - 3; | |
2361 | ||
2362 | if (normalized_interval == 0) | |
2363 | bw_table->interval0_esit_payload -= ep_bw->max_esit_payload; | |
2364 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2365 | interval_bw->num_packets -= ep_bw->num_packets; | |
2366 | switch (udev->speed) { | |
2367 | case USB_SPEED_LOW: | |
2368 | interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1; | |
2369 | break; | |
2370 | case USB_SPEED_FULL: | |
2371 | interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1; | |
2372 | break; | |
2373 | case USB_SPEED_HIGH: | |
2374 | interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1; | |
2375 | break; | |
2376 | case USB_SPEED_SUPER: | |
2377 | case USB_SPEED_UNKNOWN: | |
2378 | case USB_SPEED_WIRELESS: | |
2379 | /* Should never happen because only LS/FS/HS endpoints will get | |
2380 | * added to the endpoint list. | |
2381 | */ | |
2382 | return; | |
2383 | } | |
2384 | if (tt_info) | |
2385 | tt_info->active_eps -= 1; | |
2386 | list_del_init(&virt_ep->bw_endpoint_list); | |
2387 | } | |
2388 | ||
2389 | static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci, | |
2390 | struct xhci_bw_info *ep_bw, | |
2391 | struct xhci_interval_bw_table *bw_table, | |
2392 | struct usb_device *udev, | |
2393 | struct xhci_virt_ep *virt_ep, | |
2394 | struct xhci_tt_bw_info *tt_info) | |
2395 | { | |
2396 | struct xhci_interval_bw *interval_bw; | |
2397 | struct xhci_virt_ep *smaller_ep; | |
2398 | int normalized_interval; | |
2399 | ||
2400 | if (xhci_is_async_ep(ep_bw->type)) | |
2401 | return; | |
2402 | ||
2b698999 SS |
2403 | if (udev->speed == USB_SPEED_SUPER) { |
2404 | if (xhci_is_sync_in_ep(ep_bw->type)) | |
2405 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in += | |
2406 | xhci_get_ss_bw_consumed(ep_bw); | |
2407 | else | |
2408 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out += | |
2409 | xhci_get_ss_bw_consumed(ep_bw); | |
2410 | return; | |
2411 | } | |
2412 | ||
2e27980e SS |
2413 | /* For LS/FS devices, we need to translate the interval expressed in |
2414 | * microframes to frames. | |
2415 | */ | |
2416 | if (udev->speed == USB_SPEED_HIGH) | |
2417 | normalized_interval = ep_bw->ep_interval; | |
2418 | else | |
2419 | normalized_interval = ep_bw->ep_interval - 3; | |
2420 | ||
2421 | if (normalized_interval == 0) | |
2422 | bw_table->interval0_esit_payload += ep_bw->max_esit_payload; | |
2423 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2424 | interval_bw->num_packets += ep_bw->num_packets; | |
2425 | switch (udev->speed) { | |
2426 | case USB_SPEED_LOW: | |
2427 | interval_bw->overhead[LS_OVERHEAD_TYPE] += 1; | |
2428 | break; | |
2429 | case USB_SPEED_FULL: | |
2430 | interval_bw->overhead[FS_OVERHEAD_TYPE] += 1; | |
2431 | break; | |
2432 | case USB_SPEED_HIGH: | |
2433 | interval_bw->overhead[HS_OVERHEAD_TYPE] += 1; | |
2434 | break; | |
2435 | case USB_SPEED_SUPER: | |
2436 | case USB_SPEED_UNKNOWN: | |
2437 | case USB_SPEED_WIRELESS: | |
2438 | /* Should never happen because only LS/FS/HS endpoints will get | |
2439 | * added to the endpoint list. | |
2440 | */ | |
2441 | return; | |
2442 | } | |
2443 | ||
2444 | if (tt_info) | |
2445 | tt_info->active_eps += 1; | |
2446 | /* Insert the endpoint into the list, largest max packet size first. */ | |
2447 | list_for_each_entry(smaller_ep, &interval_bw->endpoints, | |
2448 | bw_endpoint_list) { | |
2449 | if (ep_bw->max_packet_size >= | |
2450 | smaller_ep->bw_info.max_packet_size) { | |
2451 | /* Add the new ep before the smaller endpoint */ | |
2452 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2453 | &smaller_ep->bw_endpoint_list); | |
2454 | return; | |
2455 | } | |
2456 | } | |
2457 | /* Add the new endpoint at the end of the list. */ | |
2458 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2459 | &interval_bw->endpoints); | |
2460 | } | |
2461 | ||
2462 | void xhci_update_tt_active_eps(struct xhci_hcd *xhci, | |
2463 | struct xhci_virt_device *virt_dev, | |
2464 | int old_active_eps) | |
2465 | { | |
2466 | struct xhci_root_port_bw_info *rh_bw_info; | |
2467 | if (!virt_dev->tt_info) | |
2468 | return; | |
2469 | ||
2470 | rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1]; | |
2471 | if (old_active_eps == 0 && | |
2472 | virt_dev->tt_info->active_eps != 0) { | |
2473 | rh_bw_info->num_active_tts += 1; | |
c29eea62 | 2474 | rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD; |
2e27980e SS |
2475 | } else if (old_active_eps != 0 && |
2476 | virt_dev->tt_info->active_eps == 0) { | |
2477 | rh_bw_info->num_active_tts -= 1; | |
c29eea62 | 2478 | rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD; |
2e27980e SS |
2479 | } |
2480 | } | |
2481 | ||
2482 | static int xhci_reserve_bandwidth(struct xhci_hcd *xhci, | |
2483 | struct xhci_virt_device *virt_dev, | |
2484 | struct xhci_container_ctx *in_ctx) | |
2485 | { | |
2486 | struct xhci_bw_info ep_bw_info[31]; | |
2487 | int i; | |
2488 | struct xhci_input_control_ctx *ctrl_ctx; | |
2489 | int old_active_eps = 0; | |
2490 | ||
2e27980e SS |
2491 | if (virt_dev->tt_info) |
2492 | old_active_eps = virt_dev->tt_info->active_eps; | |
2493 | ||
2494 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
92f8e767 SS |
2495 | if (!ctrl_ctx) { |
2496 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2497 | __func__); | |
2498 | return -ENOMEM; | |
2499 | } | |
2e27980e SS |
2500 | |
2501 | for (i = 0; i < 31; i++) { | |
2502 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2503 | continue; | |
2504 | ||
2505 | /* Make a copy of the BW info in case we need to revert this */ | |
2506 | memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info, | |
2507 | sizeof(ep_bw_info[i])); | |
2508 | /* Drop the endpoint from the interval table if the endpoint is | |
2509 | * being dropped or changed. | |
2510 | */ | |
2511 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2512 | xhci_drop_ep_from_interval_table(xhci, | |
2513 | &virt_dev->eps[i].bw_info, | |
2514 | virt_dev->bw_table, | |
2515 | virt_dev->udev, | |
2516 | &virt_dev->eps[i], | |
2517 | virt_dev->tt_info); | |
2518 | } | |
2519 | /* Overwrite the information stored in the endpoints' bw_info */ | |
2520 | xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev); | |
2521 | for (i = 0; i < 31; i++) { | |
2522 | /* Add any changed or added endpoints to the interval table */ | |
2523 | if (EP_IS_ADDED(ctrl_ctx, i)) | |
2524 | xhci_add_ep_to_interval_table(xhci, | |
2525 | &virt_dev->eps[i].bw_info, | |
2526 | virt_dev->bw_table, | |
2527 | virt_dev->udev, | |
2528 | &virt_dev->eps[i], | |
2529 | virt_dev->tt_info); | |
2530 | } | |
2531 | ||
2532 | if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) { | |
2533 | /* Ok, this fits in the bandwidth we have. | |
2534 | * Update the number of active TTs. | |
2535 | */ | |
2536 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
2537 | return 0; | |
2538 | } | |
2539 | ||
2540 | /* We don't have enough bandwidth for this, revert the stored info. */ | |
2541 | for (i = 0; i < 31; i++) { | |
2542 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2543 | continue; | |
2544 | ||
2545 | /* Drop the new copies of any added or changed endpoints from | |
2546 | * the interval table. | |
2547 | */ | |
2548 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
2549 | xhci_drop_ep_from_interval_table(xhci, | |
2550 | &virt_dev->eps[i].bw_info, | |
2551 | virt_dev->bw_table, | |
2552 | virt_dev->udev, | |
2553 | &virt_dev->eps[i], | |
2554 | virt_dev->tt_info); | |
2555 | } | |
2556 | /* Revert the endpoint back to its old information */ | |
2557 | memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i], | |
2558 | sizeof(ep_bw_info[i])); | |
2559 | /* Add any changed or dropped endpoints back into the table */ | |
2560 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2561 | xhci_add_ep_to_interval_table(xhci, | |
2562 | &virt_dev->eps[i].bw_info, | |
2563 | virt_dev->bw_table, | |
2564 | virt_dev->udev, | |
2565 | &virt_dev->eps[i], | |
2566 | virt_dev->tt_info); | |
2567 | } | |
2568 | return -ENOMEM; | |
2569 | } | |
2570 | ||
2571 | ||
f2217e8e SS |
2572 | /* Issue a configure endpoint command or evaluate context command |
2573 | * and wait for it to finish. | |
2574 | */ | |
2575 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |
913a8a34 SS |
2576 | struct usb_device *udev, |
2577 | struct xhci_command *command, | |
2578 | bool ctx_change, bool must_succeed) | |
f2217e8e SS |
2579 | { |
2580 | int ret; | |
f2217e8e | 2581 | unsigned long flags; |
92f8e767 | 2582 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 2583 | struct xhci_virt_device *virt_dev; |
ddba5cd0 MN |
2584 | |
2585 | if (!command) | |
2586 | return -EINVAL; | |
f2217e8e SS |
2587 | |
2588 | spin_lock_irqsave(&xhci->lock, flags); | |
913a8a34 | 2589 | virt_dev = xhci->devs[udev->slot_id]; |
750645f8 | 2590 | |
ddba5cd0 | 2591 | ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx); |
92f8e767 | 2592 | if (!ctrl_ctx) { |
1f21569c | 2593 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
2594 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
2595 | __func__); | |
2596 | return -ENOMEM; | |
2597 | } | |
2cf95c18 | 2598 | |
750645f8 | 2599 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && |
92f8e767 | 2600 | xhci_reserve_host_resources(xhci, ctrl_ctx)) { |
750645f8 SS |
2601 | spin_unlock_irqrestore(&xhci->lock, flags); |
2602 | xhci_warn(xhci, "Not enough host resources, " | |
2603 | "active endpoint contexts = %u\n", | |
2604 | xhci->num_active_eps); | |
2605 | return -ENOMEM; | |
2606 | } | |
2e27980e | 2607 | if ((xhci->quirks & XHCI_SW_BW_CHECKING) && |
ddba5cd0 | 2608 | xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) { |
2e27980e | 2609 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2610 | xhci_free_host_resources(xhci, ctrl_ctx); |
2e27980e SS |
2611 | spin_unlock_irqrestore(&xhci->lock, flags); |
2612 | xhci_warn(xhci, "Not enough bandwidth\n"); | |
2613 | return -ENOMEM; | |
2614 | } | |
750645f8 | 2615 | |
f2217e8e | 2616 | if (!ctx_change) |
ddba5cd0 MN |
2617 | ret = xhci_queue_configure_endpoint(xhci, command, |
2618 | command->in_ctx->dma, | |
913a8a34 | 2619 | udev->slot_id, must_succeed); |
f2217e8e | 2620 | else |
ddba5cd0 MN |
2621 | ret = xhci_queue_evaluate_context(xhci, command, |
2622 | command->in_ctx->dma, | |
4b266541 | 2623 | udev->slot_id, must_succeed); |
f2217e8e | 2624 | if (ret < 0) { |
2cf95c18 | 2625 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2626 | xhci_free_host_resources(xhci, ctrl_ctx); |
f2217e8e | 2627 | spin_unlock_irqrestore(&xhci->lock, flags); |
3a7fa5be XR |
2628 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
2629 | "FIXME allocate a new ring segment"); | |
f2217e8e SS |
2630 | return -ENOMEM; |
2631 | } | |
2632 | xhci_ring_cmd_db(xhci); | |
2633 | spin_unlock_irqrestore(&xhci->lock, flags); | |
2634 | ||
2635 | /* Wait for the configure endpoint command to complete */ | |
c311e391 | 2636 | wait_for_completion(command->completion); |
f2217e8e SS |
2637 | |
2638 | if (!ctx_change) | |
ddba5cd0 MN |
2639 | ret = xhci_configure_endpoint_result(xhci, udev, |
2640 | &command->status); | |
2cf95c18 | 2641 | else |
ddba5cd0 MN |
2642 | ret = xhci_evaluate_context_result(xhci, udev, |
2643 | &command->status); | |
2cf95c18 SS |
2644 | |
2645 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
2646 | spin_lock_irqsave(&xhci->lock, flags); | |
2647 | /* If the command failed, remove the reserved resources. | |
2648 | * Otherwise, clean up the estimate to include dropped eps. | |
2649 | */ | |
2650 | if (ret) | |
92f8e767 | 2651 | xhci_free_host_resources(xhci, ctrl_ctx); |
2cf95c18 | 2652 | else |
92f8e767 | 2653 | xhci_finish_resource_reservation(xhci, ctrl_ctx); |
2cf95c18 SS |
2654 | spin_unlock_irqrestore(&xhci->lock, flags); |
2655 | } | |
2656 | return ret; | |
f2217e8e SS |
2657 | } |
2658 | ||
df613834 HG |
2659 | static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci, |
2660 | struct xhci_virt_device *vdev, int i) | |
2661 | { | |
2662 | struct xhci_virt_ep *ep = &vdev->eps[i]; | |
2663 | ||
2664 | if (ep->ep_state & EP_HAS_STREAMS) { | |
2665 | xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n", | |
2666 | xhci_get_endpoint_address(i)); | |
2667 | xhci_free_stream_info(xhci, ep->stream_info); | |
2668 | ep->stream_info = NULL; | |
2669 | ep->ep_state &= ~EP_HAS_STREAMS; | |
2670 | } | |
2671 | } | |
2672 | ||
f88ba78d SS |
2673 | /* Called after one or more calls to xhci_add_endpoint() or |
2674 | * xhci_drop_endpoint(). If this call fails, the USB core is expected | |
2675 | * to call xhci_reset_bandwidth(). | |
2676 | * | |
2677 | * Since we are in the middle of changing either configuration or | |
2678 | * installing a new alt setting, the USB core won't allow URBs to be | |
2679 | * enqueued for any endpoint on the old config or interface. Nothing | |
2680 | * else should be touching the xhci->devs[slot_id] structure, so we | |
2681 | * don't need to take the xhci->lock for manipulating that. | |
2682 | */ | |
f94e0186 SS |
2683 | int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) |
2684 | { | |
2685 | int i; | |
2686 | int ret = 0; | |
f94e0186 SS |
2687 | struct xhci_hcd *xhci; |
2688 | struct xhci_virt_device *virt_dev; | |
d115b048 JY |
2689 | struct xhci_input_control_ctx *ctrl_ctx; |
2690 | struct xhci_slot_ctx *slot_ctx; | |
ddba5cd0 | 2691 | struct xhci_command *command; |
f94e0186 | 2692 | |
64927730 | 2693 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2694 | if (ret <= 0) |
2695 | return ret; | |
2696 | xhci = hcd_to_xhci(hcd); | |
fe6c6c13 SS |
2697 | if (xhci->xhc_state & XHCI_STATE_DYING) |
2698 | return -ENODEV; | |
f94e0186 | 2699 | |
700e2052 | 2700 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2701 | virt_dev = xhci->devs[udev->slot_id]; |
2702 | ||
ddba5cd0 MN |
2703 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); |
2704 | if (!command) | |
2705 | return -ENOMEM; | |
2706 | ||
2707 | command->in_ctx = virt_dev->in_ctx; | |
2708 | ||
f94e0186 | 2709 | /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */ |
ddba5cd0 | 2710 | ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx); |
92f8e767 SS |
2711 | if (!ctrl_ctx) { |
2712 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2713 | __func__); | |
ddba5cd0 MN |
2714 | ret = -ENOMEM; |
2715 | goto command_cleanup; | |
92f8e767 | 2716 | } |
28ccd296 ME |
2717 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
2718 | ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG); | |
2719 | ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG)); | |
2dc37539 SS |
2720 | |
2721 | /* Don't issue the command if there's no endpoints to update. */ | |
2722 | if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) && | |
ddba5cd0 MN |
2723 | ctrl_ctx->drop_flags == 0) { |
2724 | ret = 0; | |
2725 | goto command_cleanup; | |
2726 | } | |
d6759133 | 2727 | /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */ |
d115b048 | 2728 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
d6759133 JW |
2729 | for (i = 31; i >= 1; i--) { |
2730 | __le32 le32 = cpu_to_le32(BIT(i)); | |
2731 | ||
2732 | if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32)) | |
2733 | || (ctrl_ctx->add_flags & le32) || i == 1) { | |
2734 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
2735 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i)); | |
2736 | break; | |
2737 | } | |
2738 | } | |
2739 | xhci_dbg(xhci, "New Input Control Context:\n"); | |
d115b048 | 2740 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, |
28ccd296 | 2741 | LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); |
f94e0186 | 2742 | |
ddba5cd0 | 2743 | ret = xhci_configure_endpoint(xhci, udev, command, |
913a8a34 | 2744 | false, false); |
ddba5cd0 | 2745 | if (ret) |
f94e0186 | 2746 | /* Callee should call reset_bandwidth() */ |
ddba5cd0 | 2747 | goto command_cleanup; |
f94e0186 SS |
2748 | |
2749 | xhci_dbg(xhci, "Output context after successful config ep cmd:\n"); | |
d115b048 | 2750 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, |
28ccd296 | 2751 | LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info))); |
f94e0186 | 2752 | |
834cb0fc SS |
2753 | /* Free any rings that were dropped, but not changed. */ |
2754 | for (i = 1; i < 31; ++i) { | |
4819fef5 | 2755 | if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) && |
df613834 | 2756 | !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) { |
834cb0fc | 2757 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); |
df613834 HG |
2758 | xhci_check_bw_drop_ep_streams(xhci, virt_dev, i); |
2759 | } | |
834cb0fc | 2760 | } |
d115b048 | 2761 | xhci_zero_in_ctx(xhci, virt_dev); |
834cb0fc SS |
2762 | /* |
2763 | * Install any rings for completely new endpoints or changed endpoints, | |
2764 | * and free or cache any old rings from changed endpoints. | |
2765 | */ | |
f94e0186 | 2766 | for (i = 1; i < 31; ++i) { |
74f9fe21 SS |
2767 | if (!virt_dev->eps[i].new_ring) |
2768 | continue; | |
2769 | /* Only cache or free the old ring if it exists. | |
2770 | * It may not if this is the first add of an endpoint. | |
2771 | */ | |
2772 | if (virt_dev->eps[i].ring) { | |
412566bd | 2773 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); |
f94e0186 | 2774 | } |
df613834 | 2775 | xhci_check_bw_drop_ep_streams(xhci, virt_dev, i); |
74f9fe21 SS |
2776 | virt_dev->eps[i].ring = virt_dev->eps[i].new_ring; |
2777 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 | 2778 | } |
ddba5cd0 MN |
2779 | command_cleanup: |
2780 | kfree(command->completion); | |
2781 | kfree(command); | |
f94e0186 | 2782 | |
f94e0186 SS |
2783 | return ret; |
2784 | } | |
2785 | ||
2786 | void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) | |
2787 | { | |
f94e0186 SS |
2788 | struct xhci_hcd *xhci; |
2789 | struct xhci_virt_device *virt_dev; | |
2790 | int i, ret; | |
2791 | ||
64927730 | 2792 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2793 | if (ret <= 0) |
2794 | return; | |
2795 | xhci = hcd_to_xhci(hcd); | |
2796 | ||
700e2052 | 2797 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2798 | virt_dev = xhci->devs[udev->slot_id]; |
2799 | /* Free any rings allocated for added endpoints */ | |
2800 | for (i = 0; i < 31; ++i) { | |
63a0d9ab SS |
2801 | if (virt_dev->eps[i].new_ring) { |
2802 | xhci_ring_free(xhci, virt_dev->eps[i].new_ring); | |
2803 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 SS |
2804 | } |
2805 | } | |
d115b048 | 2806 | xhci_zero_in_ctx(xhci, virt_dev); |
f94e0186 SS |
2807 | } |
2808 | ||
5270b951 | 2809 | static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci, |
913a8a34 SS |
2810 | struct xhci_container_ctx *in_ctx, |
2811 | struct xhci_container_ctx *out_ctx, | |
92f8e767 | 2812 | struct xhci_input_control_ctx *ctrl_ctx, |
913a8a34 | 2813 | u32 add_flags, u32 drop_flags) |
5270b951 | 2814 | { |
28ccd296 ME |
2815 | ctrl_ctx->add_flags = cpu_to_le32(add_flags); |
2816 | ctrl_ctx->drop_flags = cpu_to_le32(drop_flags); | |
913a8a34 | 2817 | xhci_slot_copy(xhci, in_ctx, out_ctx); |
28ccd296 | 2818 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
5270b951 | 2819 | |
913a8a34 SS |
2820 | xhci_dbg(xhci, "Input Context:\n"); |
2821 | xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags)); | |
5270b951 SS |
2822 | } |
2823 | ||
8212a49d | 2824 | static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, |
ac9d8fe7 SS |
2825 | unsigned int slot_id, unsigned int ep_index, |
2826 | struct xhci_dequeue_state *deq_state) | |
2827 | { | |
92f8e767 | 2828 | struct xhci_input_control_ctx *ctrl_ctx; |
ac9d8fe7 | 2829 | struct xhci_container_ctx *in_ctx; |
ac9d8fe7 SS |
2830 | struct xhci_ep_ctx *ep_ctx; |
2831 | u32 added_ctxs; | |
2832 | dma_addr_t addr; | |
2833 | ||
92f8e767 SS |
2834 | in_ctx = xhci->devs[slot_id]->in_ctx; |
2835 | ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx); | |
2836 | if (!ctrl_ctx) { | |
2837 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2838 | __func__); | |
2839 | return; | |
2840 | } | |
2841 | ||
913a8a34 SS |
2842 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
2843 | xhci->devs[slot_id]->out_ctx, ep_index); | |
ac9d8fe7 SS |
2844 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); |
2845 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
2846 | deq_state->new_deq_ptr); | |
2847 | if (addr == 0) { | |
2848 | xhci_warn(xhci, "WARN Cannot submit config ep after " | |
2849 | "reset ep command\n"); | |
2850 | xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n", | |
2851 | deq_state->new_deq_seg, | |
2852 | deq_state->new_deq_ptr); | |
2853 | return; | |
2854 | } | |
28ccd296 | 2855 | ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state); |
ac9d8fe7 | 2856 | |
ac9d8fe7 | 2857 | added_ctxs = xhci_get_endpoint_flag_from_index(ep_index); |
913a8a34 | 2858 | xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx, |
92f8e767 SS |
2859 | xhci->devs[slot_id]->out_ctx, ctrl_ctx, |
2860 | added_ctxs, added_ctxs); | |
ac9d8fe7 SS |
2861 | } |
2862 | ||
82d1009f | 2863 | void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, |
63a0d9ab | 2864 | struct usb_device *udev, unsigned int ep_index) |
82d1009f SS |
2865 | { |
2866 | struct xhci_dequeue_state deq_state; | |
63a0d9ab | 2867 | struct xhci_virt_ep *ep; |
82d1009f | 2868 | |
a0254324 XR |
2869 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2870 | "Cleaning up stalled endpoint ring"); | |
63a0d9ab | 2871 | ep = &xhci->devs[udev->slot_id]->eps[ep_index]; |
82d1009f SS |
2872 | /* We need to move the HW's dequeue pointer past this TD, |
2873 | * or it will attempt to resend it on the next doorbell ring. | |
2874 | */ | |
2875 | xhci_find_new_dequeue_state(xhci, udev->slot_id, | |
e9df17eb | 2876 | ep_index, ep->stopped_stream, ep->stopped_td, |
ac9d8fe7 | 2877 | &deq_state); |
82d1009f | 2878 | |
ac9d8fe7 SS |
2879 | /* HW with the reset endpoint quirk will use the saved dequeue state to |
2880 | * issue a configure endpoint command later. | |
2881 | */ | |
2882 | if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) { | |
ddba5cd0 MN |
2883 | struct xhci_command *command; |
2884 | /* Can't sleep if we're called from cleanup_halted_endpoint() */ | |
2885 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
2886 | if (!command) | |
2887 | return; | |
a0254324 XR |
2888 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2889 | "Queueing new dequeue state"); | |
ddba5cd0 | 2890 | xhci_queue_new_dequeue_state(xhci, command, udev->slot_id, |
e9df17eb | 2891 | ep_index, ep->stopped_stream, &deq_state); |
ac9d8fe7 SS |
2892 | } else { |
2893 | /* Better hope no one uses the input context between now and the | |
2894 | * reset endpoint completion! | |
e9df17eb SS |
2895 | * XXX: No idea how this hardware will react when stream rings |
2896 | * are enabled. | |
ac9d8fe7 | 2897 | */ |
4bdfe4c3 XR |
2898 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2899 | "Setting up input context for " | |
2900 | "configure endpoint command"); | |
ac9d8fe7 SS |
2901 | xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id, |
2902 | ep_index, &deq_state); | |
2903 | } | |
82d1009f SS |
2904 | } |
2905 | ||
a1587d97 SS |
2906 | /* Deal with stalled endpoints. The core should have sent the control message |
2907 | * to clear the halt condition. However, we need to make the xHCI hardware | |
2908 | * reset its sequence number, since a device will expect a sequence number of | |
2909 | * zero after the halt condition is cleared. | |
2910 | * Context: in_interrupt | |
2911 | */ | |
2912 | void xhci_endpoint_reset(struct usb_hcd *hcd, | |
2913 | struct usb_host_endpoint *ep) | |
2914 | { | |
2915 | struct xhci_hcd *xhci; | |
2916 | struct usb_device *udev; | |
2917 | unsigned int ep_index; | |
2918 | unsigned long flags; | |
2919 | int ret; | |
63a0d9ab | 2920 | struct xhci_virt_ep *virt_ep; |
ddba5cd0 | 2921 | struct xhci_command *command; |
a1587d97 SS |
2922 | |
2923 | xhci = hcd_to_xhci(hcd); | |
2924 | udev = (struct usb_device *) ep->hcpriv; | |
2925 | /* Called with a root hub endpoint (or an endpoint that wasn't added | |
2926 | * with xhci_add_endpoint() | |
2927 | */ | |
2928 | if (!ep->hcpriv) | |
2929 | return; | |
2930 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
63a0d9ab SS |
2931 | virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index]; |
2932 | if (!virt_ep->stopped_td) { | |
a0254324 XR |
2933 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2934 | "Endpoint 0x%x not halted, refusing to reset.", | |
2935 | ep->desc.bEndpointAddress); | |
c92bcfa7 SS |
2936 | return; |
2937 | } | |
82d1009f | 2938 | if (usb_endpoint_xfer_control(&ep->desc)) { |
a0254324 XR |
2939 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2940 | "Control endpoint stall already handled."); | |
82d1009f SS |
2941 | return; |
2942 | } | |
a1587d97 | 2943 | |
ddba5cd0 MN |
2944 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); |
2945 | if (!command) | |
2946 | return; | |
2947 | ||
a0254324 XR |
2948 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2949 | "Queueing reset endpoint command"); | |
a1587d97 | 2950 | spin_lock_irqsave(&xhci->lock, flags); |
ddba5cd0 | 2951 | ret = xhci_queue_reset_ep(xhci, command, udev->slot_id, ep_index); |
c92bcfa7 SS |
2952 | /* |
2953 | * Can't change the ring dequeue pointer until it's transitioned to the | |
2954 | * stopped state, which is only upon a successful reset endpoint | |
2955 | * command. Better hope that last command worked! | |
2956 | */ | |
a1587d97 | 2957 | if (!ret) { |
63a0d9ab SS |
2958 | xhci_cleanup_stalled_ring(xhci, udev, ep_index); |
2959 | kfree(virt_ep->stopped_td); | |
a1587d97 SS |
2960 | xhci_ring_cmd_db(xhci); |
2961 | } | |
1624ae1c | 2962 | virt_ep->stopped_td = NULL; |
5e5cf6fc | 2963 | virt_ep->stopped_stream = 0; |
a1587d97 SS |
2964 | spin_unlock_irqrestore(&xhci->lock, flags); |
2965 | ||
2966 | if (ret) | |
2967 | xhci_warn(xhci, "FIXME allocate a new ring segment\n"); | |
2968 | } | |
2969 | ||
8df75f42 SS |
2970 | static int xhci_check_streams_endpoint(struct xhci_hcd *xhci, |
2971 | struct usb_device *udev, struct usb_host_endpoint *ep, | |
2972 | unsigned int slot_id) | |
2973 | { | |
2974 | int ret; | |
2975 | unsigned int ep_index; | |
2976 | unsigned int ep_state; | |
2977 | ||
2978 | if (!ep) | |
2979 | return -EINVAL; | |
64927730 | 2980 | ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__); |
8df75f42 SS |
2981 | if (ret <= 0) |
2982 | return -EINVAL; | |
a3901538 | 2983 | if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) { |
8df75f42 SS |
2984 | xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion" |
2985 | " descriptor for ep 0x%x does not support streams\n", | |
2986 | ep->desc.bEndpointAddress); | |
2987 | return -EINVAL; | |
2988 | } | |
2989 | ||
2990 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
2991 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
2992 | if (ep_state & EP_HAS_STREAMS || | |
2993 | ep_state & EP_GETTING_STREAMS) { | |
2994 | xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x " | |
2995 | "already has streams set up.\n", | |
2996 | ep->desc.bEndpointAddress); | |
2997 | xhci_warn(xhci, "Send email to xHCI maintainer and ask for " | |
2998 | "dynamic stream context array reallocation.\n"); | |
2999 | return -EINVAL; | |
3000 | } | |
3001 | if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) { | |
3002 | xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk " | |
3003 | "endpoint 0x%x; URBs are pending.\n", | |
3004 | ep->desc.bEndpointAddress); | |
3005 | return -EINVAL; | |
3006 | } | |
3007 | return 0; | |
3008 | } | |
3009 | ||
3010 | static void xhci_calculate_streams_entries(struct xhci_hcd *xhci, | |
3011 | unsigned int *num_streams, unsigned int *num_stream_ctxs) | |
3012 | { | |
3013 | unsigned int max_streams; | |
3014 | ||
3015 | /* The stream context array size must be a power of two */ | |
3016 | *num_stream_ctxs = roundup_pow_of_two(*num_streams); | |
3017 | /* | |
3018 | * Find out how many primary stream array entries the host controller | |
3019 | * supports. Later we may use secondary stream arrays (similar to 2nd | |
3020 | * level page entries), but that's an optional feature for xHCI host | |
3021 | * controllers. xHCs must support at least 4 stream IDs. | |
3022 | */ | |
3023 | max_streams = HCC_MAX_PSA(xhci->hcc_params); | |
3024 | if (*num_stream_ctxs > max_streams) { | |
3025 | xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n", | |
3026 | max_streams); | |
3027 | *num_stream_ctxs = max_streams; | |
3028 | *num_streams = max_streams; | |
3029 | } | |
3030 | } | |
3031 | ||
3032 | /* Returns an error code if one of the endpoint already has streams. | |
3033 | * This does not change any data structures, it only checks and gathers | |
3034 | * information. | |
3035 | */ | |
3036 | static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci, | |
3037 | struct usb_device *udev, | |
3038 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3039 | unsigned int *num_streams, u32 *changed_ep_bitmask) | |
3040 | { | |
8df75f42 SS |
3041 | unsigned int max_streams; |
3042 | unsigned int endpoint_flag; | |
3043 | int i; | |
3044 | int ret; | |
3045 | ||
3046 | for (i = 0; i < num_eps; i++) { | |
3047 | ret = xhci_check_streams_endpoint(xhci, udev, | |
3048 | eps[i], udev->slot_id); | |
3049 | if (ret < 0) | |
3050 | return ret; | |
3051 | ||
18b7ede5 | 3052 | max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp); |
8df75f42 SS |
3053 | if (max_streams < (*num_streams - 1)) { |
3054 | xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n", | |
3055 | eps[i]->desc.bEndpointAddress, | |
3056 | max_streams); | |
3057 | *num_streams = max_streams+1; | |
3058 | } | |
3059 | ||
3060 | endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc); | |
3061 | if (*changed_ep_bitmask & endpoint_flag) | |
3062 | return -EINVAL; | |
3063 | *changed_ep_bitmask |= endpoint_flag; | |
3064 | } | |
3065 | return 0; | |
3066 | } | |
3067 | ||
3068 | static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci, | |
3069 | struct usb_device *udev, | |
3070 | struct usb_host_endpoint **eps, unsigned int num_eps) | |
3071 | { | |
3072 | u32 changed_ep_bitmask = 0; | |
3073 | unsigned int slot_id; | |
3074 | unsigned int ep_index; | |
3075 | unsigned int ep_state; | |
3076 | int i; | |
3077 | ||
3078 | slot_id = udev->slot_id; | |
3079 | if (!xhci->devs[slot_id]) | |
3080 | return 0; | |
3081 | ||
3082 | for (i = 0; i < num_eps; i++) { | |
3083 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3084 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
3085 | /* Are streams already being freed for the endpoint? */ | |
3086 | if (ep_state & EP_GETTING_NO_STREAMS) { | |
3087 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3088 | "endpoint 0x%x, " |
3089 | "streams are being disabled already\n", | |
8df75f42 SS |
3090 | eps[i]->desc.bEndpointAddress); |
3091 | return 0; | |
3092 | } | |
3093 | /* Are there actually any streams to free? */ | |
3094 | if (!(ep_state & EP_HAS_STREAMS) && | |
3095 | !(ep_state & EP_GETTING_STREAMS)) { | |
3096 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3097 | "endpoint 0x%x, " |
3098 | "streams are already disabled!\n", | |
8df75f42 SS |
3099 | eps[i]->desc.bEndpointAddress); |
3100 | xhci_warn(xhci, "WARN xhci_free_streams() called " | |
3101 | "with non-streams endpoint\n"); | |
3102 | return 0; | |
3103 | } | |
3104 | changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc); | |
3105 | } | |
3106 | return changed_ep_bitmask; | |
3107 | } | |
3108 | ||
3109 | /* | |
3110 | * The USB device drivers use this function (though the HCD interface in USB | |
3111 | * core) to prepare a set of bulk endpoints to use streams. Streams are used to | |
3112 | * coordinate mass storage command queueing across multiple endpoints (basically | |
3113 | * a stream ID == a task ID). | |
3114 | * | |
3115 | * Setting up streams involves allocating the same size stream context array | |
3116 | * for each endpoint and issuing a configure endpoint command for all endpoints. | |
3117 | * | |
3118 | * Don't allow the call to succeed if one endpoint only supports one stream | |
3119 | * (which means it doesn't support streams at all). | |
3120 | * | |
3121 | * Drivers may get less stream IDs than they asked for, if the host controller | |
3122 | * hardware or endpoints claim they can't support the number of requested | |
3123 | * stream IDs. | |
3124 | */ | |
3125 | int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, | |
3126 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3127 | unsigned int num_streams, gfp_t mem_flags) | |
3128 | { | |
3129 | int i, ret; | |
3130 | struct xhci_hcd *xhci; | |
3131 | struct xhci_virt_device *vdev; | |
3132 | struct xhci_command *config_cmd; | |
92f8e767 | 3133 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3134 | unsigned int ep_index; |
3135 | unsigned int num_stream_ctxs; | |
3136 | unsigned long flags; | |
3137 | u32 changed_ep_bitmask = 0; | |
3138 | ||
3139 | if (!eps) | |
3140 | return -EINVAL; | |
3141 | ||
3142 | /* Add one to the number of streams requested to account for | |
3143 | * stream 0 that is reserved for xHCI usage. | |
3144 | */ | |
3145 | num_streams += 1; | |
3146 | xhci = hcd_to_xhci(hcd); | |
3147 | xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n", | |
3148 | num_streams); | |
3149 | ||
f7920884 | 3150 | /* MaxPSASize value 0 (2 streams) means streams are not supported */ |
8f873c1f HG |
3151 | if ((xhci->quirks & XHCI_BROKEN_STREAMS) || |
3152 | HCC_MAX_PSA(xhci->hcc_params) < 4) { | |
f7920884 HG |
3153 | xhci_dbg(xhci, "xHCI controller does not support streams.\n"); |
3154 | return -ENOSYS; | |
3155 | } | |
3156 | ||
8df75f42 SS |
3157 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); |
3158 | if (!config_cmd) { | |
3159 | xhci_dbg(xhci, "Could not allocate xHCI command structure.\n"); | |
3160 | return -ENOMEM; | |
3161 | } | |
92f8e767 SS |
3162 | ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx); |
3163 | if (!ctrl_ctx) { | |
3164 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3165 | __func__); | |
3166 | xhci_free_command(xhci, config_cmd); | |
3167 | return -ENOMEM; | |
3168 | } | |
8df75f42 SS |
3169 | |
3170 | /* Check to make sure all endpoints are not already configured for | |
3171 | * streams. While we're at it, find the maximum number of streams that | |
3172 | * all the endpoints will support and check for duplicate endpoints. | |
3173 | */ | |
3174 | spin_lock_irqsave(&xhci->lock, flags); | |
3175 | ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps, | |
3176 | num_eps, &num_streams, &changed_ep_bitmask); | |
3177 | if (ret < 0) { | |
3178 | xhci_free_command(xhci, config_cmd); | |
3179 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3180 | return ret; | |
3181 | } | |
3182 | if (num_streams <= 1) { | |
3183 | xhci_warn(xhci, "WARN: endpoints can't handle " | |
3184 | "more than one stream.\n"); | |
3185 | xhci_free_command(xhci, config_cmd); | |
3186 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3187 | return -EINVAL; | |
3188 | } | |
3189 | vdev = xhci->devs[udev->slot_id]; | |
25985edc | 3190 | /* Mark each endpoint as being in transition, so |
8df75f42 SS |
3191 | * xhci_urb_enqueue() will reject all URBs. |
3192 | */ | |
3193 | for (i = 0; i < num_eps; i++) { | |
3194 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3195 | vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS; | |
3196 | } | |
3197 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3198 | ||
3199 | /* Setup internal data structures and allocate HW data structures for | |
3200 | * streams (but don't install the HW structures in the input context | |
3201 | * until we're sure all memory allocation succeeded). | |
3202 | */ | |
3203 | xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs); | |
3204 | xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n", | |
3205 | num_stream_ctxs, num_streams); | |
3206 | ||
3207 | for (i = 0; i < num_eps; i++) { | |
3208 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3209 | vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci, | |
3210 | num_stream_ctxs, | |
3211 | num_streams, mem_flags); | |
3212 | if (!vdev->eps[ep_index].stream_info) | |
3213 | goto cleanup; | |
3214 | /* Set maxPstreams in endpoint context and update deq ptr to | |
3215 | * point to stream context array. FIXME | |
3216 | */ | |
3217 | } | |
3218 | ||
3219 | /* Set up the input context for a configure endpoint command. */ | |
3220 | for (i = 0; i < num_eps; i++) { | |
3221 | struct xhci_ep_ctx *ep_ctx; | |
3222 | ||
3223 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3224 | ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index); | |
3225 | ||
3226 | xhci_endpoint_copy(xhci, config_cmd->in_ctx, | |
3227 | vdev->out_ctx, ep_index); | |
3228 | xhci_setup_streams_ep_input_ctx(xhci, ep_ctx, | |
3229 | vdev->eps[ep_index].stream_info); | |
3230 | } | |
3231 | /* Tell the HW to drop its old copy of the endpoint context info | |
3232 | * and add the updated copy from the input context. | |
3233 | */ | |
3234 | xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx, | |
92f8e767 SS |
3235 | vdev->out_ctx, ctrl_ctx, |
3236 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3237 | |
3238 | /* Issue and wait for the configure endpoint command */ | |
3239 | ret = xhci_configure_endpoint(xhci, udev, config_cmd, | |
3240 | false, false); | |
3241 | ||
3242 | /* xHC rejected the configure endpoint command for some reason, so we | |
3243 | * leave the old ring intact and free our internal streams data | |
3244 | * structure. | |
3245 | */ | |
3246 | if (ret < 0) | |
3247 | goto cleanup; | |
3248 | ||
3249 | spin_lock_irqsave(&xhci->lock, flags); | |
3250 | for (i = 0; i < num_eps; i++) { | |
3251 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3252 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3253 | xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n", | |
3254 | udev->slot_id, ep_index); | |
3255 | vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS; | |
3256 | } | |
3257 | xhci_free_command(xhci, config_cmd); | |
3258 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3259 | ||
3260 | /* Subtract 1 for stream 0, which drivers can't use */ | |
3261 | return num_streams - 1; | |
3262 | ||
3263 | cleanup: | |
3264 | /* If it didn't work, free the streams! */ | |
3265 | for (i = 0; i < num_eps; i++) { | |
3266 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3267 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3268 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3269 | /* FIXME Unset maxPstreams in endpoint context and |
3270 | * update deq ptr to point to normal string ring. | |
3271 | */ | |
3272 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3273 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3274 | xhci_endpoint_zero(xhci, vdev, eps[i]); | |
3275 | } | |
3276 | xhci_free_command(xhci, config_cmd); | |
3277 | return -ENOMEM; | |
3278 | } | |
3279 | ||
3280 | /* Transition the endpoint from using streams to being a "normal" endpoint | |
3281 | * without streams. | |
3282 | * | |
3283 | * Modify the endpoint context state, submit a configure endpoint command, | |
3284 | * and free all endpoint rings for streams if that completes successfully. | |
3285 | */ | |
3286 | int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, | |
3287 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3288 | gfp_t mem_flags) | |
3289 | { | |
3290 | int i, ret; | |
3291 | struct xhci_hcd *xhci; | |
3292 | struct xhci_virt_device *vdev; | |
3293 | struct xhci_command *command; | |
92f8e767 | 3294 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3295 | unsigned int ep_index; |
3296 | unsigned long flags; | |
3297 | u32 changed_ep_bitmask; | |
3298 | ||
3299 | xhci = hcd_to_xhci(hcd); | |
3300 | vdev = xhci->devs[udev->slot_id]; | |
3301 | ||
3302 | /* Set up a configure endpoint command to remove the streams rings */ | |
3303 | spin_lock_irqsave(&xhci->lock, flags); | |
3304 | changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci, | |
3305 | udev, eps, num_eps); | |
3306 | if (changed_ep_bitmask == 0) { | |
3307 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3308 | return -EINVAL; | |
3309 | } | |
3310 | ||
3311 | /* Use the xhci_command structure from the first endpoint. We may have | |
3312 | * allocated too many, but the driver may call xhci_free_streams() for | |
3313 | * each endpoint it grouped into one call to xhci_alloc_streams(). | |
3314 | */ | |
3315 | ep_index = xhci_get_endpoint_index(&eps[0]->desc); | |
3316 | command = vdev->eps[ep_index].stream_info->free_streams_command; | |
92f8e767 SS |
3317 | ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx); |
3318 | if (!ctrl_ctx) { | |
1f21569c | 3319 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
3320 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
3321 | __func__); | |
3322 | return -EINVAL; | |
3323 | } | |
3324 | ||
8df75f42 SS |
3325 | for (i = 0; i < num_eps; i++) { |
3326 | struct xhci_ep_ctx *ep_ctx; | |
3327 | ||
3328 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3329 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); | |
3330 | xhci->devs[udev->slot_id]->eps[ep_index].ep_state |= | |
3331 | EP_GETTING_NO_STREAMS; | |
3332 | ||
3333 | xhci_endpoint_copy(xhci, command->in_ctx, | |
3334 | vdev->out_ctx, ep_index); | |
3335 | xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx, | |
3336 | &vdev->eps[ep_index]); | |
3337 | } | |
3338 | xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx, | |
92f8e767 SS |
3339 | vdev->out_ctx, ctrl_ctx, |
3340 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3341 | spin_unlock_irqrestore(&xhci->lock, flags); |
3342 | ||
3343 | /* Issue and wait for the configure endpoint command, | |
3344 | * which must succeed. | |
3345 | */ | |
3346 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3347 | false, true); | |
3348 | ||
3349 | /* xHC rejected the configure endpoint command for some reason, so we | |
3350 | * leave the streams rings intact. | |
3351 | */ | |
3352 | if (ret < 0) | |
3353 | return ret; | |
3354 | ||
3355 | spin_lock_irqsave(&xhci->lock, flags); | |
3356 | for (i = 0; i < num_eps; i++) { | |
3357 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3358 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3359 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3360 | /* FIXME Unset maxPstreams in endpoint context and |
3361 | * update deq ptr to point to normal string ring. | |
3362 | */ | |
3363 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS; | |
3364 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3365 | } | |
3366 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3367 | ||
3368 | return 0; | |
3369 | } | |
3370 | ||
2cf95c18 SS |
3371 | /* |
3372 | * Deletes endpoint resources for endpoints that were active before a Reset | |
3373 | * Device command, or a Disable Slot command. The Reset Device command leaves | |
3374 | * the control endpoint intact, whereas the Disable Slot command deletes it. | |
3375 | * | |
3376 | * Must be called with xhci->lock held. | |
3377 | */ | |
3378 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, | |
3379 | struct xhci_virt_device *virt_dev, bool drop_control_ep) | |
3380 | { | |
3381 | int i; | |
3382 | unsigned int num_dropped_eps = 0; | |
3383 | unsigned int drop_flags = 0; | |
3384 | ||
3385 | for (i = (drop_control_ep ? 0 : 1); i < 31; i++) { | |
3386 | if (virt_dev->eps[i].ring) { | |
3387 | drop_flags |= 1 << i; | |
3388 | num_dropped_eps++; | |
3389 | } | |
3390 | } | |
3391 | xhci->num_active_eps -= num_dropped_eps; | |
3392 | if (num_dropped_eps) | |
4bdfe4c3 XR |
3393 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3394 | "Dropped %u ep ctxs, flags = 0x%x, " | |
3395 | "%u now active.", | |
2cf95c18 SS |
3396 | num_dropped_eps, drop_flags, |
3397 | xhci->num_active_eps); | |
3398 | } | |
3399 | ||
2a8f82c4 SS |
3400 | /* |
3401 | * This submits a Reset Device Command, which will set the device state to 0, | |
3402 | * set the device address to 0, and disable all the endpoints except the default | |
3403 | * control endpoint. The USB core should come back and call | |
3404 | * xhci_address_device(), and then re-set up the configuration. If this is | |
3405 | * called because of a usb_reset_and_verify_device(), then the old alternate | |
3406 | * settings will be re-installed through the normal bandwidth allocation | |
3407 | * functions. | |
3408 | * | |
3409 | * Wait for the Reset Device command to finish. Remove all structures | |
3410 | * associated with the endpoints that were disabled. Clear the input device | |
3411 | * structure? Cache the rings? Reset the control endpoint 0 max packet size? | |
f0615c45 AX |
3412 | * |
3413 | * If the virt_dev to be reset does not exist or does not match the udev, | |
3414 | * it means the device is lost, possibly due to the xHC restore error and | |
3415 | * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to | |
3416 | * re-allocate the device. | |
2a8f82c4 | 3417 | */ |
f0615c45 | 3418 | int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev) |
2a8f82c4 SS |
3419 | { |
3420 | int ret, i; | |
3421 | unsigned long flags; | |
3422 | struct xhci_hcd *xhci; | |
3423 | unsigned int slot_id; | |
3424 | struct xhci_virt_device *virt_dev; | |
3425 | struct xhci_command *reset_device_cmd; | |
2a8f82c4 | 3426 | int last_freed_endpoint; |
001fd382 | 3427 | struct xhci_slot_ctx *slot_ctx; |
2e27980e | 3428 | int old_active_eps = 0; |
2a8f82c4 | 3429 | |
f0615c45 | 3430 | ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__); |
2a8f82c4 SS |
3431 | if (ret <= 0) |
3432 | return ret; | |
3433 | xhci = hcd_to_xhci(hcd); | |
3434 | slot_id = udev->slot_id; | |
3435 | virt_dev = xhci->devs[slot_id]; | |
f0615c45 AX |
3436 | if (!virt_dev) { |
3437 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3438 | "not exist. Re-allocate the device\n", slot_id); | |
3439 | ret = xhci_alloc_dev(hcd, udev); | |
3440 | if (ret == 1) | |
3441 | return 0; | |
3442 | else | |
3443 | return -EINVAL; | |
3444 | } | |
3445 | ||
3446 | if (virt_dev->udev != udev) { | |
3447 | /* If the virt_dev and the udev does not match, this virt_dev | |
3448 | * may belong to another udev. | |
3449 | * Re-allocate the device. | |
3450 | */ | |
3451 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3452 | "not match the udev. Re-allocate the device\n", | |
3453 | slot_id); | |
3454 | ret = xhci_alloc_dev(hcd, udev); | |
3455 | if (ret == 1) | |
3456 | return 0; | |
3457 | else | |
3458 | return -EINVAL; | |
3459 | } | |
2a8f82c4 | 3460 | |
001fd382 ML |
3461 | /* If device is not setup, there is no point in resetting it */ |
3462 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
3463 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == | |
3464 | SLOT_STATE_DISABLED) | |
3465 | return 0; | |
3466 | ||
2a8f82c4 SS |
3467 | xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id); |
3468 | /* Allocate the command structure that holds the struct completion. | |
3469 | * Assume we're in process context, since the normal device reset | |
3470 | * process has to wait for the device anyway. Storage devices are | |
3471 | * reset as part of error handling, so use GFP_NOIO instead of | |
3472 | * GFP_KERNEL. | |
3473 | */ | |
3474 | reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); | |
3475 | if (!reset_device_cmd) { | |
3476 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | |
3477 | return -ENOMEM; | |
3478 | } | |
3479 | ||
3480 | /* Attempt to submit the Reset Device command to the command ring */ | |
3481 | spin_lock_irqsave(&xhci->lock, flags); | |
7a3783ef | 3482 | |
ddba5cd0 | 3483 | ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id); |
2a8f82c4 SS |
3484 | if (ret) { |
3485 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
2a8f82c4 SS |
3486 | spin_unlock_irqrestore(&xhci->lock, flags); |
3487 | goto command_cleanup; | |
3488 | } | |
3489 | xhci_ring_cmd_db(xhci); | |
3490 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3491 | ||
3492 | /* Wait for the Reset Device command to finish */ | |
c311e391 | 3493 | wait_for_completion(reset_device_cmd->completion); |
2a8f82c4 SS |
3494 | |
3495 | /* The Reset Device command can't fail, according to the 0.95/0.96 spec, | |
3496 | * unless we tried to reset a slot ID that wasn't enabled, | |
3497 | * or the device wasn't in the addressed or configured state. | |
3498 | */ | |
3499 | ret = reset_device_cmd->status; | |
3500 | switch (ret) { | |
c311e391 MN |
3501 | case COMP_CMD_ABORT: |
3502 | case COMP_CMD_STOP: | |
3503 | xhci_warn(xhci, "Timeout waiting for reset device command\n"); | |
3504 | ret = -ETIME; | |
3505 | goto command_cleanup; | |
2a8f82c4 SS |
3506 | case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */ |
3507 | case COMP_CTX_STATE: /* 0.96 completion code for same thing */ | |
38a532a6 | 3508 | xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n", |
2a8f82c4 SS |
3509 | slot_id, |
3510 | xhci_get_slot_state(xhci, virt_dev->out_ctx)); | |
38a532a6 | 3511 | xhci_dbg(xhci, "Not freeing device rings.\n"); |
2a8f82c4 SS |
3512 | /* Don't treat this as an error. May change my mind later. */ |
3513 | ret = 0; | |
3514 | goto command_cleanup; | |
3515 | case COMP_SUCCESS: | |
3516 | xhci_dbg(xhci, "Successful reset device command.\n"); | |
3517 | break; | |
3518 | default: | |
3519 | if (xhci_is_vendor_info_code(xhci, ret)) | |
3520 | break; | |
3521 | xhci_warn(xhci, "Unknown completion code %u for " | |
3522 | "reset device command.\n", ret); | |
3523 | ret = -EINVAL; | |
3524 | goto command_cleanup; | |
3525 | } | |
3526 | ||
2cf95c18 SS |
3527 | /* Free up host controller endpoint resources */ |
3528 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3529 | spin_lock_irqsave(&xhci->lock, flags); | |
3530 | /* Don't delete the default control endpoint resources */ | |
3531 | xhci_free_device_endpoint_resources(xhci, virt_dev, false); | |
3532 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3533 | } | |
3534 | ||
2a8f82c4 SS |
3535 | /* Everything but endpoint 0 is disabled, so free or cache the rings. */ |
3536 | last_freed_endpoint = 1; | |
3537 | for (i = 1; i < 31; ++i) { | |
2dea75d9 DT |
3538 | struct xhci_virt_ep *ep = &virt_dev->eps[i]; |
3539 | ||
3540 | if (ep->ep_state & EP_HAS_STREAMS) { | |
df613834 HG |
3541 | xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n", |
3542 | xhci_get_endpoint_address(i)); | |
2dea75d9 DT |
3543 | xhci_free_stream_info(xhci, ep->stream_info); |
3544 | ep->stream_info = NULL; | |
3545 | ep->ep_state &= ~EP_HAS_STREAMS; | |
3546 | } | |
3547 | ||
3548 | if (ep->ring) { | |
3549 | xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i); | |
3550 | last_freed_endpoint = i; | |
3551 | } | |
2e27980e SS |
3552 | if (!list_empty(&virt_dev->eps[i].bw_endpoint_list)) |
3553 | xhci_drop_ep_from_interval_table(xhci, | |
3554 | &virt_dev->eps[i].bw_info, | |
3555 | virt_dev->bw_table, | |
3556 | udev, | |
3557 | &virt_dev->eps[i], | |
3558 | virt_dev->tt_info); | |
9af5d71d | 3559 | xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info); |
2a8f82c4 | 3560 | } |
2e27980e SS |
3561 | /* If necessary, update the number of active TTs on this root port */ |
3562 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
3563 | ||
2a8f82c4 SS |
3564 | xhci_dbg(xhci, "Output context after successful reset device cmd:\n"); |
3565 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint); | |
3566 | ret = 0; | |
3567 | ||
3568 | command_cleanup: | |
3569 | xhci_free_command(xhci, reset_device_cmd); | |
3570 | return ret; | |
3571 | } | |
3572 | ||
3ffbba95 SS |
3573 | /* |
3574 | * At this point, the struct usb_device is about to go away, the device has | |
3575 | * disconnected, and all traffic has been stopped and the endpoints have been | |
3576 | * disabled. Free any HC data structures associated with that device. | |
3577 | */ | |
3578 | void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3579 | { | |
3580 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
6f5165cf | 3581 | struct xhci_virt_device *virt_dev; |
3ffbba95 | 3582 | unsigned long flags; |
c526d0d4 | 3583 | u32 state; |
64927730 | 3584 | int i, ret; |
ddba5cd0 MN |
3585 | struct xhci_command *command; |
3586 | ||
3587 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); | |
3588 | if (!command) | |
3589 | return; | |
3ffbba95 | 3590 | |
c8476fb8 SN |
3591 | #ifndef CONFIG_USB_DEFAULT_PERSIST |
3592 | /* | |
3593 | * We called pm_runtime_get_noresume when the device was attached. | |
3594 | * Decrement the counter here to allow controller to runtime suspend | |
3595 | * if no devices remain. | |
3596 | */ | |
3597 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3598 | pm_runtime_put_noidle(hcd->self.controller); |
c8476fb8 SN |
3599 | #endif |
3600 | ||
64927730 | 3601 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
7bd89b40 SS |
3602 | /* If the host is halted due to driver unload, we still need to free the |
3603 | * device. | |
3604 | */ | |
ddba5cd0 MN |
3605 | if (ret <= 0 && ret != -ENODEV) { |
3606 | kfree(command); | |
3ffbba95 | 3607 | return; |
ddba5cd0 | 3608 | } |
64927730 | 3609 | |
6f5165cf | 3610 | virt_dev = xhci->devs[udev->slot_id]; |
6f5165cf SS |
3611 | |
3612 | /* Stop any wayward timer functions (which may grab the lock) */ | |
3613 | for (i = 0; i < 31; ++i) { | |
3614 | virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING; | |
3615 | del_timer_sync(&virt_dev->eps[i].stop_cmd_timer); | |
3616 | } | |
3ffbba95 SS |
3617 | |
3618 | spin_lock_irqsave(&xhci->lock, flags); | |
c526d0d4 | 3619 | /* Don't disable the slot if the host controller is dead. */ |
b0ba9720 | 3620 | state = readl(&xhci->op_regs->status); |
7bd89b40 SS |
3621 | if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) || |
3622 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
c526d0d4 SS |
3623 | xhci_free_virt_device(xhci, udev->slot_id); |
3624 | spin_unlock_irqrestore(&xhci->lock, flags); | |
ddba5cd0 | 3625 | kfree(command); |
c526d0d4 SS |
3626 | return; |
3627 | } | |
3628 | ||
ddba5cd0 MN |
3629 | if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT, |
3630 | udev->slot_id)) { | |
3ffbba95 SS |
3631 | spin_unlock_irqrestore(&xhci->lock, flags); |
3632 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
3633 | return; | |
3634 | } | |
23e3be11 | 3635 | xhci_ring_cmd_db(xhci); |
3ffbba95 | 3636 | spin_unlock_irqrestore(&xhci->lock, flags); |
ddba5cd0 | 3637 | |
3ffbba95 SS |
3638 | /* |
3639 | * Event command completion handler will free any data structures | |
f88ba78d | 3640 | * associated with the slot. XXX Can free sleep? |
3ffbba95 SS |
3641 | */ |
3642 | } | |
3643 | ||
2cf95c18 SS |
3644 | /* |
3645 | * Checks if we have enough host controller resources for the default control | |
3646 | * endpoint. | |
3647 | * | |
3648 | * Must be called with xhci->lock held. | |
3649 | */ | |
3650 | static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci) | |
3651 | { | |
3652 | if (xhci->num_active_eps + 1 > xhci->limit_active_eps) { | |
4bdfe4c3 XR |
3653 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3654 | "Not enough ep ctxs: " | |
3655 | "%u active, need to add 1, limit is %u.", | |
2cf95c18 SS |
3656 | xhci->num_active_eps, xhci->limit_active_eps); |
3657 | return -ENOMEM; | |
3658 | } | |
3659 | xhci->num_active_eps += 1; | |
4bdfe4c3 XR |
3660 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3661 | "Adding 1 ep ctx, %u now active.", | |
2cf95c18 SS |
3662 | xhci->num_active_eps); |
3663 | return 0; | |
3664 | } | |
3665 | ||
3666 | ||
3ffbba95 SS |
3667 | /* |
3668 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command | |
3669 | * timed out, or allocating memory failed. Returns 1 on success. | |
3670 | */ | |
3671 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3672 | { | |
3673 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
3674 | unsigned long flags; | |
3ffbba95 | 3675 | int ret; |
ddba5cd0 MN |
3676 | struct xhci_command *command; |
3677 | ||
3678 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); | |
3679 | if (!command) | |
3680 | return 0; | |
3ffbba95 SS |
3681 | |
3682 | spin_lock_irqsave(&xhci->lock, flags); | |
ddba5cd0 MN |
3683 | command->completion = &xhci->addr_dev; |
3684 | ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0); | |
3ffbba95 SS |
3685 | if (ret) { |
3686 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3687 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
ddba5cd0 | 3688 | kfree(command); |
3ffbba95 SS |
3689 | return 0; |
3690 | } | |
23e3be11 | 3691 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3692 | spin_unlock_irqrestore(&xhci->lock, flags); |
3693 | ||
c311e391 | 3694 | wait_for_completion(command->completion); |
3ffbba95 | 3695 | |
c311e391 | 3696 | if (!xhci->slot_id || command->status != COMP_SUCCESS) { |
3ffbba95 | 3697 | xhci_err(xhci, "Error while assigning device slot ID\n"); |
be982038 SS |
3698 | xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n", |
3699 | HCS_MAX_SLOTS( | |
3700 | readl(&xhci->cap_regs->hcs_params1))); | |
ddba5cd0 | 3701 | kfree(command); |
3ffbba95 SS |
3702 | return 0; |
3703 | } | |
2cf95c18 SS |
3704 | |
3705 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3706 | spin_lock_irqsave(&xhci->lock, flags); | |
3707 | ret = xhci_reserve_host_control_ep_resources(xhci); | |
3708 | if (ret) { | |
3709 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3710 | xhci_warn(xhci, "Not enough host resources, " | |
3711 | "active endpoint contexts = %u\n", | |
3712 | xhci->num_active_eps); | |
3713 | goto disable_slot; | |
3714 | } | |
3715 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3716 | } | |
3717 | /* Use GFP_NOIO, since this function can be called from | |
a6d940dd SS |
3718 | * xhci_discover_or_reset_device(), which may be called as part of |
3719 | * mass storage driver error handling. | |
3720 | */ | |
3721 | if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) { | |
3ffbba95 | 3722 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); |
2cf95c18 | 3723 | goto disable_slot; |
3ffbba95 SS |
3724 | } |
3725 | udev->slot_id = xhci->slot_id; | |
c8476fb8 SN |
3726 | |
3727 | #ifndef CONFIG_USB_DEFAULT_PERSIST | |
3728 | /* | |
3729 | * If resetting upon resume, we can't put the controller into runtime | |
3730 | * suspend if there is a device attached. | |
3731 | */ | |
3732 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3733 | pm_runtime_get_noresume(hcd->self.controller); |
c8476fb8 SN |
3734 | #endif |
3735 | ||
ddba5cd0 MN |
3736 | |
3737 | kfree(command); | |
3ffbba95 SS |
3738 | /* Is this a LS or FS device under a HS hub? */ |
3739 | /* Hub or peripherial? */ | |
3ffbba95 | 3740 | return 1; |
2cf95c18 SS |
3741 | |
3742 | disable_slot: | |
3743 | /* Disable slot, if we can do it without mem alloc */ | |
3744 | spin_lock_irqsave(&xhci->lock, flags); | |
ddba5cd0 MN |
3745 | command->completion = NULL; |
3746 | command->status = 0; | |
3747 | if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT, | |
3748 | udev->slot_id)) | |
2cf95c18 SS |
3749 | xhci_ring_cmd_db(xhci); |
3750 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3751 | return 0; | |
3ffbba95 SS |
3752 | } |
3753 | ||
3754 | /* | |
48fc7dbd DW |
3755 | * Issue an Address Device command and optionally send a corresponding |
3756 | * SetAddress request to the device. | |
3ffbba95 SS |
3757 | * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so |
3758 | * we should only issue and wait on one address command at the same time. | |
3ffbba95 | 3759 | */ |
48fc7dbd DW |
3760 | static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, |
3761 | enum xhci_setup_dev setup) | |
3ffbba95 | 3762 | { |
6f8ffc0b | 3763 | const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address"; |
3ffbba95 | 3764 | unsigned long flags; |
3ffbba95 SS |
3765 | struct xhci_virt_device *virt_dev; |
3766 | int ret = 0; | |
3767 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
d115b048 JY |
3768 | struct xhci_slot_ctx *slot_ctx; |
3769 | struct xhci_input_control_ctx *ctrl_ctx; | |
8e595a5d | 3770 | u64 temp_64; |
ddba5cd0 | 3771 | struct xhci_command *command; |
3ffbba95 SS |
3772 | |
3773 | if (!udev->slot_id) { | |
84a99f6f XR |
3774 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3775 | "Bad Slot ID %d", udev->slot_id); | |
3ffbba95 SS |
3776 | return -EINVAL; |
3777 | } | |
3778 | ||
3ffbba95 SS |
3779 | virt_dev = xhci->devs[udev->slot_id]; |
3780 | ||
7ed603ec ME |
3781 | if (WARN_ON(!virt_dev)) { |
3782 | /* | |
3783 | * In plug/unplug torture test with an NEC controller, | |
3784 | * a zero-dereference was observed once due to virt_dev = 0. | |
3785 | * Print useful debug rather than crash if it is observed again! | |
3786 | */ | |
3787 | xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n", | |
3788 | udev->slot_id); | |
3789 | return -EINVAL; | |
3790 | } | |
3791 | ||
ddba5cd0 MN |
3792 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); |
3793 | if (!command) | |
3794 | return -ENOMEM; | |
3795 | ||
3796 | command->in_ctx = virt_dev->in_ctx; | |
3797 | command->completion = &xhci->addr_dev; | |
3798 | ||
f0615c45 | 3799 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
92f8e767 SS |
3800 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
3801 | if (!ctrl_ctx) { | |
3802 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3803 | __func__); | |
ddba5cd0 | 3804 | kfree(command); |
92f8e767 SS |
3805 | return -EINVAL; |
3806 | } | |
f0615c45 AX |
3807 | /* |
3808 | * If this is the first Set Address since device plug-in or | |
3809 | * virt_device realloaction after a resume with an xHCI power loss, | |
3810 | * then set up the slot context. | |
3811 | */ | |
3812 | if (!slot_ctx->dev_info) | |
3ffbba95 | 3813 | xhci_setup_addressable_virt_dev(xhci, udev); |
f0615c45 | 3814 | /* Otherwise, update the control endpoint ring enqueue pointer. */ |
2d1ee590 SS |
3815 | else |
3816 | xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev); | |
d31c285b SS |
3817 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); |
3818 | ctrl_ctx->drop_flags = 0; | |
3819 | ||
66e49d87 | 3820 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
d115b048 | 3821 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
1d27fabe | 3822 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 3823 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 | 3824 | |
f88ba78d | 3825 | spin_lock_irqsave(&xhci->lock, flags); |
ddba5cd0 | 3826 | ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma, |
48fc7dbd | 3827 | udev->slot_id, setup); |
3ffbba95 SS |
3828 | if (ret) { |
3829 | spin_unlock_irqrestore(&xhci->lock, flags); | |
84a99f6f XR |
3830 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3831 | "FIXME: allocate a command ring segment"); | |
ddba5cd0 | 3832 | kfree(command); |
3ffbba95 SS |
3833 | return ret; |
3834 | } | |
23e3be11 | 3835 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3836 | spin_unlock_irqrestore(&xhci->lock, flags); |
3837 | ||
3838 | /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */ | |
c311e391 MN |
3839 | wait_for_completion(command->completion); |
3840 | ||
3ffbba95 SS |
3841 | /* FIXME: From section 4.3.4: "Software shall be responsible for timing |
3842 | * the SetAddress() "recovery interval" required by USB and aborting the | |
3843 | * command on a timeout. | |
3844 | */ | |
9ea1833e | 3845 | switch (command->status) { |
c311e391 MN |
3846 | case COMP_CMD_ABORT: |
3847 | case COMP_CMD_STOP: | |
3848 | xhci_warn(xhci, "Timeout while waiting for setup device command\n"); | |
3849 | ret = -ETIME; | |
3850 | break; | |
3ffbba95 SS |
3851 | case COMP_CTX_STATE: |
3852 | case COMP_EBADSLT: | |
6f8ffc0b DW |
3853 | xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n", |
3854 | act, udev->slot_id); | |
3ffbba95 SS |
3855 | ret = -EINVAL; |
3856 | break; | |
3857 | case COMP_TX_ERR: | |
6f8ffc0b | 3858 | dev_warn(&udev->dev, "Device not responding to setup %s.\n", act); |
3ffbba95 SS |
3859 | ret = -EPROTO; |
3860 | break; | |
f6ba6fe2 | 3861 | case COMP_DEV_ERR: |
6f8ffc0b DW |
3862 | dev_warn(&udev->dev, |
3863 | "ERROR: Incompatible device for setup %s command\n", act); | |
f6ba6fe2 AH |
3864 | ret = -ENODEV; |
3865 | break; | |
3ffbba95 | 3866 | case COMP_SUCCESS: |
84a99f6f | 3867 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
6f8ffc0b | 3868 | "Successful setup %s command", act); |
3ffbba95 SS |
3869 | break; |
3870 | default: | |
6f8ffc0b DW |
3871 | xhci_err(xhci, |
3872 | "ERROR: unexpected setup %s command completion code 0x%x.\n", | |
9ea1833e | 3873 | act, command->status); |
66e49d87 | 3874 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
d115b048 | 3875 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); |
1d27fabe | 3876 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1); |
3ffbba95 SS |
3877 | ret = -EINVAL; |
3878 | break; | |
3879 | } | |
3880 | if (ret) { | |
ddba5cd0 | 3881 | kfree(command); |
3ffbba95 SS |
3882 | return ret; |
3883 | } | |
f7b2e403 | 3884 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
84a99f6f XR |
3885 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3886 | "Op regs DCBAA ptr = %#016llx", temp_64); | |
3887 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3888 | "Slot ID %d dcbaa entry @%p = %#016llx", | |
3889 | udev->slot_id, | |
3890 | &xhci->dcbaa->dev_context_ptrs[udev->slot_id], | |
3891 | (unsigned long long) | |
3892 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id])); | |
3893 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3894 | "Output Context DMA address = %#08llx", | |
d115b048 | 3895 | (unsigned long long)virt_dev->out_ctx->dma); |
3ffbba95 | 3896 | xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id); |
d115b048 | 3897 | xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2); |
1d27fabe | 3898 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 3899 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 | 3900 | xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id); |
d115b048 | 3901 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2); |
3ffbba95 SS |
3902 | /* |
3903 | * USB core uses address 1 for the roothubs, so we add one to the | |
3904 | * address given back to us by the HC. | |
3905 | */ | |
d115b048 | 3906 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
1d27fabe | 3907 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, |
0c052aab | 3908 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
f94e0186 | 3909 | /* Zero the input context control for later use */ |
d115b048 JY |
3910 | ctrl_ctx->add_flags = 0; |
3911 | ctrl_ctx->drop_flags = 0; | |
3ffbba95 | 3912 | |
84a99f6f | 3913 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
a2cdc343 DW |
3914 | "Internal device address = %d", |
3915 | le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); | |
ddba5cd0 | 3916 | kfree(command); |
3ffbba95 SS |
3917 | return 0; |
3918 | } | |
3919 | ||
48fc7dbd DW |
3920 | int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) |
3921 | { | |
3922 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS); | |
3923 | } | |
3924 | ||
3925 | int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev) | |
3926 | { | |
3927 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY); | |
3928 | } | |
3929 | ||
3f5eb141 LT |
3930 | /* |
3931 | * Transfer the port index into real index in the HW port status | |
3932 | * registers. Caculate offset between the port's PORTSC register | |
3933 | * and port status base. Divide the number of per port register | |
3934 | * to get the real index. The raw port number bases 1. | |
3935 | */ | |
3936 | int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1) | |
3937 | { | |
3938 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
3939 | __le32 __iomem *base_addr = &xhci->op_regs->port_status_base; | |
3940 | __le32 __iomem *addr; | |
3941 | int raw_port; | |
3942 | ||
3943 | if (hcd->speed != HCD_USB3) | |
3944 | addr = xhci->usb2_ports[port1 - 1]; | |
3945 | else | |
3946 | addr = xhci->usb3_ports[port1 - 1]; | |
3947 | ||
3948 | raw_port = (addr - base_addr)/NUM_PORT_REGS + 1; | |
3949 | return raw_port; | |
3950 | } | |
3951 | ||
a558ccdc MN |
3952 | /* |
3953 | * Issue an Evaluate Context command to change the Maximum Exit Latency in the | |
3954 | * slot context. If that succeeds, store the new MEL in the xhci_virt_device. | |
3955 | */ | |
d5c82feb | 3956 | static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, |
a558ccdc MN |
3957 | struct usb_device *udev, u16 max_exit_latency) |
3958 | { | |
3959 | struct xhci_virt_device *virt_dev; | |
3960 | struct xhci_command *command; | |
3961 | struct xhci_input_control_ctx *ctrl_ctx; | |
3962 | struct xhci_slot_ctx *slot_ctx; | |
3963 | unsigned long flags; | |
3964 | int ret; | |
3965 | ||
3966 | spin_lock_irqsave(&xhci->lock, flags); | |
3967 | if (max_exit_latency == xhci->devs[udev->slot_id]->current_mel) { | |
3968 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3969 | return 0; | |
3970 | } | |
3971 | ||
3972 | /* Attempt to issue an Evaluate Context command to change the MEL. */ | |
3973 | virt_dev = xhci->devs[udev->slot_id]; | |
3974 | command = xhci->lpm_command; | |
92f8e767 SS |
3975 | ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx); |
3976 | if (!ctrl_ctx) { | |
3977 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3978 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3979 | __func__); | |
3980 | return -ENOMEM; | |
3981 | } | |
3982 | ||
a558ccdc MN |
3983 | xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx); |
3984 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3985 | ||
a558ccdc MN |
3986 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
3987 | slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx); | |
3988 | slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT)); | |
3989 | slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency); | |
3990 | ||
3a7fa5be XR |
3991 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
3992 | "Set up evaluate context for LPM MEL change."); | |
a558ccdc MN |
3993 | xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id); |
3994 | xhci_dbg_ctx(xhci, command->in_ctx, 0); | |
3995 | ||
3996 | /* Issue and wait for the evaluate context command. */ | |
3997 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3998 | true, true); | |
3999 | xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id); | |
4000 | xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0); | |
4001 | ||
4002 | if (!ret) { | |
4003 | spin_lock_irqsave(&xhci->lock, flags); | |
4004 | virt_dev->current_mel = max_exit_latency; | |
4005 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4006 | } | |
4007 | return ret; | |
4008 | } | |
4009 | ||
84ebc102 | 4010 | #ifdef CONFIG_PM_RUNTIME |
9574323c AX |
4011 | |
4012 | /* BESL to HIRD Encoding array for USB2 LPM */ | |
4013 | static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000, | |
4014 | 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000}; | |
4015 | ||
4016 | /* Calculate HIRD/BESL for USB2 PORTPMSC*/ | |
f99298bf AX |
4017 | static int xhci_calculate_hird_besl(struct xhci_hcd *xhci, |
4018 | struct usb_device *udev) | |
9574323c | 4019 | { |
f99298bf AX |
4020 | int u2del, besl, besl_host; |
4021 | int besl_device = 0; | |
4022 | u32 field; | |
4023 | ||
4024 | u2del = HCS_U2_LATENCY(xhci->hcs_params3); | |
4025 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
9574323c | 4026 | |
f99298bf AX |
4027 | if (field & USB_BESL_SUPPORT) { |
4028 | for (besl_host = 0; besl_host < 16; besl_host++) { | |
4029 | if (xhci_besl_encoding[besl_host] >= u2del) | |
9574323c AX |
4030 | break; |
4031 | } | |
f99298bf AX |
4032 | /* Use baseline BESL value as default */ |
4033 | if (field & USB_BESL_BASELINE_VALID) | |
4034 | besl_device = USB_GET_BESL_BASELINE(field); | |
4035 | else if (field & USB_BESL_DEEP_VALID) | |
4036 | besl_device = USB_GET_BESL_DEEP(field); | |
9574323c AX |
4037 | } else { |
4038 | if (u2del <= 50) | |
f99298bf | 4039 | besl_host = 0; |
9574323c | 4040 | else |
f99298bf | 4041 | besl_host = (u2del - 51) / 75 + 1; |
9574323c AX |
4042 | } |
4043 | ||
f99298bf AX |
4044 | besl = besl_host + besl_device; |
4045 | if (besl > 15) | |
4046 | besl = 15; | |
4047 | ||
4048 | return besl; | |
9574323c AX |
4049 | } |
4050 | ||
a558ccdc MN |
4051 | /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */ |
4052 | static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev) | |
4053 | { | |
4054 | u32 field; | |
4055 | int l1; | |
4056 | int besld = 0; | |
4057 | int hirdm = 0; | |
4058 | ||
4059 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
4060 | ||
4061 | /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */ | |
17f34867 | 4062 | l1 = udev->l1_params.timeout / 256; |
a558ccdc MN |
4063 | |
4064 | /* device has preferred BESLD */ | |
4065 | if (field & USB_BESL_DEEP_VALID) { | |
4066 | besld = USB_GET_BESL_DEEP(field); | |
4067 | hirdm = 1; | |
4068 | } | |
4069 | ||
4070 | return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm); | |
4071 | } | |
4072 | ||
65580b43 AX |
4073 | int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
4074 | struct usb_device *udev, int enable) | |
4075 | { | |
4076 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4077 | __le32 __iomem **port_array; | |
a558ccdc MN |
4078 | __le32 __iomem *pm_addr, *hlpm_addr; |
4079 | u32 pm_val, hlpm_val, field; | |
65580b43 AX |
4080 | unsigned int port_num; |
4081 | unsigned long flags; | |
a558ccdc MN |
4082 | int hird, exit_latency; |
4083 | int ret; | |
65580b43 AX |
4084 | |
4085 | if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support || | |
4086 | !udev->lpm_capable) | |
4087 | return -EPERM; | |
4088 | ||
4089 | if (!udev->parent || udev->parent->parent || | |
4090 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4091 | return -EPERM; | |
4092 | ||
4093 | if (udev->usb2_hw_lpm_capable != 1) | |
4094 | return -EPERM; | |
4095 | ||
4096 | spin_lock_irqsave(&xhci->lock, flags); | |
4097 | ||
4098 | port_array = xhci->usb2_ports; | |
4099 | port_num = udev->portnum - 1; | |
b6e76371 | 4100 | pm_addr = port_array[port_num] + PORTPMSC; |
b0ba9720 | 4101 | pm_val = readl(pm_addr); |
a558ccdc MN |
4102 | hlpm_addr = port_array[port_num] + PORTHLPMC; |
4103 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
65580b43 AX |
4104 | |
4105 | xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n", | |
654a55d3 | 4106 | enable ? "enable" : "disable", port_num + 1); |
65580b43 | 4107 | |
65580b43 | 4108 | if (enable) { |
a558ccdc MN |
4109 | /* Host supports BESL timeout instead of HIRD */ |
4110 | if (udev->usb2_hw_lpm_besl_capable) { | |
4111 | /* if device doesn't have a preferred BESL value use a | |
4112 | * default one which works with mixed HIRD and BESL | |
4113 | * systems. See XHCI_DEFAULT_BESL definition in xhci.h | |
4114 | */ | |
4115 | if ((field & USB_BESL_SUPPORT) && | |
4116 | (field & USB_BESL_BASELINE_VALID)) | |
4117 | hird = USB_GET_BESL_BASELINE(field); | |
4118 | else | |
17f34867 | 4119 | hird = udev->l1_params.besl; |
a558ccdc MN |
4120 | |
4121 | exit_latency = xhci_besl_encoding[hird]; | |
4122 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4123 | ||
4124 | /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx | |
4125 | * input context for link powermanagement evaluate | |
4126 | * context commands. It is protected by hcd->bandwidth | |
4127 | * mutex and is shared by all devices. We need to set | |
4128 | * the max ext latency in USB 2 BESL LPM as well, so | |
4129 | * use the same mutex and xhci_change_max_exit_latency() | |
4130 | */ | |
4131 | mutex_lock(hcd->bandwidth_mutex); | |
4132 | ret = xhci_change_max_exit_latency(xhci, udev, | |
4133 | exit_latency); | |
4134 | mutex_unlock(hcd->bandwidth_mutex); | |
4135 | ||
4136 | if (ret < 0) | |
4137 | return ret; | |
4138 | spin_lock_irqsave(&xhci->lock, flags); | |
4139 | ||
4140 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); | |
204b7793 | 4141 | writel(hlpm_val, hlpm_addr); |
a558ccdc | 4142 | /* flush write */ |
b0ba9720 | 4143 | readl(hlpm_addr); |
a558ccdc MN |
4144 | } else { |
4145 | hird = xhci_calculate_hird_besl(xhci, udev); | |
4146 | } | |
4147 | ||
4148 | pm_val &= ~PORT_HIRD_MASK; | |
58e21f73 | 4149 | pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id); |
204b7793 | 4150 | writel(pm_val, pm_addr); |
b0ba9720 | 4151 | pm_val = readl(pm_addr); |
a558ccdc | 4152 | pm_val |= PORT_HLE; |
204b7793 | 4153 | writel(pm_val, pm_addr); |
a558ccdc | 4154 | /* flush write */ |
b0ba9720 | 4155 | readl(pm_addr); |
65580b43 | 4156 | } else { |
58e21f73 | 4157 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK); |
204b7793 | 4158 | writel(pm_val, pm_addr); |
a558ccdc | 4159 | /* flush write */ |
b0ba9720 | 4160 | readl(pm_addr); |
a558ccdc MN |
4161 | if (udev->usb2_hw_lpm_besl_capable) { |
4162 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4163 | mutex_lock(hcd->bandwidth_mutex); | |
4164 | xhci_change_max_exit_latency(xhci, udev, 0); | |
4165 | mutex_unlock(hcd->bandwidth_mutex); | |
4166 | return 0; | |
4167 | } | |
65580b43 AX |
4168 | } |
4169 | ||
4170 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4171 | return 0; | |
4172 | } | |
4173 | ||
b630d4b9 MN |
4174 | /* check if a usb2 port supports a given extened capability protocol |
4175 | * only USB2 ports extended protocol capability values are cached. | |
4176 | * Return 1 if capability is supported | |
4177 | */ | |
4178 | static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port, | |
4179 | unsigned capability) | |
4180 | { | |
4181 | u32 port_offset, port_count; | |
4182 | int i; | |
4183 | ||
4184 | for (i = 0; i < xhci->num_ext_caps; i++) { | |
4185 | if (xhci->ext_caps[i] & capability) { | |
4186 | /* port offsets starts at 1 */ | |
4187 | port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1; | |
4188 | port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]); | |
4189 | if (port >= port_offset && | |
4190 | port < port_offset + port_count) | |
4191 | return 1; | |
4192 | } | |
4193 | } | |
4194 | return 0; | |
4195 | } | |
4196 | ||
b01bcbf7 SS |
4197 | int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
4198 | { | |
4199 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
b630d4b9 | 4200 | int portnum = udev->portnum - 1; |
b01bcbf7 | 4201 | |
de68bab4 SS |
4202 | if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support || |
4203 | !udev->lpm_capable) | |
4204 | return 0; | |
4205 | ||
4206 | /* we only support lpm for non-hub device connected to root hub yet */ | |
4207 | if (!udev->parent || udev->parent->parent || | |
4208 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4209 | return 0; | |
4210 | ||
4211 | if (xhci->hw_lpm_support == 1 && | |
4212 | xhci_check_usb2_port_capability( | |
4213 | xhci, portnum, XHCI_HLC)) { | |
4214 | udev->usb2_hw_lpm_capable = 1; | |
4215 | udev->l1_params.timeout = XHCI_L1_TIMEOUT; | |
4216 | udev->l1_params.besl = XHCI_DEFAULT_BESL; | |
4217 | if (xhci_check_usb2_port_capability(xhci, portnum, | |
4218 | XHCI_BLC)) | |
4219 | udev->usb2_hw_lpm_besl_capable = 1; | |
b01bcbf7 SS |
4220 | } |
4221 | ||
4222 | return 0; | |
4223 | } | |
4224 | ||
4225 | #else | |
4226 | ||
4227 | int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, | |
4228 | struct usb_device *udev, int enable) | |
4229 | { | |
4230 | return 0; | |
4231 | } | |
4232 | ||
4233 | int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) | |
4234 | { | |
4235 | return 0; | |
4236 | } | |
4237 | ||
84ebc102 | 4238 | #endif /* CONFIG_PM_RUNTIME */ |
b01bcbf7 | 4239 | |
3b3db026 SS |
4240 | /*---------------------- USB 3.0 Link PM functions ------------------------*/ |
4241 | ||
b01bcbf7 | 4242 | #ifdef CONFIG_PM |
e3567d2c SS |
4243 | /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */ |
4244 | static unsigned long long xhci_service_interval_to_ns( | |
4245 | struct usb_endpoint_descriptor *desc) | |
4246 | { | |
16b45fdf | 4247 | return (1ULL << (desc->bInterval - 1)) * 125 * 1000; |
e3567d2c SS |
4248 | } |
4249 | ||
3b3db026 SS |
4250 | static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev, |
4251 | enum usb3_link_state state) | |
4252 | { | |
4253 | unsigned long long sel; | |
4254 | unsigned long long pel; | |
4255 | unsigned int max_sel_pel; | |
4256 | char *state_name; | |
4257 | ||
4258 | switch (state) { | |
4259 | case USB3_LPM_U1: | |
4260 | /* Convert SEL and PEL stored in nanoseconds to microseconds */ | |
4261 | sel = DIV_ROUND_UP(udev->u1_params.sel, 1000); | |
4262 | pel = DIV_ROUND_UP(udev->u1_params.pel, 1000); | |
4263 | max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL; | |
4264 | state_name = "U1"; | |
4265 | break; | |
4266 | case USB3_LPM_U2: | |
4267 | sel = DIV_ROUND_UP(udev->u2_params.sel, 1000); | |
4268 | pel = DIV_ROUND_UP(udev->u2_params.pel, 1000); | |
4269 | max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL; | |
4270 | state_name = "U2"; | |
4271 | break; | |
4272 | default: | |
4273 | dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n", | |
4274 | __func__); | |
e25e62ae | 4275 | return USB3_LPM_DISABLED; |
3b3db026 SS |
4276 | } |
4277 | ||
4278 | if (sel <= max_sel_pel && pel <= max_sel_pel) | |
4279 | return USB3_LPM_DEVICE_INITIATED; | |
4280 | ||
4281 | if (sel > max_sel_pel) | |
4282 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
4283 | "due to long SEL %llu ms\n", | |
4284 | state_name, sel); | |
4285 | else | |
4286 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
03e64e96 | 4287 | "due to long PEL %llu ms\n", |
3b3db026 SS |
4288 | state_name, pel); |
4289 | return USB3_LPM_DISABLED; | |
4290 | } | |
4291 | ||
9502c46c | 4292 | /* The U1 timeout should be the maximum of the following values: |
e3567d2c SS |
4293 | * - For control endpoints, U1 system exit latency (SEL) * 3 |
4294 | * - For bulk endpoints, U1 SEL * 5 | |
4295 | * - For interrupt endpoints: | |
4296 | * - Notification EPs, U1 SEL * 3 | |
4297 | * - Periodic EPs, max(105% of bInterval, U1 SEL * 2) | |
4298 | * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2) | |
4299 | */ | |
9502c46c PA |
4300 | static unsigned long long xhci_calculate_intel_u1_timeout( |
4301 | struct usb_device *udev, | |
e3567d2c SS |
4302 | struct usb_endpoint_descriptor *desc) |
4303 | { | |
4304 | unsigned long long timeout_ns; | |
4305 | int ep_type; | |
4306 | int intr_type; | |
4307 | ||
4308 | ep_type = usb_endpoint_type(desc); | |
4309 | switch (ep_type) { | |
4310 | case USB_ENDPOINT_XFER_CONTROL: | |
4311 | timeout_ns = udev->u1_params.sel * 3; | |
4312 | break; | |
4313 | case USB_ENDPOINT_XFER_BULK: | |
4314 | timeout_ns = udev->u1_params.sel * 5; | |
4315 | break; | |
4316 | case USB_ENDPOINT_XFER_INT: | |
4317 | intr_type = usb_endpoint_interrupt_type(desc); | |
4318 | if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) { | |
4319 | timeout_ns = udev->u1_params.sel * 3; | |
4320 | break; | |
4321 | } | |
4322 | /* Otherwise the calculation is the same as isoc eps */ | |
4323 | case USB_ENDPOINT_XFER_ISOC: | |
4324 | timeout_ns = xhci_service_interval_to_ns(desc); | |
c88db160 | 4325 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100); |
e3567d2c SS |
4326 | if (timeout_ns < udev->u1_params.sel * 2) |
4327 | timeout_ns = udev->u1_params.sel * 2; | |
4328 | break; | |
4329 | default: | |
4330 | return 0; | |
4331 | } | |
4332 | ||
9502c46c PA |
4333 | return timeout_ns; |
4334 | } | |
4335 | ||
4336 | /* Returns the hub-encoded U1 timeout value. */ | |
4337 | static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci, | |
4338 | struct usb_device *udev, | |
4339 | struct usb_endpoint_descriptor *desc) | |
4340 | { | |
4341 | unsigned long long timeout_ns; | |
4342 | ||
4343 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4344 | timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc); | |
4345 | else | |
4346 | timeout_ns = udev->u1_params.sel; | |
4347 | ||
4348 | /* The U1 timeout is encoded in 1us intervals. | |
4349 | * Don't return a timeout of zero, because that's USB3_LPM_DISABLED. | |
4350 | */ | |
e3567d2c | 4351 | if (timeout_ns == USB3_LPM_DISABLED) |
9502c46c PA |
4352 | timeout_ns = 1; |
4353 | else | |
4354 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000); | |
e3567d2c SS |
4355 | |
4356 | /* If the necessary timeout value is bigger than what we can set in the | |
4357 | * USB 3.0 hub, we have to disable hub-initiated U1. | |
4358 | */ | |
4359 | if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT) | |
4360 | return timeout_ns; | |
4361 | dev_dbg(&udev->dev, "Hub-initiated U1 disabled " | |
4362 | "due to long timeout %llu ms\n", timeout_ns); | |
4363 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1); | |
4364 | } | |
4365 | ||
9502c46c | 4366 | /* The U2 timeout should be the maximum of: |
e3567d2c SS |
4367 | * - 10 ms (to avoid the bandwidth impact on the scheduler) |
4368 | * - largest bInterval of any active periodic endpoint (to avoid going | |
4369 | * into lower power link states between intervals). | |
4370 | * - the U2 Exit Latency of the device | |
4371 | */ | |
9502c46c PA |
4372 | static unsigned long long xhci_calculate_intel_u2_timeout( |
4373 | struct usb_device *udev, | |
e3567d2c SS |
4374 | struct usb_endpoint_descriptor *desc) |
4375 | { | |
4376 | unsigned long long timeout_ns; | |
4377 | unsigned long long u2_del_ns; | |
4378 | ||
4379 | timeout_ns = 10 * 1000 * 1000; | |
4380 | ||
4381 | if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) && | |
4382 | (xhci_service_interval_to_ns(desc) > timeout_ns)) | |
4383 | timeout_ns = xhci_service_interval_to_ns(desc); | |
4384 | ||
966e7a85 | 4385 | u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL; |
e3567d2c SS |
4386 | if (u2_del_ns > timeout_ns) |
4387 | timeout_ns = u2_del_ns; | |
4388 | ||
9502c46c PA |
4389 | return timeout_ns; |
4390 | } | |
4391 | ||
4392 | /* Returns the hub-encoded U2 timeout value. */ | |
4393 | static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci, | |
4394 | struct usb_device *udev, | |
4395 | struct usb_endpoint_descriptor *desc) | |
4396 | { | |
4397 | unsigned long long timeout_ns; | |
4398 | ||
4399 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4400 | timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc); | |
4401 | else | |
4402 | timeout_ns = udev->u2_params.sel; | |
4403 | ||
e3567d2c | 4404 | /* The U2 timeout is encoded in 256us intervals */ |
c88db160 | 4405 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000); |
e3567d2c SS |
4406 | /* If the necessary timeout value is bigger than what we can set in the |
4407 | * USB 3.0 hub, we have to disable hub-initiated U2. | |
4408 | */ | |
4409 | if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT) | |
4410 | return timeout_ns; | |
4411 | dev_dbg(&udev->dev, "Hub-initiated U2 disabled " | |
4412 | "due to long timeout %llu ms\n", timeout_ns); | |
4413 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2); | |
4414 | } | |
4415 | ||
3b3db026 SS |
4416 | static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci, |
4417 | struct usb_device *udev, | |
4418 | struct usb_endpoint_descriptor *desc, | |
4419 | enum usb3_link_state state, | |
4420 | u16 *timeout) | |
4421 | { | |
9502c46c PA |
4422 | if (state == USB3_LPM_U1) |
4423 | return xhci_calculate_u1_timeout(xhci, udev, desc); | |
4424 | else if (state == USB3_LPM_U2) | |
4425 | return xhci_calculate_u2_timeout(xhci, udev, desc); | |
e3567d2c | 4426 | |
3b3db026 SS |
4427 | return USB3_LPM_DISABLED; |
4428 | } | |
4429 | ||
4430 | static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci, | |
4431 | struct usb_device *udev, | |
4432 | struct usb_endpoint_descriptor *desc, | |
4433 | enum usb3_link_state state, | |
4434 | u16 *timeout) | |
4435 | { | |
4436 | u16 alt_timeout; | |
4437 | ||
4438 | alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev, | |
4439 | desc, state, timeout); | |
4440 | ||
4441 | /* If we found we can't enable hub-initiated LPM, or | |
4442 | * the U1 or U2 exit latency was too high to allow | |
4443 | * device-initiated LPM as well, just stop searching. | |
4444 | */ | |
4445 | if (alt_timeout == USB3_LPM_DISABLED || | |
4446 | alt_timeout == USB3_LPM_DEVICE_INITIATED) { | |
4447 | *timeout = alt_timeout; | |
4448 | return -E2BIG; | |
4449 | } | |
4450 | if (alt_timeout > *timeout) | |
4451 | *timeout = alt_timeout; | |
4452 | return 0; | |
4453 | } | |
4454 | ||
4455 | static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci, | |
4456 | struct usb_device *udev, | |
4457 | struct usb_host_interface *alt, | |
4458 | enum usb3_link_state state, | |
4459 | u16 *timeout) | |
4460 | { | |
4461 | int j; | |
4462 | ||
4463 | for (j = 0; j < alt->desc.bNumEndpoints; j++) { | |
4464 | if (xhci_update_timeout_for_endpoint(xhci, udev, | |
4465 | &alt->endpoint[j].desc, state, timeout)) | |
4466 | return -E2BIG; | |
4467 | continue; | |
4468 | } | |
4469 | return 0; | |
4470 | } | |
4471 | ||
e3567d2c SS |
4472 | static int xhci_check_intel_tier_policy(struct usb_device *udev, |
4473 | enum usb3_link_state state) | |
4474 | { | |
4475 | struct usb_device *parent; | |
4476 | unsigned int num_hubs; | |
4477 | ||
4478 | if (state == USB3_LPM_U2) | |
4479 | return 0; | |
4480 | ||
4481 | /* Don't enable U1 if the device is on a 2nd tier hub or lower. */ | |
4482 | for (parent = udev->parent, num_hubs = 0; parent->parent; | |
4483 | parent = parent->parent) | |
4484 | num_hubs++; | |
4485 | ||
4486 | if (num_hubs < 2) | |
4487 | return 0; | |
4488 | ||
4489 | dev_dbg(&udev->dev, "Disabling U1 link state for device" | |
4490 | " below second-tier hub.\n"); | |
4491 | dev_dbg(&udev->dev, "Plug device into first-tier hub " | |
4492 | "to decrease power consumption.\n"); | |
4493 | return -E2BIG; | |
4494 | } | |
4495 | ||
3b3db026 SS |
4496 | static int xhci_check_tier_policy(struct xhci_hcd *xhci, |
4497 | struct usb_device *udev, | |
4498 | enum usb3_link_state state) | |
4499 | { | |
e3567d2c SS |
4500 | if (xhci->quirks & XHCI_INTEL_HOST) |
4501 | return xhci_check_intel_tier_policy(udev, state); | |
9502c46c PA |
4502 | else |
4503 | return 0; | |
3b3db026 SS |
4504 | } |
4505 | ||
4506 | /* Returns the U1 or U2 timeout that should be enabled. | |
4507 | * If the tier check or timeout setting functions return with a non-zero exit | |
4508 | * code, that means the timeout value has been finalized and we shouldn't look | |
4509 | * at any more endpoints. | |
4510 | */ | |
4511 | static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd, | |
4512 | struct usb_device *udev, enum usb3_link_state state) | |
4513 | { | |
4514 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4515 | struct usb_host_config *config; | |
4516 | char *state_name; | |
4517 | int i; | |
4518 | u16 timeout = USB3_LPM_DISABLED; | |
4519 | ||
4520 | if (state == USB3_LPM_U1) | |
4521 | state_name = "U1"; | |
4522 | else if (state == USB3_LPM_U2) | |
4523 | state_name = "U2"; | |
4524 | else { | |
4525 | dev_warn(&udev->dev, "Can't enable unknown link state %i\n", | |
4526 | state); | |
4527 | return timeout; | |
4528 | } | |
4529 | ||
4530 | if (xhci_check_tier_policy(xhci, udev, state) < 0) | |
4531 | return timeout; | |
4532 | ||
4533 | /* Gather some information about the currently installed configuration | |
4534 | * and alternate interface settings. | |
4535 | */ | |
4536 | if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc, | |
4537 | state, &timeout)) | |
4538 | return timeout; | |
4539 | ||
4540 | config = udev->actconfig; | |
4541 | if (!config) | |
4542 | return timeout; | |
4543 | ||
64ba419b | 4544 | for (i = 0; i < config->desc.bNumInterfaces; i++) { |
3b3db026 SS |
4545 | struct usb_driver *driver; |
4546 | struct usb_interface *intf = config->interface[i]; | |
4547 | ||
4548 | if (!intf) | |
4549 | continue; | |
4550 | ||
4551 | /* Check if any currently bound drivers want hub-initiated LPM | |
4552 | * disabled. | |
4553 | */ | |
4554 | if (intf->dev.driver) { | |
4555 | driver = to_usb_driver(intf->dev.driver); | |
4556 | if (driver && driver->disable_hub_initiated_lpm) { | |
4557 | dev_dbg(&udev->dev, "Hub-initiated %s disabled " | |
4558 | "at request of driver %s\n", | |
4559 | state_name, driver->name); | |
4560 | return xhci_get_timeout_no_hub_lpm(udev, state); | |
4561 | } | |
4562 | } | |
4563 | ||
4564 | /* Not sure how this could happen... */ | |
4565 | if (!intf->cur_altsetting) | |
4566 | continue; | |
4567 | ||
4568 | if (xhci_update_timeout_for_interface(xhci, udev, | |
4569 | intf->cur_altsetting, | |
4570 | state, &timeout)) | |
4571 | return timeout; | |
4572 | } | |
4573 | return timeout; | |
4574 | } | |
4575 | ||
3b3db026 SS |
4576 | static int calculate_max_exit_latency(struct usb_device *udev, |
4577 | enum usb3_link_state state_changed, | |
4578 | u16 hub_encoded_timeout) | |
4579 | { | |
4580 | unsigned long long u1_mel_us = 0; | |
4581 | unsigned long long u2_mel_us = 0; | |
4582 | unsigned long long mel_us = 0; | |
4583 | bool disabling_u1; | |
4584 | bool disabling_u2; | |
4585 | bool enabling_u1; | |
4586 | bool enabling_u2; | |
4587 | ||
4588 | disabling_u1 = (state_changed == USB3_LPM_U1 && | |
4589 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4590 | disabling_u2 = (state_changed == USB3_LPM_U2 && | |
4591 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4592 | ||
4593 | enabling_u1 = (state_changed == USB3_LPM_U1 && | |
4594 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4595 | enabling_u2 = (state_changed == USB3_LPM_U2 && | |
4596 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4597 | ||
4598 | /* If U1 was already enabled and we're not disabling it, | |
4599 | * or we're going to enable U1, account for the U1 max exit latency. | |
4600 | */ | |
4601 | if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) || | |
4602 | enabling_u1) | |
4603 | u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000); | |
4604 | if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) || | |
4605 | enabling_u2) | |
4606 | u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000); | |
4607 | ||
4608 | if (u1_mel_us > u2_mel_us) | |
4609 | mel_us = u1_mel_us; | |
4610 | else | |
4611 | mel_us = u2_mel_us; | |
4612 | /* xHCI host controller max exit latency field is only 16 bits wide. */ | |
4613 | if (mel_us > MAX_EXIT) { | |
4614 | dev_warn(&udev->dev, "Link PM max exit latency of %lluus " | |
4615 | "is too big.\n", mel_us); | |
4616 | return -E2BIG; | |
4617 | } | |
4618 | return mel_us; | |
4619 | } | |
4620 | ||
4621 | /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */ | |
4622 | int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, | |
4623 | struct usb_device *udev, enum usb3_link_state state) | |
4624 | { | |
4625 | struct xhci_hcd *xhci; | |
4626 | u16 hub_encoded_timeout; | |
4627 | int mel; | |
4628 | int ret; | |
4629 | ||
4630 | xhci = hcd_to_xhci(hcd); | |
4631 | /* The LPM timeout values are pretty host-controller specific, so don't | |
4632 | * enable hub-initiated timeouts unless the vendor has provided | |
4633 | * information about their timeout algorithm. | |
4634 | */ | |
4635 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4636 | !xhci->devs[udev->slot_id]) | |
4637 | return USB3_LPM_DISABLED; | |
4638 | ||
4639 | hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state); | |
4640 | mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout); | |
4641 | if (mel < 0) { | |
4642 | /* Max Exit Latency is too big, disable LPM. */ | |
4643 | hub_encoded_timeout = USB3_LPM_DISABLED; | |
4644 | mel = 0; | |
4645 | } | |
4646 | ||
4647 | ret = xhci_change_max_exit_latency(xhci, udev, mel); | |
4648 | if (ret) | |
4649 | return ret; | |
4650 | return hub_encoded_timeout; | |
4651 | } | |
4652 | ||
4653 | int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, | |
4654 | struct usb_device *udev, enum usb3_link_state state) | |
4655 | { | |
4656 | struct xhci_hcd *xhci; | |
4657 | u16 mel; | |
4658 | int ret; | |
4659 | ||
4660 | xhci = hcd_to_xhci(hcd); | |
4661 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4662 | !xhci->devs[udev->slot_id]) | |
4663 | return 0; | |
4664 | ||
4665 | mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED); | |
4666 | ret = xhci_change_max_exit_latency(xhci, udev, mel); | |
4667 | if (ret) | |
4668 | return ret; | |
4669 | return 0; | |
4670 | } | |
b01bcbf7 | 4671 | #else /* CONFIG_PM */ |
9574323c | 4672 | |
b01bcbf7 SS |
4673 | int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
4674 | struct usb_device *udev, enum usb3_link_state state) | |
65580b43 | 4675 | { |
b01bcbf7 | 4676 | return USB3_LPM_DISABLED; |
65580b43 AX |
4677 | } |
4678 | ||
b01bcbf7 SS |
4679 | int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, |
4680 | struct usb_device *udev, enum usb3_link_state state) | |
9574323c AX |
4681 | { |
4682 | return 0; | |
4683 | } | |
b01bcbf7 | 4684 | #endif /* CONFIG_PM */ |
9574323c | 4685 | |
b01bcbf7 | 4686 | /*-------------------------------------------------------------------------*/ |
9574323c | 4687 | |
ac1c1b7f SS |
4688 | /* Once a hub descriptor is fetched for a device, we need to update the xHC's |
4689 | * internal data structures for the device. | |
4690 | */ | |
4691 | int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, | |
4692 | struct usb_tt *tt, gfp_t mem_flags) | |
4693 | { | |
4694 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4695 | struct xhci_virt_device *vdev; | |
4696 | struct xhci_command *config_cmd; | |
4697 | struct xhci_input_control_ctx *ctrl_ctx; | |
4698 | struct xhci_slot_ctx *slot_ctx; | |
4699 | unsigned long flags; | |
4700 | unsigned think_time; | |
4701 | int ret; | |
4702 | ||
4703 | /* Ignore root hubs */ | |
4704 | if (!hdev->parent) | |
4705 | return 0; | |
4706 | ||
4707 | vdev = xhci->devs[hdev->slot_id]; | |
4708 | if (!vdev) { | |
4709 | xhci_warn(xhci, "Cannot update hub desc for unknown device.\n"); | |
4710 | return -EINVAL; | |
4711 | } | |
a1d78c16 | 4712 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); |
ac1c1b7f SS |
4713 | if (!config_cmd) { |
4714 | xhci_dbg(xhci, "Could not allocate xHCI command structure.\n"); | |
4715 | return -ENOMEM; | |
4716 | } | |
92f8e767 SS |
4717 | ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx); |
4718 | if (!ctrl_ctx) { | |
4719 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
4720 | __func__); | |
4721 | xhci_free_command(xhci, config_cmd); | |
4722 | return -ENOMEM; | |
4723 | } | |
ac1c1b7f SS |
4724 | |
4725 | spin_lock_irqsave(&xhci->lock, flags); | |
839c817c SS |
4726 | if (hdev->speed == USB_SPEED_HIGH && |
4727 | xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) { | |
4728 | xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n"); | |
4729 | xhci_free_command(xhci, config_cmd); | |
4730 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4731 | return -ENOMEM; | |
4732 | } | |
4733 | ||
ac1c1b7f | 4734 | xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx); |
28ccd296 | 4735 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
ac1c1b7f | 4736 | slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx); |
28ccd296 | 4737 | slot_ctx->dev_info |= cpu_to_le32(DEV_HUB); |
ac1c1b7f | 4738 | if (tt->multi) |
28ccd296 | 4739 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
ac1c1b7f SS |
4740 | if (xhci->hci_version > 0x95) { |
4741 | xhci_dbg(xhci, "xHCI version %x needs hub " | |
4742 | "TT think time and number of ports\n", | |
4743 | (unsigned int) xhci->hci_version); | |
28ccd296 | 4744 | slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild)); |
ac1c1b7f SS |
4745 | /* Set TT think time - convert from ns to FS bit times. |
4746 | * 0 = 8 FS bit times, 1 = 16 FS bit times, | |
4747 | * 2 = 24 FS bit times, 3 = 32 FS bit times. | |
700b4173 AX |
4748 | * |
4749 | * xHCI 1.0: this field shall be 0 if the device is not a | |
4750 | * High-spped hub. | |
ac1c1b7f SS |
4751 | */ |
4752 | think_time = tt->think_time; | |
4753 | if (think_time != 0) | |
4754 | think_time = (think_time / 666) - 1; | |
700b4173 AX |
4755 | if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH) |
4756 | slot_ctx->tt_info |= | |
4757 | cpu_to_le32(TT_THINK_TIME(think_time)); | |
ac1c1b7f SS |
4758 | } else { |
4759 | xhci_dbg(xhci, "xHCI version %x doesn't need hub " | |
4760 | "TT think time or number of ports\n", | |
4761 | (unsigned int) xhci->hci_version); | |
4762 | } | |
4763 | slot_ctx->dev_state = 0; | |
4764 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4765 | ||
4766 | xhci_dbg(xhci, "Set up %s for hub device.\n", | |
4767 | (xhci->hci_version > 0x95) ? | |
4768 | "configure endpoint" : "evaluate context"); | |
4769 | xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id); | |
4770 | xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0); | |
4771 | ||
4772 | /* Issue and wait for the configure endpoint or | |
4773 | * evaluate context command. | |
4774 | */ | |
4775 | if (xhci->hci_version > 0x95) | |
4776 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4777 | false, false); | |
4778 | else | |
4779 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4780 | true, false); | |
4781 | ||
4782 | xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id); | |
4783 | xhci_dbg_ctx(xhci, vdev->out_ctx, 0); | |
4784 | ||
4785 | xhci_free_command(xhci, config_cmd); | |
4786 | return ret; | |
4787 | } | |
4788 | ||
66d4eadd SS |
4789 | int xhci_get_frame(struct usb_hcd *hcd) |
4790 | { | |
4791 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4792 | /* EHCI mods by the periodic size. Why? */ | |
b0ba9720 | 4793 | return readl(&xhci->run_regs->microframe_index) >> 3; |
66d4eadd SS |
4794 | } |
4795 | ||
552e0c4f SAS |
4796 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) |
4797 | { | |
4798 | struct xhci_hcd *xhci; | |
4799 | struct device *dev = hcd->self.controller; | |
4800 | int retval; | |
552e0c4f | 4801 | |
1386ff75 SS |
4802 | /* Accept arbitrarily long scatter-gather lists */ |
4803 | hcd->self.sg_tablesize = ~0; | |
fc76051c | 4804 | |
e2ed5114 MN |
4805 | /* support to build packet from discontinuous buffers */ |
4806 | hcd->self.no_sg_constraint = 1; | |
4807 | ||
19181bc5 HG |
4808 | /* XHCI controllers don't stop the ep queue on short packets :| */ |
4809 | hcd->self.no_stop_on_short = 1; | |
552e0c4f SAS |
4810 | |
4811 | if (usb_hcd_is_primary_hcd(hcd)) { | |
4812 | xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL); | |
4813 | if (!xhci) | |
4814 | return -ENOMEM; | |
4815 | *((struct xhci_hcd **) hcd->hcd_priv) = xhci; | |
4816 | xhci->main_hcd = hcd; | |
4817 | /* Mark the first roothub as being USB 2.0. | |
4818 | * The xHCI driver will register the USB 3.0 roothub. | |
4819 | */ | |
4820 | hcd->speed = HCD_USB2; | |
4821 | hcd->self.root_hub->speed = USB_SPEED_HIGH; | |
4822 | /* | |
4823 | * USB 2.0 roothub under xHCI has an integrated TT, | |
4824 | * (rate matching hub) as opposed to having an OHCI/UHCI | |
4825 | * companion controller. | |
4826 | */ | |
4827 | hcd->has_tt = 1; | |
4828 | } else { | |
4829 | /* xHCI private pointer was set in xhci_pci_probe for the second | |
4830 | * registered roothub. | |
4831 | */ | |
552e0c4f SAS |
4832 | return 0; |
4833 | } | |
4834 | ||
4835 | xhci->cap_regs = hcd->regs; | |
4836 | xhci->op_regs = hcd->regs + | |
b0ba9720 | 4837 | HC_LENGTH(readl(&xhci->cap_regs->hc_capbase)); |
552e0c4f | 4838 | xhci->run_regs = hcd->regs + |
b0ba9720 | 4839 | (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK); |
552e0c4f | 4840 | /* Cache read-only capability registers */ |
b0ba9720 XR |
4841 | xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1); |
4842 | xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2); | |
4843 | xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3); | |
4844 | xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase); | |
552e0c4f | 4845 | xhci->hci_version = HC_VERSION(xhci->hcc_params); |
b0ba9720 | 4846 | xhci->hcc_params = readl(&xhci->cap_regs->hcc_params); |
552e0c4f SAS |
4847 | xhci_print_registers(xhci); |
4848 | ||
4e6a1ee7 TI |
4849 | xhci->quirks = quirks; |
4850 | ||
552e0c4f SAS |
4851 | get_quirks(dev, xhci); |
4852 | ||
07f3cb7c GC |
4853 | /* In xhci controllers which follow xhci 1.0 spec gives a spurious |
4854 | * success event after a short transfer. This quirk will ignore such | |
4855 | * spurious event. | |
4856 | */ | |
4857 | if (xhci->hci_version > 0x96) | |
4858 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; | |
4859 | ||
552e0c4f SAS |
4860 | /* Make sure the HC is halted. */ |
4861 | retval = xhci_halt(xhci); | |
4862 | if (retval) | |
4863 | goto error; | |
4864 | ||
4865 | xhci_dbg(xhci, "Resetting HCD\n"); | |
4866 | /* Reset the internal HC memory state and registers. */ | |
4867 | retval = xhci_reset(xhci); | |
4868 | if (retval) | |
4869 | goto error; | |
4870 | xhci_dbg(xhci, "Reset complete\n"); | |
4871 | ||
c10cf118 XR |
4872 | /* Set dma_mask and coherent_dma_mask to 64-bits, |
4873 | * if xHC supports 64-bit addressing */ | |
4874 | if (HCC_64BIT_ADDR(xhci->hcc_params) && | |
4875 | !dma_set_mask(dev, DMA_BIT_MASK(64))) { | |
552e0c4f | 4876 | xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); |
c10cf118 | 4877 | dma_set_coherent_mask(dev, DMA_BIT_MASK(64)); |
552e0c4f SAS |
4878 | } |
4879 | ||
4880 | xhci_dbg(xhci, "Calling HCD init\n"); | |
4881 | /* Initialize HCD and host controller data structures. */ | |
4882 | retval = xhci_init(hcd); | |
4883 | if (retval) | |
4884 | goto error; | |
4885 | xhci_dbg(xhci, "Called HCD init\n"); | |
4886 | return 0; | |
4887 | error: | |
4888 | kfree(xhci); | |
4889 | return retval; | |
4890 | } | |
4891 | ||
66d4eadd SS |
4892 | MODULE_DESCRIPTION(DRIVER_DESC); |
4893 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
4894 | MODULE_LICENSE("GPL"); | |
4895 | ||
4896 | static int __init xhci_hcd_init(void) | |
4897 | { | |
0cc47d54 | 4898 | int retval; |
66d4eadd SS |
4899 | |
4900 | retval = xhci_register_pci(); | |
66d4eadd | 4901 | if (retval < 0) { |
5c1127d3 | 4902 | pr_debug("Problem registering PCI driver.\n"); |
66d4eadd SS |
4903 | return retval; |
4904 | } | |
3429e91a SAS |
4905 | retval = xhci_register_plat(); |
4906 | if (retval < 0) { | |
5c1127d3 | 4907 | pr_debug("Problem registering platform driver.\n"); |
3429e91a SAS |
4908 | goto unreg_pci; |
4909 | } | |
98441973 SS |
4910 | /* |
4911 | * Check the compiler generated sizes of structures that must be laid | |
4912 | * out in specific ways for hardware access. | |
4913 | */ | |
4914 | BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8); | |
4915 | BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8); | |
4916 | BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8); | |
4917 | /* xhci_device_control has eight fields, and also | |
4918 | * embeds one xhci_slot_ctx and 31 xhci_ep_ctx | |
4919 | */ | |
98441973 SS |
4920 | BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8); |
4921 | BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8); | |
4922 | BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8); | |
4923 | BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8); | |
4924 | BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8); | |
4925 | /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */ | |
4926 | BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8); | |
66d4eadd | 4927 | return 0; |
3429e91a SAS |
4928 | unreg_pci: |
4929 | xhci_unregister_pci(); | |
4930 | return retval; | |
66d4eadd SS |
4931 | } |
4932 | module_init(xhci_hcd_init); | |
4933 | ||
4934 | static void __exit xhci_hcd_cleanup(void) | |
4935 | { | |
66d4eadd | 4936 | xhci_unregister_pci(); |
3429e91a | 4937 | xhci_unregister_plat(); |
66d4eadd SS |
4938 | } |
4939 | module_exit(xhci_hcd_cleanup); |