Commit | Line | Data |
---|---|---|
e84fce0f TR |
1 | /* |
2 | * NVIDIA Tegra xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2014 NVIDIA Corporation | |
5 | * Copyright (C) 2014 Google, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/firmware.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of_device.h> | |
20 | #include <linux/phy/phy.h> | |
21 | #include <linux/phy/tegra/xusb.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/pm.h> | |
24 | #include <linux/regulator/consumer.h> | |
25 | #include <linux/reset.h> | |
26 | #include <linux/slab.h> | |
27 | ||
28 | #include "xhci.h" | |
29 | ||
30 | #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 | |
31 | #define TEGRA_XHCI_SS_LOW_SPEED 12000000 | |
32 | ||
33 | /* FPCI CFG registers */ | |
34 | #define XUSB_CFG_1 0x004 | |
35 | #define XUSB_IO_SPACE_EN BIT(0) | |
36 | #define XUSB_MEM_SPACE_EN BIT(1) | |
37 | #define XUSB_BUS_MASTER_EN BIT(2) | |
38 | #define XUSB_CFG_4 0x010 | |
39 | #define XUSB_BASE_ADDR_SHIFT 15 | |
40 | #define XUSB_BASE_ADDR_MASK 0x1ffff | |
41 | #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c | |
42 | #define XUSB_CFG_CSB_BASE_ADDR 0x800 | |
43 | ||
44 | /* FPCI mailbox registers */ | |
45 | #define XUSB_CFG_ARU_MBOX_CMD 0x0e4 | |
46 | #define MBOX_DEST_FALC BIT(27) | |
47 | #define MBOX_DEST_PME BIT(28) | |
48 | #define MBOX_DEST_SMI BIT(29) | |
49 | #define MBOX_DEST_XHCI BIT(30) | |
50 | #define MBOX_INT_EN BIT(31) | |
51 | #define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8 | |
52 | #define CMD_DATA_SHIFT 0 | |
53 | #define CMD_DATA_MASK 0xffffff | |
54 | #define CMD_TYPE_SHIFT 24 | |
55 | #define CMD_TYPE_MASK 0xff | |
56 | #define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec | |
57 | #define XUSB_CFG_ARU_MBOX_OWNER 0x0f0 | |
58 | #define MBOX_OWNER_NONE 0 | |
59 | #define MBOX_OWNER_FW 1 | |
60 | #define MBOX_OWNER_SW 2 | |
61 | #define XUSB_CFG_ARU_SMI_INTR 0x428 | |
62 | #define MBOX_SMI_INTR_FW_HANG BIT(1) | |
63 | #define MBOX_SMI_INTR_EN BIT(3) | |
64 | ||
65 | /* IPFS registers */ | |
66 | #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180 | |
67 | #define IPFS_EN_FPCI BIT(0) | |
68 | #define IPFS_XUSB_HOST_INTR_MASK_0 0x188 | |
69 | #define IPFS_IP_INT_MASK BIT(16) | |
70 | #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc | |
71 | ||
72 | #define CSB_PAGE_SELECT_MASK 0x7fffff | |
73 | #define CSB_PAGE_SELECT_SHIFT 9 | |
74 | #define CSB_PAGE_OFFSET_MASK 0x1ff | |
75 | #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \ | |
76 | CSB_PAGE_SELECT_MASK) | |
77 | #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK) | |
78 | ||
79 | /* Falcon CSB registers */ | |
80 | #define XUSB_FALC_CPUCTL 0x100 | |
81 | #define CPUCTL_STARTCPU BIT(1) | |
82 | #define CPUCTL_STATE_HALTED BIT(4) | |
83 | #define CPUCTL_STATE_STOPPED BIT(5) | |
84 | #define XUSB_FALC_BOOTVEC 0x104 | |
85 | #define XUSB_FALC_DMACTL 0x10c | |
86 | #define XUSB_FALC_IMFILLRNG1 0x154 | |
87 | #define IMFILLRNG1_TAG_MASK 0xffff | |
88 | #define IMFILLRNG1_TAG_LO_SHIFT 0 | |
89 | #define IMFILLRNG1_TAG_HI_SHIFT 16 | |
90 | #define XUSB_FALC_IMFILLCTL 0x158 | |
91 | ||
92 | /* MP CSB registers */ | |
93 | #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 | |
94 | #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 | |
95 | #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08 | |
96 | #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10 | |
97 | #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8 | |
98 | #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff | |
99 | #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24 | |
100 | #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff | |
101 | #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14 | |
102 | #define L2IMEMOP_ACTION_SHIFT 24 | |
103 | #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT) | |
104 | #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT) | |
105 | #define XUSB_CSB_MP_APMAP 0x10181c | |
106 | #define APMAP_BOOTPATH BIT(31) | |
107 | ||
108 | #define IMEM_BLOCK_SIZE 256 | |
109 | ||
110 | struct tegra_xusb_fw_header { | |
111 | u32 boot_loadaddr_in_imem; | |
112 | u32 boot_codedfi_offset; | |
113 | u32 boot_codetag; | |
114 | u32 boot_codesize; | |
115 | u32 phys_memaddr; | |
116 | u16 reqphys_memsize; | |
117 | u16 alloc_phys_memsize; | |
118 | u32 rodata_img_offset; | |
119 | u32 rodata_section_start; | |
120 | u32 rodata_section_end; | |
121 | u32 main_fnaddr; | |
122 | u32 fwimg_cksum; | |
123 | u32 fwimg_created_time; | |
124 | u32 imem_resident_start; | |
125 | u32 imem_resident_end; | |
126 | u32 idirect_start; | |
127 | u32 idirect_end; | |
128 | u32 l2_imem_start; | |
129 | u32 l2_imem_end; | |
130 | u32 version_id; | |
131 | u8 init_ddirect; | |
132 | u8 reserved[3]; | |
133 | u32 phys_addr_log_buffer; | |
134 | u32 total_log_entries; | |
135 | u32 dequeue_ptr; | |
136 | u32 dummy_var[2]; | |
137 | u32 fwimg_len; | |
138 | u8 magic[8]; | |
139 | u32 ss_low_power_entry_timeout; | |
140 | u8 num_hsic_port; | |
141 | u8 padding[139]; /* Pad to 256 bytes */ | |
142 | }; | |
143 | ||
144 | struct tegra_xusb_phy_type { | |
145 | const char *name; | |
146 | unsigned int num; | |
147 | }; | |
148 | ||
149 | struct tegra_xusb_soc { | |
150 | const char *firmware; | |
151 | const char * const *supply_names; | |
152 | unsigned int num_supplies; | |
153 | const struct tegra_xusb_phy_type *phy_types; | |
154 | unsigned int num_types; | |
155 | ||
156 | struct { | |
157 | struct { | |
158 | unsigned int offset; | |
159 | unsigned int count; | |
160 | } usb2, ulpi, hsic, usb3; | |
161 | } ports; | |
ab065e96 TR |
162 | |
163 | bool scale_ss_clock; | |
e84fce0f TR |
164 | }; |
165 | ||
166 | struct tegra_xusb { | |
167 | struct device *dev; | |
168 | void __iomem *regs; | |
169 | struct usb_hcd *hcd; | |
170 | ||
171 | struct mutex lock; | |
172 | ||
173 | int xhci_irq; | |
174 | int mbox_irq; | |
175 | ||
176 | void __iomem *ipfs_base; | |
177 | void __iomem *fpci_base; | |
178 | ||
179 | const struct tegra_xusb_soc *soc; | |
180 | ||
181 | struct regulator_bulk_data *supplies; | |
182 | ||
183 | struct tegra_xusb_padctl *padctl; | |
184 | ||
185 | struct clk *host_clk; | |
186 | struct clk *falcon_clk; | |
187 | struct clk *ss_clk; | |
188 | struct clk *ss_src_clk; | |
189 | struct clk *hs_src_clk; | |
190 | struct clk *fs_src_clk; | |
191 | struct clk *pll_u_480m; | |
192 | struct clk *clk_m; | |
193 | struct clk *pll_e; | |
194 | ||
195 | struct reset_control *host_rst; | |
196 | struct reset_control *ss_rst; | |
197 | ||
198 | struct phy **phys; | |
199 | unsigned int num_phys; | |
200 | ||
201 | /* Firmware loading related */ | |
202 | struct { | |
203 | size_t size; | |
204 | void *virt; | |
205 | dma_addr_t phys; | |
206 | } fw; | |
207 | }; | |
208 | ||
209 | static struct hc_driver __read_mostly tegra_xhci_hc_driver; | |
210 | ||
211 | static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) | |
212 | { | |
213 | return readl(tegra->fpci_base + offset); | |
214 | } | |
215 | ||
216 | static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, | |
217 | unsigned int offset) | |
218 | { | |
219 | writel(value, tegra->fpci_base + offset); | |
220 | } | |
221 | ||
222 | static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) | |
223 | { | |
224 | return readl(tegra->ipfs_base + offset); | |
225 | } | |
226 | ||
227 | static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, | |
228 | unsigned int offset) | |
229 | { | |
230 | writel(value, tegra->ipfs_base + offset); | |
231 | } | |
232 | ||
233 | static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) | |
234 | { | |
235 | u32 page = CSB_PAGE_SELECT(offset); | |
236 | u32 ofs = CSB_PAGE_OFFSET(offset); | |
237 | ||
238 | fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); | |
239 | ||
240 | return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); | |
241 | } | |
242 | ||
243 | static void csb_writel(struct tegra_xusb *tegra, u32 value, | |
244 | unsigned int offset) | |
245 | { | |
246 | u32 page = CSB_PAGE_SELECT(offset); | |
247 | u32 ofs = CSB_PAGE_OFFSET(offset); | |
248 | ||
249 | fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); | |
250 | fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); | |
251 | } | |
252 | ||
253 | static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, | |
254 | unsigned long rate) | |
255 | { | |
256 | unsigned long new_parent_rate, old_parent_rate; | |
257 | struct clk *clk = tegra->ss_src_clk; | |
258 | unsigned int div; | |
259 | int err; | |
260 | ||
261 | if (clk_get_rate(clk) == rate) | |
262 | return 0; | |
263 | ||
264 | switch (rate) { | |
265 | case TEGRA_XHCI_SS_HIGH_SPEED: | |
266 | /* | |
267 | * Reparent to PLLU_480M. Set divider first to avoid | |
268 | * overclocking. | |
269 | */ | |
270 | old_parent_rate = clk_get_rate(clk_get_parent(clk)); | |
271 | new_parent_rate = clk_get_rate(tegra->pll_u_480m); | |
272 | div = new_parent_rate / rate; | |
273 | ||
274 | err = clk_set_rate(clk, old_parent_rate / div); | |
275 | if (err) | |
276 | return err; | |
277 | ||
278 | err = clk_set_parent(clk, tegra->pll_u_480m); | |
279 | if (err) | |
280 | return err; | |
281 | ||
282 | /* | |
283 | * The rate should already be correct, but set it again just | |
284 | * to be sure. | |
285 | */ | |
286 | err = clk_set_rate(clk, rate); | |
287 | if (err) | |
288 | return err; | |
289 | ||
290 | break; | |
291 | ||
292 | case TEGRA_XHCI_SS_LOW_SPEED: | |
293 | /* Reparent to CLK_M */ | |
294 | err = clk_set_parent(clk, tegra->clk_m); | |
295 | if (err) | |
296 | return err; | |
297 | ||
298 | err = clk_set_rate(clk, rate); | |
299 | if (err) | |
300 | return err; | |
301 | ||
302 | break; | |
303 | ||
304 | default: | |
305 | dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate); | |
306 | return -EINVAL; | |
307 | } | |
308 | ||
309 | if (clk_get_rate(clk) != rate) { | |
310 | dev_err(tegra->dev, "SS clock doesn't match requested rate\n"); | |
311 | return -EINVAL; | |
312 | } | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | static unsigned long extract_field(u32 value, unsigned int start, | |
318 | unsigned int count) | |
319 | { | |
320 | return (value >> start) & ((1 << count) - 1); | |
321 | } | |
322 | ||
323 | /* Command requests from the firmware */ | |
324 | enum tegra_xusb_mbox_cmd { | |
325 | MBOX_CMD_MSG_ENABLED = 1, | |
326 | MBOX_CMD_INC_FALC_CLOCK, | |
327 | MBOX_CMD_DEC_FALC_CLOCK, | |
328 | MBOX_CMD_INC_SSPI_CLOCK, | |
329 | MBOX_CMD_DEC_SSPI_CLOCK, | |
330 | MBOX_CMD_SET_BW, /* no ACK/NAK required */ | |
331 | MBOX_CMD_SET_SS_PWR_GATING, | |
332 | MBOX_CMD_SET_SS_PWR_UNGATING, | |
333 | MBOX_CMD_SAVE_DFE_CTLE_CTX, | |
334 | MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */ | |
335 | MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */ | |
336 | MBOX_CMD_START_HSIC_IDLE, | |
337 | MBOX_CMD_STOP_HSIC_IDLE, | |
338 | MBOX_CMD_DBC_WAKE_STACK, /* unused */ | |
339 | MBOX_CMD_HSIC_PRETEND_CONNECT, | |
340 | MBOX_CMD_RESET_SSPI, | |
341 | MBOX_CMD_DISABLE_SS_LFPS_DETECTION, | |
342 | MBOX_CMD_ENABLE_SS_LFPS_DETECTION, | |
343 | ||
344 | MBOX_CMD_MAX, | |
345 | ||
346 | /* Response message to above commands */ | |
347 | MBOX_CMD_ACK = 128, | |
348 | MBOX_CMD_NAK | |
349 | }; | |
350 | ||
351 | static const char * const mbox_cmd_name[] = { | |
352 | [ 1] = "MSG_ENABLE", | |
353 | [ 2] = "INC_FALCON_CLOCK", | |
354 | [ 3] = "DEC_FALCON_CLOCK", | |
355 | [ 4] = "INC_SSPI_CLOCK", | |
356 | [ 5] = "DEC_SSPI_CLOCK", | |
357 | [ 6] = "SET_BW", | |
358 | [ 7] = "SET_SS_PWR_GATING", | |
359 | [ 8] = "SET_SS_PWR_UNGATING", | |
360 | [ 9] = "SAVE_DFE_CTLE_CTX", | |
361 | [ 10] = "AIRPLANE_MODE_ENABLED", | |
362 | [ 11] = "AIRPLANE_MODE_DISABLED", | |
363 | [ 12] = "START_HSIC_IDLE", | |
364 | [ 13] = "STOP_HSIC_IDLE", | |
365 | [ 14] = "DBC_WAKE_STACK", | |
366 | [ 15] = "HSIC_PRETEND_CONNECT", | |
367 | [ 16] = "RESET_SSPI", | |
368 | [ 17] = "DISABLE_SS_LFPS_DETECTION", | |
369 | [ 18] = "ENABLE_SS_LFPS_DETECTION", | |
370 | [128] = "ACK", | |
371 | [129] = "NAK", | |
372 | }; | |
373 | ||
374 | struct tegra_xusb_mbox_msg { | |
375 | u32 cmd; | |
376 | u32 data; | |
377 | }; | |
378 | ||
379 | static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg) | |
380 | { | |
381 | return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT | | |
382 | (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT; | |
383 | } | |
384 | static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg, | |
385 | u32 value) | |
386 | { | |
387 | msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK; | |
388 | msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK; | |
389 | } | |
390 | ||
391 | static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) | |
392 | { | |
393 | switch (cmd) { | |
394 | case MBOX_CMD_SET_BW: | |
395 | case MBOX_CMD_ACK: | |
396 | case MBOX_CMD_NAK: | |
397 | return false; | |
398 | ||
399 | default: | |
400 | return true; | |
401 | } | |
402 | } | |
403 | ||
404 | static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, | |
405 | const struct tegra_xusb_mbox_msg *msg) | |
406 | { | |
407 | bool wait_for_idle = false; | |
408 | u32 value; | |
409 | ||
410 | /* | |
411 | * Acquire the mailbox. The firmware still owns the mailbox for | |
412 | * ACK/NAK messages. | |
413 | */ | |
414 | if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { | |
415 | value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); | |
416 | if (value != MBOX_OWNER_NONE) { | |
417 | dev_err(tegra->dev, "mailbox is busy\n"); | |
418 | return -EBUSY; | |
419 | } | |
420 | ||
421 | fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER); | |
422 | ||
423 | value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); | |
424 | if (value != MBOX_OWNER_SW) { | |
425 | dev_err(tegra->dev, "failed to acquire mailbox\n"); | |
426 | return -EBUSY; | |
427 | } | |
428 | ||
429 | wait_for_idle = true; | |
430 | } | |
431 | ||
432 | value = tegra_xusb_mbox_pack(msg); | |
433 | fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN); | |
434 | ||
435 | value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD); | |
436 | value |= MBOX_INT_EN | MBOX_DEST_FALC; | |
437 | fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD); | |
438 | ||
439 | if (wait_for_idle) { | |
440 | unsigned long timeout = jiffies + msecs_to_jiffies(250); | |
441 | ||
442 | while (time_before(jiffies, timeout)) { | |
443 | value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); | |
444 | if (value == MBOX_OWNER_NONE) | |
445 | break; | |
446 | ||
447 | usleep_range(10, 20); | |
448 | } | |
449 | ||
450 | if (time_after(jiffies, timeout)) | |
451 | value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER); | |
452 | ||
453 | if (value != MBOX_OWNER_NONE) | |
454 | return -ETIMEDOUT; | |
455 | } | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) | |
461 | { | |
462 | struct tegra_xusb *tegra = data; | |
463 | u32 value; | |
464 | ||
465 | /* clear mailbox interrupts */ | |
466 | value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR); | |
467 | fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR); | |
468 | ||
469 | if (value & MBOX_SMI_INTR_FW_HANG) | |
470 | dev_err(tegra->dev, "controller firmware hang\n"); | |
471 | ||
472 | return IRQ_WAKE_THREAD; | |
473 | } | |
474 | ||
475 | static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, | |
476 | const struct tegra_xusb_mbox_msg *msg) | |
477 | { | |
478 | struct tegra_xusb_padctl *padctl = tegra->padctl; | |
479 | const struct tegra_xusb_soc *soc = tegra->soc; | |
480 | struct device *dev = tegra->dev; | |
481 | struct tegra_xusb_mbox_msg rsp; | |
482 | unsigned long mask; | |
483 | unsigned int port; | |
484 | bool idle, enable; | |
485 | int err; | |
486 | ||
487 | memset(&rsp, 0, sizeof(rsp)); | |
488 | ||
489 | switch (msg->cmd) { | |
490 | case MBOX_CMD_INC_FALC_CLOCK: | |
491 | case MBOX_CMD_DEC_FALC_CLOCK: | |
492 | rsp.data = clk_get_rate(tegra->falcon_clk) / 1000; | |
493 | if (rsp.data != msg->data) | |
494 | rsp.cmd = MBOX_CMD_NAK; | |
495 | else | |
496 | rsp.cmd = MBOX_CMD_ACK; | |
497 | ||
498 | break; | |
499 | ||
500 | case MBOX_CMD_INC_SSPI_CLOCK: | |
501 | case MBOX_CMD_DEC_SSPI_CLOCK: | |
ab065e96 TR |
502 | if (tegra->soc->scale_ss_clock) { |
503 | err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000); | |
504 | if (err < 0) | |
505 | rsp.cmd = MBOX_CMD_NAK; | |
506 | else | |
507 | rsp.cmd = MBOX_CMD_ACK; | |
508 | ||
509 | rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000; | |
510 | } else { | |
e84fce0f | 511 | rsp.cmd = MBOX_CMD_ACK; |
ab065e96 TR |
512 | rsp.data = msg->data; |
513 | } | |
e84fce0f | 514 | |
e84fce0f TR |
515 | break; |
516 | ||
517 | case MBOX_CMD_SET_BW: | |
518 | /* | |
519 | * TODO: Request bandwidth once EMC scaling is supported. | |
520 | * Ignore for now since ACK/NAK is not required for SET_BW | |
521 | * messages. | |
522 | */ | |
523 | break; | |
524 | ||
525 | case MBOX_CMD_SAVE_DFE_CTLE_CTX: | |
526 | err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data); | |
527 | if (err < 0) { | |
528 | dev_err(dev, "failed to save context for USB3#%u: %d\n", | |
529 | msg->data, err); | |
530 | rsp.cmd = MBOX_CMD_NAK; | |
531 | } else { | |
532 | rsp.cmd = MBOX_CMD_ACK; | |
533 | } | |
534 | ||
535 | rsp.data = msg->data; | |
536 | break; | |
537 | ||
538 | case MBOX_CMD_START_HSIC_IDLE: | |
539 | case MBOX_CMD_STOP_HSIC_IDLE: | |
540 | if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE) | |
541 | idle = false; | |
542 | else | |
543 | idle = true; | |
544 | ||
545 | mask = extract_field(msg->data, 1 + soc->ports.hsic.offset, | |
546 | soc->ports.hsic.count); | |
547 | ||
548 | for_each_set_bit(port, &mask, 32) { | |
549 | err = tegra_xusb_padctl_hsic_set_idle(padctl, port, | |
550 | idle); | |
551 | if (err < 0) | |
552 | break; | |
553 | } | |
554 | ||
555 | if (err < 0) { | |
556 | dev_err(dev, "failed to set HSIC#%u %s: %d\n", port, | |
557 | idle ? "idle" : "busy", err); | |
558 | rsp.cmd = MBOX_CMD_NAK; | |
559 | } else { | |
560 | rsp.cmd = MBOX_CMD_ACK; | |
561 | } | |
562 | ||
563 | rsp.data = msg->data; | |
564 | break; | |
565 | ||
566 | case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: | |
567 | case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: | |
568 | if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION) | |
569 | enable = false; | |
570 | else | |
571 | enable = true; | |
572 | ||
573 | mask = extract_field(msg->data, 1 + soc->ports.usb3.offset, | |
574 | soc->ports.usb3.count); | |
575 | ||
576 | for_each_set_bit(port, &mask, soc->ports.usb3.count) { | |
577 | err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl, | |
578 | port, | |
579 | enable); | |
580 | if (err < 0) | |
581 | break; | |
582 | } | |
583 | ||
584 | if (err < 0) { | |
585 | dev_err(dev, | |
586 | "failed to %s LFPS detection on USB3#%u: %d\n", | |
587 | enable ? "enable" : "disable", port, err); | |
588 | rsp.cmd = MBOX_CMD_NAK; | |
589 | } else { | |
590 | rsp.cmd = MBOX_CMD_ACK; | |
591 | } | |
592 | ||
593 | rsp.data = msg->data; | |
594 | break; | |
595 | ||
596 | default: | |
597 | dev_warn(dev, "unknown message: %#x\n", msg->cmd); | |
598 | break; | |
599 | } | |
600 | ||
601 | if (rsp.cmd) { | |
602 | const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK"; | |
603 | ||
604 | err = tegra_xusb_mbox_send(tegra, &rsp); | |
605 | if (err < 0) | |
606 | dev_err(dev, "failed to send %s: %d\n", cmd, err); | |
607 | } | |
608 | } | |
609 | ||
610 | static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) | |
611 | { | |
612 | struct tegra_xusb *tegra = data; | |
613 | struct tegra_xusb_mbox_msg msg; | |
614 | u32 value; | |
615 | ||
616 | mutex_lock(&tegra->lock); | |
617 | ||
618 | value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT); | |
619 | tegra_xusb_mbox_unpack(&msg, value); | |
620 | ||
621 | value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD); | |
622 | value &= ~MBOX_DEST_SMI; | |
623 | fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD); | |
624 | ||
625 | /* clear mailbox owner if no ACK/NAK is required */ | |
626 | if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) | |
627 | fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER); | |
628 | ||
629 | tegra_xusb_mbox_handle(tegra, &msg); | |
630 | ||
631 | mutex_unlock(&tegra->lock); | |
632 | return IRQ_HANDLED; | |
633 | } | |
634 | ||
635 | static void tegra_xusb_ipfs_config(struct tegra_xusb *tegra, | |
636 | struct resource *regs) | |
637 | { | |
638 | u32 value; | |
639 | ||
640 | value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0); | |
641 | value |= IPFS_EN_FPCI; | |
642 | ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0); | |
643 | ||
644 | usleep_range(10, 20); | |
645 | ||
646 | /* Program BAR0 space */ | |
647 | value = fpci_readl(tegra, XUSB_CFG_4); | |
648 | value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); | |
649 | value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); | |
650 | fpci_writel(tegra, value, XUSB_CFG_4); | |
651 | ||
652 | usleep_range(100, 200); | |
653 | ||
654 | /* Enable bus master */ | |
655 | value = fpci_readl(tegra, XUSB_CFG_1); | |
656 | value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN; | |
657 | fpci_writel(tegra, value, XUSB_CFG_1); | |
658 | ||
659 | /* Enable interrupt assertion */ | |
660 | value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0); | |
661 | value |= IPFS_IP_INT_MASK; | |
662 | ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0); | |
663 | ||
664 | /* Set hysteresis */ | |
665 | ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0); | |
666 | } | |
667 | ||
668 | static int tegra_xusb_clk_enable(struct tegra_xusb *tegra) | |
669 | { | |
670 | int err; | |
671 | ||
672 | err = clk_prepare_enable(tegra->pll_e); | |
673 | if (err < 0) | |
674 | return err; | |
675 | ||
676 | err = clk_prepare_enable(tegra->host_clk); | |
677 | if (err < 0) | |
678 | goto disable_plle; | |
679 | ||
680 | err = clk_prepare_enable(tegra->ss_clk); | |
681 | if (err < 0) | |
682 | goto disable_host; | |
683 | ||
684 | err = clk_prepare_enable(tegra->falcon_clk); | |
685 | if (err < 0) | |
686 | goto disable_ss; | |
687 | ||
688 | err = clk_prepare_enable(tegra->fs_src_clk); | |
689 | if (err < 0) | |
690 | goto disable_falc; | |
691 | ||
692 | err = clk_prepare_enable(tegra->hs_src_clk); | |
693 | if (err < 0) | |
694 | goto disable_fs_src; | |
695 | ||
ab065e96 TR |
696 | if (tegra->soc->scale_ss_clock) { |
697 | err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED); | |
698 | if (err < 0) | |
699 | goto disable_hs_src; | |
700 | } | |
e84fce0f TR |
701 | |
702 | return 0; | |
703 | ||
704 | disable_hs_src: | |
705 | clk_disable_unprepare(tegra->hs_src_clk); | |
706 | disable_fs_src: | |
707 | clk_disable_unprepare(tegra->fs_src_clk); | |
708 | disable_falc: | |
709 | clk_disable_unprepare(tegra->falcon_clk); | |
710 | disable_ss: | |
711 | clk_disable_unprepare(tegra->ss_clk); | |
712 | disable_host: | |
713 | clk_disable_unprepare(tegra->host_clk); | |
714 | disable_plle: | |
715 | clk_disable_unprepare(tegra->pll_e); | |
716 | return err; | |
717 | } | |
718 | ||
719 | static void tegra_xusb_clk_disable(struct tegra_xusb *tegra) | |
720 | { | |
721 | clk_disable_unprepare(tegra->pll_e); | |
722 | clk_disable_unprepare(tegra->host_clk); | |
723 | clk_disable_unprepare(tegra->ss_clk); | |
724 | clk_disable_unprepare(tegra->falcon_clk); | |
725 | clk_disable_unprepare(tegra->fs_src_clk); | |
726 | clk_disable_unprepare(tegra->hs_src_clk); | |
727 | } | |
728 | ||
729 | static int tegra_xusb_phy_enable(struct tegra_xusb *tegra) | |
730 | { | |
731 | unsigned int i; | |
732 | int err; | |
733 | ||
734 | for (i = 0; i < tegra->num_phys; i++) { | |
735 | err = phy_init(tegra->phys[i]); | |
736 | if (err) | |
737 | goto disable_phy; | |
738 | ||
739 | err = phy_power_on(tegra->phys[i]); | |
740 | if (err) { | |
741 | phy_exit(tegra->phys[i]); | |
742 | goto disable_phy; | |
743 | } | |
744 | } | |
745 | ||
746 | return 0; | |
747 | ||
748 | disable_phy: | |
749 | while (i--) { | |
750 | phy_power_off(tegra->phys[i]); | |
751 | phy_exit(tegra->phys[i]); | |
752 | } | |
753 | ||
754 | return err; | |
755 | } | |
756 | ||
757 | static void tegra_xusb_phy_disable(struct tegra_xusb *tegra) | |
758 | { | |
759 | unsigned int i; | |
760 | ||
761 | for (i = 0; i < tegra->num_phys; i++) { | |
762 | phy_power_off(tegra->phys[i]); | |
763 | phy_exit(tegra->phys[i]); | |
764 | } | |
765 | } | |
766 | ||
767 | static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) | |
768 | { | |
769 | unsigned int code_tag_blocks, code_size_blocks, code_blocks; | |
770 | struct tegra_xusb_fw_header *header; | |
771 | struct device *dev = tegra->dev; | |
772 | const struct firmware *fw; | |
773 | unsigned long timeout; | |
774 | time_t timestamp; | |
775 | struct tm time; | |
776 | u64 address; | |
777 | u32 value; | |
778 | int err; | |
779 | ||
780 | err = request_firmware(&fw, tegra->soc->firmware, tegra->dev); | |
781 | if (err < 0) { | |
782 | dev_err(tegra->dev, "failed to request firmware: %d\n", err); | |
783 | return err; | |
784 | } | |
785 | ||
786 | /* Load Falcon controller with its firmware. */ | |
787 | header = (struct tegra_xusb_fw_header *)fw->data; | |
788 | tegra->fw.size = le32_to_cpu(header->fwimg_len); | |
789 | ||
790 | tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size, | |
791 | &tegra->fw.phys, GFP_KERNEL); | |
792 | if (!tegra->fw.virt) { | |
793 | dev_err(tegra->dev, "failed to allocate memory for firmware\n"); | |
794 | release_firmware(fw); | |
795 | return -ENOMEM; | |
796 | } | |
797 | ||
798 | header = (struct tegra_xusb_fw_header *)tegra->fw.virt; | |
799 | memcpy(tegra->fw.virt, fw->data, tegra->fw.size); | |
800 | release_firmware(fw); | |
801 | ||
802 | if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { | |
803 | dev_info(dev, "Firmware already loaded, Falcon state %#x\n", | |
804 | csb_readl(tegra, XUSB_FALC_CPUCTL)); | |
805 | return 0; | |
806 | } | |
807 | ||
808 | /* Program the size of DFI into ILOAD_ATTR. */ | |
809 | csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR); | |
810 | ||
811 | /* | |
812 | * Boot code of the firmware reads the ILOAD_BASE registers | |
813 | * to get to the start of the DFI in system memory. | |
814 | */ | |
815 | address = tegra->fw.phys + sizeof(*header); | |
816 | csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI); | |
817 | csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO); | |
818 | ||
819 | /* Set BOOTPATH to 1 in APMAP. */ | |
820 | csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP); | |
821 | ||
822 | /* Invalidate L2IMEM. */ | |
823 | csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG); | |
824 | ||
825 | /* | |
826 | * Initiate fetch of bootcode from system memory into L2IMEM. | |
827 | * Program bootcode location and size in system memory. | |
828 | */ | |
829 | code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag), | |
830 | IMEM_BLOCK_SIZE); | |
831 | code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize), | |
832 | IMEM_BLOCK_SIZE); | |
833 | code_blocks = code_tag_blocks + code_size_blocks; | |
834 | ||
835 | value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) << | |
836 | L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) | | |
837 | ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) << | |
838 | L2IMEMOP_SIZE_SRC_COUNT_SHIFT); | |
839 | csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE); | |
840 | ||
841 | /* Trigger L2IMEM load operation. */ | |
842 | csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT, | |
843 | XUSB_CSB_MP_L2IMEMOP_TRIG); | |
844 | ||
845 | /* Setup Falcon auto-fill. */ | |
846 | csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL); | |
847 | ||
848 | value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) << | |
849 | IMFILLRNG1_TAG_LO_SHIFT) | | |
850 | ((code_blocks & IMFILLRNG1_TAG_MASK) << | |
851 | IMFILLRNG1_TAG_HI_SHIFT); | |
852 | csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1); | |
853 | ||
854 | csb_writel(tegra, 0, XUSB_FALC_DMACTL); | |
855 | ||
856 | msleep(50); | |
857 | ||
858 | csb_writel(tegra, le32_to_cpu(header->boot_codetag), | |
859 | XUSB_FALC_BOOTVEC); | |
860 | ||
861 | /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */ | |
862 | timeout = jiffies + msecs_to_jiffies(5); | |
863 | ||
864 | csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); | |
865 | ||
866 | while (time_before(jiffies, timeout)) { | |
867 | if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED) | |
868 | break; | |
869 | ||
870 | usleep_range(100, 200); | |
871 | } | |
872 | ||
873 | if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) { | |
874 | dev_err(dev, "Falcon failed to start, state: %#x\n", | |
875 | csb_readl(tegra, XUSB_FALC_CPUCTL)); | |
876 | return -EIO; | |
877 | } | |
878 | ||
879 | timestamp = le32_to_cpu(header->fwimg_created_time); | |
880 | time_to_tm(timestamp, 0, &time); | |
881 | ||
882 | dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n", | |
883 | time.tm_year + 1900, time.tm_mon + 1, time.tm_mday, | |
884 | time.tm_hour, time.tm_min, time.tm_sec); | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
889 | static int tegra_xusb_probe(struct platform_device *pdev) | |
890 | { | |
891 | struct tegra_xusb_mbox_msg msg; | |
892 | struct resource *res, *regs; | |
893 | struct tegra_xusb *tegra; | |
894 | struct xhci_hcd *xhci; | |
895 | unsigned int i, j, k; | |
896 | struct phy *phy; | |
897 | int err; | |
898 | ||
899 | BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256); | |
900 | ||
901 | tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); | |
902 | if (!tegra) | |
903 | return -ENOMEM; | |
904 | ||
905 | tegra->soc = of_device_get_match_data(&pdev->dev); | |
906 | mutex_init(&tegra->lock); | |
907 | tegra->dev = &pdev->dev; | |
908 | ||
909 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
910 | tegra->regs = devm_ioremap_resource(&pdev->dev, regs); | |
911 | if (IS_ERR(tegra->regs)) | |
912 | return PTR_ERR(tegra->regs); | |
913 | ||
914 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
915 | tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res); | |
916 | if (IS_ERR(tegra->fpci_base)) | |
917 | return PTR_ERR(tegra->fpci_base); | |
918 | ||
919 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
920 | tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res); | |
921 | if (IS_ERR(tegra->ipfs_base)) | |
922 | return PTR_ERR(tegra->ipfs_base); | |
923 | ||
924 | tegra->xhci_irq = platform_get_irq(pdev, 0); | |
925 | if (tegra->xhci_irq < 0) | |
926 | return tegra->xhci_irq; | |
927 | ||
928 | tegra->mbox_irq = platform_get_irq(pdev, 1); | |
929 | if (tegra->mbox_irq < 0) | |
930 | return tegra->mbox_irq; | |
931 | ||
932 | tegra->padctl = tegra_xusb_padctl_get(&pdev->dev); | |
933 | if (IS_ERR(tegra->padctl)) | |
934 | return PTR_ERR(tegra->padctl); | |
935 | ||
936 | tegra->host_rst = devm_reset_control_get(&pdev->dev, "xusb_host"); | |
937 | if (IS_ERR(tegra->host_rst)) { | |
938 | err = PTR_ERR(tegra->host_rst); | |
939 | dev_err(&pdev->dev, "failed to get xusb_host reset: %d\n", err); | |
940 | goto put_padctl; | |
941 | } | |
942 | ||
943 | tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss"); | |
944 | if (IS_ERR(tegra->ss_rst)) { | |
945 | err = PTR_ERR(tegra->ss_rst); | |
946 | dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", err); | |
947 | goto put_padctl; | |
948 | } | |
949 | ||
950 | tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host"); | |
951 | if (IS_ERR(tegra->host_clk)) { | |
952 | err = PTR_ERR(tegra->host_clk); | |
953 | dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err); | |
954 | goto put_padctl; | |
955 | } | |
956 | ||
957 | tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src"); | |
958 | if (IS_ERR(tegra->falcon_clk)) { | |
959 | err = PTR_ERR(tegra->falcon_clk); | |
960 | dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err); | |
961 | goto put_padctl; | |
962 | } | |
963 | ||
964 | tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss"); | |
965 | if (IS_ERR(tegra->ss_clk)) { | |
966 | err = PTR_ERR(tegra->ss_clk); | |
967 | dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err); | |
968 | goto put_padctl; | |
969 | } | |
970 | ||
971 | tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src"); | |
972 | if (IS_ERR(tegra->ss_src_clk)) { | |
973 | err = PTR_ERR(tegra->ss_src_clk); | |
974 | dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err); | |
975 | goto put_padctl; | |
976 | } | |
977 | ||
978 | tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src"); | |
979 | if (IS_ERR(tegra->hs_src_clk)) { | |
980 | err = PTR_ERR(tegra->hs_src_clk); | |
981 | dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err); | |
982 | goto put_padctl; | |
983 | } | |
984 | ||
985 | tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src"); | |
986 | if (IS_ERR(tegra->fs_src_clk)) { | |
987 | err = PTR_ERR(tegra->fs_src_clk); | |
988 | dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err); | |
989 | goto put_padctl; | |
990 | } | |
991 | ||
992 | tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m"); | |
993 | if (IS_ERR(tegra->pll_u_480m)) { | |
994 | err = PTR_ERR(tegra->pll_u_480m); | |
995 | dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err); | |
996 | goto put_padctl; | |
997 | } | |
998 | ||
999 | tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m"); | |
1000 | if (IS_ERR(tegra->clk_m)) { | |
1001 | err = PTR_ERR(tegra->clk_m); | |
1002 | dev_err(&pdev->dev, "failed to get clk_m: %d\n", err); | |
1003 | goto put_padctl; | |
1004 | } | |
1005 | ||
1006 | tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e"); | |
1007 | if (IS_ERR(tegra->pll_e)) { | |
1008 | err = PTR_ERR(tegra->pll_e); | |
1009 | dev_err(&pdev->dev, "failed to get pll_e: %d\n", err); | |
1010 | goto put_padctl; | |
1011 | } | |
1012 | ||
1013 | tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies, | |
1014 | sizeof(*tegra->supplies), GFP_KERNEL); | |
1015 | if (!tegra->supplies) { | |
1016 | err = -ENOMEM; | |
1017 | goto put_padctl; | |
1018 | } | |
1019 | ||
1020 | for (i = 0; i < tegra->soc->num_supplies; i++) | |
1021 | tegra->supplies[i].supply = tegra->soc->supply_names[i]; | |
1022 | ||
1023 | err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies, | |
1024 | tegra->supplies); | |
1025 | if (err) { | |
1026 | dev_err(&pdev->dev, "failed to get regulators: %d\n", err); | |
1027 | goto put_padctl; | |
1028 | } | |
1029 | ||
1030 | for (i = 0; i < tegra->soc->num_types; i++) | |
1031 | tegra->num_phys += tegra->soc->phy_types[i].num; | |
1032 | ||
1033 | tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys, | |
1034 | sizeof(*tegra->phys), GFP_KERNEL); | |
1035 | if (!tegra->phys) { | |
e84fce0f TR |
1036 | err = -ENOMEM; |
1037 | goto put_padctl; | |
1038 | } | |
1039 | ||
1040 | for (i = 0, k = 0; i < tegra->soc->num_types; i++) { | |
1041 | char prop[8]; | |
1042 | ||
1043 | for (j = 0; j < tegra->soc->phy_types[i].num; j++) { | |
1044 | snprintf(prop, sizeof(prop), "%s-%d", | |
1045 | tegra->soc->phy_types[i].name, j); | |
1046 | ||
1047 | phy = devm_phy_optional_get(&pdev->dev, prop); | |
1048 | if (IS_ERR(phy)) { | |
1049 | dev_err(&pdev->dev, | |
1050 | "failed to get PHY %s: %ld\n", prop, | |
1051 | PTR_ERR(phy)); | |
1052 | err = PTR_ERR(phy); | |
1053 | goto put_padctl; | |
1054 | } | |
1055 | ||
1056 | tegra->phys[k++] = phy; | |
1057 | } | |
1058 | } | |
1059 | ||
1060 | err = tegra_xusb_clk_enable(tegra); | |
1061 | if (err) { | |
1062 | dev_err(&pdev->dev, "failed to enable clocks: %d\n", err); | |
1063 | goto put_padctl; | |
1064 | } | |
1065 | ||
1066 | err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies); | |
1067 | if (err) { | |
1068 | dev_err(&pdev->dev, "failed to enable regulators: %d\n", err); | |
1069 | goto disable_clk; | |
1070 | } | |
1071 | ||
1072 | err = tegra_xusb_phy_enable(tegra); | |
1073 | if (err < 0) { | |
1074 | dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err); | |
1075 | goto disable_regulator; | |
1076 | } | |
1077 | ||
1078 | tegra_xusb_ipfs_config(tegra, regs); | |
1079 | ||
1080 | err = tegra_xusb_load_firmware(tegra); | |
1081 | if (err < 0) { | |
1082 | dev_err(&pdev->dev, "failed to load firmware: %d\n", err); | |
1083 | goto disable_phy; | |
1084 | } | |
1085 | ||
1086 | tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev, | |
1087 | dev_name(&pdev->dev)); | |
1088 | if (!tegra->hcd) { | |
1089 | err = -ENOMEM; | |
1090 | goto disable_phy; | |
1091 | } | |
1092 | ||
1093 | /* | |
1094 | * This must happen after usb_create_hcd(), because usb_create_hcd() | |
1095 | * will overwrite the drvdata of the device with the hcd it creates. | |
1096 | */ | |
1097 | platform_set_drvdata(pdev, tegra); | |
1098 | ||
1099 | tegra->hcd->regs = tegra->regs; | |
1100 | tegra->hcd->rsrc_start = regs->start; | |
1101 | tegra->hcd->rsrc_len = resource_size(regs); | |
1102 | ||
1103 | err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED); | |
1104 | if (err < 0) { | |
1105 | dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err); | |
1106 | goto put_usb2; | |
1107 | } | |
1108 | ||
1109 | device_wakeup_enable(tegra->hcd->self.controller); | |
1110 | ||
1111 | xhci = hcd_to_xhci(tegra->hcd); | |
1112 | ||
1113 | xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver, | |
1114 | &pdev->dev, | |
1115 | dev_name(&pdev->dev), | |
1116 | tegra->hcd); | |
1117 | if (!xhci->shared_hcd) { | |
1118 | dev_err(&pdev->dev, "failed to create shared HCD\n"); | |
b175b38a | 1119 | err = -ENOMEM; |
e84fce0f TR |
1120 | goto remove_usb2; |
1121 | } | |
1122 | ||
1123 | err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED); | |
1124 | if (err < 0) { | |
1125 | dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err); | |
1126 | goto put_usb3; | |
1127 | } | |
1128 | ||
1129 | mutex_lock(&tegra->lock); | |
1130 | ||
1131 | /* Enable firmware messages from controller. */ | |
1132 | msg.cmd = MBOX_CMD_MSG_ENABLED; | |
1133 | msg.data = 0; | |
1134 | ||
1135 | err = tegra_xusb_mbox_send(tegra, &msg); | |
1136 | if (err < 0) { | |
1137 | dev_err(&pdev->dev, "failed to enable messages: %d\n", err); | |
1138 | mutex_unlock(&tegra->lock); | |
1139 | goto remove_usb3; | |
1140 | } | |
1141 | ||
1142 | mutex_unlock(&tegra->lock); | |
1143 | ||
1144 | err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq, | |
1145 | tegra_xusb_mbox_irq, | |
1146 | tegra_xusb_mbox_thread, 0, | |
1147 | dev_name(&pdev->dev), tegra); | |
1148 | if (err < 0) { | |
1149 | dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); | |
1150 | goto remove_usb3; | |
1151 | } | |
1152 | ||
1153 | return 0; | |
1154 | ||
1155 | remove_usb3: | |
1156 | usb_remove_hcd(xhci->shared_hcd); | |
1157 | put_usb3: | |
1158 | usb_put_hcd(xhci->shared_hcd); | |
1159 | remove_usb2: | |
1160 | usb_remove_hcd(tegra->hcd); | |
1161 | put_usb2: | |
1162 | usb_put_hcd(tegra->hcd); | |
1163 | disable_phy: | |
1164 | tegra_xusb_phy_disable(tegra); | |
1165 | disable_regulator: | |
1166 | regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); | |
1167 | disable_clk: | |
1168 | tegra_xusb_clk_disable(tegra); | |
1169 | put_padctl: | |
1170 | tegra_xusb_padctl_put(tegra->padctl); | |
1171 | return err; | |
1172 | } | |
1173 | ||
1174 | static int tegra_xusb_remove(struct platform_device *pdev) | |
1175 | { | |
1176 | struct tegra_xusb *tegra = platform_get_drvdata(pdev); | |
1177 | struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); | |
1178 | ||
1179 | usb_remove_hcd(xhci->shared_hcd); | |
1180 | usb_put_hcd(xhci->shared_hcd); | |
1181 | usb_remove_hcd(tegra->hcd); | |
1182 | usb_put_hcd(tegra->hcd); | |
1183 | ||
1184 | dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, | |
1185 | tegra->fw.phys); | |
1186 | ||
1187 | tegra_xusb_phy_disable(tegra); | |
1188 | regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); | |
1189 | tegra_xusb_clk_disable(tegra); | |
1190 | ||
1191 | tegra_xusb_padctl_put(tegra->padctl); | |
1192 | ||
1193 | return 0; | |
1194 | } | |
1195 | ||
1196 | #ifdef CONFIG_PM_SLEEP | |
1197 | static int tegra_xusb_suspend(struct device *dev) | |
1198 | { | |
1199 | struct tegra_xusb *tegra = dev_get_drvdata(dev); | |
1200 | struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); | |
1201 | bool wakeup = device_may_wakeup(dev); | |
1202 | ||
1203 | /* TODO: Powergate controller across suspend/resume. */ | |
1204 | return xhci_suspend(xhci, wakeup); | |
1205 | } | |
1206 | ||
1207 | static int tegra_xusb_resume(struct device *dev) | |
1208 | { | |
1209 | struct tegra_xusb *tegra = dev_get_drvdata(dev); | |
1210 | struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); | |
1211 | ||
1212 | return xhci_resume(xhci, 0); | |
1213 | } | |
1214 | #endif | |
1215 | ||
1216 | static const struct dev_pm_ops tegra_xusb_pm_ops = { | |
1217 | SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume) | |
1218 | }; | |
1219 | ||
1220 | static const char * const tegra124_supply_names[] = { | |
1221 | "avddio-pex", | |
1222 | "dvddio-pex", | |
1223 | "avdd-usb", | |
1224 | "avdd-pll-utmip", | |
1225 | "avdd-pll-erefe", | |
1226 | "avdd-usb-ss-pll", | |
1227 | "hvdd-usb-ss", | |
1228 | "hvdd-usb-ss-pll-e", | |
1229 | }; | |
1230 | ||
1231 | static const struct tegra_xusb_phy_type tegra124_phy_types[] = { | |
1232 | { .name = "usb3", .num = 2, }, | |
1233 | { .name = "usb2", .num = 3, }, | |
1234 | { .name = "hsic", .num = 2, }, | |
1235 | }; | |
1236 | ||
1237 | static const struct tegra_xusb_soc tegra124_soc = { | |
1238 | .firmware = "nvidia/tegra124/xusb.bin", | |
1239 | .supply_names = tegra124_supply_names, | |
1240 | .num_supplies = ARRAY_SIZE(tegra124_supply_names), | |
1241 | .phy_types = tegra124_phy_types, | |
1242 | .num_types = ARRAY_SIZE(tegra124_phy_types), | |
1243 | .ports = { | |
1244 | .usb2 = { .offset = 4, .count = 4, }, | |
1245 | .hsic = { .offset = 6, .count = 2, }, | |
1246 | .usb3 = { .offset = 0, .count = 2, }, | |
1247 | }, | |
ab065e96 | 1248 | .scale_ss_clock = true, |
e84fce0f TR |
1249 | }; |
1250 | MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); | |
1251 | ||
ab065e96 TR |
1252 | static const char * const tegra210_supply_names[] = { |
1253 | "dvddio-pex", | |
1254 | "hvddio-pex", | |
1255 | "avdd-usb", | |
1256 | "avdd-pll-utmip", | |
1257 | "avdd-pll-uerefe", | |
1258 | "dvdd-pex-pll", | |
1259 | "hvdd-pex-pll-e", | |
1260 | }; | |
1261 | ||
1262 | static const struct tegra_xusb_phy_type tegra210_phy_types[] = { | |
1263 | { .name = "usb3", .num = 4, }, | |
1264 | { .name = "usb2", .num = 4, }, | |
1265 | { .name = "hsic", .num = 1, }, | |
1266 | }; | |
1267 | ||
1268 | static const struct tegra_xusb_soc tegra210_soc = { | |
1269 | .firmware = "nvidia/tegra210/xusb.bin", | |
1270 | .supply_names = tegra210_supply_names, | |
1271 | .num_supplies = ARRAY_SIZE(tegra210_supply_names), | |
1272 | .phy_types = tegra210_phy_types, | |
1273 | .num_types = ARRAY_SIZE(tegra210_phy_types), | |
1274 | .ports = { | |
1275 | .usb2 = { .offset = 4, .count = 4, }, | |
1276 | .hsic = { .offset = 8, .count = 1, }, | |
1277 | .usb3 = { .offset = 0, .count = 4, }, | |
1278 | }, | |
1279 | .scale_ss_clock = false, | |
1280 | }; | |
1281 | MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); | |
1282 | ||
e84fce0f TR |
1283 | static const struct of_device_id tegra_xusb_of_match[] = { |
1284 | { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, | |
ab065e96 | 1285 | { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, |
e84fce0f TR |
1286 | { }, |
1287 | }; | |
1288 | MODULE_DEVICE_TABLE(of, tegra_xusb_of_match); | |
1289 | ||
1290 | static struct platform_driver tegra_xusb_driver = { | |
1291 | .probe = tegra_xusb_probe, | |
1292 | .remove = tegra_xusb_remove, | |
1293 | .driver = { | |
1294 | .name = "tegra-xusb", | |
1295 | .pm = &tegra_xusb_pm_ops, | |
1296 | .of_match_table = tegra_xusb_of_match, | |
1297 | }, | |
1298 | }; | |
1299 | ||
1300 | static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci) | |
1301 | { | |
1302 | xhci->quirks |= XHCI_PLAT; | |
1303 | } | |
1304 | ||
1305 | static int tegra_xhci_setup(struct usb_hcd *hcd) | |
1306 | { | |
1307 | return xhci_gen_setup(hcd, tegra_xhci_quirks); | |
1308 | } | |
1309 | ||
1310 | static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = { | |
e84fce0f TR |
1311 | .reset = tegra_xhci_setup, |
1312 | }; | |
1313 | ||
1314 | static int __init tegra_xusb_init(void) | |
1315 | { | |
1316 | xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides); | |
1317 | ||
1318 | return platform_driver_register(&tegra_xusb_driver); | |
1319 | } | |
1320 | module_init(tegra_xusb_init); | |
1321 | ||
1322 | static void __exit tegra_xusb_exit(void) | |
1323 | { | |
1324 | platform_driver_unregister(&tegra_xusb_driver); | |
1325 | } | |
1326 | module_exit(tegra_xusb_exit); | |
1327 | ||
1328 | MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); | |
1329 | MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver"); | |
1330 | MODULE_LICENSE("GPL v2"); |