[linux-block.git] / drivers / usb / host / xhci-pci.c

/*
 * xHCI host controller driver PCI Bus Glue.
 *
 * Copyright (C) 2008 Intel Corp.
 *
 * Author: Sarah Sharp
 * Some code borrowed from the Linux EHCI driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>

#include "xhci.h"
#include "xhci-trace.h"

/* Device for a quirk */
#define PCI_VENDOR_ID_FRESCO_LOGIC	0x1b73
#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK	0x1000
#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400	0x1400

#define PCI_VENDOR_ID_ETRON		0x1b6f
#define PCI_DEVICE_ID_ASROCK_P67	0x7023

static const char hcd_name[] = "xhci_hcd";

/* called after powerup, by probe or system-pm "wakeup" */
static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
{
	/*
	 * TODO: Implement finding debug ports later.
	 * TODO: see if there are any quirks that need to be added to handle
	 * new extended capabilities.
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	if (!pci_set_mwi(pdev))
		xhci_dbg(xhci, "MWI active\n");

	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	return 0;
}

static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct pci_dev		*pdev = to_pci_dev(dev);

	/* Look for vendor-specific quirks */
	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
			(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
			 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
		if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
				pdev->revision == 0x0) {
			xhci->quirks |= XHCI_RESET_EP_QUIRK;
			xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic xHC needs configure"
				" endpoint cmd after reset endpoint");
		}
		/* Fresco Logic confirms: all revisions of this chip do not
		 * support MSI, even though some of them claim to in their PCI
		 * capabilities.
		 */
		xhci->quirks |= XHCI_BROKEN_MSI;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Fresco Logic revision %u "
				"has broken MSI implementation",
				pdev->revision);
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}

	if (pdev->vendor == PCI_VENDOR_ID_NEC)
		xhci->quirks |= XHCI_NEC_HOST;

	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
		xhci->quirks |= XHCI_AMD_0x96_HOST;

	/* AMD PLL quirk */
	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
		xhci->quirks |= XHCI_AMD_PLL_FIX;
	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		xhci->quirks |= XHCI_LPM_SUPPORT;
		xhci->quirks |= XHCI_INTEL_HOST;
	}
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
			pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
		xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
		xhci->limit_active_eps = 64;
		xhci->quirks |= XHCI_SW_BW_CHECKING;
		/*
		 * PPT desktop boards DH77EB and DH77DF will power back on after
		 * a few seconds of being shutdown.  The fix for this is to
		 * switch the ports from xHCI to EHCI on shutdown.  We can't use
		 * DMI information to find those particular boards (since each
		 * vendor will change the board name), so we have to key off all
		 * PPT chipsets.
		 */
		xhci->quirks |= XHCI_SPURIOUS_REBOOT;
		xhci->quirks |= XHCI_AVOID_BEI;
	}
	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
			pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
		xhci->quirks |= XHCI_RESET_ON_RESUME;
		xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
				"QUIRK: Resetting on resume");
		xhci->quirks |= XHCI_TRUST_TX_LENGTH;
	}
	if (pdev->vendor == PCI_VENDOR_ID_VIA)
		xhci->quirks |= XHCI_RESET_ON_RESUME;
}

/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd		*xhci;
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval;

	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
	if (retval)
		return retval;

	xhci = hcd_to_xhci(hcd);
	if (!usb_hcd_is_primary_hcd(hcd))
		return 0;

	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);

	/* Find any debug ports */
	retval = xhci_pci_reinit(xhci, pdev);
	if (!retval)
		return retval;

	kfree(xhci);
	return retval;
}

/*
 * We need to register our own PCI probe function (instead of the USB core's
 * function) in order to create a second roothub under xHCI.
 */
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
	int retval;
	struct xhci_hcd *xhci;
	struct hc_driver *driver;
	struct usb_hcd *hcd;

	driver = (struct hc_driver *)id->driver_data;
	/* Register the USB 2.0 roothub.
	 * FIXME: USB core must know to register the USB 2.0 roothub first.
	 * This is sort of silly, because we could just set the HCD driver flags
	 * to say USB 2.0, but I'm not sure what the implications would be in
	 * the other parts of the HCD code.
	 */
	retval = usb_hcd_pci_probe(dev, id);

	if (retval)
		return retval;

	/* USB 2.0 roothub is stored in the PCI device now. */
	hcd = dev_get_drvdata(&dev->dev);
	xhci = hcd_to_xhci(hcd);
	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
				pci_name(dev), hcd);
	if (!xhci->shared_hcd) {
		retval = -ENOMEM;
		goto dealloc_usb2_hcd;
	}

	/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
	 * is called by usb_add_hcd().
	 */
	*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;

	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
			IRQF_SHARED);
	if (retval)
		goto put_usb3_hcd;
	/* Roothub already marked as USB 3.0 speed */

	/* We know the LPM timeout algorithms for this host, let the USB core
	 * enable and disable LPM for devices under the USB 3.0 roothub.
	 */
	if (xhci->quirks & XHCI_LPM_SUPPORT)
		hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;

	return 0;

put_usb3_hcd:
	usb_put_hcd(xhci->shared_hcd);
dealloc_usb2_hcd:
	usb_hcd_pci_remove(dev);
	return retval;
}

static void xhci_pci_remove(struct pci_dev *dev)
{
	struct xhci_hcd *xhci;

	xhci = hcd_to_xhci(pci_get_drvdata(dev));
	if (xhci->shared_hcd) {
		usb_remove_hcd(xhci->shared_hcd);
		usb_put_hcd(xhci->shared_hcd);
	}
	usb_hcd_pci_remove(dev);
	kfree(xhci);
}

#ifdef CONFIG_PM
static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
{
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	/*
	 * Systems with the TI redriver that loses port status change events
	 * need to have the registers polled during D3, so avoid D3cold.
	 */
	if (xhci_compliance_mode_recovery_timer_quirk_check())
		pdev->no_d3cold = true;

	return xhci_suspend(xhci);
}

static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct xhci_hcd		*xhci = hcd_to_xhci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	int			retval = 0;

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * It should not matter whether the EHCI or xHCI controller is
	 * resumed first. It's enough to do the switchover in xHCI because
	 * USB core won't notice anything as the hub driver doesn't start
	 * running again until after all the devices (including both EHCI and
	 * xHCI host controllers) have been resumed.
	 */

	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
		usb_enable_intel_xhci_ports(pdev);

	retval = xhci_resume(xhci, hibernated);
	return retval;
}
#endif /* CONFIG_PM */

static const struct hc_driver xhci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"xHCI Host Controller",
	.hcd_priv_size =	sizeof(struct xhci_hcd *),

	/*
	 * generic hardware linkage
	 */
	.irq =			xhci_irq,
	.flags =		HCD_MEMORY | HCD_USB3 | HCD_SHARED,

	/*
	 * basic lifecycle operations
	 */
	.reset =		xhci_pci_setup,
	.start =		xhci_run,
#ifdef CONFIG_PM
	.pci_suspend =          xhci_pci_suspend,
	.pci_resume =           xhci_pci_resume,
#endif
	.stop =			xhci_stop,
	.shutdown =		xhci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		xhci_urb_enqueue,
	.urb_dequeue =		xhci_urb_dequeue,
	.alloc_dev =		xhci_alloc_dev,
	.free_dev =		xhci_free_dev,
	.alloc_streams =	xhci_alloc_streams,
	.free_streams =		xhci_free_streams,
	.add_endpoint =		xhci_add_endpoint,
	.drop_endpoint =	xhci_drop_endpoint,
	.endpoint_reset =	xhci_endpoint_reset,
	.check_bandwidth =	xhci_check_bandwidth,
	.reset_bandwidth =	xhci_reset_bandwidth,
	.address_device =	xhci_address_device,
	.update_hub_device =	xhci_update_hub_device,
	.reset_device =		xhci_discover_or_reset_device,

	/*
	 * scheduling support
	 */
	.get_frame_number =	xhci_get_frame,

	/* Root hub support */
	.hub_control =		xhci_hub_control,
	.hub_status_data =	xhci_hub_status_data,
	.bus_suspend =		xhci_bus_suspend,
	.bus_resume =		xhci_bus_resume,
	/*
	 * call back when device connected and addressed
	 */
	.update_device =        xhci_update_device,
	.set_usb2_hw_lpm =	xhci_set_usb2_hardware_lpm,
	.enable_usb3_lpm_timeout =	xhci_enable_usb3_lpm_timeout,
	.disable_usb3_lpm_timeout =	xhci_disable_usb3_lpm_timeout,
	.find_raw_port_number =	xhci_find_raw_port_number,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids[] = { {
	/* handle any USB 3.0 xHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	.driver_data =	(unsigned long) &xhci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver xhci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	xhci_pci_probe,
	.remove =	xhci_pci_remove,
	/* suspend and resume implemented later */

	.shutdown = 	usb_hcd_pci_shutdown,
#ifdef CONFIG_PM
	.driver = {
		.pm = &usb_hcd_pci_pm_ops
	},
#endif
};

int __init xhci_register_pci(void)
{
	return pci_register_driver(&xhci_pci_driver);
}

void xhci_unregister_pci(void)
{
	pci_unregister_driver(&xhci_pci_driver);
}
Commit	Line	Data
66d4eadd SS	1	/*
	2	* xHCI host controller driver PCI Bus Glue.
	3	*
	4	* Copyright (C) 2008 Intel Corp.
	5	*
	6	* Author: Sarah Sharp
	7	* Some code borrowed from the Linux EHCI driver.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software Foundation,
	20	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <linux/pci.h>
7fc2a616	24	#include <linux/slab.h>
6eb0de82	25	#include <linux/module.h>
66d4eadd SS	26
66d4eadd SS	27	#include "xhci.h"
4bdfe4c3	28	#include "xhci-trace.h"
66d4eadd	29
ac9d8fe7 SS	30	/* Device for a quirk */
	31	#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
	32	#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
bba18e33	33	#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7	34
c877b3b2 ML	35	#define PCI_VENDOR_ID_ETRON 0x1b6f
	36	#define PCI_DEVICE_ID_ASROCK_P67 0x7023
	37
66d4eadd SS	38	static const char hcd_name[] = "xhci_hcd";
	39
	40	/* called after powerup, by probe or system-pm "wakeup" */
	41	static int xhci_pci_reinit(struct xhci_hcd xhci, struct pci_dev pdev)
	42	{
	43	/*
	44	* TODO: Implement finding debug ports later.
	45	* TODO: see if there are any quirks that need to be added to handle
	46	* new extended capabilities.
	47	*/
	48
	49	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	50	if (!pci_set_mwi(pdev))
	51	xhci_dbg(xhci, "MWI active\n");
	52
	53	xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
	54	return 0;
	55	}
	56
da3c9c4f SAS	57	static void xhci_pci_quirks(struct device dev, struct xhci_hcd xhci)
	58	{
	59	struct pci_dev *pdev = to_pci_dev(dev);
	60
ac9d8fe7 SS	61	/* Look for vendor-specific quirks */
ac9d8fe7 SS	62	if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33 SS	63	(pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK \|\|
	64	pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
	65	if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
	66	pdev->revision == 0x0) {
ac9d8fe7	67	xhci->quirks \|= XHCI_RESET_EP_QUIRK;
4bdfe4c3 XR	68	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	69	"QUIRK: Fresco Logic xHC needs configure"
	70	" endpoint cmd after reset endpoint");
f5182b41 SS	71	}
	72	/* Fresco Logic confirms: all revisions of this chip do not
	73	* support MSI, even though some of them claim to in their PCI
	74	* capabilities.
	75	*/
	76	xhci->quirks \|= XHCI_BROKEN_MSI;
4bdfe4c3 XR	77	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
	78	"QUIRK: Fresco Logic revision %u "
	79	"has broken MSI implementation",
f5182b41	80	pdev->revision);
1530bbc6	81	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
ac9d8fe7	82	}
f5182b41	83
0238634d SS	84	if (pdev->vendor == PCI_VENDOR_ID_NEC)
0238634d SS	85	xhci->quirks \|= XHCI_NEC_HOST;
ac9d8fe7	86
7e393a83 AX	87	if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
	88	xhci->quirks \|= XHCI_AMD_0x96_HOST;
	89
c41136b0 AX	90	/* AMD PLL quirk */
	91	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
	92	xhci->quirks \|= XHCI_AMD_PLL_FIX;
e3567d2c SS	93	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
	94	xhci->quirks \|= XHCI_LPM_SUPPORT;
	95	xhci->quirks \|= XHCI_INTEL_HOST;
	96	}
ad808333 SS	97	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
ad808333 SS	98	pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18 SS	99	xhci->quirks \|= XHCI_EP_LIMIT_QUIRK;
2cf95c18 SS	100	xhci->limit_active_eps = 64;
86cc558e	101	xhci->quirks \|= XHCI_SW_BW_CHECKING;
e95829f4 SS	102	/*
	103	* PPT desktop boards DH77EB and DH77DF will power back on after
	104	* a few seconds of being shutdown. The fix for this is to
	105	* switch the ports from xHCI to EHCI on shutdown. We can't use
	106	* DMI information to find those particular boards (since each
	107	* vendor will change the board name), so we have to key off all
	108	* PPT chipsets.
	109	*/
	110	xhci->quirks \|= XHCI_SPURIOUS_REBOOT;
80fab3b2	111	xhci->quirks \|= XHCI_AVOID_BEI;
ad808333	112	}
c877b3b2 ML	113	if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
	114	pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
	115	xhci->quirks \|= XHCI_RESET_ON_RESUME;
4bdfe4c3 XR	116	xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4bdfe4c3 XR	117	"QUIRK: Resetting on resume");
5cb7df2b	118	xhci->quirks \|= XHCI_TRUST_TX_LENGTH;
c877b3b2	119	}
457a4f61 EF	120	if (pdev->vendor == PCI_VENDOR_ID_VIA)
457a4f61 EF	121	xhci->quirks \|= XHCI_RESET_ON_RESUME;
da3c9c4f	122	}
c41136b0	123
da3c9c4f SAS	124	/* called during probe() after chip reset completes */
	125	static int xhci_pci_setup(struct usb_hcd *hcd)
	126	{
	127	struct xhci_hcd *xhci;
	128	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	129	int retval;
66d4eadd	130
da3c9c4f	131	retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd	132	if (retval)
da3c9c4f	133	return retval;
006d5820	134
da3c9c4f SAS	135	xhci = hcd_to_xhci(hcd);
	136	if (!usb_hcd_is_primary_hcd(hcd))
	137	return 0;
66d4eadd SS	138
	139	pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
	140	xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
	141
	142	/* Find any debug ports */
b02d0ed6 SS	143	retval = xhci_pci_reinit(xhci, pdev);
	144	if (!retval)
	145	return retval;
	146
b02d0ed6 SS	147	kfree(xhci);
	148	return retval;
	149	}
	150
f6ff0ac8 SS	151	/*
	152	* We need to register our own PCI probe function (instead of the USB core's
	153	* function) in order to create a second roothub under xHCI.
	154	*/
	155	static int xhci_pci_probe(struct pci_dev dev, const struct pci_device_id id)
	156	{
	157	int retval;
	158	struct xhci_hcd *xhci;
	159	struct hc_driver *driver;
	160	struct usb_hcd *hcd;
	161
	162	driver = (struct hc_driver *)id->driver_data;
	163	/* Register the USB 2.0 roothub.
	164	* FIXME: USB core must know to register the USB 2.0 roothub first.
	165	* This is sort of silly, because we could just set the HCD driver flags
	166	* to say USB 2.0, but I'm not sure what the implications would be in
	167	* the other parts of the HCD code.
	168	*/
	169	retval = usb_hcd_pci_probe(dev, id);
	170
	171	if (retval)
	172	return retval;
	173
	174	/* USB 2.0 roothub is stored in the PCI device now. */
	175	hcd = dev_get_drvdata(&dev->dev);
	176	xhci = hcd_to_xhci(hcd);
	177	xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
	178	pci_name(dev), hcd);
	179	if (!xhci->shared_hcd) {
	180	retval = -ENOMEM;
	181	goto dealloc_usb2_hcd;
	182	}
	183
	184	/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
	185	* is called by usb_add_hcd().
	186	*/
	187	((struct xhci_hcd *) xhci->shared_hcd->hcd_priv) = xhci;
	188
	189	retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8	190	IRQF_SHARED);
f6ff0ac8 SS	191	if (retval)
	192	goto put_usb3_hcd;
	193	/* Roothub already marked as USB 3.0 speed */
3b3db026 SS	194
	195	/* We know the LPM timeout algorithms for this host, let the USB core
	196	* enable and disable LPM for devices under the USB 3.0 roothub.
	197	*/
	198	if (xhci->quirks & XHCI_LPM_SUPPORT)
	199	hcd_to_bus(xhci->shared_hcd)->root_hub->lpm_capable = 1;
	200
f6ff0ac8 SS	201	return 0;
	202
	203	put_usb3_hcd:
	204	usb_put_hcd(xhci->shared_hcd);
	205	dealloc_usb2_hcd:
	206	usb_hcd_pci_remove(dev);
	207	return retval;
	208	}
	209
b02d0ed6 SS	210	static void xhci_pci_remove(struct pci_dev *dev)
	211	{
	212	struct xhci_hcd *xhci;
	213
	214	xhci = hcd_to_xhci(pci_get_drvdata(dev));
f6ff0ac8 SS	215	if (xhci->shared_hcd) {
	216	usb_remove_hcd(xhci->shared_hcd);
	217	usb_put_hcd(xhci->shared_hcd);
	218	}
b02d0ed6 SS	219	usb_hcd_pci_remove(dev);
b02d0ed6 SS	220	kfree(xhci);
66d4eadd SS	221	}
66d4eadd SS	222
5535b1d5 AX	223	#ifdef CONFIG_PM
	224	static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
	225	{
	226	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5 SS	227	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	228
	229	/*
	230	* Systems with the TI redriver that loses port status change events
	231	* need to have the registers polled during D3, so avoid D3cold.
	232	*/
	233	if (xhci_compliance_mode_recovery_timer_quirk_check())
	234	pdev->no_d3cold = true;
5535b1d5	235
77b84767	236	return xhci_suspend(xhci);
5535b1d5 AX	237	}
	238
	239	static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
	240	{
	241	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2	242	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5 AX	243	int retval = 0;
5535b1d5 AX	244
69e848c2 SS	245	/* The BIOS on systems with the Intel Panther Point chipset may or may
	246	* not support xHCI natively. That means that during system resume, it
	247	* may switch the ports back to EHCI so that users can use their
	248	* keyboard to select a kernel from GRUB after resume from hibernate.
	249	*
	250	* The BIOS is supposed to remember whether the OS had xHCI ports
	251	* enabled before resume, and switch the ports back to xHCI when the
	252	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	253	* writers.
	254	*
	255	* Unconditionally switch the ports back to xHCI after a system resume.
26b76798 MN	256	* It should not matter whether the EHCI or xHCI controller is
	257	* resumed first. It's enough to do the switchover in xHCI because
	258	* USB core won't notice anything as the hub driver doesn't start
	259	* running again until after all the devices (including both EHCI and
	260	* xHCI host controllers) have been resumed.
69e848c2	261	*/
26b76798 MN	262
	263	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
	264	usb_enable_intel_xhci_ports(pdev);
69e848c2	265
5535b1d5 AX	266	retval = xhci_resume(xhci, hibernated);
	267	return retval;
	268	}
	269	#endif /* CONFIG_PM */
	270
66d4eadd SS	271	static const struct hc_driver xhci_pci_hc_driver = {
	272	.description = hcd_name,
	273	.product_desc = "xHCI Host Controller",
b02d0ed6	274	.hcd_priv_size = sizeof(struct xhci_hcd *),
66d4eadd SS	275
	276	/*
	277	* generic hardware linkage
	278	*/
7f84eef0	279	.irq = xhci_irq,
f6ff0ac8	280	.flags = HCD_MEMORY \| HCD_USB3 \| HCD_SHARED,
66d4eadd SS	281
	282	/*
	283	* basic lifecycle operations
	284	*/
	285	.reset = xhci_pci_setup,
	286	.start = xhci_run,
5535b1d5 AX	287	#ifdef CONFIG_PM
	288	.pci_suspend = xhci_pci_suspend,
	289	.pci_resume = xhci_pci_resume,
	290	#endif
66d4eadd SS	291	.stop = xhci_stop,
	292	.shutdown = xhci_shutdown,
	293
3ffbba95 SS	294	/*
	295	* managing i/o requests and associated device resources
	296	*/
d0e96f5a SS	297	.urb_enqueue = xhci_urb_enqueue,
d0e96f5a SS	298	.urb_dequeue = xhci_urb_dequeue,
3ffbba95 SS	299	.alloc_dev = xhci_alloc_dev,
3ffbba95 SS	300	.free_dev = xhci_free_dev,
eab1cafc SS	301	.alloc_streams = xhci_alloc_streams,
eab1cafc SS	302	.free_streams = xhci_free_streams,
f94e0186 SS	303	.add_endpoint = xhci_add_endpoint,
f94e0186 SS	304	.drop_endpoint = xhci_drop_endpoint,
a1587d97	305	.endpoint_reset = xhci_endpoint_reset,
f94e0186 SS	306	.check_bandwidth = xhci_check_bandwidth,
f94e0186 SS	307	.reset_bandwidth = xhci_reset_bandwidth,
3ffbba95	308	.address_device = xhci_address_device,
b356b7c7	309	.update_hub_device = xhci_update_hub_device,
f0615c45	310	.reset_device = xhci_discover_or_reset_device,
3ffbba95	311
66d4eadd SS	312	/*
	313	* scheduling support
	314	*/
	315	.get_frame_number = xhci_get_frame,
	316
0f2a7930 SS	317	/* Root hub support */
	318	.hub_control = xhci_hub_control,
	319	.hub_status_data = xhci_hub_status_data,
9777e3ce AX	320	.bus_suspend = xhci_bus_suspend,
9777e3ce AX	321	.bus_resume = xhci_bus_resume,
9574323c AX	322	/*
	323	* call back when device connected and addressed
	324	*/
	325	.update_device = xhci_update_device,
65580b43	326	.set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
3b3db026 SS	327	.enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
3b3db026 SS	328	.disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
3f5eb141	329	.find_raw_port_number = xhci_find_raw_port_number,
66d4eadd SS	330	};
	331
	332	/-------------------------------------------------------------------------/
	333
	334	/* PCI driver selection metadata; PCI hotplugging uses this */
	335	static const struct pci_device_id pci_ids[] = { {
	336	/* handle any USB 3.0 xHCI controller */
	337	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
	338	.driver_data = (unsigned long) &xhci_pci_hc_driver,
	339	},
	340	{ /* end: all zeroes */ }
	341	};
	342	MODULE_DEVICE_TABLE(pci, pci_ids);
	343
	344	/* pci driver glue; this is a "new style" PCI driver module */
	345	static struct pci_driver xhci_pci_driver = {
	346	.name = (char *) hcd_name,
	347	.id_table = pci_ids,
	348
f6ff0ac8	349	.probe = xhci_pci_probe,
b02d0ed6	350	.remove = xhci_pci_remove,
66d4eadd SS	351	/* suspend and resume implemented later */
	352
	353	.shutdown = usb_hcd_pci_shutdown,
f875fdbf	354	#ifdef CONFIG_PM
5535b1d5 AX	355	.driver = {
	356	.pm = &usb_hcd_pci_pm_ops
	357	},
	358	#endif
66d4eadd SS	359	};
66d4eadd SS	360
0cc47d54	361	int __init xhci_register_pci(void)
66d4eadd SS	362	{
	363	return pci_register_driver(&xhci_pci_driver);
	364	}
	365
a46c46a1	366	void xhci_unregister_pci(void)
66d4eadd SS	367	{
	368	pci_unregister_driver(&xhci_pci_driver);
	369	}