Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
66d4eadd SS |
2 | /* |
3 | * xHCI host controller driver PCI Bus Glue. | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
66d4eadd SS |
9 | */ |
10 | ||
11 | #include <linux/pci.h> | |
7fc2a616 | 12 | #include <linux/slab.h> |
6eb0de82 | 13 | #include <linux/module.h> |
c3c5819a | 14 | #include <linux/acpi.h> |
66d4eadd SS |
15 | |
16 | #include "xhci.h" | |
4bdfe4c3 | 17 | #include "xhci-trace.h" |
66d4eadd | 18 | |
fa895377 LB |
19 | #define SSIC_PORT_NUM 2 |
20 | #define SSIC_PORT_CFG2 0x880c | |
21 | #define SSIC_PORT_CFG2_OFFSET 0x30 | |
abce329c RM |
22 | #define PROG_DONE (1 << 30) |
23 | #define SSIC_PORT_UNUSED (1 << 31) | |
24 | ||
ac9d8fe7 SS |
25 | /* Device for a quirk */ |
26 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 | |
27 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 | |
d95815ba | 28 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009 |
bba18e33 | 29 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 |
ac9d8fe7 | 30 | |
c877b3b2 | 31 | #define PCI_VENDOR_ID_ETRON 0x1b6f |
170625e9 | 32 | #define PCI_DEVICE_ID_EJ168 0x7023 |
c877b3b2 | 33 | |
638298dc TI |
34 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 |
35 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 | |
4c39135a | 36 | #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1 |
b8cb91e0 MN |
37 | #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 |
38 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f | |
39 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f | |
ccc04afb | 40 | #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 |
0d46faca | 41 | #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 |
346e9973 | 42 | #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 |
a0c16630 | 43 | #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0 |
2815ef7f MN |
44 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5 |
45 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6 | |
46 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db | |
47 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4 | |
48 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9 | |
49 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec | |
50 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0 | |
638298dc | 51 | |
bde0716d JL |
52 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 |
53 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba | |
54 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb | |
55 | #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc | |
9da5a109 JC |
56 | #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142 |
57 | ||
66d4eadd SS |
58 | static const char hcd_name[] = "xhci_hcd"; |
59 | ||
1885d9a3 AB |
60 | static struct hc_driver __read_mostly xhci_pci_hc_driver; |
61 | ||
cd33a321 RQ |
62 | static int xhci_pci_setup(struct usb_hcd *hcd); |
63 | ||
64 | static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { | |
cd33a321 RQ |
65 | .reset = xhci_pci_setup, |
66 | }; | |
67 | ||
66d4eadd SS |
68 | /* called after powerup, by probe or system-pm "wakeup" */ |
69 | static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) | |
70 | { | |
71 | /* | |
72 | * TODO: Implement finding debug ports later. | |
73 | * TODO: see if there are any quirks that need to be added to handle | |
74 | * new extended capabilities. | |
75 | */ | |
76 | ||
77 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
78 | if (!pci_set_mwi(pdev)) | |
79 | xhci_dbg(xhci, "MWI active\n"); | |
80 | ||
81 | xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); | |
82 | return 0; | |
83 | } | |
84 | ||
da3c9c4f SAS |
85 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
86 | { | |
87 | struct pci_dev *pdev = to_pci_dev(dev); | |
88 | ||
ac9d8fe7 SS |
89 | /* Look for vendor-specific quirks */ |
90 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && | |
bba18e33 SS |
91 | (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || |
92 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { | |
93 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && | |
94 | pdev->revision == 0x0) { | |
ac9d8fe7 | 95 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
4bdfe4c3 XR |
96 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
97 | "QUIRK: Fresco Logic xHC needs configure" | |
98 | " endpoint cmd after reset endpoint"); | |
f5182b41 | 99 | } |
455f5892 ON |
100 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && |
101 | pdev->revision == 0x4) { | |
102 | xhci->quirks |= XHCI_SLOW_SUSPEND; | |
103 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
104 | "QUIRK: Fresco Logic xHC revision %u" | |
105 | "must be suspended extra slowly", | |
106 | pdev->revision); | |
107 | } | |
7f5c4d63 HG |
108 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) |
109 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
f5182b41 SS |
110 | /* Fresco Logic confirms: all revisions of this chip do not |
111 | * support MSI, even though some of them claim to in their PCI | |
112 | * capabilities. | |
113 | */ | |
114 | xhci->quirks |= XHCI_BROKEN_MSI; | |
4bdfe4c3 XR |
115 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
116 | "QUIRK: Fresco Logic revision %u " | |
117 | "has broken MSI implementation", | |
f5182b41 | 118 | pdev->revision); |
1530bbc6 | 119 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
ac9d8fe7 | 120 | } |
f5182b41 | 121 | |
d95815ba HG |
122 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && |
123 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009) | |
124 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
125 | ||
0238634d SS |
126 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
127 | xhci->quirks |= XHCI_NEC_HOST; | |
ac9d8fe7 | 128 | |
7e393a83 AX |
129 | if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) |
130 | xhci->quirks |= XHCI_AMD_0x96_HOST; | |
131 | ||
c41136b0 | 132 | /* AMD PLL quirk */ |
4fbb8aa7 | 133 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check()) |
c41136b0 | 134 | xhci->quirks |= XHCI_AMD_PLL_FIX; |
2597fe99 | 135 | |
621faf4f KHF |
136 | if (pdev->vendor == PCI_VENDOR_ID_AMD && |
137 | (pdev->device == 0x15e0 || | |
138 | pdev->device == 0x15e1 || | |
139 | pdev->device == 0x43bb)) | |
191edc5e KHF |
140 | xhci->quirks |= XHCI_SUSPEND_DELAY; |
141 | ||
a7d57abc SS |
142 | if (pdev->vendor == PCI_VENDOR_ID_AMD && |
143 | (pdev->device == 0x15e0 || pdev->device == 0x15e1)) | |
144 | xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND; | |
145 | ||
2597fe99 HR |
146 | if (pdev->vendor == PCI_VENDOR_ID_AMD) |
147 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
148 | ||
bde0716d JL |
149 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) && |
150 | ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) || | |
151 | (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) || | |
152 | (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || | |
153 | (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) | |
154 | xhci->quirks |= XHCI_U2_DISABLE_WAKE; | |
155 | ||
e3567d2c SS |
156 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
157 | xhci->quirks |= XHCI_LPM_SUPPORT; | |
158 | xhci->quirks |= XHCI_INTEL_HOST; | |
227a4fd8 | 159 | xhci->quirks |= XHCI_AVOID_BEI; |
e3567d2c | 160 | } |
ad808333 SS |
161 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
162 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { | |
2cf95c18 SS |
163 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; |
164 | xhci->limit_active_eps = 64; | |
86cc558e | 165 | xhci->quirks |= XHCI_SW_BW_CHECKING; |
e95829f4 SS |
166 | /* |
167 | * PPT desktop boards DH77EB and DH77DF will power back on after | |
168 | * a few seconds of being shutdown. The fix for this is to | |
169 | * switch the ports from xHCI to EHCI on shutdown. We can't use | |
170 | * DMI information to find those particular boards (since each | |
171 | * vendor will change the board name), so we have to key off all | |
172 | * PPT chipsets. | |
173 | */ | |
174 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; | |
ad808333 | 175 | } |
0a939993 | 176 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
4c39135a MN |
177 | (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI || |
178 | pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) { | |
c09ec25d | 179 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; |
fd7cd061 | 180 | xhci->quirks |= XHCI_SPURIOUS_WAKEUP; |
638298dc | 181 | } |
b8cb91e0 MN |
182 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
183 | (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || | |
184 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || | |
ccc04afb | 185 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || |
0d46faca | 186 | pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || |
6c97cfc1 | 187 | pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI || |
a0c16630 MN |
188 | pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || |
189 | pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) { | |
b8cb91e0 MN |
190 | xhci->quirks |= XHCI_PME_STUCK_QUIRK; |
191 | } | |
7e70cbff | 192 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
c02588a3 | 193 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) |
7e70cbff | 194 | xhci->quirks |= XHCI_SSIC_PORT_UNUSED; |
c02588a3 HK |
195 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
196 | (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || | |
8fde481e | 197 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || |
c02588a3 | 198 | pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI)) |
fa31b3cb | 199 | xhci->quirks |= XHCI_INTEL_USB_ROLE_SW; |
346e9973 MN |
200 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
201 | (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || | |
ffe84e01 MN |
202 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || |
203 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || | |
a0c16630 MN |
204 | pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI || |
205 | pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) | |
346e9973 MN |
206 | xhci->quirks |= XHCI_MISSING_CAS; |
207 | ||
2815ef7f MN |
208 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
209 | (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI || | |
210 | pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI || | |
211 | pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI || | |
212 | pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI || | |
213 | pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI || | |
214 | pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI || | |
215 | pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI)) | |
216 | xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW; | |
217 | ||
c877b3b2 | 218 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
170625e9 | 219 | pdev->device == PCI_DEVICE_ID_EJ168) { |
c877b3b2 | 220 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
5cb7df2b | 221 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
8f873c1f | 222 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
c877b3b2 | 223 | } |
da997066 | 224 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
12de0a35 | 225 | pdev->device == 0x0014) { |
da997066 | 226 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
12de0a35 MZ |
227 | xhci->quirks |= XHCI_ZERO_64B_REGS; |
228 | } | |
1aa9578c | 229 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
12de0a35 | 230 | pdev->device == 0x0015) { |
1aa9578c | 231 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
12de0a35 MZ |
232 | xhci->quirks |= XHCI_ZERO_64B_REGS; |
233 | } | |
457a4f61 EF |
234 | if (pdev->vendor == PCI_VENDOR_ID_VIA) |
235 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
85f4e45b | 236 | |
e21eba05 HG |
237 | /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ |
238 | if (pdev->vendor == PCI_VENDOR_ID_VIA && | |
239 | pdev->device == 0x3432) | |
240 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
241 | ||
2391eacb HG |
242 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
243 | pdev->device == 0x1042) | |
244 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
d2f48f05 CL |
245 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
246 | pdev->device == 0x1142) | |
247 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
2391eacb | 248 | |
9da5a109 JC |
249 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
250 | pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) | |
251 | xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL; | |
252 | ||
69307ccb RQ |
253 | if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) |
254 | xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; | |
255 | ||
11644a76 CG |
256 | if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || |
257 | pdev->vendor == PCI_VENDOR_ID_CAVIUM) && | |
258 | pdev->device == 0x9026) | |
259 | xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; | |
260 | ||
85f4e45b ON |
261 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
262 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
263 | "QUIRK: Resetting on resume"); | |
da3c9c4f | 264 | } |
c41136b0 | 265 | |
c3c5819a MN |
266 | #ifdef CONFIG_ACPI |
267 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) | |
268 | { | |
94116f81 AS |
269 | static const guid_t intel_dsm_guid = |
270 | GUID_INIT(0xac340cb7, 0xe901, 0x45bf, | |
271 | 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23); | |
84ed9152 MW |
272 | union acpi_object *obj; |
273 | ||
94116f81 | 274 | obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1, |
84ed9152 MW |
275 | NULL); |
276 | ACPI_FREE(obj); | |
c3c5819a MN |
277 | } |
278 | #else | |
84ed9152 | 279 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } |
c3c5819a MN |
280 | #endif /* CONFIG_ACPI */ |
281 | ||
da3c9c4f SAS |
282 | /* called during probe() after chip reset completes */ |
283 | static int xhci_pci_setup(struct usb_hcd *hcd) | |
284 | { | |
285 | struct xhci_hcd *xhci; | |
286 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
287 | int retval; | |
66d4eadd | 288 | |
b50107bb MN |
289 | xhci = hcd_to_xhci(hcd); |
290 | if (!xhci->sbrn) | |
291 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); | |
292 | ||
ab725cbe AW |
293 | /* imod_interval is the interrupt moderation value in nanoseconds. */ |
294 | xhci->imod_interval = 40000; | |
295 | ||
da3c9c4f | 296 | retval = xhci_gen_setup(hcd, xhci_pci_quirks); |
66d4eadd | 297 | if (retval) |
da3c9c4f | 298 | return retval; |
006d5820 | 299 | |
da3c9c4f SAS |
300 | if (!usb_hcd_is_primary_hcd(hcd)) |
301 | return 0; | |
66d4eadd | 302 | |
66d4eadd SS |
303 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); |
304 | ||
305 | /* Find any debug ports */ | |
989bad11 | 306 | return xhci_pci_reinit(xhci, pdev); |
b02d0ed6 SS |
307 | } |
308 | ||
f6ff0ac8 SS |
309 | /* |
310 | * We need to register our own PCI probe function (instead of the USB core's | |
311 | * function) in order to create a second roothub under xHCI. | |
312 | */ | |
313 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
314 | { | |
315 | int retval; | |
316 | struct xhci_hcd *xhci; | |
317 | struct hc_driver *driver; | |
318 | struct usb_hcd *hcd; | |
319 | ||
320 | driver = (struct hc_driver *)id->driver_data; | |
bcffae77 MN |
321 | |
322 | /* Prevent runtime suspending between USB-2 and USB-3 initialization */ | |
323 | pm_runtime_get_noresume(&dev->dev); | |
324 | ||
f6ff0ac8 SS |
325 | /* Register the USB 2.0 roothub. |
326 | * FIXME: USB core must know to register the USB 2.0 roothub first. | |
327 | * This is sort of silly, because we could just set the HCD driver flags | |
328 | * to say USB 2.0, but I'm not sure what the implications would be in | |
329 | * the other parts of the HCD code. | |
330 | */ | |
331 | retval = usb_hcd_pci_probe(dev, id); | |
332 | ||
333 | if (retval) | |
bcffae77 | 334 | goto put_runtime_pm; |
f6ff0ac8 SS |
335 | |
336 | /* USB 2.0 roothub is stored in the PCI device now. */ | |
337 | hcd = dev_get_drvdata(&dev->dev); | |
338 | xhci = hcd_to_xhci(hcd); | |
339 | xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, | |
340 | pci_name(dev), hcd); | |
341 | if (!xhci->shared_hcd) { | |
342 | retval = -ENOMEM; | |
343 | goto dealloc_usb2_hcd; | |
344 | } | |
345 | ||
fa31b3cb HG |
346 | retval = xhci_ext_cap_init(xhci); |
347 | if (retval) | |
348 | goto put_usb3_hcd; | |
349 | ||
f6ff0ac8 | 350 | retval = usb_add_hcd(xhci->shared_hcd, dev->irq, |
b5dd18d8 | 351 | IRQF_SHARED); |
f6ff0ac8 SS |
352 | if (retval) |
353 | goto put_usb3_hcd; | |
354 | /* Roothub already marked as USB 3.0 speed */ | |
3b3db026 | 355 | |
8f873c1f HG |
356 | if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && |
357 | HCC_MAX_PSA(xhci->hcc_params) >= 4) | |
14aec589 ON |
358 | xhci->shared_hcd->can_do_streams = 1; |
359 | ||
c3c5819a MN |
360 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
361 | xhci_pme_acpi_rtd3_enable(dev); | |
362 | ||
bcffae77 MN |
363 | /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ |
364 | pm_runtime_put_noidle(&dev->dev); | |
365 | ||
2815ef7f MN |
366 | if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) |
367 | pm_runtime_allow(&dev->dev); | |
368 | ||
f6ff0ac8 SS |
369 | return 0; |
370 | ||
371 | put_usb3_hcd: | |
372 | usb_put_hcd(xhci->shared_hcd); | |
373 | dealloc_usb2_hcd: | |
374 | usb_hcd_pci_remove(dev); | |
bcffae77 MN |
375 | put_runtime_pm: |
376 | pm_runtime_put_noidle(&dev->dev); | |
f6ff0ac8 SS |
377 | return retval; |
378 | } | |
379 | ||
b02d0ed6 SS |
380 | static void xhci_pci_remove(struct pci_dev *dev) |
381 | { | |
382 | struct xhci_hcd *xhci; | |
383 | ||
384 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); | |
98d74f9c | 385 | xhci->xhc_state |= XHCI_STATE_REMOVING; |
2815ef7f MN |
386 | |
387 | if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW) | |
388 | pm_runtime_forbid(&dev->dev); | |
389 | ||
f6ff0ac8 SS |
390 | if (xhci->shared_hcd) { |
391 | usb_remove_hcd(xhci->shared_hcd); | |
392 | usb_put_hcd(xhci->shared_hcd); | |
f0680904 | 393 | xhci->shared_hcd = NULL; |
f6ff0ac8 | 394 | } |
638298dc TI |
395 | |
396 | /* Workaround for spurious wakeups at shutdown with HSW */ | |
397 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
398 | pci_set_power_state(dev, PCI_D3hot); | |
f1f6d9a8 MN |
399 | |
400 | usb_hcd_pci_remove(dev); | |
66d4eadd SS |
401 | } |
402 | ||
5535b1d5 | 403 | #ifdef CONFIG_PM |
2b7627b7 TB |
404 | /* |
405 | * In some Intel xHCI controllers, in order to get D3 working, | |
406 | * through a vendor specific SSIC CONFIG register at offset 0x883c, | |
407 | * SSIC PORT need to be marked as "unused" before putting xHCI | |
408 | * into D3. After D3 exit, the SSIC port need to be marked as "used". | |
409 | * Without this change, xHCI might not enter D3 state. | |
2b7627b7 | 410 | */ |
7e70cbff | 411 | static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) |
2b7627b7 TB |
412 | { |
413 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
2b7627b7 TB |
414 | u32 val; |
415 | void __iomem *reg; | |
fa895377 | 416 | int i; |
2b7627b7 | 417 | |
7e70cbff LB |
418 | for (i = 0; i < SSIC_PORT_NUM; i++) { |
419 | reg = (void __iomem *) xhci->cap_regs + | |
420 | SSIC_PORT_CFG2 + | |
421 | i * SSIC_PORT_CFG2_OFFSET; | |
422 | ||
423 | /* Notify SSIC that SSIC profile programming is not done. */ | |
424 | val = readl(reg) & ~PROG_DONE; | |
425 | writel(val, reg); | |
426 | ||
427 | /* Mark SSIC port as unused(suspend) or used(resume) */ | |
428 | val = readl(reg); | |
429 | if (suspend) | |
430 | val |= SSIC_PORT_UNUSED; | |
431 | else | |
432 | val &= ~SSIC_PORT_UNUSED; | |
433 | writel(val, reg); | |
434 | ||
435 | /* Notify SSIC that SSIC profile programming is done */ | |
436 | val = readl(reg) | PROG_DONE; | |
437 | writel(val, reg); | |
438 | readl(reg); | |
2b7627b7 | 439 | } |
7e70cbff LB |
440 | } |
441 | ||
442 | /* | |
443 | * Make sure PME works on some Intel xHCI controllers by writing 1 to clear | |
444 | * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 | |
445 | */ | |
446 | static void xhci_pme_quirk(struct usb_hcd *hcd) | |
447 | { | |
448 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
449 | void __iomem *reg; | |
450 | u32 val; | |
2b7627b7 TB |
451 | |
452 | reg = (void __iomem *) xhci->cap_regs + 0x80a4; | |
453 | val = readl(reg); | |
454 | writel(val | BIT(28), reg); | |
455 | readl(reg); | |
456 | } | |
457 | ||
5535b1d5 AX |
458 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
459 | { | |
460 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c3897aa5 | 461 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
92149c93 | 462 | int ret; |
c3897aa5 SS |
463 | |
464 | /* | |
465 | * Systems with the TI redriver that loses port status change events | |
466 | * need to have the registers polled during D3, so avoid D3cold. | |
467 | */ | |
e1cd9727 | 468 | if (xhci->quirks & XHCI_COMP_MODE_QUIRK) |
9d26d3a8 | 469 | pci_d3cold_disable(pdev); |
5535b1d5 | 470 | |
b8cb91e0 | 471 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
7e70cbff LB |
472 | xhci_pme_quirk(hcd); |
473 | ||
474 | if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) | |
475 | xhci_ssic_port_unused_quirk(hcd, true); | |
b8cb91e0 | 476 | |
92149c93 LB |
477 | ret = xhci_suspend(xhci, do_wakeup); |
478 | if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) | |
479 | xhci_ssic_port_unused_quirk(hcd, false); | |
480 | ||
481 | return ret; | |
5535b1d5 AX |
482 | } |
483 | ||
484 | static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | |
485 | { | |
486 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
69e848c2 | 487 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
5535b1d5 AX |
488 | int retval = 0; |
489 | ||
69e848c2 SS |
490 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
491 | * not support xHCI natively. That means that during system resume, it | |
492 | * may switch the ports back to EHCI so that users can use their | |
493 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
494 | * | |
495 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
496 | * enabled before resume, and switch the ports back to xHCI when the | |
497 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
498 | * writers. | |
499 | * | |
500 | * Unconditionally switch the ports back to xHCI after a system resume. | |
26b76798 MN |
501 | * It should not matter whether the EHCI or xHCI controller is |
502 | * resumed first. It's enough to do the switchover in xHCI because | |
503 | * USB core won't notice anything as the hub driver doesn't start | |
504 | * running again until after all the devices (including both EHCI and | |
505 | * xHCI host controllers) have been resumed. | |
69e848c2 | 506 | */ |
26b76798 MN |
507 | |
508 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | |
509 | usb_enable_intel_xhci_ports(pdev); | |
69e848c2 | 510 | |
7e70cbff LB |
511 | if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) |
512 | xhci_ssic_port_unused_quirk(hcd, false); | |
513 | ||
b8cb91e0 | 514 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
7e70cbff | 515 | xhci_pme_quirk(hcd); |
b8cb91e0 | 516 | |
5535b1d5 AX |
517 | retval = xhci_resume(xhci, hibernated); |
518 | return retval; | |
519 | } | |
520 | #endif /* CONFIG_PM */ | |
521 | ||
66d4eadd SS |
522 | /*-------------------------------------------------------------------------*/ |
523 | ||
524 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
525 | static const struct pci_device_id pci_ids[] = { { | |
526 | /* handle any USB 3.0 xHCI controller */ | |
527 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), | |
528 | .driver_data = (unsigned long) &xhci_pci_hc_driver, | |
529 | }, | |
530 | { /* end: all zeroes */ } | |
531 | }; | |
532 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
533 | ||
534 | /* pci driver glue; this is a "new style" PCI driver module */ | |
535 | static struct pci_driver xhci_pci_driver = { | |
536 | .name = (char *) hcd_name, | |
537 | .id_table = pci_ids, | |
538 | ||
f6ff0ac8 | 539 | .probe = xhci_pci_probe, |
b02d0ed6 | 540 | .remove = xhci_pci_remove, |
66d4eadd SS |
541 | /* suspend and resume implemented later */ |
542 | ||
543 | .shutdown = usb_hcd_pci_shutdown, | |
f875fdbf | 544 | #ifdef CONFIG_PM |
5535b1d5 AX |
545 | .driver = { |
546 | .pm = &usb_hcd_pci_pm_ops | |
547 | }, | |
548 | #endif | |
66d4eadd SS |
549 | }; |
550 | ||
29e409f0 | 551 | static int __init xhci_pci_init(void) |
66d4eadd | 552 | { |
cd33a321 | 553 | xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); |
1885d9a3 AB |
554 | #ifdef CONFIG_PM |
555 | xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; | |
556 | xhci_pci_hc_driver.pci_resume = xhci_pci_resume; | |
557 | #endif | |
66d4eadd SS |
558 | return pci_register_driver(&xhci_pci_driver); |
559 | } | |
29e409f0 | 560 | module_init(xhci_pci_init); |
66d4eadd | 561 | |
29e409f0 | 562 | static void __exit xhci_pci_exit(void) |
66d4eadd SS |
563 | { |
564 | pci_unregister_driver(&xhci_pci_driver); | |
565 | } | |
29e409f0 AB |
566 | module_exit(xhci_pci_exit); |
567 | ||
568 | MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); | |
569 | MODULE_LICENSE("GPL"); |