Merge remote-tracking branch 'asoc/topic/core' into asoc-next
[linux-2.6-block.git] / drivers / usb / host / xhci-pci.c
CommitLineData
66d4eadd
SS
1/*
2 * xHCI host controller driver PCI Bus Glue.
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
7fc2a616 24#include <linux/slab.h>
6eb0de82 25#include <linux/module.h>
c3c5819a 26#include <linux/acpi.h>
66d4eadd
SS
27
28#include "xhci.h"
4bdfe4c3 29#include "xhci-trace.h"
66d4eadd 30
abce329c
RM
31#define PORT2_SSIC_CONFIG_REG2 0x883c
32#define PROG_DONE (1 << 30)
33#define SSIC_PORT_UNUSED (1 << 31)
34
ac9d8fe7
SS
35/* Device for a quirk */
36#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
37#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
bba18e33 38#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7 39
c877b3b2 40#define PCI_VENDOR_ID_ETRON 0x1b6f
170625e9 41#define PCI_DEVICE_ID_EJ168 0x7023
c877b3b2 42
638298dc
TI
43#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
44#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
b8cb91e0
MN
45#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
46#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
47#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
638298dc 48
66d4eadd
SS
49static const char hcd_name[] = "xhci_hcd";
50
1885d9a3
AB
51static struct hc_driver __read_mostly xhci_pci_hc_driver;
52
cd33a321
RQ
53static int xhci_pci_setup(struct usb_hcd *hcd);
54
55static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
56 .extra_priv_size = sizeof(struct xhci_hcd),
57 .reset = xhci_pci_setup,
58};
59
66d4eadd
SS
60/* called after powerup, by probe or system-pm "wakeup" */
61static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
62{
63 /*
64 * TODO: Implement finding debug ports later.
65 * TODO: see if there are any quirks that need to be added to handle
66 * new extended capabilities.
67 */
68
69 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
70 if (!pci_set_mwi(pdev))
71 xhci_dbg(xhci, "MWI active\n");
72
73 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
74 return 0;
75}
76
da3c9c4f
SAS
77static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
78{
79 struct pci_dev *pdev = to_pci_dev(dev);
80
ac9d8fe7
SS
81 /* Look for vendor-specific quirks */
82 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33
SS
83 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
84 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
85 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
86 pdev->revision == 0x0) {
ac9d8fe7 87 xhci->quirks |= XHCI_RESET_EP_QUIRK;
4bdfe4c3
XR
88 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
89 "QUIRK: Fresco Logic xHC needs configure"
90 " endpoint cmd after reset endpoint");
f5182b41 91 }
455f5892
ON
92 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
93 pdev->revision == 0x4) {
94 xhci->quirks |= XHCI_SLOW_SUSPEND;
95 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
96 "QUIRK: Fresco Logic xHC revision %u"
97 "must be suspended extra slowly",
98 pdev->revision);
99 }
7f5c4d63
HG
100 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
101 xhci->quirks |= XHCI_BROKEN_STREAMS;
f5182b41
SS
102 /* Fresco Logic confirms: all revisions of this chip do not
103 * support MSI, even though some of them claim to in their PCI
104 * capabilities.
105 */
106 xhci->quirks |= XHCI_BROKEN_MSI;
4bdfe4c3
XR
107 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
108 "QUIRK: Fresco Logic revision %u "
109 "has broken MSI implementation",
f5182b41 110 pdev->revision);
1530bbc6 111 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
ac9d8fe7 112 }
f5182b41 113
0238634d
SS
114 if (pdev->vendor == PCI_VENDOR_ID_NEC)
115 xhci->quirks |= XHCI_NEC_HOST;
ac9d8fe7 116
7e393a83
AX
117 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
118 xhci->quirks |= XHCI_AMD_0x96_HOST;
119
c41136b0
AX
120 /* AMD PLL quirk */
121 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
122 xhci->quirks |= XHCI_AMD_PLL_FIX;
2597fe99
HR
123
124 if (pdev->vendor == PCI_VENDOR_ID_AMD)
125 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
126
e3567d2c
SS
127 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
128 xhci->quirks |= XHCI_LPM_SUPPORT;
129 xhci->quirks |= XHCI_INTEL_HOST;
227a4fd8 130 xhci->quirks |= XHCI_AVOID_BEI;
e3567d2c 131 }
ad808333
SS
132 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
133 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18
SS
134 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
135 xhci->limit_active_eps = 64;
86cc558e 136 xhci->quirks |= XHCI_SW_BW_CHECKING;
e95829f4
SS
137 /*
138 * PPT desktop boards DH77EB and DH77DF will power back on after
139 * a few seconds of being shutdown. The fix for this is to
140 * switch the ports from xHCI to EHCI on shutdown. We can't use
141 * DMI information to find those particular boards (since each
142 * vendor will change the board name), so we have to key off all
143 * PPT chipsets.
144 */
145 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
ad808333 146 }
0a939993
DT
147 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
148 pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) {
c09ec25d 149 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
638298dc 150 }
b8cb91e0
MN
151 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
152 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
153 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
154 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)) {
155 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
156 }
c877b3b2 157 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
170625e9 158 pdev->device == PCI_DEVICE_ID_EJ168) {
c877b3b2 159 xhci->quirks |= XHCI_RESET_ON_RESUME;
5cb7df2b 160 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
8f873c1f 161 xhci->quirks |= XHCI_BROKEN_STREAMS;
c877b3b2 162 }
1aa9578c 163 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
6db249eb 164 pdev->device == 0x0015)
1aa9578c 165 xhci->quirks |= XHCI_RESET_ON_RESUME;
457a4f61
EF
166 if (pdev->vendor == PCI_VENDOR_ID_VIA)
167 xhci->quirks |= XHCI_RESET_ON_RESUME;
85f4e45b 168
e21eba05
HG
169 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
170 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
171 pdev->device == 0x3432)
172 xhci->quirks |= XHCI_BROKEN_STREAMS;
173
2391eacb
HG
174 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
175 pdev->device == 0x1042)
176 xhci->quirks |= XHCI_BROKEN_STREAMS;
177
85f4e45b
ON
178 if (xhci->quirks & XHCI_RESET_ON_RESUME)
179 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
180 "QUIRK: Resetting on resume");
da3c9c4f 181}
c41136b0 182
b8cb91e0 183/*
abce329c
RM
184 * In some Intel xHCI controllers, in order to get D3 working,
185 * through a vendor specific SSIC CONFIG register at offset 0x883c,
186 * SSIC PORT need to be marked as "unused" before putting xHCI
187 * into D3. After D3 exit, the SSIC port need to be marked as "used".
188 * Without this change, xHCI might not enter D3 state.
b8cb91e0
MN
189 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
190 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
191 */
abce329c 192static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend)
b8cb91e0 193{
abce329c
RM
194 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
195 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
b8cb91e0
MN
196 u32 val;
197 void __iomem *reg;
198
abce329c
RM
199 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
200 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
201
202 reg = (void __iomem *) xhci->cap_regs + PORT2_SSIC_CONFIG_REG2;
203
204 /* Notify SSIC that SSIC profile programming is not done */
205 val = readl(reg) & ~PROG_DONE;
206 writel(val, reg);
207
208 /* Mark SSIC port as unused(suspend) or used(resume) */
209 val = readl(reg);
210 if (suspend)
211 val |= SSIC_PORT_UNUSED;
212 else
213 val &= ~SSIC_PORT_UNUSED;
214 writel(val, reg);
215
216 /* Notify SSIC that SSIC profile programming is done */
217 val = readl(reg) | PROG_DONE;
218 writel(val, reg);
219 readl(reg);
220 }
221
b8cb91e0
MN
222 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
223 val = readl(reg);
224 writel(val | BIT(28), reg);
225 readl(reg);
226}
227
c3c5819a
MN
228#ifdef CONFIG_ACPI
229static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
230{
231 static const u8 intel_dsm_uuid[] = {
232 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
233 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
234 };
235 acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, NULL);
236}
237#else
238 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
239#endif /* CONFIG_ACPI */
240
da3c9c4f
SAS
241/* called during probe() after chip reset completes */
242static int xhci_pci_setup(struct usb_hcd *hcd)
243{
244 struct xhci_hcd *xhci;
245 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
246 int retval;
66d4eadd 247
da3c9c4f 248 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd 249 if (retval)
da3c9c4f 250 return retval;
006d5820 251
da3c9c4f
SAS
252 xhci = hcd_to_xhci(hcd);
253 if (!usb_hcd_is_primary_hcd(hcd))
254 return 0;
66d4eadd
SS
255
256 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
257 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
258
259 /* Find any debug ports */
b02d0ed6
SS
260 retval = xhci_pci_reinit(xhci, pdev);
261 if (!retval)
262 return retval;
263
b02d0ed6
SS
264 return retval;
265}
266
f6ff0ac8
SS
267/*
268 * We need to register our own PCI probe function (instead of the USB core's
269 * function) in order to create a second roothub under xHCI.
270 */
271static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
272{
273 int retval;
274 struct xhci_hcd *xhci;
275 struct hc_driver *driver;
276 struct usb_hcd *hcd;
277
278 driver = (struct hc_driver *)id->driver_data;
bcffae77
MN
279
280 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
281 pm_runtime_get_noresume(&dev->dev);
282
f6ff0ac8
SS
283 /* Register the USB 2.0 roothub.
284 * FIXME: USB core must know to register the USB 2.0 roothub first.
285 * This is sort of silly, because we could just set the HCD driver flags
286 * to say USB 2.0, but I'm not sure what the implications would be in
287 * the other parts of the HCD code.
288 */
289 retval = usb_hcd_pci_probe(dev, id);
290
291 if (retval)
bcffae77 292 goto put_runtime_pm;
f6ff0ac8
SS
293
294 /* USB 2.0 roothub is stored in the PCI device now. */
295 hcd = dev_get_drvdata(&dev->dev);
296 xhci = hcd_to_xhci(hcd);
297 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
298 pci_name(dev), hcd);
299 if (!xhci->shared_hcd) {
300 retval = -ENOMEM;
301 goto dealloc_usb2_hcd;
302 }
303
f6ff0ac8 304 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8 305 IRQF_SHARED);
f6ff0ac8
SS
306 if (retval)
307 goto put_usb3_hcd;
308 /* Roothub already marked as USB 3.0 speed */
3b3db026 309
8f873c1f
HG
310 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
311 HCC_MAX_PSA(xhci->hcc_params) >= 4)
14aec589
ON
312 xhci->shared_hcd->can_do_streams = 1;
313
c3c5819a
MN
314 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
315 xhci_pme_acpi_rtd3_enable(dev);
316
bcffae77
MN
317 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
318 pm_runtime_put_noidle(&dev->dev);
319
f6ff0ac8
SS
320 return 0;
321
322put_usb3_hcd:
323 usb_put_hcd(xhci->shared_hcd);
324dealloc_usb2_hcd:
325 usb_hcd_pci_remove(dev);
bcffae77
MN
326put_runtime_pm:
327 pm_runtime_put_noidle(&dev->dev);
f6ff0ac8
SS
328 return retval;
329}
330
b02d0ed6
SS
331static void xhci_pci_remove(struct pci_dev *dev)
332{
333 struct xhci_hcd *xhci;
334
335 xhci = hcd_to_xhci(pci_get_drvdata(dev));
f6ff0ac8
SS
336 if (xhci->shared_hcd) {
337 usb_remove_hcd(xhci->shared_hcd);
338 usb_put_hcd(xhci->shared_hcd);
339 }
b02d0ed6 340 usb_hcd_pci_remove(dev);
638298dc
TI
341
342 /* Workaround for spurious wakeups at shutdown with HSW */
343 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
344 pci_set_power_state(dev, PCI_D3hot);
66d4eadd
SS
345}
346
5535b1d5
AX
347#ifdef CONFIG_PM
348static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
349{
350 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5
SS
351 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
352
353 /*
354 * Systems with the TI redriver that loses port status change events
355 * need to have the registers polled during D3, so avoid D3cold.
356 */
e1cd9727 357 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
c3897aa5 358 pdev->no_d3cold = true;
5535b1d5 359
b8cb91e0 360 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
abce329c 361 xhci_pme_quirk(hcd, true);
b8cb91e0 362
a1377e53 363 return xhci_suspend(xhci, do_wakeup);
5535b1d5
AX
364}
365
366static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
367{
368 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2 369 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5
AX
370 int retval = 0;
371
69e848c2
SS
372 /* The BIOS on systems with the Intel Panther Point chipset may or may
373 * not support xHCI natively. That means that during system resume, it
374 * may switch the ports back to EHCI so that users can use their
375 * keyboard to select a kernel from GRUB after resume from hibernate.
376 *
377 * The BIOS is supposed to remember whether the OS had xHCI ports
378 * enabled before resume, and switch the ports back to xHCI when the
379 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
380 * writers.
381 *
382 * Unconditionally switch the ports back to xHCI after a system resume.
26b76798
MN
383 * It should not matter whether the EHCI or xHCI controller is
384 * resumed first. It's enough to do the switchover in xHCI because
385 * USB core won't notice anything as the hub driver doesn't start
386 * running again until after all the devices (including both EHCI and
387 * xHCI host controllers) have been resumed.
69e848c2 388 */
26b76798
MN
389
390 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
391 usb_enable_intel_xhci_ports(pdev);
69e848c2 392
b8cb91e0 393 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
abce329c 394 xhci_pme_quirk(hcd, false);
b8cb91e0 395
5535b1d5
AX
396 retval = xhci_resume(xhci, hibernated);
397 return retval;
398}
399#endif /* CONFIG_PM */
400
66d4eadd
SS
401/*-------------------------------------------------------------------------*/
402
403/* PCI driver selection metadata; PCI hotplugging uses this */
404static const struct pci_device_id pci_ids[] = { {
405 /* handle any USB 3.0 xHCI controller */
406 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
407 .driver_data = (unsigned long) &xhci_pci_hc_driver,
408 },
409 { /* end: all zeroes */ }
410};
411MODULE_DEVICE_TABLE(pci, pci_ids);
412
413/* pci driver glue; this is a "new style" PCI driver module */
414static struct pci_driver xhci_pci_driver = {
415 .name = (char *) hcd_name,
416 .id_table = pci_ids,
417
f6ff0ac8 418 .probe = xhci_pci_probe,
b02d0ed6 419 .remove = xhci_pci_remove,
66d4eadd
SS
420 /* suspend and resume implemented later */
421
422 .shutdown = usb_hcd_pci_shutdown,
f875fdbf 423#ifdef CONFIG_PM
5535b1d5
AX
424 .driver = {
425 .pm = &usb_hcd_pci_pm_ops
426 },
427#endif
66d4eadd
SS
428};
429
29e409f0 430static int __init xhci_pci_init(void)
66d4eadd 431{
cd33a321 432 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
1885d9a3
AB
433#ifdef CONFIG_PM
434 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
435 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
436#endif
66d4eadd
SS
437 return pci_register_driver(&xhci_pci_driver);
438}
29e409f0 439module_init(xhci_pci_init);
66d4eadd 440
29e409f0 441static void __exit xhci_pci_exit(void)
66d4eadd
SS
442{
443 pci_unregister_driver(&xhci_pci_driver);
444}
29e409f0
AB
445module_exit(xhci_pci_exit);
446
447MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
448MODULE_LICENSE("GPL");