Commit | Line | Data |
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66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver PCI Bus Glue. | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/pci.h> | |
7fc2a616 | 24 | #include <linux/slab.h> |
6eb0de82 | 25 | #include <linux/module.h> |
c3c5819a | 26 | #include <linux/acpi.h> |
66d4eadd SS |
27 | |
28 | #include "xhci.h" | |
4bdfe4c3 | 29 | #include "xhci-trace.h" |
66d4eadd | 30 | |
fa895377 LB |
31 | #define SSIC_PORT_NUM 2 |
32 | #define SSIC_PORT_CFG2 0x880c | |
33 | #define SSIC_PORT_CFG2_OFFSET 0x30 | |
abce329c RM |
34 | #define PROG_DONE (1 << 30) |
35 | #define SSIC_PORT_UNUSED (1 << 31) | |
36 | ||
ac9d8fe7 SS |
37 | /* Device for a quirk */ |
38 | #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73 | |
39 | #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000 | |
bba18e33 | 40 | #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400 |
ac9d8fe7 | 41 | |
c877b3b2 | 42 | #define PCI_VENDOR_ID_ETRON 0x1b6f |
170625e9 | 43 | #define PCI_DEVICE_ID_EJ168 0x7023 |
c877b3b2 | 44 | |
638298dc TI |
45 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31 |
46 | #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31 | |
b8cb91e0 MN |
47 | #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5 |
48 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f | |
49 | #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f | |
ccc04afb | 50 | #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8 |
0d46faca | 51 | #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8 |
638298dc | 52 | |
66d4eadd SS |
53 | static const char hcd_name[] = "xhci_hcd"; |
54 | ||
1885d9a3 AB |
55 | static struct hc_driver __read_mostly xhci_pci_hc_driver; |
56 | ||
cd33a321 RQ |
57 | static int xhci_pci_setup(struct usb_hcd *hcd); |
58 | ||
59 | static const struct xhci_driver_overrides xhci_pci_overrides __initconst = { | |
cd33a321 RQ |
60 | .reset = xhci_pci_setup, |
61 | }; | |
62 | ||
66d4eadd SS |
63 | /* called after powerup, by probe or system-pm "wakeup" */ |
64 | static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev) | |
65 | { | |
66 | /* | |
67 | * TODO: Implement finding debug ports later. | |
68 | * TODO: see if there are any quirks that need to be added to handle | |
69 | * new extended capabilities. | |
70 | */ | |
71 | ||
72 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
73 | if (!pci_set_mwi(pdev)) | |
74 | xhci_dbg(xhci, "MWI active\n"); | |
75 | ||
76 | xhci_dbg(xhci, "Finished xhci_pci_reinit\n"); | |
77 | return 0; | |
78 | } | |
79 | ||
da3c9c4f SAS |
80 | static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) |
81 | { | |
82 | struct pci_dev *pdev = to_pci_dev(dev); | |
83 | ||
ac9d8fe7 SS |
84 | /* Look for vendor-specific quirks */ |
85 | if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC && | |
bba18e33 SS |
86 | (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK || |
87 | pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) { | |
88 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && | |
89 | pdev->revision == 0x0) { | |
ac9d8fe7 | 90 | xhci->quirks |= XHCI_RESET_EP_QUIRK; |
4bdfe4c3 XR |
91 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
92 | "QUIRK: Fresco Logic xHC needs configure" | |
93 | " endpoint cmd after reset endpoint"); | |
f5182b41 | 94 | } |
455f5892 ON |
95 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK && |
96 | pdev->revision == 0x4) { | |
97 | xhci->quirks |= XHCI_SLOW_SUSPEND; | |
98 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
99 | "QUIRK: Fresco Logic xHC revision %u" | |
100 | "must be suspended extra slowly", | |
101 | pdev->revision); | |
102 | } | |
7f5c4d63 HG |
103 | if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK) |
104 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
f5182b41 SS |
105 | /* Fresco Logic confirms: all revisions of this chip do not |
106 | * support MSI, even though some of them claim to in their PCI | |
107 | * capabilities. | |
108 | */ | |
109 | xhci->quirks |= XHCI_BROKEN_MSI; | |
4bdfe4c3 XR |
110 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
111 | "QUIRK: Fresco Logic revision %u " | |
112 | "has broken MSI implementation", | |
f5182b41 | 113 | pdev->revision); |
1530bbc6 | 114 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
ac9d8fe7 | 115 | } |
f5182b41 | 116 | |
0238634d SS |
117 | if (pdev->vendor == PCI_VENDOR_ID_NEC) |
118 | xhci->quirks |= XHCI_NEC_HOST; | |
ac9d8fe7 | 119 | |
7e393a83 AX |
120 | if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96) |
121 | xhci->quirks |= XHCI_AMD_0x96_HOST; | |
122 | ||
c41136b0 AX |
123 | /* AMD PLL quirk */ |
124 | if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info()) | |
125 | xhci->quirks |= XHCI_AMD_PLL_FIX; | |
2597fe99 HR |
126 | |
127 | if (pdev->vendor == PCI_VENDOR_ID_AMD) | |
128 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; | |
129 | ||
e3567d2c SS |
130 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
131 | xhci->quirks |= XHCI_LPM_SUPPORT; | |
132 | xhci->quirks |= XHCI_INTEL_HOST; | |
227a4fd8 | 133 | xhci->quirks |= XHCI_AVOID_BEI; |
e3567d2c | 134 | } |
ad808333 SS |
135 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
136 | pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) { | |
2cf95c18 SS |
137 | xhci->quirks |= XHCI_EP_LIMIT_QUIRK; |
138 | xhci->limit_active_eps = 64; | |
86cc558e | 139 | xhci->quirks |= XHCI_SW_BW_CHECKING; |
e95829f4 SS |
140 | /* |
141 | * PPT desktop boards DH77EB and DH77DF will power back on after | |
142 | * a few seconds of being shutdown. The fix for this is to | |
143 | * switch the ports from xHCI to EHCI on shutdown. We can't use | |
144 | * DMI information to find those particular boards (since each | |
145 | * vendor will change the board name), so we have to key off all | |
146 | * PPT chipsets. | |
147 | */ | |
148 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; | |
ad808333 | 149 | } |
0a939993 DT |
150 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
151 | pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI) { | |
c09ec25d | 152 | xhci->quirks |= XHCI_SPURIOUS_REBOOT; |
fd7cd061 | 153 | xhci->quirks |= XHCI_SPURIOUS_WAKEUP; |
638298dc | 154 | } |
b8cb91e0 MN |
155 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
156 | (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI || | |
157 | pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI || | |
ccc04afb | 158 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI || |
0d46faca RR |
159 | pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI || |
160 | pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI)) { | |
b8cb91e0 MN |
161 | xhci->quirks |= XHCI_PME_STUCK_QUIRK; |
162 | } | |
7e70cbff LB |
163 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
164 | pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) { | |
165 | xhci->quirks |= XHCI_SSIC_PORT_UNUSED; | |
166 | } | |
c877b3b2 | 167 | if (pdev->vendor == PCI_VENDOR_ID_ETRON && |
170625e9 | 168 | pdev->device == PCI_DEVICE_ID_EJ168) { |
c877b3b2 | 169 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
5cb7df2b | 170 | xhci->quirks |= XHCI_TRUST_TX_LENGTH; |
8f873c1f | 171 | xhci->quirks |= XHCI_BROKEN_STREAMS; |
c877b3b2 | 172 | } |
1aa9578c | 173 | if (pdev->vendor == PCI_VENDOR_ID_RENESAS && |
6db249eb | 174 | pdev->device == 0x0015) |
1aa9578c | 175 | xhci->quirks |= XHCI_RESET_ON_RESUME; |
457a4f61 EF |
176 | if (pdev->vendor == PCI_VENDOR_ID_VIA) |
177 | xhci->quirks |= XHCI_RESET_ON_RESUME; | |
85f4e45b | 178 | |
e21eba05 HG |
179 | /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */ |
180 | if (pdev->vendor == PCI_VENDOR_ID_VIA && | |
181 | pdev->device == 0x3432) | |
182 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
183 | ||
2391eacb HG |
184 | if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && |
185 | pdev->device == 0x1042) | |
186 | xhci->quirks |= XHCI_BROKEN_STREAMS; | |
187 | ||
85f4e45b ON |
188 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
189 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
190 | "QUIRK: Resetting on resume"); | |
da3c9c4f | 191 | } |
c41136b0 | 192 | |
c3c5819a MN |
193 | #ifdef CONFIG_ACPI |
194 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) | |
195 | { | |
196 | static const u8 intel_dsm_uuid[] = { | |
197 | 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45, | |
198 | 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23, | |
199 | }; | |
84ed9152 MW |
200 | union acpi_object *obj; |
201 | ||
202 | obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), intel_dsm_uuid, 3, 1, | |
203 | NULL); | |
204 | ACPI_FREE(obj); | |
c3c5819a MN |
205 | } |
206 | #else | |
84ed9152 | 207 | static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } |
c3c5819a MN |
208 | #endif /* CONFIG_ACPI */ |
209 | ||
da3c9c4f SAS |
210 | /* called during probe() after chip reset completes */ |
211 | static int xhci_pci_setup(struct usb_hcd *hcd) | |
212 | { | |
213 | struct xhci_hcd *xhci; | |
214 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
215 | int retval; | |
66d4eadd | 216 | |
b50107bb MN |
217 | xhci = hcd_to_xhci(hcd); |
218 | if (!xhci->sbrn) | |
219 | pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); | |
220 | ||
da3c9c4f | 221 | retval = xhci_gen_setup(hcd, xhci_pci_quirks); |
66d4eadd | 222 | if (retval) |
da3c9c4f | 223 | return retval; |
006d5820 | 224 | |
da3c9c4f SAS |
225 | if (!usb_hcd_is_primary_hcd(hcd)) |
226 | return 0; | |
66d4eadd | 227 | |
66d4eadd SS |
228 | xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn); |
229 | ||
230 | /* Find any debug ports */ | |
b02d0ed6 SS |
231 | retval = xhci_pci_reinit(xhci, pdev); |
232 | if (!retval) | |
233 | return retval; | |
234 | ||
b02d0ed6 SS |
235 | return retval; |
236 | } | |
237 | ||
f6ff0ac8 SS |
238 | /* |
239 | * We need to register our own PCI probe function (instead of the USB core's | |
240 | * function) in order to create a second roothub under xHCI. | |
241 | */ | |
242 | static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
243 | { | |
244 | int retval; | |
245 | struct xhci_hcd *xhci; | |
246 | struct hc_driver *driver; | |
247 | struct usb_hcd *hcd; | |
248 | ||
249 | driver = (struct hc_driver *)id->driver_data; | |
bcffae77 MN |
250 | |
251 | /* Prevent runtime suspending between USB-2 and USB-3 initialization */ | |
252 | pm_runtime_get_noresume(&dev->dev); | |
253 | ||
f6ff0ac8 SS |
254 | /* Register the USB 2.0 roothub. |
255 | * FIXME: USB core must know to register the USB 2.0 roothub first. | |
256 | * This is sort of silly, because we could just set the HCD driver flags | |
257 | * to say USB 2.0, but I'm not sure what the implications would be in | |
258 | * the other parts of the HCD code. | |
259 | */ | |
260 | retval = usb_hcd_pci_probe(dev, id); | |
261 | ||
262 | if (retval) | |
bcffae77 | 263 | goto put_runtime_pm; |
f6ff0ac8 SS |
264 | |
265 | /* USB 2.0 roothub is stored in the PCI device now. */ | |
266 | hcd = dev_get_drvdata(&dev->dev); | |
267 | xhci = hcd_to_xhci(hcd); | |
268 | xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev, | |
269 | pci_name(dev), hcd); | |
270 | if (!xhci->shared_hcd) { | |
271 | retval = -ENOMEM; | |
272 | goto dealloc_usb2_hcd; | |
273 | } | |
274 | ||
f6ff0ac8 | 275 | retval = usb_add_hcd(xhci->shared_hcd, dev->irq, |
b5dd18d8 | 276 | IRQF_SHARED); |
f6ff0ac8 SS |
277 | if (retval) |
278 | goto put_usb3_hcd; | |
279 | /* Roothub already marked as USB 3.0 speed */ | |
3b3db026 | 280 | |
8f873c1f HG |
281 | if (!(xhci->quirks & XHCI_BROKEN_STREAMS) && |
282 | HCC_MAX_PSA(xhci->hcc_params) >= 4) | |
14aec589 ON |
283 | xhci->shared_hcd->can_do_streams = 1; |
284 | ||
c3c5819a MN |
285 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
286 | xhci_pme_acpi_rtd3_enable(dev); | |
287 | ||
bcffae77 MN |
288 | /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */ |
289 | pm_runtime_put_noidle(&dev->dev); | |
290 | ||
f6ff0ac8 SS |
291 | return 0; |
292 | ||
293 | put_usb3_hcd: | |
294 | usb_put_hcd(xhci->shared_hcd); | |
295 | dealloc_usb2_hcd: | |
296 | usb_hcd_pci_remove(dev); | |
bcffae77 MN |
297 | put_runtime_pm: |
298 | pm_runtime_put_noidle(&dev->dev); | |
f6ff0ac8 SS |
299 | return retval; |
300 | } | |
301 | ||
b02d0ed6 SS |
302 | static void xhci_pci_remove(struct pci_dev *dev) |
303 | { | |
304 | struct xhci_hcd *xhci; | |
305 | ||
306 | xhci = hcd_to_xhci(pci_get_drvdata(dev)); | |
98d74f9c | 307 | xhci->xhc_state |= XHCI_STATE_REMOVING; |
f6ff0ac8 SS |
308 | if (xhci->shared_hcd) { |
309 | usb_remove_hcd(xhci->shared_hcd); | |
310 | usb_put_hcd(xhci->shared_hcd); | |
311 | } | |
b02d0ed6 | 312 | usb_hcd_pci_remove(dev); |
638298dc TI |
313 | |
314 | /* Workaround for spurious wakeups at shutdown with HSW */ | |
315 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
316 | pci_set_power_state(dev, PCI_D3hot); | |
66d4eadd SS |
317 | } |
318 | ||
5535b1d5 | 319 | #ifdef CONFIG_PM |
2b7627b7 TB |
320 | /* |
321 | * In some Intel xHCI controllers, in order to get D3 working, | |
322 | * through a vendor specific SSIC CONFIG register at offset 0x883c, | |
323 | * SSIC PORT need to be marked as "unused" before putting xHCI | |
324 | * into D3. After D3 exit, the SSIC port need to be marked as "used". | |
325 | * Without this change, xHCI might not enter D3 state. | |
2b7627b7 | 326 | */ |
7e70cbff | 327 | static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend) |
2b7627b7 TB |
328 | { |
329 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
2b7627b7 TB |
330 | u32 val; |
331 | void __iomem *reg; | |
fa895377 | 332 | int i; |
2b7627b7 | 333 | |
7e70cbff LB |
334 | for (i = 0; i < SSIC_PORT_NUM; i++) { |
335 | reg = (void __iomem *) xhci->cap_regs + | |
336 | SSIC_PORT_CFG2 + | |
337 | i * SSIC_PORT_CFG2_OFFSET; | |
338 | ||
339 | /* Notify SSIC that SSIC profile programming is not done. */ | |
340 | val = readl(reg) & ~PROG_DONE; | |
341 | writel(val, reg); | |
342 | ||
343 | /* Mark SSIC port as unused(suspend) or used(resume) */ | |
344 | val = readl(reg); | |
345 | if (suspend) | |
346 | val |= SSIC_PORT_UNUSED; | |
347 | else | |
348 | val &= ~SSIC_PORT_UNUSED; | |
349 | writel(val, reg); | |
350 | ||
351 | /* Notify SSIC that SSIC profile programming is done */ | |
352 | val = readl(reg) | PROG_DONE; | |
353 | writel(val, reg); | |
354 | readl(reg); | |
2b7627b7 | 355 | } |
7e70cbff LB |
356 | } |
357 | ||
358 | /* | |
359 | * Make sure PME works on some Intel xHCI controllers by writing 1 to clear | |
360 | * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4 | |
361 | */ | |
362 | static void xhci_pme_quirk(struct usb_hcd *hcd) | |
363 | { | |
364 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
365 | void __iomem *reg; | |
366 | u32 val; | |
2b7627b7 TB |
367 | |
368 | reg = (void __iomem *) xhci->cap_regs + 0x80a4; | |
369 | val = readl(reg); | |
370 | writel(val | BIT(28), reg); | |
371 | readl(reg); | |
372 | } | |
373 | ||
5535b1d5 AX |
374 | static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
375 | { | |
376 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c3897aa5 | 377 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
92149c93 | 378 | int ret; |
c3897aa5 SS |
379 | |
380 | /* | |
381 | * Systems with the TI redriver that loses port status change events | |
382 | * need to have the registers polled during D3, so avoid D3cold. | |
383 | */ | |
e1cd9727 | 384 | if (xhci->quirks & XHCI_COMP_MODE_QUIRK) |
c3897aa5 | 385 | pdev->no_d3cold = true; |
5535b1d5 | 386 | |
b8cb91e0 | 387 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
7e70cbff LB |
388 | xhci_pme_quirk(hcd); |
389 | ||
390 | if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) | |
391 | xhci_ssic_port_unused_quirk(hcd, true); | |
b8cb91e0 | 392 | |
92149c93 LB |
393 | ret = xhci_suspend(xhci, do_wakeup); |
394 | if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED)) | |
395 | xhci_ssic_port_unused_quirk(hcd, false); | |
396 | ||
397 | return ret; | |
5535b1d5 AX |
398 | } |
399 | ||
400 | static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated) | |
401 | { | |
402 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
69e848c2 | 403 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
5535b1d5 AX |
404 | int retval = 0; |
405 | ||
69e848c2 SS |
406 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
407 | * not support xHCI natively. That means that during system resume, it | |
408 | * may switch the ports back to EHCI so that users can use their | |
409 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
410 | * | |
411 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
412 | * enabled before resume, and switch the ports back to xHCI when the | |
413 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
414 | * writers. | |
415 | * | |
416 | * Unconditionally switch the ports back to xHCI after a system resume. | |
26b76798 MN |
417 | * It should not matter whether the EHCI or xHCI controller is |
418 | * resumed first. It's enough to do the switchover in xHCI because | |
419 | * USB core won't notice anything as the hub driver doesn't start | |
420 | * running again until after all the devices (including both EHCI and | |
421 | * xHCI host controllers) have been resumed. | |
69e848c2 | 422 | */ |
26b76798 MN |
423 | |
424 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) | |
425 | usb_enable_intel_xhci_ports(pdev); | |
69e848c2 | 426 | |
7e70cbff LB |
427 | if (xhci->quirks & XHCI_SSIC_PORT_UNUSED) |
428 | xhci_ssic_port_unused_quirk(hcd, false); | |
429 | ||
b8cb91e0 | 430 | if (xhci->quirks & XHCI_PME_STUCK_QUIRK) |
7e70cbff | 431 | xhci_pme_quirk(hcd); |
b8cb91e0 | 432 | |
5535b1d5 AX |
433 | retval = xhci_resume(xhci, hibernated); |
434 | return retval; | |
435 | } | |
436 | #endif /* CONFIG_PM */ | |
437 | ||
66d4eadd SS |
438 | /*-------------------------------------------------------------------------*/ |
439 | ||
440 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
441 | static const struct pci_device_id pci_ids[] = { { | |
442 | /* handle any USB 3.0 xHCI controller */ | |
443 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0), | |
444 | .driver_data = (unsigned long) &xhci_pci_hc_driver, | |
445 | }, | |
446 | { /* end: all zeroes */ } | |
447 | }; | |
448 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
449 | ||
450 | /* pci driver glue; this is a "new style" PCI driver module */ | |
451 | static struct pci_driver xhci_pci_driver = { | |
452 | .name = (char *) hcd_name, | |
453 | .id_table = pci_ids, | |
454 | ||
f6ff0ac8 | 455 | .probe = xhci_pci_probe, |
b02d0ed6 | 456 | .remove = xhci_pci_remove, |
66d4eadd SS |
457 | /* suspend and resume implemented later */ |
458 | ||
459 | .shutdown = usb_hcd_pci_shutdown, | |
f875fdbf | 460 | #ifdef CONFIG_PM |
5535b1d5 AX |
461 | .driver = { |
462 | .pm = &usb_hcd_pci_pm_ops | |
463 | }, | |
464 | #endif | |
66d4eadd SS |
465 | }; |
466 | ||
29e409f0 | 467 | static int __init xhci_pci_init(void) |
66d4eadd | 468 | { |
cd33a321 | 469 | xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides); |
1885d9a3 AB |
470 | #ifdef CONFIG_PM |
471 | xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend; | |
472 | xhci_pci_hc_driver.pci_resume = xhci_pci_resume; | |
473 | #endif | |
66d4eadd SS |
474 | return pci_register_driver(&xhci_pci_driver); |
475 | } | |
29e409f0 | 476 | module_init(xhci_pci_init); |
66d4eadd | 477 | |
29e409f0 | 478 | static void __exit xhci_pci_exit(void) |
66d4eadd SS |
479 | { |
480 | pci_unregister_driver(&xhci_pci_driver); | |
481 | } | |
29e409f0 AB |
482 | module_exit(xhci_pci_exit); |
483 | ||
484 | MODULE_DESCRIPTION("xHCI PCI Host Controller Driver"); | |
485 | MODULE_LICENSE("GPL"); |