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Merge tag 'pci-v4.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[linux-2.6-block.git] / drivers / usb / host / xhci-pci.c
CommitLineData
66d4eadd
SS		 1/*
2 * xHCI host controller driver PCI Bus Glue.
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
7fc2a616 24#include <linux/slab.h>
6eb0de82 25#include <linux/module.h>
c3c5819a 26#include <linux/acpi.h>
66d4eadd
SS		 27
28#include "xhci.h"
4bdfe4c3 29#include "xhci-trace.h"
66d4eadd 30
fa895377
LB		 31#define SSIC_PORT_NUM 2
32#define SSIC_PORT_CFG2 0x880c
33#define SSIC_PORT_CFG2_OFFSET 0x30
abce329c
RM		 34#define PROG_DONE (1 << 30)
35#define SSIC_PORT_UNUSED (1 << 31)
36
ac9d8fe7
SS		 37/* Device for a quirk */
38#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
39#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
d95815ba 40#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
bba18e33 41#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
ac9d8fe7 42
c877b3b2 43#define PCI_VENDOR_ID_ETRON 0x1b6f
170625e9 44#define PCI_DEVICE_ID_EJ168 0x7023
c877b3b2 45
638298dc
TI		 46#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
47#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
4c39135a 48#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
b8cb91e0
MN		 49#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
50#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
51#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
ccc04afb 52#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
0d46faca 53#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
346e9973 54#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
a0c16630 55#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
638298dc 56
dec08194
JC		 57#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
58#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
59#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
60#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
61
66d4eadd
SS		 62static const char hcd_name[] = "xhci_hcd";
63
1885d9a3
AB		 64static struct hc_driver __read_mostly xhci_pci_hc_driver;
65
cd33a321
RQ		 66static int xhci_pci_setup(struct usb_hcd *hcd);
67
68static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
cd33a321
RQ		 69 .reset = xhci_pci_setup,
70};
71
66d4eadd
SS		 72/* called after powerup, by probe or system-pm "wakeup" */
73static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
74{
75 /*
76 * TODO: Implement finding debug ports later.
77 * TODO: see if there are any quirks that need to be added to handle
78 * new extended capabilities.
79 */
80
81 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
82 if (!pci_set_mwi(pdev))
83 xhci_dbg(xhci, "MWI active\n");
84
85 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
86 return 0;
87}
88
da3c9c4f
SAS		 89static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
90{
91 struct pci_dev *pdev = to_pci_dev(dev);
92
ac9d8fe7
SS		 93 /* Look for vendor-specific quirks */
94 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
bba18e33
SS		 95 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
96 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
97 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
98 pdev->revision == 0x0) {
ac9d8fe7 99 xhci->quirks |= XHCI_RESET_EP_QUIRK;
4bdfe4c3
XR		 100 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
101 "QUIRK: Fresco Logic xHC needs configure"
102 " endpoint cmd after reset endpoint");
f5182b41 103 }
455f5892
ON		 104 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
105 pdev->revision == 0x4) {
106 xhci->quirks |= XHCI_SLOW_SUSPEND;
107 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
108 "QUIRK: Fresco Logic xHC revision %u"
109 "must be suspended extra slowly",
110 pdev->revision);
111 }
7f5c4d63
HG		 112 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
113 xhci->quirks |= XHCI_BROKEN_STREAMS;
f5182b41
SS		 114 /* Fresco Logic confirms: all revisions of this chip do not
115 * support MSI, even though some of them claim to in their PCI
116 * capabilities.
117 */
118 xhci->quirks |= XHCI_BROKEN_MSI;
4bdfe4c3
XR		 119 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
120 "QUIRK: Fresco Logic revision %u "
121 "has broken MSI implementation",
f5182b41 122 pdev->revision);
1530bbc6 123 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
ac9d8fe7 124 }
f5182b41 125
d95815ba
HG		 126 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
127 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
128 xhci->quirks |= XHCI_BROKEN_STREAMS;
129
0238634d
SS		 130 if (pdev->vendor == PCI_VENDOR_ID_NEC)
131 xhci->quirks |= XHCI_NEC_HOST;
ac9d8fe7 132
7e393a83
AX		 133 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
134 xhci->quirks |= XHCI_AMD_0x96_HOST;
135
c41136b0
AX		 136 /* AMD PLL quirk */
137 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
138 xhci->quirks |= XHCI_AMD_PLL_FIX;
2597fe99
HR		 139
140 if (pdev->vendor == PCI_VENDOR_ID_AMD)
141 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
142
dec08194
JC		 143 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
144 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
145 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
146 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
147 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
148 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
149
e3567d2c
SS		 150 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
151 xhci->quirks |= XHCI_LPM_SUPPORT;
152 xhci->quirks |= XHCI_INTEL_HOST;
227a4fd8 153 xhci->quirks |= XHCI_AVOID_BEI;
e3567d2c 154 }
ad808333
SS		 155 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
156 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
2cf95c18
SS		 157 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
158 xhci->limit_active_eps = 64;
86cc558e 159 xhci->quirks |= XHCI_SW_BW_CHECKING;
e95829f4
SS		 160 /*
161 * PPT desktop boards DH77EB and DH77DF will power back on after
162 * a few seconds of being shutdown. The fix for this is to
163 * switch the ports from xHCI to EHCI on shutdown. We can't use
164 * DMI information to find those particular boards (since each
165 * vendor will change the board name), so we have to key off all
166 * PPT chipsets.
167 */
168 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
ad808333 169 }
0a939993 170 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
4c39135a
MN		 171 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
172 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
c09ec25d 173 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
fd7cd061 174 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
638298dc 175 }
b8cb91e0
MN		 176 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
177 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
178 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
ccc04afb 179 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
0d46faca 180 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
6c97cfc1 181 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
a0c16630
MN		 182 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
183 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
b8cb91e0
MN		 184 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
185 }
7e70cbff
LB		 186 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
187 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
188 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
189 }
346e9973
MN		 190 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
191 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
a0c16630
MN		 192 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
193 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
346e9973
MN		 194 xhci->quirks |= XHCI_MISSING_CAS;
195
c877b3b2 196 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
170625e9 197 pdev->device == PCI_DEVICE_ID_EJ168) {
c877b3b2 198 xhci->quirks |= XHCI_RESET_ON_RESUME;
5cb7df2b 199 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
8f873c1f 200 xhci->quirks |= XHCI_BROKEN_STREAMS;
c877b3b2 201 }
1aa9578c 202 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
6db249eb 203 pdev->device == 0x0015)
1aa9578c 204 xhci->quirks |= XHCI_RESET_ON_RESUME;
457a4f61
EF		 205 if (pdev->vendor == PCI_VENDOR_ID_VIA)
206 xhci->quirks |= XHCI_RESET_ON_RESUME;
85f4e45b 207
e21eba05
HG		 208 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
209 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
210 pdev->device == 0x3432)
211 xhci->quirks |= XHCI_BROKEN_STREAMS;
212
2391eacb
HG		 213 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
214 pdev->device == 0x1042)
215 xhci->quirks |= XHCI_BROKEN_STREAMS;
d2f48f05
CL		 216 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
217 pdev->device == 0x1142)
218 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
2391eacb 219
69307ccb
RQ		 220 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
221 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
222
85f4e45b
ON		 223 if (xhci->quirks & XHCI_RESET_ON_RESUME)
224 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
225 "QUIRK: Resetting on resume");
da3c9c4f 226}
c41136b0 227
c3c5819a
MN		 228#ifdef CONFIG_ACPI
229static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
230{
94116f81
AS		 231 static const guid_t intel_dsm_guid =
232 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
233 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
84ed9152
MW		 234 union acpi_object *obj;
235
94116f81 236 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
84ed9152
MW		 237 NULL);
238 ACPI_FREE(obj);
c3c5819a
MN		 239}
240#else
84ed9152 241static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
c3c5819a
MN		 242#endif /* CONFIG_ACPI */
243
da3c9c4f
SAS		 244/* called during probe() after chip reset completes */
245static int xhci_pci_setup(struct usb_hcd *hcd)
246{
247 struct xhci_hcd *xhci;
248 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
249 int retval;
66d4eadd 250
b50107bb
MN		 251 xhci = hcd_to_xhci(hcd);
252 if (!xhci->sbrn)
253 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
254
da3c9c4f 255 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
66d4eadd 256 if (retval)
da3c9c4f 257 return retval;
006d5820 258
da3c9c4f
SAS		 259 if (!usb_hcd_is_primary_hcd(hcd))
260 return 0;
66d4eadd 261
66d4eadd
SS		 262 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
263
264 /* Find any debug ports */
989bad11 265 return xhci_pci_reinit(xhci, pdev);
b02d0ed6
SS		 266}
267
f6ff0ac8
SS		 268/*
269 * We need to register our own PCI probe function (instead of the USB core's
270 * function) in order to create a second roothub under xHCI.
271 */
272static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
273{
274 int retval;
275 struct xhci_hcd *xhci;
276 struct hc_driver *driver;
277 struct usb_hcd *hcd;
278
279 driver = (struct hc_driver *)id->driver_data;
bcffae77
MN		 280
281 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
282 pm_runtime_get_noresume(&dev->dev);
283
f6ff0ac8
SS		 284 /* Register the USB 2.0 roothub.
285 * FIXME: USB core must know to register the USB 2.0 roothub first.
286 * This is sort of silly, because we could just set the HCD driver flags
287 * to say USB 2.0, but I'm not sure what the implications would be in
288 * the other parts of the HCD code.
289 */
290 retval = usb_hcd_pci_probe(dev, id);
291
292 if (retval)
bcffae77 293 goto put_runtime_pm;
f6ff0ac8
SS		 294
295 /* USB 2.0 roothub is stored in the PCI device now. */
296 hcd = dev_get_drvdata(&dev->dev);
297 xhci = hcd_to_xhci(hcd);
298 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
299 pci_name(dev), hcd);
300 if (!xhci->shared_hcd) {
301 retval = -ENOMEM;
302 goto dealloc_usb2_hcd;
303 }
304
f6ff0ac8 305 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
b5dd18d8 306 IRQF_SHARED);
f6ff0ac8
SS		 307 if (retval)
308 goto put_usb3_hcd;
309 /* Roothub already marked as USB 3.0 speed */
3b3db026 310
8f873c1f
HG		 311 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
312 HCC_MAX_PSA(xhci->hcc_params) >= 4)
14aec589
ON		 313 xhci->shared_hcd->can_do_streams = 1;
314
c3c5819a
MN		 315 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
316 xhci_pme_acpi_rtd3_enable(dev);
317
bcffae77
MN		 318 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
319 pm_runtime_put_noidle(&dev->dev);
320
f6ff0ac8
SS		 321 return 0;
322
323put_usb3_hcd:
324 usb_put_hcd(xhci->shared_hcd);
325dealloc_usb2_hcd:
326 usb_hcd_pci_remove(dev);
bcffae77
MN		 327put_runtime_pm:
328 pm_runtime_put_noidle(&dev->dev);
f6ff0ac8
SS		 329 return retval;
330}
331
b02d0ed6
SS		 332static void xhci_pci_remove(struct pci_dev *dev)
333{
334 struct xhci_hcd *xhci;
335
336 xhci = hcd_to_xhci(pci_get_drvdata(dev));
98d74f9c 337 xhci->xhc_state |= XHCI_STATE_REMOVING;
f6ff0ac8
SS		 338 if (xhci->shared_hcd) {
339 usb_remove_hcd(xhci->shared_hcd);
340 usb_put_hcd(xhci->shared_hcd);
341 }
638298dc
TI		 342
343 /* Workaround for spurious wakeups at shutdown with HSW */
344 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
345 pci_set_power_state(dev, PCI_D3hot);
f1f6d9a8
MN		 346
347 usb_hcd_pci_remove(dev);
66d4eadd
SS		 348}
349
5535b1d5 350#ifdef CONFIG_PM
2b7627b7
TB		 351/*
352 * In some Intel xHCI controllers, in order to get D3 working,
353 * through a vendor specific SSIC CONFIG register at offset 0x883c,
354 * SSIC PORT need to be marked as "unused" before putting xHCI
355 * into D3. After D3 exit, the SSIC port need to be marked as "used".
356 * Without this change, xHCI might not enter D3 state.
2b7627b7 357 */
7e70cbff 358static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
2b7627b7
TB		 359{
360 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2b7627b7
TB		 361 u32 val;
362 void __iomem *reg;
fa895377 363 int i;
2b7627b7 364
7e70cbff
LB		 365 for (i = 0; i < SSIC_PORT_NUM; i++) {
366 reg = (void __iomem *) xhci->cap_regs +
367 SSIC_PORT_CFG2 +
368 i * SSIC_PORT_CFG2_OFFSET;
369
370 /* Notify SSIC that SSIC profile programming is not done. */
371 val = readl(reg) & ~PROG_DONE;
372 writel(val, reg);
373
374 /* Mark SSIC port as unused(suspend) or used(resume) */
375 val = readl(reg);
376 if (suspend)
377 val |= SSIC_PORT_UNUSED;
378 else
379 val &= ~SSIC_PORT_UNUSED;
380 writel(val, reg);
381
382 /* Notify SSIC that SSIC profile programming is done */
383 val = readl(reg) | PROG_DONE;
384 writel(val, reg);
385 readl(reg);
2b7627b7 386 }
7e70cbff
LB		 387}
388
389/*
390 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
391 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
392 */
393static void xhci_pme_quirk(struct usb_hcd *hcd)
394{
395 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
396 void __iomem *reg;
397 u32 val;
2b7627b7
TB		 398
399 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
400 val = readl(reg);
401 writel(val | BIT(28), reg);
402 readl(reg);
403}
404
5535b1d5
AX		 405static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
406{
407 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c3897aa5 408 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
92149c93 409 int ret;
c3897aa5
SS		 410
411 /*
412 * Systems with the TI redriver that loses port status change events
413 * need to have the registers polled during D3, so avoid D3cold.
414 */
e1cd9727 415 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
9d26d3a8 416 pci_d3cold_disable(pdev);
5535b1d5 417
b8cb91e0 418 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff
LB		 419 xhci_pme_quirk(hcd);
420
421 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
422 xhci_ssic_port_unused_quirk(hcd, true);
b8cb91e0 423
92149c93
LB		 424 ret = xhci_suspend(xhci, do_wakeup);
425 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
426 xhci_ssic_port_unused_quirk(hcd, false);
427
428 return ret;
5535b1d5
AX		 429}
430
431static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
432{
433 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
69e848c2 434 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
5535b1d5
AX		 435 int retval = 0;
436
69e848c2
SS		 437 /* The BIOS on systems with the Intel Panther Point chipset may or may
438 * not support xHCI natively. That means that during system resume, it
439 * may switch the ports back to EHCI so that users can use their
440 * keyboard to select a kernel from GRUB after resume from hibernate.
441 *
442 * The BIOS is supposed to remember whether the OS had xHCI ports
443 * enabled before resume, and switch the ports back to xHCI when the
444 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
445 * writers.
446 *
447 * Unconditionally switch the ports back to xHCI after a system resume.
26b76798
MN		 448 * It should not matter whether the EHCI or xHCI controller is
449 * resumed first. It's enough to do the switchover in xHCI because
450 * USB core won't notice anything as the hub driver doesn't start
451 * running again until after all the devices (including both EHCI and
452 * xHCI host controllers) have been resumed.
69e848c2 453 */
26b76798
MN		 454
455 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
456 usb_enable_intel_xhci_ports(pdev);
69e848c2 457
7e70cbff
LB		 458 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
459 xhci_ssic_port_unused_quirk(hcd, false);
460
b8cb91e0 461 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
7e70cbff 462 xhci_pme_quirk(hcd);
b8cb91e0 463
5535b1d5
AX		 464 retval = xhci_resume(xhci, hibernated);
465 return retval;
466}
467#endif /* CONFIG_PM */
468
66d4eadd
SS		 469/*-------------------------------------------------------------------------*/
470
471/* PCI driver selection metadata; PCI hotplugging uses this */
472static const struct pci_device_id pci_ids[] = { {
473 /* handle any USB 3.0 xHCI controller */
474 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
475 .driver_data = (unsigned long) &xhci_pci_hc_driver,
476 },
477 { /* end: all zeroes */ }
478};
479MODULE_DEVICE_TABLE(pci, pci_ids);
480
481/* pci driver glue; this is a "new style" PCI driver module */
482static struct pci_driver xhci_pci_driver = {
483 .name = (char *) hcd_name,
484 .id_table = pci_ids,
485
f6ff0ac8 486 .probe = xhci_pci_probe,
b02d0ed6 487 .remove = xhci_pci_remove,
66d4eadd
SS		 488 /* suspend and resume implemented later */
489
490 .shutdown = usb_hcd_pci_shutdown,
f875fdbf 491#ifdef CONFIG_PM
5535b1d5
AX		 492 .driver = {
493 .pm = &usb_hcd_pci_pm_ops
494 },
495#endif
66d4eadd
SS		 496};
497
29e409f0 498static int __init xhci_pci_init(void)
66d4eadd 499{
cd33a321 500 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
1885d9a3
AB		 501#ifdef CONFIG_PM
502 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
503 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
504#endif
66d4eadd
SS		 505 return pci_register_driver(&xhci_pci_driver);
506}
29e409f0 507module_init(xhci_pci_init);
66d4eadd 508
29e409f0 509static void __exit xhci_pci_exit(void)
66d4eadd
SS		 510{
511 pci_unregister_driver(&xhci_pci_driver);
512}
29e409f0
AB		 513module_exit(xhci_pci_exit);
514
515MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
516MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)