[linux-2.6-block.git] / drivers / usb / host / xhci-mtk.h

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author:
 *  Zhigang.Wei <zhigang.wei@mediatek.com>
 *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
 */

#ifndef _XHCI_MTK_H_
#define _XHCI_MTK_H_

#include "xhci.h"

/**
 * To simplify scheduler algorithm, set a upper limit for ESIT,
 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
 * round down to the limit value, that means allocating more
 * bandwidth to it.
 */
#define XHCI_MTK_MAX_ESIT	64

/**
 * @split_bit_map: used to avoid split microframes overlay
 * @ep_list: Endpoints using this TT
 * @usb_tt: usb TT related
 * @tt_port: TT port number
 */
struct mu3h_sch_tt {
	DECLARE_BITMAP(split_bit_map, XHCI_MTK_MAX_ESIT);
	struct list_head ep_list;
	struct usb_tt *usb_tt;
	int tt_port;
};

/**
 * struct mu3h_sch_bw_info: schedule information for bandwidth domain
 *
 * @bus_bw: array to keep track of bandwidth already used at each uframes
 * @bw_ep_list: eps in the bandwidth domain
 *
 * treat a HS root port as a bandwidth domain, but treat a SS root port as
 * two bandwidth domains, one for IN eps and another for OUT eps.
 */
struct mu3h_sch_bw_info {
	u32 bus_bw[XHCI_MTK_MAX_ESIT];
	struct list_head bw_ep_list;
};

/**
 * struct mu3h_sch_ep_info: schedule information for endpoint
 *
 * @esit: unit is 125us, equal to 2 << Interval field in ep-context
 * @num_budget_microframes: number of continuous uframes
 *		(@repeat==1) scheduled within the interval
 * @bw_cost_per_microframe: bandwidth cost per microframe
 * @endpoint: linked into bandwidth domain which it belongs to
 * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
 * @sch_tt: mu3h_sch_tt linked into
 * @ep_type: endpoint type
 * @maxpkt: max packet size of endpoint
 * @ep: address of usb_host_endpoint struct
 * @offset: which uframe of the interval that transfer should be
 *		scheduled first time within the interval
 * @repeat: the time gap between two uframes that transfers are
 *		scheduled within a interval. in the simple algorithm, only
 *		assign 0 or 1 to it; 0 means using only one uframe in a
 *		interval, and 1 means using @num_budget_microframes
 *		continuous uframes
 * @pkts: number of packets to be transferred in the scheduled uframes
 * @cs_count: number of CS that host will trigger
 * @burst_mode: burst mode for scheduling. 0: normal burst mode,
 *		distribute the bMaxBurst+1 packets for a single burst
 *		according to @pkts and @repeat, repeate the burst multiple
 *		times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
 *		according to @pkts and @repeat. normal mode is used by
 *		default
 * @bw_budget_table: table to record bandwidth budget per microframe
 */
struct mu3h_sch_ep_info {
	u32 esit;
	u32 num_budget_microframes;
	u32 bw_cost_per_microframe;
	struct list_head endpoint;
	struct list_head tt_endpoint;
	struct mu3h_sch_tt *sch_tt;
	u32 ep_type;
	u32 maxpkt;
	void *ep;
	/*
	 * mtk xHCI scheduling information put into reserved DWs
	 * in ep context
	 */
	u32 offset;
	u32 repeat;
	u32 pkts;
	u32 cs_count;
	u32 burst_mode;
	u32 bw_budget_table[0];
};

#define MU3C_U3_PORT_MAX 4
#define MU3C_U2_PORT_MAX 5

/**
 * struct mu3c_ippc_regs: MTK ssusb ip port control registers
 * @ip_pw_ctr0~3: ip power and clock control registers
 * @ip_pw_sts1~2: ip power and clock status registers
 * @ip_xhci_cap: ip xHCI capability register
 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
 * @u2_phy_pll: usb2 phy pll control register
 */
struct mu3c_ippc_regs {
	__le32 ip_pw_ctr0;
	__le32 ip_pw_ctr1;
	__le32 ip_pw_ctr2;
	__le32 ip_pw_ctr3;
	__le32 ip_pw_sts1;
	__le32 ip_pw_sts2;
	__le32 reserved0[3];
	__le32 ip_xhci_cap;
	__le32 reserved1[2];
	__le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
	__le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
	__le32 reserved2;
	__le32 u2_phy_pll;
	__le32 reserved3[33]; /* 0x80 ~ 0xff */
};

struct xhci_hcd_mtk {
	struct device *dev;
	struct usb_hcd *hcd;
	struct mu3h_sch_bw_info *sch_array;
	struct mu3c_ippc_regs __iomem *ippc_regs;
	bool has_ippc;
	int num_u2_ports;
	int num_u3_ports;
	int u3p_dis_msk;
	struct regulator *vusb33;
	struct regulator *vbus;
	struct clk *sys_clk;	/* sys and mac clock */
	struct clk *ref_clk;
	struct clk *mcu_clk;
	struct clk *dma_clk;
	struct regmap *pericfg;
	struct phy **phys;
	int num_phys;
	bool lpm_support;
	/* usb remote wakeup */
	bool uwk_en;
	struct regmap *uwk;
	u32 uwk_reg_base;
	u32 uwk_vers;
};

static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
{
	return dev_get_drvdata(hcd->self.controller);
}

#if IS_ENABLED(CONFIG_USB_XHCI_MTK)
int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
		struct usb_host_endpoint *ep);
void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
		struct usb_host_endpoint *ep);

#else
static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
	struct usb_device *udev, struct usb_host_endpoint *ep)
{
	return 0;
}

static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
	struct usb_device *udev, struct usb_host_endpoint *ep)
{
}

#endif

#endif		/* _XHCI_MTK_H_ */
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
0cbd4b34 CY	2	/*
	3	* Copyright (c) 2015 MediaTek Inc.
	4	* Author:
	5	* Zhigang.Wei <zhigang.wei@mediatek.com>
	6	* Chunfeng.Yun <chunfeng.yun@mediatek.com>
0cbd4b34 CY	7	*/
	8
	9	#ifndef _XHCI_MTK_H_
	10	#define _XHCI_MTK_H_
	11
	12	#include "xhci.h"
	13
	14	/**
	15	* To simplify scheduler algorithm, set a upper limit for ESIT,
	16	* if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
	17	* round down to the limit value, that means allocating more
	18	* bandwidth to it.
	19	*/
	20	#define XHCI_MTK_MAX_ESIT 64
	21
08e469de CY	22	/**
	23	* @split_bit_map: used to avoid split microframes overlay
	24	* @ep_list: Endpoints using this TT
	25	* @usb_tt: usb TT related
	26	* @tt_port: TT port number
	27	*/
	28	struct mu3h_sch_tt {
	29	DECLARE_BITMAP(split_bit_map, XHCI_MTK_MAX_ESIT);
	30	struct list_head ep_list;
	31	struct usb_tt *usb_tt;
	32	int tt_port;
	33	};
	34
0cbd4b34 CY	35	/**
	36	* struct mu3h_sch_bw_info: schedule information for bandwidth domain
	37	*
	38	* @bus_bw: array to keep track of bandwidth already used at each uframes
	39	* @bw_ep_list: eps in the bandwidth domain
	40	*
	41	* treat a HS root port as a bandwidth domain, but treat a SS root port as
	42	* two bandwidth domains, one for IN eps and another for OUT eps.
	43	*/
	44	struct mu3h_sch_bw_info {
	45	u32 bus_bw[XHCI_MTK_MAX_ESIT];
	46	struct list_head bw_ep_list;
	47	};
	48
	49	/**
	50	* struct mu3h_sch_ep_info: schedule information for endpoint
	51	*
	52	* @esit: unit is 125us, equal to 2 << Interval field in ep-context
	53	* @num_budget_microframes: number of continuous uframes
	54	* (@repeat==1) scheduled within the interval
	55	* @bw_cost_per_microframe: bandwidth cost per microframe
	56	* @endpoint: linked into bandwidth domain which it belongs to
08e469de CY	57	* @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
	58	* @sch_tt: mu3h_sch_tt linked into
	59	* @ep_type: endpoint type
	60	* @maxpkt: max packet size of endpoint
0cbd4b34 CY	61	* @ep: address of usb_host_endpoint struct
	62	* @offset: which uframe of the interval that transfer should be
	63	* scheduled first time within the interval
	64	* @repeat: the time gap between two uframes that transfers are
	65	* scheduled within a interval. in the simple algorithm, only
	66	* assign 0 or 1 to it; 0 means using only one uframe in a
	67	* interval, and 1 means using @num_budget_microframes
	68	* continuous uframes
	69	* @pkts: number of packets to be transferred in the scheduled uframes
	70	* @cs_count: number of CS that host will trigger
	71	* @burst_mode: burst mode for scheduling. 0: normal burst mode,
	72	* distribute the bMaxBurst+1 packets for a single burst
	73	* according to @pkts and @repeat, repeate the burst multiple
	74	* times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
	75	* according to @pkts and @repeat. normal mode is used by
	76	* default
95b516c1	77	* @bw_budget_table: table to record bandwidth budget per microframe
0cbd4b34 CY	78	*/
	79	struct mu3h_sch_ep_info {
	80	u32 esit;
	81	u32 num_budget_microframes;
	82	u32 bw_cost_per_microframe;
	83	struct list_head endpoint;
08e469de CY	84	struct list_head tt_endpoint;
	85	struct mu3h_sch_tt *sch_tt;
	86	u32 ep_type;
	87	u32 maxpkt;
0cbd4b34 CY	88	void *ep;
	89	/*
	90	* mtk xHCI scheduling information put into reserved DWs
	91	* in ep context
	92	*/
	93	u32 offset;
	94	u32 repeat;
	95	u32 pkts;
	96	u32 cs_count;
	97	u32 burst_mode;
95b516c1	98	u32 bw_budget_table[0];
0cbd4b34 CY	99	};
	100
	101	#define MU3C_U3_PORT_MAX 4
	102	#define MU3C_U2_PORT_MAX 5
	103
	104	/**
	105	* struct mu3c_ippc_regs: MTK ssusb ip port control registers
	106	* @ip_pw_ctr0~3: ip power and clock control registers
	107	* @ip_pw_sts1~2: ip power and clock status registers
	108	* @ip_xhci_cap: ip xHCI capability register
	109	* @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
	110	* @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
	111	* @u2_phy_pll: usb2 phy pll control register
	112	*/
	113	struct mu3c_ippc_regs {
	114	__le32 ip_pw_ctr0;
	115	__le32 ip_pw_ctr1;
	116	__le32 ip_pw_ctr2;
	117	__le32 ip_pw_ctr3;
	118	__le32 ip_pw_sts1;
	119	__le32 ip_pw_sts2;
	120	__le32 reserved0[3];
	121	__le32 ip_xhci_cap;
	122	__le32 reserved1[2];
	123	__le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
	124	__le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
	125	__le32 reserved2;
	126	__le32 u2_phy_pll;
	127	__le32 reserved3[33]; /* 0x80 ~ 0xff */
	128	};
	129
	130	struct xhci_hcd_mtk {
	131	struct device *dev;
	132	struct usb_hcd *hcd;
	133	struct mu3h_sch_bw_info *sch_array;
	134	struct mu3c_ippc_regs __iomem *ippc_regs;
065d48cf	135	bool has_ippc;
0cbd4b34 CY	136	int num_u2_ports;
0cbd4b34 CY	137	int num_u3_ports;
55ba6e9e	138	int u3p_dis_msk;
0cbd4b34 CY	139	struct regulator *vusb33;
	140	struct regulator *vbus;
	141	struct clk sys_clk; / sys and mac clock */
9c4afd42	142	struct clk *ref_clk;
b6bb72cf CY	143	struct clk *mcu_clk;
b6bb72cf CY	144	struct clk *dma_clk;
0cbd4b34 CY	145	struct regmap *pericfg;
	146	struct phy **phys;
	147	int num_phys;
0cbd4b34	148	bool lpm_support;
a2ecc4df CY	149	/* usb remote wakeup */
	150	bool uwk_en;
	151	struct regmap *uwk;
	152	u32 uwk_reg_base;
	153	u32 uwk_vers;
0cbd4b34 CY	154	};
	155
	156	static inline struct xhci_hcd_mtk hcd_to_mtk(struct usb_hcd hcd)
	157	{
	158	return dev_get_drvdata(hcd->self.controller);
	159	}
	160
	161	#if IS_ENABLED(CONFIG_USB_XHCI_MTK)
	162	int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
	163	void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
	164	int xhci_mtk_add_ep_quirk(struct usb_hcd hcd, struct usb_device udev,
	165	struct usb_host_endpoint *ep);
	166	void xhci_mtk_drop_ep_quirk(struct usb_hcd hcd, struct usb_device udev,
	167	struct usb_host_endpoint *ep);
	168
	169	#else
	170	static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
	171	struct usb_device udev, struct usb_host_endpoint ep)
	172	{
	173	return 0;
	174	}
	175
	176	static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
	177	struct usb_device udev, struct usb_host_endpoint ep)
	178	{
	179	}
	180
	181	#endif
	182
	183	#endif /* _XHCI_MTK_H_ */