[linux-2.6-block.git] / drivers / usb / host / xhci-mtk.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MediaTek xHCI Host Controller Driver
 *
 * Copyright (c) 2015 MediaTek Inc.
 * Author:
 *  Chunfeng Yun <chunfeng.yun@mediatek.com>
 */

#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>

#include "xhci.h"
#include "xhci-mtk.h"

/* ip_pw_ctrl0 register */
#define CTRL0_IP_SW_RST	BIT(0)

/* ip_pw_ctrl1 register */
#define CTRL1_IP_HOST_PDN	BIT(0)

/* ip_pw_ctrl2 register */
#define CTRL2_IP_DEV_PDN	BIT(0)

/* ip_pw_sts1 register */
#define STS1_IP_SLEEP_STS	BIT(30)
#define STS1_U3_MAC_RST	BIT(16)
#define STS1_XHCI_RST		BIT(11)
#define STS1_SYS125_RST	BIT(10)
#define STS1_REF_RST		BIT(8)
#define STS1_SYSPLL_STABLE	BIT(0)

/* ip_xhci_cap register */
#define CAP_U3_PORT_NUM(p)	((p) & 0xff)
#define CAP_U2_PORT_NUM(p)	(((p) >> 8) & 0xff)

/* u3_ctrl_p register */
#define CTRL_U3_PORT_HOST_SEL	BIT(2)
#define CTRL_U3_PORT_PDN	BIT(1)
#define CTRL_U3_PORT_DIS	BIT(0)

/* u2_ctrl_p register */
#define CTRL_U2_PORT_HOST_SEL	BIT(2)
#define CTRL_U2_PORT_PDN	BIT(1)
#define CTRL_U2_PORT_DIS	BIT(0)

/* u2_phy_pll register */
#define CTRL_U2_FORCE_PLL_STB	BIT(28)

/* usb remote wakeup registers in syscon */
/* mt8173 etc */
#define PERI_WK_CTRL1	0x4
#define WC1_IS_C(x)	(((x) & 0xf) << 26)  /* cycle debounce */
#define WC1_IS_EN	BIT(25)
#define WC1_IS_P	BIT(6)  /* polarity for ip sleep */

/* mt2712 etc */
#define PERI_SSUSB_SPM_CTRL	0x0
#define SSC_IP_SLEEP_EN	BIT(4)
#define SSC_SPM_INT_EN		BIT(1)

enum ssusb_uwk_vers {
	SSUSB_UWK_V1 = 1,
	SSUSB_UWK_V2,
};

static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
{
	struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
	u32 value, check_val;
	int u3_ports_disabed = 0;
	int ret;
	int i;

	if (!mtk->has_ippc)
		return 0;

	/* power on host ip */
	value = readl(&ippc->ip_pw_ctr1);
	value &= ~CTRL1_IP_HOST_PDN;
	writel(value, &ippc->ip_pw_ctr1);

	/* power on and enable u3 ports except skipped ones */
	for (i = 0; i < mtk->num_u3_ports; i++) {
		if ((0x1 << i) & mtk->u3p_dis_msk) {
			u3_ports_disabed++;
			continue;
		}

		value = readl(&ippc->u3_ctrl_p[i]);
		value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
		value |= CTRL_U3_PORT_HOST_SEL;
		writel(value, &ippc->u3_ctrl_p[i]);
	}

	/* power on and enable all u2 ports */
	for (i = 0; i < mtk->num_u2_ports; i++) {
		value = readl(&ippc->u2_ctrl_p[i]);
		value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
		value |= CTRL_U2_PORT_HOST_SEL;
		writel(value, &ippc->u2_ctrl_p[i]);
	}

	/*
	 * wait for clocks to be stable, and clock domains reset to
	 * be inactive after power on and enable ports
	 */
	check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
			STS1_SYS125_RST | STS1_XHCI_RST;

	if (mtk->num_u3_ports > u3_ports_disabed)
		check_val |= STS1_U3_MAC_RST;

	ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
			  (check_val == (value & check_val)), 100, 20000);
	if (ret) {
		dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
		return ret;
	}

	return 0;
}

static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
{
	struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
	u32 value;
	int ret;
	int i;

	if (!mtk->has_ippc)
		return 0;

	/* power down u3 ports except skipped ones */
	for (i = 0; i < mtk->num_u3_ports; i++) {
		if ((0x1 << i) & mtk->u3p_dis_msk)
			continue;

		value = readl(&ippc->u3_ctrl_p[i]);
		value |= CTRL_U3_PORT_PDN;
		writel(value, &ippc->u3_ctrl_p[i]);
	}

	/* power down all u2 ports */
	for (i = 0; i < mtk->num_u2_ports; i++) {
		value = readl(&ippc->u2_ctrl_p[i]);
		value |= CTRL_U2_PORT_PDN;
		writel(value, &ippc->u2_ctrl_p[i]);
	}

	/* power down host ip */
	value = readl(&ippc->ip_pw_ctr1);
	value |= CTRL1_IP_HOST_PDN;
	writel(value, &ippc->ip_pw_ctr1);

	/* wait for host ip to sleep */
	ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
			  (value & STS1_IP_SLEEP_STS), 100, 100000);
	if (ret) {
		dev_err(mtk->dev, "ip sleep failed!!!\n");
		return ret;
	}
	return 0;
}

static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
{
	struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
	u32 value;

	if (!mtk->has_ippc)
		return 0;

	/* reset whole ip */
	value = readl(&ippc->ip_pw_ctr0);
	value |= CTRL0_IP_SW_RST;
	writel(value, &ippc->ip_pw_ctr0);
	udelay(1);
	value = readl(&ippc->ip_pw_ctr0);
	value &= ~CTRL0_IP_SW_RST;
	writel(value, &ippc->ip_pw_ctr0);

	/*
	 * device ip is default power-on in fact
	 * power down device ip, otherwise ip-sleep will fail
	 */
	value = readl(&ippc->ip_pw_ctr2);
	value |= CTRL2_IP_DEV_PDN;
	writel(value, &ippc->ip_pw_ctr2);

	value = readl(&ippc->ip_xhci_cap);
	mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
	mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
	dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
			mtk->num_u2_ports, mtk->num_u3_ports);

	return xhci_mtk_host_enable(mtk);
}

/* ignore the error if the clock does not exist */
static struct clk *optional_clk_get(struct device *dev, const char *id)
{
	struct clk *opt_clk;

	opt_clk = devm_clk_get(dev, id);
	/* ignore error number except EPROBE_DEFER */
	if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
		opt_clk = NULL;

	return opt_clk;
}

static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
{
	struct device *dev = mtk->dev;

	mtk->sys_clk = devm_clk_get(dev, "sys_ck");
	if (IS_ERR(mtk->sys_clk)) {
		dev_err(dev, "fail to get sys_ck\n");
		return PTR_ERR(mtk->sys_clk);
	}

	mtk->ref_clk = optional_clk_get(dev, "ref_ck");
	if (IS_ERR(mtk->ref_clk))
		return PTR_ERR(mtk->ref_clk);

	mtk->mcu_clk = optional_clk_get(dev, "mcu_ck");
	if (IS_ERR(mtk->mcu_clk))
		return PTR_ERR(mtk->mcu_clk);

	mtk->dma_clk = optional_clk_get(dev, "dma_ck");
	return PTR_ERR_OR_ZERO(mtk->dma_clk);
}

static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
{
	int ret;

	ret = clk_prepare_enable(mtk->ref_clk);
	if (ret) {
		dev_err(mtk->dev, "failed to enable ref_clk\n");
		goto ref_clk_err;
	}

	ret = clk_prepare_enable(mtk->sys_clk);
	if (ret) {
		dev_err(mtk->dev, "failed to enable sys_clk\n");
		goto sys_clk_err;
	}

	ret = clk_prepare_enable(mtk->mcu_clk);
	if (ret) {
		dev_err(mtk->dev, "failed to enable mcu_clk\n");
		goto mcu_clk_err;
	}

	ret = clk_prepare_enable(mtk->dma_clk);
	if (ret) {
		dev_err(mtk->dev, "failed to enable dma_clk\n");
		goto dma_clk_err;
	}

	return 0;

dma_clk_err:
	clk_disable_unprepare(mtk->mcu_clk);
mcu_clk_err:
	clk_disable_unprepare(mtk->sys_clk);
sys_clk_err:
	clk_disable_unprepare(mtk->ref_clk);
ref_clk_err:
	return ret;
}

static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
{
	clk_disable_unprepare(mtk->dma_clk);
	clk_disable_unprepare(mtk->mcu_clk);
	clk_disable_unprepare(mtk->sys_clk);
	clk_disable_unprepare(mtk->ref_clk);
}

/* only clocks can be turn off for ip-sleep wakeup mode */
static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
{
	u32 reg, msk, val;

	switch (mtk->uwk_vers) {
	case SSUSB_UWK_V1:
		reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
		msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
		val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
		break;
	case SSUSB_UWK_V2:
		reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
		msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
		val = enable ? msk : 0;
		break;
	default:
		return;
	}
	regmap_update_bits(mtk->uwk, reg, msk, val);
}

static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
				struct device_node *dn)
{
	struct of_phandle_args args;
	int ret;

	/* Wakeup function is optional */
	mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
	if (!mtk->uwk_en)
		return 0;

	ret = of_parse_phandle_with_fixed_args(dn,
				"mediatek,syscon-wakeup", 2, 0, &args);
	if (ret)
		return ret;

	mtk->uwk_reg_base = args.args[0];
	mtk->uwk_vers = args.args[1];
	mtk->uwk = syscon_node_to_regmap(args.np);
	of_node_put(args.np);
	dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
			mtk->uwk_reg_base, mtk->uwk_vers);

	return PTR_ERR_OR_ZERO(mtk->uwk);

}

static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
{
	if (mtk->uwk_en)
		usb_wakeup_ip_sleep_set(mtk, enable);
}

static int xhci_mtk_setup(struct usb_hcd *hcd);
static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
	.reset = xhci_mtk_setup,
};

static struct hc_driver __read_mostly xhci_mtk_hc_driver;

static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
{
	int ret;

	ret = regulator_enable(mtk->vbus);
	if (ret) {
		dev_err(mtk->dev, "failed to enable vbus\n");
		return ret;
	}

	ret = regulator_enable(mtk->vusb33);
	if (ret) {
		dev_err(mtk->dev, "failed to enable vusb33\n");
		regulator_disable(mtk->vbus);
		return ret;
	}
	return 0;
}

static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
{
	regulator_disable(mtk->vbus);
	regulator_disable(mtk->vusb33);
}

static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
{
	struct usb_hcd *hcd = xhci_to_hcd(xhci);
	struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);

	/*
	 * As of now platform drivers don't provide MSI support so we ensure
	 * here that the generic code does not try to make a pci_dev from our
	 * dev struct in order to setup MSI
	 */
	xhci->quirks |= XHCI_PLAT;
	xhci->quirks |= XHCI_MTK_HOST;
	/*
	 * MTK host controller gives a spurious successful event after a
	 * short transfer. Ignore it.
	 */
	xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
	if (mtk->lpm_support)
		xhci->quirks |= XHCI_LPM_SUPPORT;
}

/* called during probe() after chip reset completes */
static int xhci_mtk_setup(struct usb_hcd *hcd)
{
	struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
	int ret;

	if (usb_hcd_is_primary_hcd(hcd)) {
		ret = xhci_mtk_ssusb_config(mtk);
		if (ret)
			return ret;
	}

	ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
	if (ret)
		return ret;

	if (usb_hcd_is_primary_hcd(hcd)) {
		ret = xhci_mtk_sch_init(mtk);
		if (ret)
			return ret;
	}

	return ret;
}

static int xhci_mtk_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *node = dev->of_node;
	struct xhci_hcd_mtk *mtk;
	const struct hc_driver *driver;
	struct xhci_hcd *xhci;
	struct resource *res;
	struct usb_hcd *hcd;
	int ret = -ENODEV;
	int irq;

	if (usb_disabled())
		return -ENODEV;

	driver = &xhci_mtk_hc_driver;
	mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
	if (!mtk)
		return -ENOMEM;

	mtk->dev = dev;
	mtk->vbus = devm_regulator_get(dev, "vbus");
	if (IS_ERR(mtk->vbus)) {
		dev_err(dev, "fail to get vbus\n");
		return PTR_ERR(mtk->vbus);
	}

	mtk->vusb33 = devm_regulator_get(dev, "vusb33");
	if (IS_ERR(mtk->vusb33)) {
		dev_err(dev, "fail to get vusb33\n");
		return PTR_ERR(mtk->vusb33);
	}

	ret = xhci_mtk_clks_get(mtk);
	if (ret)
		return ret;

	mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
	/* optional property, ignore the error if it does not exist */
	of_property_read_u32(node, "mediatek,u3p-dis-msk",
			     &mtk->u3p_dis_msk);

	ret = usb_wakeup_of_property_parse(mtk, node);
	if (ret) {
		dev_err(dev, "failed to parse uwk property\n");
		return ret;
	}

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);
	device_enable_async_suspend(dev);

	ret = xhci_mtk_ldos_enable(mtk);
	if (ret)
		goto disable_pm;

	ret = xhci_mtk_clks_enable(mtk);
	if (ret)
		goto disable_ldos;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		ret = irq;
		goto disable_clk;
	}

	/* Initialize dma_mask and coherent_dma_mask to 32-bits */
	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
	if (ret)
		goto disable_clk;

	hcd = usb_create_hcd(driver, dev, dev_name(dev));
	if (!hcd) {
		ret = -ENOMEM;
		goto disable_clk;
	}

	/*
	 * USB 2.0 roothub is stored in the platform_device.
	 * Swap it with mtk HCD.
	 */
	mtk->hcd = platform_get_drvdata(pdev);
	platform_set_drvdata(pdev, mtk);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
	hcd->regs = devm_ioremap_resource(dev, res);
	if (IS_ERR(hcd->regs)) {
		ret = PTR_ERR(hcd->regs);
		goto put_usb2_hcd;
	}
	hcd->rsrc_start = res->start;
	hcd->rsrc_len = resource_size(res);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
	if (res) {	/* ippc register is optional */
		mtk->ippc_regs = devm_ioremap_resource(dev, res);
		if (IS_ERR(mtk->ippc_regs)) {
			ret = PTR_ERR(mtk->ippc_regs);
			goto put_usb2_hcd;
		}
		mtk->has_ippc = true;
	} else {
		mtk->has_ippc = false;
	}

	device_init_wakeup(dev, true);

	xhci = hcd_to_xhci(hcd);
	xhci->main_hcd = hcd;

	/*
	 * imod_interval is the interrupt moderation value in nanoseconds.
	 * The increment interval is 8 times as much as that defined in
	 * the xHCI spec on MTK's controller.
	 */
	xhci->imod_interval = 5000;
	device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);

	xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
			dev_name(dev), hcd);
	if (!xhci->shared_hcd) {
		ret = -ENOMEM;
		goto disable_device_wakeup;
	}

	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
	if (ret)
		goto put_usb3_hcd;

	if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
		xhci->shared_hcd->can_do_streams = 1;

	ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
	if (ret)
		goto dealloc_usb2_hcd;

	return 0;

dealloc_usb2_hcd:
	usb_remove_hcd(hcd);

put_usb3_hcd:
	xhci_mtk_sch_exit(mtk);
	usb_put_hcd(xhci->shared_hcd);

disable_device_wakeup:
	device_init_wakeup(dev, false);

put_usb2_hcd:
	usb_put_hcd(hcd);

disable_clk:
	xhci_mtk_clks_disable(mtk);

disable_ldos:
	xhci_mtk_ldos_disable(mtk);

disable_pm:
	pm_runtime_put_sync(dev);
	pm_runtime_disable(dev);
	return ret;
}

static int xhci_mtk_remove(struct platform_device *dev)
{
	struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
	struct usb_hcd	*hcd = mtk->hcd;
	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);

	usb_remove_hcd(xhci->shared_hcd);
	device_init_wakeup(&dev->dev, false);

	usb_remove_hcd(hcd);
	usb_put_hcd(xhci->shared_hcd);
	usb_put_hcd(hcd);
	xhci_mtk_sch_exit(mtk);
	xhci_mtk_clks_disable(mtk);
	xhci_mtk_ldos_disable(mtk);
	pm_runtime_put_sync(&dev->dev);
	pm_runtime_disable(&dev->dev);

	return 0;
}

/*
 * if ip sleep fails, and all clocks are disabled, access register will hang
 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend.
 * and no need to check whether ip sleep failed or not; this will cause SPM
 * to wake up system immediately after system suspend complete if ip sleep
 * fails, it is what we wanted.
 */
static int __maybe_unused xhci_mtk_suspend(struct device *dev)
{
	struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
	struct usb_hcd *hcd = mtk->hcd;
	struct xhci_hcd *xhci = hcd_to_xhci(hcd);

	xhci_dbg(xhci, "%s: stop port polling\n", __func__);
	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
	del_timer_sync(&hcd->rh_timer);
	clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
	del_timer_sync(&xhci->shared_hcd->rh_timer);

	xhci_mtk_host_disable(mtk);
	xhci_mtk_clks_disable(mtk);
	usb_wakeup_set(mtk, true);
	return 0;
}

static int __maybe_unused xhci_mtk_resume(struct device *dev)
{
	struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
	struct usb_hcd *hcd = mtk->hcd;
	struct xhci_hcd *xhci = hcd_to_xhci(hcd);

	usb_wakeup_set(mtk, false);
	xhci_mtk_clks_enable(mtk);
	xhci_mtk_host_enable(mtk);

	xhci_dbg(xhci, "%s: restart port polling\n", __func__);
	set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
	usb_hcd_poll_rh_status(xhci->shared_hcd);
	set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
	usb_hcd_poll_rh_status(hcd);
	return 0;
}

static const struct dev_pm_ops xhci_mtk_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
};
#define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL

#ifdef CONFIG_OF
static const struct of_device_id mtk_xhci_of_match[] = {
	{ .compatible = "mediatek,mt8173-xhci"},
	{ .compatible = "mediatek,mtk-xhci"},
	{ },
};
MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
#endif

static struct platform_driver mtk_xhci_driver = {
	.probe	= xhci_mtk_probe,
	.remove	= xhci_mtk_remove,
	.driver	= {
		.name = "xhci-mtk",
		.pm = DEV_PM_OPS,
		.of_match_table = of_match_ptr(mtk_xhci_of_match),
	},
};
MODULE_ALIAS("platform:xhci-mtk");

static int __init xhci_mtk_init(void)
{
	xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
	return platform_driver_register(&mtk_xhci_driver);
}
module_init(xhci_mtk_init);

static void __exit xhci_mtk_exit(void)
{
	platform_driver_unregister(&mtk_xhci_driver);
}
module_exit(xhci_mtk_exit);

MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
0cbd4b34 CY	2	/*
	3	* MediaTek xHCI Host Controller Driver
	4	*
	5	* Copyright (c) 2015 MediaTek Inc.
	6	* Author:
	7	* Chunfeng Yun <chunfeng.yun@mediatek.com>
0cbd4b34 CY	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/dma-mapping.h>
	12	#include <linux/iopoll.h>
	13	#include <linux/kernel.h>
	14	#include <linux/mfd/syscon.h>
	15	#include <linux/module.h>
	16	#include <linux/of.h>
0cbd4b34 CY	17	#include <linux/platform_device.h>
	18	#include <linux/pm_runtime.h>
	19	#include <linux/regmap.h>
	20	#include <linux/regulator/consumer.h>
	21
	22	#include "xhci.h"
	23	#include "xhci-mtk.h"
	24
	25	/* ip_pw_ctrl0 register */
	26	#define CTRL0_IP_SW_RST BIT(0)
	27
	28	/* ip_pw_ctrl1 register */
	29	#define CTRL1_IP_HOST_PDN BIT(0)
	30
	31	/* ip_pw_ctrl2 register */
	32	#define CTRL2_IP_DEV_PDN BIT(0)
	33
	34	/* ip_pw_sts1 register */
	35	#define STS1_IP_SLEEP_STS BIT(30)
ce370bfd	36	#define STS1_U3_MAC_RST BIT(16)
0cbd4b34 CY	37	#define STS1_XHCI_RST BIT(11)
	38	#define STS1_SYS125_RST BIT(10)
	39	#define STS1_REF_RST BIT(8)
	40	#define STS1_SYSPLL_STABLE BIT(0)
	41
	42	/* ip_xhci_cap register */
	43	#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
	44	#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
	45
	46	/* u3_ctrl_p register */
	47	#define CTRL_U3_PORT_HOST_SEL BIT(2)
	48	#define CTRL_U3_PORT_PDN BIT(1)
	49	#define CTRL_U3_PORT_DIS BIT(0)
	50
	51	/* u2_ctrl_p register */
	52	#define CTRL_U2_PORT_HOST_SEL BIT(2)
	53	#define CTRL_U2_PORT_PDN BIT(1)
	54	#define CTRL_U2_PORT_DIS BIT(0)
	55
	56	/* u2_phy_pll register */
	57	#define CTRL_U2_FORCE_PLL_STB BIT(28)
	58
a2ecc4df CY	59	/* usb remote wakeup registers in syscon */
	60	/* mt8173 etc */
	61	#define PERI_WK_CTRL1 0x4
	62	#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
	63	#define WC1_IS_EN BIT(25)
	64	#define WC1_IS_P BIT(6) /* polarity for ip sleep */
	65
	66	/* mt2712 etc */
	67	#define PERI_SSUSB_SPM_CTRL 0x0
	68	#define SSC_IP_SLEEP_EN BIT(4)
	69	#define SSC_SPM_INT_EN BIT(1)
	70
	71	enum ssusb_uwk_vers {
	72	SSUSB_UWK_V1 = 1,
	73	SSUSB_UWK_V2,
0cbd4b34 CY	74	};
	75
	76	static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
	77	{
	78	struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
	79	u32 value, check_val;
55ba6e9e	80	int u3_ports_disabed = 0;
0cbd4b34 CY	81	int ret;
	82	int i;
	83
065d48cf CY	84	if (!mtk->has_ippc)
	85	return 0;
	86
0cbd4b34 CY	87	/* power on host ip */
	88	value = readl(&ippc->ip_pw_ctr1);
	89	value &= ~CTRL1_IP_HOST_PDN;
	90	writel(value, &ippc->ip_pw_ctr1);
	91
55ba6e9e	92	/* power on and enable u3 ports except skipped ones */
0cbd4b34	93	for (i = 0; i < mtk->num_u3_ports; i++) {
55ba6e9e CY	94	if ((0x1 << i) & mtk->u3p_dis_msk) {
	95	u3_ports_disabed++;
	96	continue;
	97	}
	98
0cbd4b34 CY	99	value = readl(&ippc->u3_ctrl_p[i]);
	100	value &= ~(CTRL_U3_PORT_PDN \| CTRL_U3_PORT_DIS);
	101	value \|= CTRL_U3_PORT_HOST_SEL;
	102	writel(value, &ippc->u3_ctrl_p[i]);
	103	}
	104
	105	/* power on and enable all u2 ports */
	106	for (i = 0; i < mtk->num_u2_ports; i++) {
	107	value = readl(&ippc->u2_ctrl_p[i]);
	108	value &= ~(CTRL_U2_PORT_PDN \| CTRL_U2_PORT_DIS);
	109	value \|= CTRL_U2_PORT_HOST_SEL;
	110	writel(value, &ippc->u2_ctrl_p[i]);
	111	}
	112
	113	/*
	114	* wait for clocks to be stable, and clock domains reset to
	115	* be inactive after power on and enable ports
	116	*/
	117	check_val = STS1_SYSPLL_STABLE \| STS1_REF_RST \|
	118	STS1_SYS125_RST \| STS1_XHCI_RST;
	119
55ba6e9e	120	if (mtk->num_u3_ports > u3_ports_disabed)
ce370bfd CY	121	check_val \|= STS1_U3_MAC_RST;
ce370bfd CY	122
0cbd4b34 CY	123	ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
	124	(check_val == (value & check_val)), 100, 20000);
	125	if (ret) {
	126	dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
	127	return ret;
	128	}
	129
	130	return 0;
	131	}
	132
	133	static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
	134	{
	135	struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
	136	u32 value;
	137	int ret;
	138	int i;
	139
065d48cf CY	140	if (!mtk->has_ippc)
	141	return 0;
	142
55ba6e9e	143	/* power down u3 ports except skipped ones */
0cbd4b34	144	for (i = 0; i < mtk->num_u3_ports; i++) {
55ba6e9e CY	145	if ((0x1 << i) & mtk->u3p_dis_msk)
	146	continue;
	147
0cbd4b34 CY	148	value = readl(&ippc->u3_ctrl_p[i]);
	149	value \|= CTRL_U3_PORT_PDN;
	150	writel(value, &ippc->u3_ctrl_p[i]);
	151	}
	152
	153	/* power down all u2 ports */
	154	for (i = 0; i < mtk->num_u2_ports; i++) {
	155	value = readl(&ippc->u2_ctrl_p[i]);
	156	value \|= CTRL_U2_PORT_PDN;
	157	writel(value, &ippc->u2_ctrl_p[i]);
	158	}
	159
	160	/* power down host ip */
	161	value = readl(&ippc->ip_pw_ctr1);
	162	value \|= CTRL1_IP_HOST_PDN;
	163	writel(value, &ippc->ip_pw_ctr1);
	164
	165	/* wait for host ip to sleep */
	166	ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
	167	(value & STS1_IP_SLEEP_STS), 100, 100000);
	168	if (ret) {
	169	dev_err(mtk->dev, "ip sleep failed!!!\n");
	170	return ret;
	171	}
	172	return 0;
	173	}
	174
	175	static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
	176	{
	177	struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
	178	u32 value;
	179
065d48cf CY	180	if (!mtk->has_ippc)
	181	return 0;
	182
0cbd4b34 CY	183	/* reset whole ip */
	184	value = readl(&ippc->ip_pw_ctr0);
	185	value \|= CTRL0_IP_SW_RST;
	186	writel(value, &ippc->ip_pw_ctr0);
	187	udelay(1);
	188	value = readl(&ippc->ip_pw_ctr0);
	189	value &= ~CTRL0_IP_SW_RST;
	190	writel(value, &ippc->ip_pw_ctr0);
	191
	192	/*
	193	* device ip is default power-on in fact
	194	* power down device ip, otherwise ip-sleep will fail
	195	*/
	196	value = readl(&ippc->ip_pw_ctr2);
	197	value \|= CTRL2_IP_DEV_PDN;
	198	writel(value, &ippc->ip_pw_ctr2);
	199
	200	value = readl(&ippc->ip_xhci_cap);
	201	mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
	202	mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
	203	dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
	204	mtk->num_u2_ports, mtk->num_u3_ports);
	205
	206	return xhci_mtk_host_enable(mtk);
	207	}
	208
b6bb72cf CY	209	/* ignore the error if the clock does not exist */
	210	static struct clk optional_clk_get(struct device dev, const char *id)
	211	{
	212	struct clk *opt_clk;
	213
	214	opt_clk = devm_clk_get(dev, id);
	215	/* ignore error number except EPROBE_DEFER */
	216	if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
	217	opt_clk = NULL;
	218
	219	return opt_clk;
	220	}
	221
	222	static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
	223	{
	224	struct device *dev = mtk->dev;
	225
	226	mtk->sys_clk = devm_clk_get(dev, "sys_ck");
	227	if (IS_ERR(mtk->sys_clk)) {
	228	dev_err(dev, "fail to get sys_ck\n");
	229	return PTR_ERR(mtk->sys_clk);
	230	}
	231
	232	mtk->ref_clk = optional_clk_get(dev, "ref_ck");
	233	if (IS_ERR(mtk->ref_clk))
	234	return PTR_ERR(mtk->ref_clk);
	235
	236	mtk->mcu_clk = optional_clk_get(dev, "mcu_ck");
	237	if (IS_ERR(mtk->mcu_clk))
	238	return PTR_ERR(mtk->mcu_clk);
	239
	240	mtk->dma_clk = optional_clk_get(dev, "dma_ck");
c929d847	241	return PTR_ERR_OR_ZERO(mtk->dma_clk);
b6bb72cf CY	242	}
b6bb72cf CY	243
0cbd4b34 CY	244	static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
	245	{
	246	int ret;
	247
9c4afd42 CY	248	ret = clk_prepare_enable(mtk->ref_clk);
	249	if (ret) {
	250	dev_err(mtk->dev, "failed to enable ref_clk\n");
	251	goto ref_clk_err;
	252	}
	253
0cbd4b34 CY	254	ret = clk_prepare_enable(mtk->sys_clk);
	255	if (ret) {
	256	dev_err(mtk->dev, "failed to enable sys_clk\n");
	257	goto sys_clk_err;
	258	}
	259
b6bb72cf CY	260	ret = clk_prepare_enable(mtk->mcu_clk);
	261	if (ret) {
	262	dev_err(mtk->dev, "failed to enable mcu_clk\n");
	263	goto mcu_clk_err;
	264	}
	265
	266	ret = clk_prepare_enable(mtk->dma_clk);
	267	if (ret) {
	268	dev_err(mtk->dev, "failed to enable dma_clk\n");
	269	goto dma_clk_err;
	270	}
	271
0cbd4b34 CY	272	return 0;
0cbd4b34 CY	273
b6bb72cf CY	274	dma_clk_err:
	275	clk_disable_unprepare(mtk->mcu_clk);
	276	mcu_clk_err:
	277	clk_disable_unprepare(mtk->sys_clk);
0cbd4b34	278	sys_clk_err:
9c4afd42 CY	279	clk_disable_unprepare(mtk->ref_clk);
9c4afd42 CY	280	ref_clk_err:
b6bb72cf	281	return ret;
0cbd4b34 CY	282	}
	283
	284	static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
	285	{
b6bb72cf CY	286	clk_disable_unprepare(mtk->dma_clk);
b6bb72cf CY	287	clk_disable_unprepare(mtk->mcu_clk);
0cbd4b34	288	clk_disable_unprepare(mtk->sys_clk);
9c4afd42	289	clk_disable_unprepare(mtk->ref_clk);
0cbd4b34 CY	290	}
	291
	292	/* only clocks can be turn off for ip-sleep wakeup mode */
a2ecc4df	293	static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
0cbd4b34	294	{
a2ecc4df CY	295	u32 reg, msk, val;
	296
	297	switch (mtk->uwk_vers) {
	298	case SSUSB_UWK_V1:
	299	reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
	300	msk = WC1_IS_EN \| WC1_IS_C(0xf) \| WC1_IS_P;
	301	val = enable ? (WC1_IS_EN \| WC1_IS_C(0x8)) : 0;
	302	break;
	303	case SSUSB_UWK_V2:
	304	reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
	305	msk = SSC_IP_SLEEP_EN \| SSC_SPM_INT_EN;
	306	val = enable ? msk : 0;
	307	break;
	308	default:
	309	return;
dae06208	310	}
a2ecc4df	311	regmap_update_bits(mtk->uwk, reg, msk, val);
0cbd4b34 CY	312	}
0cbd4b34 CY	313
a2ecc4df CY	314	static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
a2ecc4df CY	315	struct device_node *dn)
0cbd4b34	316	{
a2ecc4df CY	317	struct of_phandle_args args;
a2ecc4df CY	318	int ret;
0cbd4b34	319
a2ecc4df CY	320	/* Wakeup function is optional */
	321	mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
	322	if (!mtk->uwk_en)
	323	return 0;
0cbd4b34	324
a2ecc4df CY	325	ret = of_parse_phandle_with_fixed_args(dn,
	326	"mediatek,syscon-wakeup", 2, 0, &args);
	327	if (ret)
	328	return ret;
0cbd4b34	329
a2ecc4df CY	330	mtk->uwk_reg_base = args.args[0];
	331	mtk->uwk_vers = args.args[1];
	332	mtk->uwk = syscon_node_to_regmap(args.np);
	333	of_node_put(args.np);
	334	dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
	335	mtk->uwk_reg_base, mtk->uwk_vers);
0cbd4b34	336
a2ecc4df	337	return PTR_ERR_OR_ZERO(mtk->uwk);
0cbd4b34	338
0cbd4b34 CY	339	}
0cbd4b34 CY	340
a2ecc4df	341	static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
0cbd4b34	342	{
a2ecc4df CY	343	if (mtk->uwk_en)
a2ecc4df CY	344	usb_wakeup_ip_sleep_set(mtk, enable);
0cbd4b34 CY	345	}
	346
	347	static int xhci_mtk_setup(struct usb_hcd *hcd);
	348	static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
0cbd4b34 CY	349	.reset = xhci_mtk_setup,
	350	};
	351
	352	static struct hc_driver __read_mostly xhci_mtk_hc_driver;
	353
0cbd4b34 CY	354	static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
	355	{
	356	int ret;
	357
	358	ret = regulator_enable(mtk->vbus);
	359	if (ret) {
	360	dev_err(mtk->dev, "failed to enable vbus\n");
	361	return ret;
	362	}
	363
	364	ret = regulator_enable(mtk->vusb33);
	365	if (ret) {
	366	dev_err(mtk->dev, "failed to enable vusb33\n");
	367	regulator_disable(mtk->vbus);
	368	return ret;
	369	}
	370	return 0;
	371	}
	372
	373	static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
	374	{
	375	regulator_disable(mtk->vbus);
	376	regulator_disable(mtk->vusb33);
	377	}
	378
	379	static void xhci_mtk_quirks(struct device dev, struct xhci_hcd xhci)
	380	{
	381	struct usb_hcd *hcd = xhci_to_hcd(xhci);
	382	struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
	383
	384	/*
	385	* As of now platform drivers don't provide MSI support so we ensure
	386	* here that the generic code does not try to make a pci_dev from our
	387	* dev struct in order to setup MSI
	388	*/
	389	xhci->quirks \|= XHCI_PLAT;
	390	xhci->quirks \|= XHCI_MTK_HOST;
	391	/*
	392	* MTK host controller gives a spurious successful event after a
	393	* short transfer. Ignore it.
	394	*/
	395	xhci->quirks \|= XHCI_SPURIOUS_SUCCESS;
	396	if (mtk->lpm_support)
	397	xhci->quirks \|= XHCI_LPM_SUPPORT;
	398	}
	399
	400	/* called during probe() after chip reset completes */
	401	static int xhci_mtk_setup(struct usb_hcd *hcd)
	402	{
	403	struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
	404	int ret;
	405
	406	if (usb_hcd_is_primary_hcd(hcd)) {
	407	ret = xhci_mtk_ssusb_config(mtk);
	408	if (ret)
	409	return ret;
065d48cf CY	410	}
	411
	412	ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
	413	if (ret)
	414	return ret;
	415
	416	if (usb_hcd_is_primary_hcd(hcd)) {
0cbd4b34 CY	417	ret = xhci_mtk_sch_init(mtk);
	418	if (ret)
	419	return ret;
	420	}
	421
065d48cf	422	return ret;
0cbd4b34 CY	423	}
	424
	425	static int xhci_mtk_probe(struct platform_device *pdev)
	426	{
	427	struct device *dev = &pdev->dev;
	428	struct device_node *node = dev->of_node;
	429	struct xhci_hcd_mtk *mtk;
	430	const struct hc_driver *driver;
	431	struct xhci_hcd *xhci;
	432	struct resource *res;
	433	struct usb_hcd *hcd;
0cbd4b34 CY	434	int ret = -ENODEV;
	435	int irq;
	436
	437	if (usb_disabled())
	438	return -ENODEV;
	439
	440	driver = &xhci_mtk_hc_driver;
	441	mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
	442	if (!mtk)
	443	return -ENOMEM;
	444
	445	mtk->dev = dev;
	446	mtk->vbus = devm_regulator_get(dev, "vbus");
	447	if (IS_ERR(mtk->vbus)) {
	448	dev_err(dev, "fail to get vbus\n");
	449	return PTR_ERR(mtk->vbus);
	450	}
	451
	452	mtk->vusb33 = devm_regulator_get(dev, "vusb33");
	453	if (IS_ERR(mtk->vusb33)) {
	454	dev_err(dev, "fail to get vusb33\n");
	455	return PTR_ERR(mtk->vusb33);
	456	}
	457
b6bb72cf CY	458	ret = xhci_mtk_clks_get(mtk);
	459	if (ret)
	460	return ret;
9c4afd42	461
0cbd4b34	462	mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
55ba6e9e CY	463	/* optional property, ignore the error if it does not exist */
	464	of_property_read_u32(node, "mediatek,u3p-dis-msk",
	465	&mtk->u3p_dis_msk);
0cbd4b34 CY	466
0cbd4b34 CY	467	ret = usb_wakeup_of_property_parse(mtk, node);
a2ecc4df CY	468	if (ret) {
a2ecc4df CY	469	dev_err(dev, "failed to parse uwk property\n");
0cbd4b34	470	return ret;
a2ecc4df	471	}
0cbd4b34	472
0cbd4b34 CY	473	pm_runtime_enable(dev);
	474	pm_runtime_get_sync(dev);
	475	device_enable_async_suspend(dev);
	476
	477	ret = xhci_mtk_ldos_enable(mtk);
	478	if (ret)
	479	goto disable_pm;
	480
	481	ret = xhci_mtk_clks_enable(mtk);
	482	if (ret)
	483	goto disable_ldos;
	484
	485	irq = platform_get_irq(pdev, 0);
28bedb5a PB	486	if (irq < 0) {
28bedb5a PB	487	ret = irq;
0cbd4b34	488	goto disable_clk;
28bedb5a	489	}
0cbd4b34 CY	490
0cbd4b34 CY	491	/* Initialize dma_mask and coherent_dma_mask to 32-bits */
da087419	492	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
0cbd4b34 CY	493	if (ret)
	494	goto disable_clk;
	495
0cbd4b34 CY	496	hcd = usb_create_hcd(driver, dev, dev_name(dev));
	497	if (!hcd) {
	498	ret = -ENOMEM;
	499	goto disable_clk;
	500	}
	501
	502	/*
	503	* USB 2.0 roothub is stored in the platform_device.
	504	* Swap it with mtk HCD.
	505	*/
	506	mtk->hcd = platform_get_drvdata(pdev);
	507	platform_set_drvdata(pdev, mtk);
	508
065d48cf	509	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
0cbd4b34 CY	510	hcd->regs = devm_ioremap_resource(dev, res);
	511	if (IS_ERR(hcd->regs)) {
	512	ret = PTR_ERR(hcd->regs);
	513	goto put_usb2_hcd;
	514	}
	515	hcd->rsrc_start = res->start;
	516	hcd->rsrc_len = resource_size(res);
	517
065d48cf CY	518	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
	519	if (res) { /* ippc register is optional */
	520	mtk->ippc_regs = devm_ioremap_resource(dev, res);
	521	if (IS_ERR(mtk->ippc_regs)) {
	522	ret = PTR_ERR(mtk->ippc_regs);
	523	goto put_usb2_hcd;
	524	}
	525	mtk->has_ippc = true;
	526	} else {
	527	mtk->has_ippc = false;
0cbd4b34 CY	528	}
0cbd4b34 CY	529
0cbd4b34 CY	530	device_init_wakeup(dev, true);
	531
	532	xhci = hcd_to_xhci(hcd);
	533	xhci->main_hcd = hcd;
ab725cbe AW	534
	535	/*
	536	* imod_interval is the interrupt moderation value in nanoseconds.
	537	* The increment interval is 8 times as much as that defined in
	538	* the xHCI spec on MTK's controller.
	539	*/
	540	xhci->imod_interval = 5000;
	541	device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
	542
0cbd4b34 CY	543	xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
	544	dev_name(dev), hcd);
	545	if (!xhci->shared_hcd) {
	546	ret = -ENOMEM;
6ae9f506	547	goto disable_device_wakeup;
0cbd4b34 CY	548	}
0cbd4b34 CY	549
0cbd4b34 CY	550	ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
	551	if (ret)
	552	goto put_usb3_hcd;
	553
94a631d9 CY	554	if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
	555	xhci->shared_hcd->can_do_streams = 1;
	556
0cbd4b34 CY	557	ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
	558	if (ret)
	559	goto dealloc_usb2_hcd;
	560
	561	return 0;
	562
	563	dealloc_usb2_hcd:
	564	usb_remove_hcd(hcd);
	565
	566	put_usb3_hcd:
	567	xhci_mtk_sch_exit(mtk);
	568	usb_put_hcd(xhci->shared_hcd);
	569
6ae9f506	570	disable_device_wakeup:
0cbd4b34 CY	571	device_init_wakeup(dev, false);
0cbd4b34 CY	572
0cbd4b34 CY	573	put_usb2_hcd:
	574	usb_put_hcd(hcd);
	575
	576	disable_clk:
	577	xhci_mtk_clks_disable(mtk);
	578
	579	disable_ldos:
	580	xhci_mtk_ldos_disable(mtk);
	581
	582	disable_pm:
	583	pm_runtime_put_sync(dev);
	584	pm_runtime_disable(dev);
	585	return ret;
	586	}
	587
	588	static int xhci_mtk_remove(struct platform_device *dev)
	589	{
	590	struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
	591	struct usb_hcd *hcd = mtk->hcd;
	592	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
	593
	594	usb_remove_hcd(xhci->shared_hcd);
0cbd4b34 CY	595	device_init_wakeup(&dev->dev, false);
	596
	597	usb_remove_hcd(hcd);
	598	usb_put_hcd(xhci->shared_hcd);
	599	usb_put_hcd(hcd);
	600	xhci_mtk_sch_exit(mtk);
	601	xhci_mtk_clks_disable(mtk);
	602	xhci_mtk_ldos_disable(mtk);
	603	pm_runtime_put_sync(&dev->dev);
	604	pm_runtime_disable(&dev->dev);
	605
	606	return 0;
	607	}
	608
882fa27f CY	609	/*
	610	* if ip sleep fails, and all clocks are disabled, access register will hang
	611	* AHB bus, so stop polling roothubs to avoid regs access on bus suspend.
	612	* and no need to check whether ip sleep failed or not; this will cause SPM
	613	* to wake up system immediately after system suspend complete if ip sleep
	614	* fails, it is what we wanted.
	615	*/
8dac5300	616	static int __maybe_unused xhci_mtk_suspend(struct device *dev)
0cbd4b34 CY	617	{
0cbd4b34 CY	618	struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
882fa27f CY	619	struct usb_hcd *hcd = mtk->hcd;
	620	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
	621
	622	xhci_dbg(xhci, "%s: stop port polling\n", __func__);
	623	clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
	624	del_timer_sync(&hcd->rh_timer);
	625	clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
	626	del_timer_sync(&xhci->shared_hcd->rh_timer);
0cbd4b34 CY	627
0cbd4b34 CY	628	xhci_mtk_host_disable(mtk);
0cbd4b34	629	xhci_mtk_clks_disable(mtk);
a2ecc4df	630	usb_wakeup_set(mtk, true);
0cbd4b34 CY	631	return 0;
	632	}
	633
8dac5300	634	static int __maybe_unused xhci_mtk_resume(struct device *dev)
0cbd4b34 CY	635	{
0cbd4b34 CY	636	struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
882fa27f CY	637	struct usb_hcd *hcd = mtk->hcd;
882fa27f CY	638	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
0cbd4b34	639
a2ecc4df	640	usb_wakeup_set(mtk, false);
0cbd4b34	641	xhci_mtk_clks_enable(mtk);
0cbd4b34	642	xhci_mtk_host_enable(mtk);
882fa27f CY	643
882fa27f CY	644	xhci_dbg(xhci, "%s: restart port polling\n", __func__);
882fa27f CY	645	set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
882fa27f CY	646	usb_hcd_poll_rh_status(xhci->shared_hcd);
555df582 CY	647	set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
555df582 CY	648	usb_hcd_poll_rh_status(hcd);
0cbd4b34 CY	649	return 0;
	650	}
	651
	652	static const struct dev_pm_ops xhci_mtk_pm_ops = {
	653	SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
	654	};
8dac5300	655	#define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL
0cbd4b34 CY	656
	657	#ifdef CONFIG_OF
	658	static const struct of_device_id mtk_xhci_of_match[] = {
	659	{ .compatible = "mediatek,mt8173-xhci"},
5675b4d4	660	{ .compatible = "mediatek,mtk-xhci"},
0cbd4b34 CY	661	{ },
	662	};
	663	MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
	664	#endif
	665
	666	static struct platform_driver mtk_xhci_driver = {
	667	.probe = xhci_mtk_probe,
	668	.remove = xhci_mtk_remove,
	669	.driver = {
	670	.name = "xhci-mtk",
	671	.pm = DEV_PM_OPS,
	672	.of_match_table = of_match_ptr(mtk_xhci_of_match),
	673	},
	674	};
	675	MODULE_ALIAS("platform:xhci-mtk");
	676
	677	static int __init xhci_mtk_init(void)
	678	{
	679	xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
	680	return platform_driver_register(&mtk_xhci_driver);
	681	}
	682	module_init(xhci_mtk_init);
	683
	684	static void __exit xhci_mtk_exit(void)
	685	{
	686	platform_driver_unregister(&mtk_xhci_driver);
	687	}
	688	module_exit(xhci_mtk_exit);
	689
	690	MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
	691	MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
	692	MODULE_LICENSE("GPL v2");