Commit | Line | Data |
---|---|---|
66d4eadd SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/usb.h> | |
0ebbab37 | 24 | #include <linux/pci.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
527c6d7f | 26 | #include <linux/dmapool.h> |
66d4eadd SS |
27 | |
28 | #include "xhci.h" | |
29 | ||
0ebbab37 SS |
30 | /* |
31 | * Allocates a generic ring segment from the ring pool, sets the dma address, | |
32 | * initializes the segment to zero, and sets the private next pointer to NULL. | |
33 | * | |
34 | * Section 4.11.1.1: | |
35 | * "All components of all Command and Transfer TRBs shall be initialized to '0'" | |
36 | */ | |
186a7ef1 AX |
37 | static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, |
38 | unsigned int cycle_state, gfp_t flags) | |
0ebbab37 SS |
39 | { |
40 | struct xhci_segment *seg; | |
41 | dma_addr_t dma; | |
186a7ef1 | 42 | int i; |
0ebbab37 SS |
43 | |
44 | seg = kzalloc(sizeof *seg, flags); | |
45 | if (!seg) | |
326b4810 | 46 | return NULL; |
0ebbab37 SS |
47 | |
48 | seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma); | |
49 | if (!seg->trbs) { | |
50 | kfree(seg); | |
326b4810 | 51 | return NULL; |
0ebbab37 | 52 | } |
0ebbab37 SS |
53 | |
54 | memset(seg->trbs, 0, SEGMENT_SIZE); | |
186a7ef1 AX |
55 | /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */ |
56 | if (cycle_state == 0) { | |
57 | for (i = 0; i < TRBS_PER_SEGMENT; i++) | |
58 | seg->trbs[i].link.control |= TRB_CYCLE; | |
59 | } | |
0ebbab37 SS |
60 | seg->dma = dma; |
61 | seg->next = NULL; | |
62 | ||
63 | return seg; | |
64 | } | |
65 | ||
66 | static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg) | |
67 | { | |
0ebbab37 | 68 | if (seg->trbs) { |
0ebbab37 SS |
69 | dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma); |
70 | seg->trbs = NULL; | |
71 | } | |
0ebbab37 SS |
72 | kfree(seg); |
73 | } | |
74 | ||
70d43601 AX |
75 | static void xhci_free_segments_for_ring(struct xhci_hcd *xhci, |
76 | struct xhci_segment *first) | |
77 | { | |
78 | struct xhci_segment *seg; | |
79 | ||
80 | seg = first->next; | |
81 | while (seg != first) { | |
82 | struct xhci_segment *next = seg->next; | |
83 | xhci_segment_free(xhci, seg); | |
84 | seg = next; | |
85 | } | |
86 | xhci_segment_free(xhci, first); | |
87 | } | |
88 | ||
0ebbab37 SS |
89 | /* |
90 | * Make the prev segment point to the next segment. | |
91 | * | |
92 | * Change the last TRB in the prev segment to be a Link TRB which points to the | |
93 | * DMA address of the next segment. The caller needs to set any Link TRB | |
94 | * related flags, such as End TRB, Toggle Cycle, and no snoop. | |
95 | */ | |
96 | static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev, | |
3b72fca0 | 97 | struct xhci_segment *next, enum xhci_ring_type type) |
0ebbab37 SS |
98 | { |
99 | u32 val; | |
100 | ||
101 | if (!prev || !next) | |
102 | return; | |
103 | prev->next = next; | |
3b72fca0 | 104 | if (type != TYPE_EVENT) { |
f5960b69 ME |
105 | prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = |
106 | cpu_to_le64(next->dma); | |
0ebbab37 SS |
107 | |
108 | /* Set the last TRB in the segment to have a TRB type ID of Link TRB */ | |
28ccd296 | 109 | val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); |
0ebbab37 SS |
110 | val &= ~TRB_TYPE_BITMASK; |
111 | val |= TRB_TYPE(TRB_LINK); | |
b0567b3f | 112 | /* Always set the chain bit with 0.95 hardware */ |
7e393a83 AX |
113 | /* Set chain bit for isoc rings on AMD 0.96 host */ |
114 | if (xhci_link_trb_quirk(xhci) || | |
3b72fca0 AX |
115 | (type == TYPE_ISOC && |
116 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
b0567b3f | 117 | val |= TRB_CHAIN; |
28ccd296 | 118 | prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); |
0ebbab37 | 119 | } |
0ebbab37 SS |
120 | } |
121 | ||
8dfec614 AX |
122 | /* |
123 | * Link the ring to the new segments. | |
124 | * Set Toggle Cycle for the new ring if needed. | |
125 | */ | |
126 | static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
127 | struct xhci_segment *first, struct xhci_segment *last, | |
128 | unsigned int num_segs) | |
129 | { | |
130 | struct xhci_segment *next; | |
131 | ||
132 | if (!ring || !first || !last) | |
133 | return; | |
134 | ||
135 | next = ring->enq_seg->next; | |
136 | xhci_link_segments(xhci, ring->enq_seg, first, ring->type); | |
137 | xhci_link_segments(xhci, last, next, ring->type); | |
138 | ring->num_segs += num_segs; | |
139 | ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs; | |
140 | ||
141 | if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) { | |
142 | ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control | |
143 | &= ~cpu_to_le32(LINK_TOGGLE); | |
144 | last->trbs[TRBS_PER_SEGMENT-1].link.control | |
145 | |= cpu_to_le32(LINK_TOGGLE); | |
146 | ring->last_seg = last; | |
147 | } | |
148 | } | |
149 | ||
0ebbab37 | 150 | /* XXX: Do we need the hcd structure in all these functions? */ |
f94e0186 | 151 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring) |
0ebbab37 | 152 | { |
0e6c7f74 | 153 | if (!ring) |
0ebbab37 | 154 | return; |
70d43601 AX |
155 | |
156 | if (ring->first_seg) | |
157 | xhci_free_segments_for_ring(xhci, ring->first_seg); | |
158 | ||
0ebbab37 SS |
159 | kfree(ring); |
160 | } | |
161 | ||
186a7ef1 AX |
162 | static void xhci_initialize_ring_info(struct xhci_ring *ring, |
163 | unsigned int cycle_state) | |
74f9fe21 SS |
164 | { |
165 | /* The ring is empty, so the enqueue pointer == dequeue pointer */ | |
166 | ring->enqueue = ring->first_seg->trbs; | |
167 | ring->enq_seg = ring->first_seg; | |
168 | ring->dequeue = ring->enqueue; | |
169 | ring->deq_seg = ring->first_seg; | |
170 | /* The ring is initialized to 0. The producer must write 1 to the cycle | |
171 | * bit to handover ownership of the TRB, so PCS = 1. The consumer must | |
172 | * compare CCS to the cycle bit to check ownership, so CCS = 1. | |
186a7ef1 AX |
173 | * |
174 | * New rings are initialized with cycle state equal to 1; if we are | |
175 | * handling ring expansion, set the cycle state equal to the old ring. | |
74f9fe21 | 176 | */ |
186a7ef1 | 177 | ring->cycle_state = cycle_state; |
74f9fe21 SS |
178 | /* Not necessary for new rings, but needed for re-initialized rings */ |
179 | ring->enq_updates = 0; | |
180 | ring->deq_updates = 0; | |
b008df60 AX |
181 | |
182 | /* | |
183 | * Each segment has a link TRB, and leave an extra TRB for SW | |
184 | * accounting purpose | |
185 | */ | |
186 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; | |
74f9fe21 SS |
187 | } |
188 | ||
70d43601 AX |
189 | /* Allocate segments and link them for a ring */ |
190 | static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci, | |
191 | struct xhci_segment **first, struct xhci_segment **last, | |
186a7ef1 AX |
192 | unsigned int num_segs, unsigned int cycle_state, |
193 | enum xhci_ring_type type, gfp_t flags) | |
70d43601 AX |
194 | { |
195 | struct xhci_segment *prev; | |
196 | ||
186a7ef1 | 197 | prev = xhci_segment_alloc(xhci, cycle_state, flags); |
70d43601 AX |
198 | if (!prev) |
199 | return -ENOMEM; | |
200 | num_segs--; | |
201 | ||
202 | *first = prev; | |
203 | while (num_segs > 0) { | |
204 | struct xhci_segment *next; | |
205 | ||
186a7ef1 | 206 | next = xhci_segment_alloc(xhci, cycle_state, flags); |
70d43601 AX |
207 | if (!next) { |
208 | xhci_free_segments_for_ring(xhci, *first); | |
209 | return -ENOMEM; | |
210 | } | |
211 | xhci_link_segments(xhci, prev, next, type); | |
212 | ||
213 | prev = next; | |
214 | num_segs--; | |
215 | } | |
216 | xhci_link_segments(xhci, prev, *first, type); | |
217 | *last = prev; | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
0ebbab37 SS |
222 | /** |
223 | * Create a new ring with zero or more segments. | |
224 | * | |
225 | * Link each segment together into a ring. | |
226 | * Set the end flag and the cycle toggle bit on the last segment. | |
227 | * See section 4.9.1 and figures 15 and 16. | |
228 | */ | |
229 | static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, | |
186a7ef1 AX |
230 | unsigned int num_segs, unsigned int cycle_state, |
231 | enum xhci_ring_type type, gfp_t flags) | |
0ebbab37 SS |
232 | { |
233 | struct xhci_ring *ring; | |
70d43601 | 234 | int ret; |
0ebbab37 SS |
235 | |
236 | ring = kzalloc(sizeof *(ring), flags); | |
0ebbab37 | 237 | if (!ring) |
326b4810 | 238 | return NULL; |
0ebbab37 | 239 | |
3fe4fe08 | 240 | ring->num_segs = num_segs; |
d0e96f5a | 241 | INIT_LIST_HEAD(&ring->td_list); |
3b72fca0 | 242 | ring->type = type; |
0ebbab37 SS |
243 | if (num_segs == 0) |
244 | return ring; | |
245 | ||
70d43601 | 246 | ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg, |
186a7ef1 | 247 | &ring->last_seg, num_segs, cycle_state, type, flags); |
70d43601 | 248 | if (ret) |
0ebbab37 | 249 | goto fail; |
0ebbab37 | 250 | |
3b72fca0 AX |
251 | /* Only event ring does not use link TRB */ |
252 | if (type != TYPE_EVENT) { | |
0ebbab37 | 253 | /* See section 4.9.2.1 and 6.4.4.1 */ |
70d43601 | 254 | ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |= |
f5960b69 | 255 | cpu_to_le32(LINK_TOGGLE); |
0ebbab37 | 256 | } |
186a7ef1 | 257 | xhci_initialize_ring_info(ring, cycle_state); |
0ebbab37 SS |
258 | return ring; |
259 | ||
260 | fail: | |
261 | xhci_ring_free(xhci, ring); | |
326b4810 | 262 | return NULL; |
0ebbab37 SS |
263 | } |
264 | ||
412566bd SS |
265 | void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, |
266 | struct xhci_virt_device *virt_dev, | |
267 | unsigned int ep_index) | |
268 | { | |
269 | int rings_cached; | |
270 | ||
271 | rings_cached = virt_dev->num_rings_cached; | |
272 | if (rings_cached < XHCI_MAX_RINGS_CACHED) { | |
412566bd SS |
273 | virt_dev->ring_cache[rings_cached] = |
274 | virt_dev->eps[ep_index].ring; | |
30f89ca0 | 275 | virt_dev->num_rings_cached++; |
412566bd SS |
276 | xhci_dbg(xhci, "Cached old ring, " |
277 | "%d ring%s cached\n", | |
30f89ca0 SS |
278 | virt_dev->num_rings_cached, |
279 | (virt_dev->num_rings_cached > 1) ? "s" : ""); | |
412566bd SS |
280 | } else { |
281 | xhci_ring_free(xhci, virt_dev->eps[ep_index].ring); | |
282 | xhci_dbg(xhci, "Ring cache full (%d rings), " | |
283 | "freeing ring\n", | |
284 | virt_dev->num_rings_cached); | |
285 | } | |
286 | virt_dev->eps[ep_index].ring = NULL; | |
287 | } | |
288 | ||
74f9fe21 SS |
289 | /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue |
290 | * pointers to the beginning of the ring. | |
291 | */ | |
292 | static void xhci_reinit_cached_ring(struct xhci_hcd *xhci, | |
186a7ef1 AX |
293 | struct xhci_ring *ring, unsigned int cycle_state, |
294 | enum xhci_ring_type type) | |
74f9fe21 SS |
295 | { |
296 | struct xhci_segment *seg = ring->first_seg; | |
186a7ef1 AX |
297 | int i; |
298 | ||
74f9fe21 SS |
299 | do { |
300 | memset(seg->trbs, 0, | |
301 | sizeof(union xhci_trb)*TRBS_PER_SEGMENT); | |
186a7ef1 AX |
302 | if (cycle_state == 0) { |
303 | for (i = 0; i < TRBS_PER_SEGMENT; i++) | |
304 | seg->trbs[i].link.control |= TRB_CYCLE; | |
305 | } | |
74f9fe21 | 306 | /* All endpoint rings have link TRBs */ |
3b72fca0 | 307 | xhci_link_segments(xhci, seg, seg->next, type); |
74f9fe21 SS |
308 | seg = seg->next; |
309 | } while (seg != ring->first_seg); | |
3b72fca0 | 310 | ring->type = type; |
186a7ef1 | 311 | xhci_initialize_ring_info(ring, cycle_state); |
74f9fe21 SS |
312 | /* td list should be empty since all URBs have been cancelled, |
313 | * but just in case... | |
314 | */ | |
315 | INIT_LIST_HEAD(&ring->td_list); | |
316 | } | |
317 | ||
8dfec614 AX |
318 | /* |
319 | * Expand an existing ring. | |
320 | * Look for a cached ring or allocate a new ring which has same segment numbers | |
321 | * and link the two rings. | |
322 | */ | |
323 | int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
324 | unsigned int num_trbs, gfp_t flags) | |
325 | { | |
326 | struct xhci_segment *first; | |
327 | struct xhci_segment *last; | |
328 | unsigned int num_segs; | |
329 | unsigned int num_segs_needed; | |
330 | int ret; | |
331 | ||
332 | num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) / | |
333 | (TRBS_PER_SEGMENT - 1); | |
334 | ||
335 | /* Allocate number of segments we needed, or double the ring size */ | |
336 | num_segs = ring->num_segs > num_segs_needed ? | |
337 | ring->num_segs : num_segs_needed; | |
338 | ||
339 | ret = xhci_alloc_segments_for_ring(xhci, &first, &last, | |
340 | num_segs, ring->cycle_state, ring->type, flags); | |
341 | if (ret) | |
342 | return -ENOMEM; | |
343 | ||
344 | xhci_link_rings(xhci, ring, first, last, num_segs); | |
345 | xhci_dbg(xhci, "ring expansion succeed, now has %d segments\n", | |
346 | ring->num_segs); | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
d115b048 JY |
351 | #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) |
352 | ||
326b4810 | 353 | static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
354 | int type, gfp_t flags) |
355 | { | |
356 | struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags); | |
357 | if (!ctx) | |
358 | return NULL; | |
359 | ||
360 | BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT)); | |
361 | ctx->type = type; | |
362 | ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024; | |
363 | if (type == XHCI_CTX_TYPE_INPUT) | |
364 | ctx->size += CTX_SIZE(xhci->hcc_params); | |
365 | ||
366 | ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma); | |
367 | memset(ctx->bytes, 0, ctx->size); | |
368 | return ctx; | |
369 | } | |
370 | ||
326b4810 | 371 | static void xhci_free_container_ctx(struct xhci_hcd *xhci, |
d115b048 JY |
372 | struct xhci_container_ctx *ctx) |
373 | { | |
a1d78c16 SS |
374 | if (!ctx) |
375 | return; | |
d115b048 JY |
376 | dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma); |
377 | kfree(ctx); | |
378 | } | |
379 | ||
380 | struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, | |
381 | struct xhci_container_ctx *ctx) | |
382 | { | |
383 | BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT); | |
384 | return (struct xhci_input_control_ctx *)ctx->bytes; | |
385 | } | |
386 | ||
387 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, | |
388 | struct xhci_container_ctx *ctx) | |
389 | { | |
390 | if (ctx->type == XHCI_CTX_TYPE_DEVICE) | |
391 | return (struct xhci_slot_ctx *)ctx->bytes; | |
392 | ||
393 | return (struct xhci_slot_ctx *) | |
394 | (ctx->bytes + CTX_SIZE(xhci->hcc_params)); | |
395 | } | |
396 | ||
397 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, | |
398 | struct xhci_container_ctx *ctx, | |
399 | unsigned int ep_index) | |
400 | { | |
401 | /* increment ep index by offset of start of ep ctx array */ | |
402 | ep_index++; | |
403 | if (ctx->type == XHCI_CTX_TYPE_INPUT) | |
404 | ep_index++; | |
405 | ||
406 | return (struct xhci_ep_ctx *) | |
407 | (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params))); | |
408 | } | |
409 | ||
8df75f42 SS |
410 | |
411 | /***************** Streams structures manipulation *************************/ | |
412 | ||
8212a49d | 413 | static void xhci_free_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
414 | unsigned int num_stream_ctxs, |
415 | struct xhci_stream_ctx *stream_ctx, dma_addr_t dma) | |
416 | { | |
417 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
418 | ||
419 | if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE) | |
22d45f01 | 420 | dma_free_coherent(&pdev->dev, |
8df75f42 SS |
421 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs, |
422 | stream_ctx, dma); | |
423 | else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE) | |
424 | return dma_pool_free(xhci->small_streams_pool, | |
425 | stream_ctx, dma); | |
426 | else | |
427 | return dma_pool_free(xhci->medium_streams_pool, | |
428 | stream_ctx, dma); | |
429 | } | |
430 | ||
431 | /* | |
432 | * The stream context array for each endpoint with bulk streams enabled can | |
433 | * vary in size, based on: | |
434 | * - how many streams the endpoint supports, | |
435 | * - the maximum primary stream array size the host controller supports, | |
436 | * - and how many streams the device driver asks for. | |
437 | * | |
438 | * The stream context array must be a power of 2, and can be as small as | |
439 | * 64 bytes or as large as 1MB. | |
440 | */ | |
8212a49d | 441 | static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci, |
8df75f42 SS |
442 | unsigned int num_stream_ctxs, dma_addr_t *dma, |
443 | gfp_t mem_flags) | |
444 | { | |
445 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
446 | ||
447 | if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE) | |
22d45f01 | 448 | return dma_alloc_coherent(&pdev->dev, |
8df75f42 | 449 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs, |
22d45f01 | 450 | dma, mem_flags); |
8df75f42 SS |
451 | else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE) |
452 | return dma_pool_alloc(xhci->small_streams_pool, | |
453 | mem_flags, dma); | |
454 | else | |
455 | return dma_pool_alloc(xhci->medium_streams_pool, | |
456 | mem_flags, dma); | |
457 | } | |
458 | ||
e9df17eb SS |
459 | struct xhci_ring *xhci_dma_to_transfer_ring( |
460 | struct xhci_virt_ep *ep, | |
461 | u64 address) | |
462 | { | |
463 | if (ep->ep_state & EP_HAS_STREAMS) | |
464 | return radix_tree_lookup(&ep->stream_info->trb_address_map, | |
465 | address >> SEGMENT_SHIFT); | |
466 | return ep->ring; | |
467 | } | |
468 | ||
469 | /* Only use this when you know stream_info is valid */ | |
8df75f42 | 470 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
e9df17eb | 471 | static struct xhci_ring *dma_to_stream_ring( |
8df75f42 SS |
472 | struct xhci_stream_info *stream_info, |
473 | u64 address) | |
474 | { | |
475 | return radix_tree_lookup(&stream_info->trb_address_map, | |
476 | address >> SEGMENT_SHIFT); | |
477 | } | |
478 | #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */ | |
479 | ||
e9df17eb SS |
480 | struct xhci_ring *xhci_stream_id_to_ring( |
481 | struct xhci_virt_device *dev, | |
482 | unsigned int ep_index, | |
483 | unsigned int stream_id) | |
484 | { | |
485 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; | |
486 | ||
487 | if (stream_id == 0) | |
488 | return ep->ring; | |
489 | if (!ep->stream_info) | |
490 | return NULL; | |
491 | ||
492 | if (stream_id > ep->stream_info->num_streams) | |
493 | return NULL; | |
494 | return ep->stream_info->stream_rings[stream_id]; | |
495 | } | |
496 | ||
8df75f42 SS |
497 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING |
498 | static int xhci_test_radix_tree(struct xhci_hcd *xhci, | |
499 | unsigned int num_streams, | |
500 | struct xhci_stream_info *stream_info) | |
501 | { | |
502 | u32 cur_stream; | |
503 | struct xhci_ring *cur_ring; | |
504 | u64 addr; | |
505 | ||
506 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
507 | struct xhci_ring *mapped_ring; | |
508 | int trb_size = sizeof(union xhci_trb); | |
509 | ||
510 | cur_ring = stream_info->stream_rings[cur_stream]; | |
511 | for (addr = cur_ring->first_seg->dma; | |
512 | addr < cur_ring->first_seg->dma + SEGMENT_SIZE; | |
513 | addr += trb_size) { | |
514 | mapped_ring = dma_to_stream_ring(stream_info, addr); | |
515 | if (cur_ring != mapped_ring) { | |
516 | xhci_warn(xhci, "WARN: DMA address 0x%08llx " | |
517 | "didn't map to stream ID %u; " | |
518 | "mapped to ring %p\n", | |
519 | (unsigned long long) addr, | |
520 | cur_stream, | |
521 | mapped_ring); | |
522 | return -EINVAL; | |
523 | } | |
524 | } | |
525 | /* One TRB after the end of the ring segment shouldn't return a | |
526 | * pointer to the current ring (although it may be a part of a | |
527 | * different ring). | |
528 | */ | |
529 | mapped_ring = dma_to_stream_ring(stream_info, addr); | |
530 | if (mapped_ring != cur_ring) { | |
531 | /* One TRB before should also fail */ | |
532 | addr = cur_ring->first_seg->dma - trb_size; | |
533 | mapped_ring = dma_to_stream_ring(stream_info, addr); | |
534 | } | |
535 | if (mapped_ring == cur_ring) { | |
536 | xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx " | |
537 | "mapped to valid stream ID %u; " | |
538 | "mapped ring = %p\n", | |
539 | (unsigned long long) addr, | |
540 | cur_stream, | |
541 | mapped_ring); | |
542 | return -EINVAL; | |
543 | } | |
544 | } | |
545 | return 0; | |
546 | } | |
547 | #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */ | |
548 | ||
549 | /* | |
550 | * Change an endpoint's internal structure so it supports stream IDs. The | |
551 | * number of requested streams includes stream 0, which cannot be used by device | |
552 | * drivers. | |
553 | * | |
554 | * The number of stream contexts in the stream context array may be bigger than | |
555 | * the number of streams the driver wants to use. This is because the number of | |
556 | * stream context array entries must be a power of two. | |
557 | * | |
558 | * We need a radix tree for mapping physical addresses of TRBs to which stream | |
559 | * ID they belong to. We need to do this because the host controller won't tell | |
560 | * us which stream ring the TRB came from. We could store the stream ID in an | |
561 | * event data TRB, but that doesn't help us for the cancellation case, since the | |
562 | * endpoint may stop before it reaches that event data TRB. | |
563 | * | |
564 | * The radix tree maps the upper portion of the TRB DMA address to a ring | |
565 | * segment that has the same upper portion of DMA addresses. For example, say I | |
566 | * have segments of size 1KB, that are always 64-byte aligned. A segment may | |
567 | * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the | |
568 | * key to the stream ID is 0x43244. I can use the DMA address of the TRB to | |
569 | * pass the radix tree a key to get the right stream ID: | |
570 | * | |
571 | * 0x10c90fff >> 10 = 0x43243 | |
572 | * 0x10c912c0 >> 10 = 0x43244 | |
573 | * 0x10c91400 >> 10 = 0x43245 | |
574 | * | |
575 | * Obviously, only those TRBs with DMA addresses that are within the segment | |
576 | * will make the radix tree return the stream ID for that ring. | |
577 | * | |
578 | * Caveats for the radix tree: | |
579 | * | |
580 | * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an | |
581 | * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be | |
582 | * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the | |
583 | * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit | |
584 | * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit | |
585 | * extended systems (where the DMA address can be bigger than 32-bits), | |
586 | * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that. | |
587 | */ | |
588 | struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, | |
589 | unsigned int num_stream_ctxs, | |
590 | unsigned int num_streams, gfp_t mem_flags) | |
591 | { | |
592 | struct xhci_stream_info *stream_info; | |
593 | u32 cur_stream; | |
594 | struct xhci_ring *cur_ring; | |
595 | unsigned long key; | |
596 | u64 addr; | |
597 | int ret; | |
598 | ||
599 | xhci_dbg(xhci, "Allocating %u streams and %u " | |
600 | "stream context array entries.\n", | |
601 | num_streams, num_stream_ctxs); | |
602 | if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) { | |
603 | xhci_dbg(xhci, "Command ring has no reserved TRBs available\n"); | |
604 | return NULL; | |
605 | } | |
606 | xhci->cmd_ring_reserved_trbs++; | |
607 | ||
608 | stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags); | |
609 | if (!stream_info) | |
610 | goto cleanup_trbs; | |
611 | ||
612 | stream_info->num_streams = num_streams; | |
613 | stream_info->num_stream_ctxs = num_stream_ctxs; | |
614 | ||
615 | /* Initialize the array of virtual pointers to stream rings. */ | |
616 | stream_info->stream_rings = kzalloc( | |
617 | sizeof(struct xhci_ring *)*num_streams, | |
618 | mem_flags); | |
619 | if (!stream_info->stream_rings) | |
620 | goto cleanup_info; | |
621 | ||
622 | /* Initialize the array of DMA addresses for stream rings for the HW. */ | |
623 | stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci, | |
624 | num_stream_ctxs, &stream_info->ctx_array_dma, | |
625 | mem_flags); | |
626 | if (!stream_info->stream_ctx_array) | |
627 | goto cleanup_ctx; | |
628 | memset(stream_info->stream_ctx_array, 0, | |
629 | sizeof(struct xhci_stream_ctx)*num_stream_ctxs); | |
630 | ||
631 | /* Allocate everything needed to free the stream rings later */ | |
632 | stream_info->free_streams_command = | |
633 | xhci_alloc_command(xhci, true, true, mem_flags); | |
634 | if (!stream_info->free_streams_command) | |
635 | goto cleanup_ctx; | |
636 | ||
637 | INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC); | |
638 | ||
639 | /* Allocate rings for all the streams that the driver will use, | |
640 | * and add their segment DMA addresses to the radix tree. | |
641 | * Stream 0 is reserved. | |
642 | */ | |
643 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
644 | stream_info->stream_rings[cur_stream] = | |
2fdcd47b | 645 | xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags); |
8df75f42 SS |
646 | cur_ring = stream_info->stream_rings[cur_stream]; |
647 | if (!cur_ring) | |
648 | goto cleanup_rings; | |
e9df17eb | 649 | cur_ring->stream_id = cur_stream; |
8df75f42 SS |
650 | /* Set deq ptr, cycle bit, and stream context type */ |
651 | addr = cur_ring->first_seg->dma | | |
652 | SCT_FOR_CTX(SCT_PRI_TR) | | |
653 | cur_ring->cycle_state; | |
f5960b69 ME |
654 | stream_info->stream_ctx_array[cur_stream].stream_ring = |
655 | cpu_to_le64(addr); | |
8df75f42 SS |
656 | xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n", |
657 | cur_stream, (unsigned long long) addr); | |
658 | ||
659 | key = (unsigned long) | |
660 | (cur_ring->first_seg->dma >> SEGMENT_SHIFT); | |
661 | ret = radix_tree_insert(&stream_info->trb_address_map, | |
662 | key, cur_ring); | |
663 | if (ret) { | |
664 | xhci_ring_free(xhci, cur_ring); | |
665 | stream_info->stream_rings[cur_stream] = NULL; | |
666 | goto cleanup_rings; | |
667 | } | |
668 | } | |
669 | /* Leave the other unused stream ring pointers in the stream context | |
670 | * array initialized to zero. This will cause the xHC to give us an | |
671 | * error if the device asks for a stream ID we don't have setup (if it | |
672 | * was any other way, the host controller would assume the ring is | |
673 | * "empty" and wait forever for data to be queued to that stream ID). | |
674 | */ | |
675 | #if XHCI_DEBUG | |
676 | /* Do a little test on the radix tree to make sure it returns the | |
677 | * correct values. | |
678 | */ | |
679 | if (xhci_test_radix_tree(xhci, num_streams, stream_info)) | |
680 | goto cleanup_rings; | |
681 | #endif | |
682 | ||
683 | return stream_info; | |
684 | ||
685 | cleanup_rings: | |
686 | for (cur_stream = 1; cur_stream < num_streams; cur_stream++) { | |
687 | cur_ring = stream_info->stream_rings[cur_stream]; | |
688 | if (cur_ring) { | |
689 | addr = cur_ring->first_seg->dma; | |
690 | radix_tree_delete(&stream_info->trb_address_map, | |
691 | addr >> SEGMENT_SHIFT); | |
692 | xhci_ring_free(xhci, cur_ring); | |
693 | stream_info->stream_rings[cur_stream] = NULL; | |
694 | } | |
695 | } | |
696 | xhci_free_command(xhci, stream_info->free_streams_command); | |
697 | cleanup_ctx: | |
698 | kfree(stream_info->stream_rings); | |
699 | cleanup_info: | |
700 | kfree(stream_info); | |
701 | cleanup_trbs: | |
702 | xhci->cmd_ring_reserved_trbs--; | |
703 | return NULL; | |
704 | } | |
705 | /* | |
706 | * Sets the MaxPStreams field and the Linear Stream Array field. | |
707 | * Sets the dequeue pointer to the stream context array. | |
708 | */ | |
709 | void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
710 | struct xhci_ep_ctx *ep_ctx, | |
711 | struct xhci_stream_info *stream_info) | |
712 | { | |
713 | u32 max_primary_streams; | |
714 | /* MaxPStreams is the number of stream context array entries, not the | |
715 | * number we're actually using. Must be in 2^(MaxPstreams + 1) format. | |
716 | * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc. | |
717 | */ | |
718 | max_primary_streams = fls(stream_info->num_stream_ctxs) - 2; | |
719 | xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n", | |
720 | 1 << (max_primary_streams + 1)); | |
28ccd296 ME |
721 | ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK); |
722 | ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams) | |
723 | | EP_HAS_LSA); | |
724 | ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma); | |
8df75f42 SS |
725 | } |
726 | ||
727 | /* | |
728 | * Sets the MaxPStreams field and the Linear Stream Array field to 0. | |
729 | * Reinstalls the "normal" endpoint ring (at its previous dequeue mark, | |
730 | * not at the beginning of the ring). | |
731 | */ | |
732 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
733 | struct xhci_ep_ctx *ep_ctx, | |
734 | struct xhci_virt_ep *ep) | |
735 | { | |
736 | dma_addr_t addr; | |
28ccd296 | 737 | ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA)); |
8df75f42 | 738 | addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue); |
28ccd296 | 739 | ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state); |
8df75f42 SS |
740 | } |
741 | ||
742 | /* Frees all stream contexts associated with the endpoint, | |
743 | * | |
744 | * Caller should fix the endpoint context streams fields. | |
745 | */ | |
746 | void xhci_free_stream_info(struct xhci_hcd *xhci, | |
747 | struct xhci_stream_info *stream_info) | |
748 | { | |
749 | int cur_stream; | |
750 | struct xhci_ring *cur_ring; | |
751 | dma_addr_t addr; | |
752 | ||
753 | if (!stream_info) | |
754 | return; | |
755 | ||
756 | for (cur_stream = 1; cur_stream < stream_info->num_streams; | |
757 | cur_stream++) { | |
758 | cur_ring = stream_info->stream_rings[cur_stream]; | |
759 | if (cur_ring) { | |
760 | addr = cur_ring->first_seg->dma; | |
761 | radix_tree_delete(&stream_info->trb_address_map, | |
762 | addr >> SEGMENT_SHIFT); | |
763 | xhci_ring_free(xhci, cur_ring); | |
764 | stream_info->stream_rings[cur_stream] = NULL; | |
765 | } | |
766 | } | |
767 | xhci_free_command(xhci, stream_info->free_streams_command); | |
768 | xhci->cmd_ring_reserved_trbs--; | |
769 | if (stream_info->stream_ctx_array) | |
770 | xhci_free_stream_ctx(xhci, | |
771 | stream_info->num_stream_ctxs, | |
772 | stream_info->stream_ctx_array, | |
773 | stream_info->ctx_array_dma); | |
774 | ||
775 | if (stream_info) | |
776 | kfree(stream_info->stream_rings); | |
777 | kfree(stream_info); | |
778 | } | |
779 | ||
780 | ||
781 | /***************** Device context manipulation *************************/ | |
782 | ||
6f5165cf SS |
783 | static void xhci_init_endpoint_timer(struct xhci_hcd *xhci, |
784 | struct xhci_virt_ep *ep) | |
785 | { | |
786 | init_timer(&ep->stop_cmd_timer); | |
787 | ep->stop_cmd_timer.data = (unsigned long) ep; | |
788 | ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog; | |
789 | ep->xhci = xhci; | |
790 | } | |
791 | ||
839c817c SS |
792 | static void xhci_free_tt_info(struct xhci_hcd *xhci, |
793 | struct xhci_virt_device *virt_dev, | |
794 | int slot_id) | |
795 | { | |
796 | struct list_head *tt; | |
797 | struct list_head *tt_list_head; | |
798 | struct list_head *tt_next; | |
799 | struct xhci_tt_bw_info *tt_info; | |
800 | ||
801 | /* If the device never made it past the Set Address stage, | |
802 | * it may not have the real_port set correctly. | |
803 | */ | |
804 | if (virt_dev->real_port == 0 || | |
805 | virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) { | |
806 | xhci_dbg(xhci, "Bad real port.\n"); | |
807 | return; | |
808 | } | |
809 | ||
810 | tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts); | |
811 | if (list_empty(tt_list_head)) | |
812 | return; | |
813 | ||
814 | list_for_each(tt, tt_list_head) { | |
815 | tt_info = list_entry(tt, struct xhci_tt_bw_info, tt_list); | |
816 | if (tt_info->slot_id == slot_id) | |
817 | break; | |
818 | } | |
819 | /* Cautionary measure in case the hub was disconnected before we | |
820 | * stored the TT information. | |
821 | */ | |
822 | if (tt_info->slot_id != slot_id) | |
823 | return; | |
824 | ||
825 | tt_next = tt->next; | |
826 | tt_info = list_entry(tt, struct xhci_tt_bw_info, | |
827 | tt_list); | |
828 | /* Multi-TT hubs will have more than one entry */ | |
829 | do { | |
830 | list_del(tt); | |
831 | kfree(tt_info); | |
832 | tt = tt_next; | |
833 | if (list_empty(tt_list_head)) | |
834 | break; | |
835 | tt_next = tt->next; | |
836 | tt_info = list_entry(tt, struct xhci_tt_bw_info, | |
837 | tt_list); | |
838 | } while (tt_info->slot_id == slot_id); | |
839 | } | |
840 | ||
841 | int xhci_alloc_tt_info(struct xhci_hcd *xhci, | |
842 | struct xhci_virt_device *virt_dev, | |
843 | struct usb_device *hdev, | |
844 | struct usb_tt *tt, gfp_t mem_flags) | |
845 | { | |
846 | struct xhci_tt_bw_info *tt_info; | |
847 | unsigned int num_ports; | |
848 | int i, j; | |
849 | ||
850 | if (!tt->multi) | |
851 | num_ports = 1; | |
852 | else | |
853 | num_ports = hdev->maxchild; | |
854 | ||
855 | for (i = 0; i < num_ports; i++, tt_info++) { | |
856 | struct xhci_interval_bw_table *bw_table; | |
857 | ||
858 | tt_info = kzalloc(sizeof(*tt_info), mem_flags); | |
859 | if (!tt_info) | |
860 | goto free_tts; | |
861 | INIT_LIST_HEAD(&tt_info->tt_list); | |
862 | list_add(&tt_info->tt_list, | |
863 | &xhci->rh_bw[virt_dev->real_port - 1].tts); | |
864 | tt_info->slot_id = virt_dev->udev->slot_id; | |
865 | if (tt->multi) | |
866 | tt_info->ttport = i+1; | |
867 | bw_table = &tt_info->bw_table; | |
868 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
869 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
870 | } | |
871 | return 0; | |
872 | ||
873 | free_tts: | |
874 | xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id); | |
875 | return -ENOMEM; | |
876 | } | |
877 | ||
878 | ||
879 | /* All the xhci_tds in the ring's TD list should be freed at this point. | |
880 | * Should be called with xhci->lock held if there is any chance the TT lists | |
881 | * will be manipulated by the configure endpoint, allocate device, or update | |
882 | * hub functions while this function is removing the TT entries from the list. | |
883 | */ | |
3ffbba95 SS |
884 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id) |
885 | { | |
886 | struct xhci_virt_device *dev; | |
887 | int i; | |
2e27980e | 888 | int old_active_eps = 0; |
3ffbba95 SS |
889 | |
890 | /* Slot ID 0 is reserved */ | |
891 | if (slot_id == 0 || !xhci->devs[slot_id]) | |
892 | return; | |
893 | ||
894 | dev = xhci->devs[slot_id]; | |
8e595a5d | 895 | xhci->dcbaa->dev_context_ptrs[slot_id] = 0; |
3ffbba95 SS |
896 | if (!dev) |
897 | return; | |
898 | ||
2e27980e SS |
899 | if (dev->tt_info) |
900 | old_active_eps = dev->tt_info->active_eps; | |
901 | ||
8df75f42 | 902 | for (i = 0; i < 31; ++i) { |
63a0d9ab SS |
903 | if (dev->eps[i].ring) |
904 | xhci_ring_free(xhci, dev->eps[i].ring); | |
8df75f42 SS |
905 | if (dev->eps[i].stream_info) |
906 | xhci_free_stream_info(xhci, | |
907 | dev->eps[i].stream_info); | |
2e27980e SS |
908 | /* Endpoints on the TT/root port lists should have been removed |
909 | * when usb_disable_device() was called for the device. | |
910 | * We can't drop them anyway, because the udev might have gone | |
911 | * away by this point, and we can't tell what speed it was. | |
912 | */ | |
913 | if (!list_empty(&dev->eps[i].bw_endpoint_list)) | |
914 | xhci_warn(xhci, "Slot %u endpoint %u " | |
915 | "not removed from BW list!\n", | |
916 | slot_id, i); | |
8df75f42 | 917 | } |
839c817c SS |
918 | /* If this is a hub, free the TT(s) from the TT list */ |
919 | xhci_free_tt_info(xhci, dev, slot_id); | |
2e27980e SS |
920 | /* If necessary, update the number of active TTs on this root port */ |
921 | xhci_update_tt_active_eps(xhci, dev, old_active_eps); | |
3ffbba95 | 922 | |
74f9fe21 SS |
923 | if (dev->ring_cache) { |
924 | for (i = 0; i < dev->num_rings_cached; i++) | |
925 | xhci_ring_free(xhci, dev->ring_cache[i]); | |
926 | kfree(dev->ring_cache); | |
927 | } | |
928 | ||
3ffbba95 | 929 | if (dev->in_ctx) |
d115b048 | 930 | xhci_free_container_ctx(xhci, dev->in_ctx); |
3ffbba95 | 931 | if (dev->out_ctx) |
d115b048 JY |
932 | xhci_free_container_ctx(xhci, dev->out_ctx); |
933 | ||
3ffbba95 | 934 | kfree(xhci->devs[slot_id]); |
326b4810 | 935 | xhci->devs[slot_id] = NULL; |
3ffbba95 SS |
936 | } |
937 | ||
938 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, | |
939 | struct usb_device *udev, gfp_t flags) | |
940 | { | |
3ffbba95 | 941 | struct xhci_virt_device *dev; |
63a0d9ab | 942 | int i; |
3ffbba95 SS |
943 | |
944 | /* Slot ID 0 is reserved */ | |
945 | if (slot_id == 0 || xhci->devs[slot_id]) { | |
946 | xhci_warn(xhci, "Bad Slot ID %d\n", slot_id); | |
947 | return 0; | |
948 | } | |
949 | ||
950 | xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags); | |
951 | if (!xhci->devs[slot_id]) | |
952 | return 0; | |
953 | dev = xhci->devs[slot_id]; | |
954 | ||
d115b048 JY |
955 | /* Allocate the (output) device context that will be used in the HC. */ |
956 | dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags); | |
3ffbba95 SS |
957 | if (!dev->out_ctx) |
958 | goto fail; | |
d115b048 | 959 | |
700e2052 | 960 | xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 961 | (unsigned long long)dev->out_ctx->dma); |
3ffbba95 SS |
962 | |
963 | /* Allocate the (input) device context for address device command */ | |
d115b048 | 964 | dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags); |
3ffbba95 SS |
965 | if (!dev->in_ctx) |
966 | goto fail; | |
d115b048 | 967 | |
700e2052 | 968 | xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id, |
d115b048 | 969 | (unsigned long long)dev->in_ctx->dma); |
3ffbba95 | 970 | |
6f5165cf SS |
971 | /* Initialize the cancellation list and watchdog timers for each ep */ |
972 | for (i = 0; i < 31; i++) { | |
973 | xhci_init_endpoint_timer(xhci, &dev->eps[i]); | |
63a0d9ab | 974 | INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list); |
2e27980e | 975 | INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list); |
6f5165cf | 976 | } |
63a0d9ab | 977 | |
3ffbba95 | 978 | /* Allocate endpoint 0 ring */ |
2fdcd47b | 979 | dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags); |
63a0d9ab | 980 | if (!dev->eps[0].ring) |
3ffbba95 SS |
981 | goto fail; |
982 | ||
74f9fe21 SS |
983 | /* Allocate pointers to the ring cache */ |
984 | dev->ring_cache = kzalloc( | |
985 | sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED, | |
986 | flags); | |
987 | if (!dev->ring_cache) | |
988 | goto fail; | |
989 | dev->num_rings_cached = 0; | |
990 | ||
f94e0186 | 991 | init_completion(&dev->cmd_completion); |
913a8a34 | 992 | INIT_LIST_HEAD(&dev->cmd_list); |
64927730 | 993 | dev->udev = udev; |
f94e0186 | 994 | |
28c2d2ef | 995 | /* Point to output device context in dcbaa. */ |
28ccd296 | 996 | xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma); |
700e2052 | 997 | xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n", |
28ccd296 ME |
998 | slot_id, |
999 | &xhci->dcbaa->dev_context_ptrs[slot_id], | |
f5960b69 | 1000 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id])); |
3ffbba95 SS |
1001 | |
1002 | return 1; | |
1003 | fail: | |
1004 | xhci_free_virt_device(xhci, slot_id); | |
1005 | return 0; | |
1006 | } | |
1007 | ||
2d1ee590 SS |
1008 | void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, |
1009 | struct usb_device *udev) | |
1010 | { | |
1011 | struct xhci_virt_device *virt_dev; | |
1012 | struct xhci_ep_ctx *ep0_ctx; | |
1013 | struct xhci_ring *ep_ring; | |
1014 | ||
1015 | virt_dev = xhci->devs[udev->slot_id]; | |
1016 | ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0); | |
1017 | ep_ring = virt_dev->eps[0].ring; | |
1018 | /* | |
1019 | * FIXME we don't keep track of the dequeue pointer very well after a | |
1020 | * Set TR dequeue pointer, so we're setting the dequeue pointer of the | |
1021 | * host to our enqueue pointer. This should only be called after a | |
1022 | * configured device has reset, so all control transfers should have | |
1023 | * been completed or cancelled before the reset. | |
1024 | */ | |
28ccd296 ME |
1025 | ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg, |
1026 | ep_ring->enqueue) | |
1027 | | ep_ring->cycle_state); | |
2d1ee590 SS |
1028 | } |
1029 | ||
f6ff0ac8 SS |
1030 | /* |
1031 | * The xHCI roothub may have ports of differing speeds in any order in the port | |
1032 | * status registers. xhci->port_array provides an array of the port speed for | |
1033 | * each offset into the port status registers. | |
1034 | * | |
1035 | * The xHCI hardware wants to know the roothub port number that the USB device | |
1036 | * is attached to (or the roothub port its ancestor hub is attached to). All we | |
1037 | * know is the index of that port under either the USB 2.0 or the USB 3.0 | |
1038 | * roothub, but that doesn't give us the real index into the HW port status | |
1039 | * registers. Scan through the xHCI roothub port array, looking for the Nth | |
1040 | * entry of the correct port speed. Return the port number of that entry. | |
1041 | */ | |
1042 | static u32 xhci_find_real_port_number(struct xhci_hcd *xhci, | |
1043 | struct usb_device *udev) | |
1044 | { | |
1045 | struct usb_device *top_dev; | |
1046 | unsigned int num_similar_speed_ports; | |
1047 | unsigned int faked_port_num; | |
1048 | int i; | |
1049 | ||
1050 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; | |
1051 | top_dev = top_dev->parent) | |
1052 | /* Found device below root hub */; | |
1053 | faked_port_num = top_dev->portnum; | |
1054 | for (i = 0, num_similar_speed_ports = 0; | |
1055 | i < HCS_MAX_PORTS(xhci->hcs_params1); i++) { | |
1056 | u8 port_speed = xhci->port_array[i]; | |
1057 | ||
1058 | /* | |
1059 | * Skip ports that don't have known speeds, or have duplicate | |
1060 | * Extended Capabilities port speed entries. | |
1061 | */ | |
22e04870 | 1062 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1063 | continue; |
1064 | ||
1065 | /* | |
1066 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1067 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1068 | * matches the device speed, it's a similar speed port. | |
1069 | */ | |
1070 | if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER)) | |
1071 | num_similar_speed_ports++; | |
1072 | if (num_similar_speed_ports == faked_port_num) | |
1073 | /* Roothub ports are numbered from 1 to N */ | |
1074 | return i+1; | |
1075 | } | |
1076 | return 0; | |
1077 | } | |
1078 | ||
3ffbba95 SS |
1079 | /* Setup an xHCI virtual device for a Set Address command */ |
1080 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev) | |
1081 | { | |
1082 | struct xhci_virt_device *dev; | |
1083 | struct xhci_ep_ctx *ep0_ctx; | |
d115b048 | 1084 | struct xhci_slot_ctx *slot_ctx; |
f6ff0ac8 SS |
1085 | u32 port_num; |
1086 | struct usb_device *top_dev; | |
3ffbba95 SS |
1087 | |
1088 | dev = xhci->devs[udev->slot_id]; | |
1089 | /* Slot ID 0 is reserved */ | |
1090 | if (udev->slot_id == 0 || !dev) { | |
1091 | xhci_warn(xhci, "Slot ID %d is not assigned to this device\n", | |
1092 | udev->slot_id); | |
1093 | return -EINVAL; | |
1094 | } | |
d115b048 | 1095 | ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0); |
d115b048 | 1096 | slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx); |
3ffbba95 | 1097 | |
3ffbba95 | 1098 | /* 3) Only the control endpoint is valid - one endpoint context */ |
f5960b69 | 1099 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route); |
3ffbba95 SS |
1100 | switch (udev->speed) { |
1101 | case USB_SPEED_SUPER: | |
f5960b69 | 1102 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS); |
3ffbba95 SS |
1103 | break; |
1104 | case USB_SPEED_HIGH: | |
f5960b69 | 1105 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS); |
3ffbba95 SS |
1106 | break; |
1107 | case USB_SPEED_FULL: | |
f5960b69 | 1108 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS); |
3ffbba95 SS |
1109 | break; |
1110 | case USB_SPEED_LOW: | |
f5960b69 | 1111 | slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS); |
3ffbba95 | 1112 | break; |
551cdbbe | 1113 | case USB_SPEED_WIRELESS: |
3ffbba95 SS |
1114 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
1115 | return -EINVAL; | |
1116 | break; | |
1117 | default: | |
1118 | /* Speed was set earlier, this shouldn't happen. */ | |
1119 | BUG(); | |
1120 | } | |
1121 | /* Find the root hub port this device is under */ | |
f6ff0ac8 SS |
1122 | port_num = xhci_find_real_port_number(xhci, udev); |
1123 | if (!port_num) | |
1124 | return -EINVAL; | |
f5960b69 | 1125 | slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num)); |
f6ff0ac8 | 1126 | /* Set the port number in the virtual_device to the faked port number */ |
3ffbba95 SS |
1127 | for (top_dev = udev; top_dev->parent && top_dev->parent->parent; |
1128 | top_dev = top_dev->parent) | |
1129 | /* Found device below root hub */; | |
fe30182c | 1130 | dev->fake_port = top_dev->portnum; |
66381755 | 1131 | dev->real_port = port_num; |
f6ff0ac8 | 1132 | xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num); |
fe30182c | 1133 | xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port); |
3ffbba95 | 1134 | |
839c817c SS |
1135 | /* Find the right bandwidth table that this device will be a part of. |
1136 | * If this is a full speed device attached directly to a root port (or a | |
1137 | * decendent of one), it counts as a primary bandwidth domain, not a | |
1138 | * secondary bandwidth domain under a TT. An xhci_tt_info structure | |
1139 | * will never be created for the HS root hub. | |
1140 | */ | |
1141 | if (!udev->tt || !udev->tt->hub->parent) { | |
1142 | dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table; | |
1143 | } else { | |
1144 | struct xhci_root_port_bw_info *rh_bw; | |
1145 | struct xhci_tt_bw_info *tt_bw; | |
1146 | ||
1147 | rh_bw = &xhci->rh_bw[port_num - 1]; | |
1148 | /* Find the right TT. */ | |
1149 | list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) { | |
1150 | if (tt_bw->slot_id != udev->tt->hub->slot_id) | |
1151 | continue; | |
1152 | ||
1153 | if (!dev->udev->tt->multi || | |
1154 | (udev->tt->multi && | |
1155 | tt_bw->ttport == dev->udev->ttport)) { | |
1156 | dev->bw_table = &tt_bw->bw_table; | |
1157 | dev->tt_info = tt_bw; | |
1158 | break; | |
1159 | } | |
1160 | } | |
1161 | if (!dev->tt_info) | |
1162 | xhci_warn(xhci, "WARN: Didn't find a matching TT\n"); | |
1163 | } | |
1164 | ||
aa1b13ef SS |
1165 | /* Is this a LS/FS device under an external HS hub? */ |
1166 | if (udev->tt && udev->tt->hub->parent) { | |
28ccd296 ME |
1167 | slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id | |
1168 | (udev->ttport << 8)); | |
07b6de10 | 1169 | if (udev->tt->multi) |
28ccd296 | 1170 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
3ffbba95 | 1171 | } |
700e2052 | 1172 | xhci_dbg(xhci, "udev->tt = %p\n", udev->tt); |
3ffbba95 SS |
1173 | xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport); |
1174 | ||
1175 | /* Step 4 - ring already allocated */ | |
1176 | /* Step 5 */ | |
28ccd296 | 1177 | ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); |
3ffbba95 | 1178 | /* |
3ffbba95 SS |
1179 | * XXX: Not sure about wireless USB devices. |
1180 | */ | |
47aded8a SS |
1181 | switch (udev->speed) { |
1182 | case USB_SPEED_SUPER: | |
28ccd296 | 1183 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512)); |
47aded8a SS |
1184 | break; |
1185 | case USB_SPEED_HIGH: | |
1186 | /* USB core guesses at a 64-byte max packet first for FS devices */ | |
1187 | case USB_SPEED_FULL: | |
28ccd296 | 1188 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64)); |
47aded8a SS |
1189 | break; |
1190 | case USB_SPEED_LOW: | |
28ccd296 | 1191 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8)); |
47aded8a | 1192 | break; |
551cdbbe | 1193 | case USB_SPEED_WIRELESS: |
47aded8a SS |
1194 | xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n"); |
1195 | return -EINVAL; | |
1196 | break; | |
1197 | default: | |
1198 | /* New speed? */ | |
1199 | BUG(); | |
1200 | } | |
3ffbba95 | 1201 | /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ |
28ccd296 | 1202 | ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3)); |
3ffbba95 | 1203 | |
28ccd296 ME |
1204 | ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma | |
1205 | dev->eps[0].ring->cycle_state); | |
3ffbba95 SS |
1206 | |
1207 | /* Steps 7 and 8 were done in xhci_alloc_virt_device() */ | |
1208 | ||
1209 | return 0; | |
1210 | } | |
1211 | ||
dfa49c4a DT |
1212 | /* |
1213 | * Convert interval expressed as 2^(bInterval - 1) == interval into | |
1214 | * straight exponent value 2^n == interval. | |
1215 | * | |
1216 | */ | |
1217 | static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, | |
1218 | struct usb_host_endpoint *ep) | |
1219 | { | |
1220 | unsigned int interval; | |
1221 | ||
1222 | interval = clamp_val(ep->desc.bInterval, 1, 16) - 1; | |
1223 | if (interval != ep->desc.bInterval - 1) | |
1224 | dev_warn(&udev->dev, | |
cd3c18ba | 1225 | "ep %#x - rounding interval to %d %sframes\n", |
dfa49c4a | 1226 | ep->desc.bEndpointAddress, |
cd3c18ba DT |
1227 | 1 << interval, |
1228 | udev->speed == USB_SPEED_FULL ? "" : "micro"); | |
1229 | ||
1230 | if (udev->speed == USB_SPEED_FULL) { | |
1231 | /* | |
1232 | * Full speed isoc endpoints specify interval in frames, | |
1233 | * not microframes. We are using microframes everywhere, | |
1234 | * so adjust accordingly. | |
1235 | */ | |
1236 | interval += 3; /* 1 frame = 2^3 uframes */ | |
1237 | } | |
dfa49c4a DT |
1238 | |
1239 | return interval; | |
1240 | } | |
1241 | ||
1242 | /* | |
340a3504 | 1243 | * Convert bInterval expressed in microframes (in 1-255 range) to exponent of |
dfa49c4a DT |
1244 | * microframes, rounded down to nearest power of 2. |
1245 | */ | |
340a3504 SS |
1246 | static unsigned int xhci_microframes_to_exponent(struct usb_device *udev, |
1247 | struct usb_host_endpoint *ep, unsigned int desc_interval, | |
1248 | unsigned int min_exponent, unsigned int max_exponent) | |
dfa49c4a DT |
1249 | { |
1250 | unsigned int interval; | |
1251 | ||
340a3504 SS |
1252 | interval = fls(desc_interval) - 1; |
1253 | interval = clamp_val(interval, min_exponent, max_exponent); | |
1254 | if ((1 << interval) != desc_interval) | |
dfa49c4a DT |
1255 | dev_warn(&udev->dev, |
1256 | "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n", | |
1257 | ep->desc.bEndpointAddress, | |
1258 | 1 << interval, | |
340a3504 | 1259 | desc_interval); |
dfa49c4a DT |
1260 | |
1261 | return interval; | |
1262 | } | |
1263 | ||
340a3504 SS |
1264 | static unsigned int xhci_parse_microframe_interval(struct usb_device *udev, |
1265 | struct usb_host_endpoint *ep) | |
1266 | { | |
1267 | return xhci_microframes_to_exponent(udev, ep, | |
1268 | ep->desc.bInterval, 0, 15); | |
1269 | } | |
1270 | ||
1271 | ||
1272 | static unsigned int xhci_parse_frame_interval(struct usb_device *udev, | |
1273 | struct usb_host_endpoint *ep) | |
1274 | { | |
1275 | return xhci_microframes_to_exponent(udev, ep, | |
1276 | ep->desc.bInterval * 8, 3, 10); | |
1277 | } | |
1278 | ||
f94e0186 SS |
1279 | /* Return the polling or NAK interval. |
1280 | * | |
1281 | * The polling interval is expressed in "microframes". If xHCI's Interval field | |
1282 | * is set to N, it will service the endpoint every 2^(Interval)*125us. | |
1283 | * | |
1284 | * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval | |
1285 | * is set to 0. | |
1286 | */ | |
575688e1 | 1287 | static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, |
f94e0186 SS |
1288 | struct usb_host_endpoint *ep) |
1289 | { | |
1290 | unsigned int interval = 0; | |
1291 | ||
1292 | switch (udev->speed) { | |
1293 | case USB_SPEED_HIGH: | |
1294 | /* Max NAK rate */ | |
1295 | if (usb_endpoint_xfer_control(&ep->desc) || | |
dfa49c4a | 1296 | usb_endpoint_xfer_bulk(&ep->desc)) { |
340a3504 | 1297 | interval = xhci_parse_microframe_interval(udev, ep); |
dfa49c4a DT |
1298 | break; |
1299 | } | |
f94e0186 | 1300 | /* Fall through - SS and HS isoc/int have same decoding */ |
dfa49c4a | 1301 | |
f94e0186 SS |
1302 | case USB_SPEED_SUPER: |
1303 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1304 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1305 | interval = xhci_parse_exponent_interval(udev, ep); | |
f94e0186 SS |
1306 | } |
1307 | break; | |
dfa49c4a | 1308 | |
f94e0186 | 1309 | case USB_SPEED_FULL: |
b513d447 | 1310 | if (usb_endpoint_xfer_isoc(&ep->desc)) { |
dfa49c4a DT |
1311 | interval = xhci_parse_exponent_interval(udev, ep); |
1312 | break; | |
1313 | } | |
1314 | /* | |
b513d447 | 1315 | * Fall through for interrupt endpoint interval decoding |
dfa49c4a DT |
1316 | * since it uses the same rules as low speed interrupt |
1317 | * endpoints. | |
1318 | */ | |
1319 | ||
f94e0186 SS |
1320 | case USB_SPEED_LOW: |
1321 | if (usb_endpoint_xfer_int(&ep->desc) || | |
dfa49c4a DT |
1322 | usb_endpoint_xfer_isoc(&ep->desc)) { |
1323 | ||
1324 | interval = xhci_parse_frame_interval(udev, ep); | |
f94e0186 SS |
1325 | } |
1326 | break; | |
dfa49c4a | 1327 | |
f94e0186 SS |
1328 | default: |
1329 | BUG(); | |
1330 | } | |
1331 | return EP_INTERVAL(interval); | |
1332 | } | |
1333 | ||
c30c791c | 1334 | /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. |
1cf62246 SS |
1335 | * High speed endpoint descriptors can define "the number of additional |
1336 | * transaction opportunities per microframe", but that goes in the Max Burst | |
1337 | * endpoint context field. | |
1338 | */ | |
575688e1 | 1339 | static u32 xhci_get_endpoint_mult(struct usb_device *udev, |
1cf62246 SS |
1340 | struct usb_host_endpoint *ep) |
1341 | { | |
c30c791c SS |
1342 | if (udev->speed != USB_SPEED_SUPER || |
1343 | !usb_endpoint_xfer_isoc(&ep->desc)) | |
1cf62246 | 1344 | return 0; |
842f1690 | 1345 | return ep->ss_ep_comp.bmAttributes; |
1cf62246 SS |
1346 | } |
1347 | ||
575688e1 | 1348 | static u32 xhci_get_endpoint_type(struct usb_device *udev, |
f94e0186 SS |
1349 | struct usb_host_endpoint *ep) |
1350 | { | |
1351 | int in; | |
1352 | u32 type; | |
1353 | ||
1354 | in = usb_endpoint_dir_in(&ep->desc); | |
1355 | if (usb_endpoint_xfer_control(&ep->desc)) { | |
1356 | type = EP_TYPE(CTRL_EP); | |
1357 | } else if (usb_endpoint_xfer_bulk(&ep->desc)) { | |
1358 | if (in) | |
1359 | type = EP_TYPE(BULK_IN_EP); | |
1360 | else | |
1361 | type = EP_TYPE(BULK_OUT_EP); | |
1362 | } else if (usb_endpoint_xfer_isoc(&ep->desc)) { | |
1363 | if (in) | |
1364 | type = EP_TYPE(ISOC_IN_EP); | |
1365 | else | |
1366 | type = EP_TYPE(ISOC_OUT_EP); | |
1367 | } else if (usb_endpoint_xfer_int(&ep->desc)) { | |
1368 | if (in) | |
1369 | type = EP_TYPE(INT_IN_EP); | |
1370 | else | |
1371 | type = EP_TYPE(INT_OUT_EP); | |
1372 | } else { | |
1373 | BUG(); | |
1374 | } | |
1375 | return type; | |
1376 | } | |
1377 | ||
9238f25d SS |
1378 | /* Return the maximum endpoint service interval time (ESIT) payload. |
1379 | * Basically, this is the maxpacket size, multiplied by the burst size | |
1380 | * and mult size. | |
1381 | */ | |
575688e1 | 1382 | static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci, |
9238f25d SS |
1383 | struct usb_device *udev, |
1384 | struct usb_host_endpoint *ep) | |
1385 | { | |
1386 | int max_burst; | |
1387 | int max_packet; | |
1388 | ||
1389 | /* Only applies for interrupt or isochronous endpoints */ | |
1390 | if (usb_endpoint_xfer_control(&ep->desc) || | |
1391 | usb_endpoint_xfer_bulk(&ep->desc)) | |
1392 | return 0; | |
1393 | ||
842f1690 | 1394 | if (udev->speed == USB_SPEED_SUPER) |
64b3c304 | 1395 | return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval); |
9238f25d | 1396 | |
29cc8897 KM |
1397 | max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)); |
1398 | max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11; | |
9238f25d SS |
1399 | /* A 0 in max burst means 1 transfer per ESIT */ |
1400 | return max_packet * (max_burst + 1); | |
1401 | } | |
1402 | ||
8df75f42 SS |
1403 | /* Set up an endpoint with one ring segment. Do not allocate stream rings. |
1404 | * Drivers will have to call usb_alloc_streams() to do that. | |
1405 | */ | |
f94e0186 SS |
1406 | int xhci_endpoint_init(struct xhci_hcd *xhci, |
1407 | struct xhci_virt_device *virt_dev, | |
1408 | struct usb_device *udev, | |
f88ba78d SS |
1409 | struct usb_host_endpoint *ep, |
1410 | gfp_t mem_flags) | |
f94e0186 SS |
1411 | { |
1412 | unsigned int ep_index; | |
1413 | struct xhci_ep_ctx *ep_ctx; | |
1414 | struct xhci_ring *ep_ring; | |
1415 | unsigned int max_packet; | |
1416 | unsigned int max_burst; | |
3b72fca0 | 1417 | enum xhci_ring_type type; |
9238f25d | 1418 | u32 max_esit_payload; |
f94e0186 SS |
1419 | |
1420 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1421 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 | 1422 | |
3b72fca0 | 1423 | type = usb_endpoint_type(&ep->desc); |
f94e0186 | 1424 | /* Set up the endpoint ring */ |
8dfec614 | 1425 | virt_dev->eps[ep_index].new_ring = |
2fdcd47b | 1426 | xhci_ring_alloc(xhci, 2, 1, type, mem_flags); |
74f9fe21 SS |
1427 | if (!virt_dev->eps[ep_index].new_ring) { |
1428 | /* Attempt to use the ring cache */ | |
1429 | if (virt_dev->num_rings_cached == 0) | |
1430 | return -ENOMEM; | |
1431 | virt_dev->eps[ep_index].new_ring = | |
1432 | virt_dev->ring_cache[virt_dev->num_rings_cached]; | |
1433 | virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL; | |
1434 | virt_dev->num_rings_cached--; | |
7e393a83 | 1435 | xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring, |
186a7ef1 | 1436 | 1, type); |
74f9fe21 | 1437 | } |
d18240db | 1438 | virt_dev->eps[ep_index].skip = false; |
63a0d9ab | 1439 | ep_ring = virt_dev->eps[ep_index].new_ring; |
28ccd296 | 1440 | ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state); |
f94e0186 | 1441 | |
28ccd296 ME |
1442 | ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep) |
1443 | | EP_MULT(xhci_get_endpoint_mult(udev, ep))); | |
f94e0186 SS |
1444 | |
1445 | /* FIXME dig Mult and streams info out of ep companion desc */ | |
1446 | ||
47692d17 | 1447 | /* Allow 3 retries for everything but isoc; |
7b1fc2ea | 1448 | * CErr shall be set to 0 for Isoch endpoints. |
47692d17 | 1449 | */ |
f94e0186 | 1450 | if (!usb_endpoint_xfer_isoc(&ep->desc)) |
28ccd296 | 1451 | ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3)); |
f94e0186 | 1452 | else |
7b1fc2ea | 1453 | ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0)); |
f94e0186 | 1454 | |
28ccd296 | 1455 | ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep)); |
f94e0186 SS |
1456 | |
1457 | /* Set the max packet size and max burst */ | |
1458 | switch (udev->speed) { | |
1459 | case USB_SPEED_SUPER: | |
29cc8897 | 1460 | max_packet = usb_endpoint_maxp(&ep->desc); |
28ccd296 | 1461 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet)); |
b10de142 | 1462 | /* dig out max burst from ep companion desc */ |
842f1690 | 1463 | max_packet = ep->ss_ep_comp.bMaxBurst; |
28ccd296 | 1464 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet)); |
f94e0186 SS |
1465 | break; |
1466 | case USB_SPEED_HIGH: | |
1467 | /* bits 11:12 specify the number of additional transaction | |
1468 | * opportunities per microframe (USB 2.0, section 9.6.6) | |
1469 | */ | |
1470 | if (usb_endpoint_xfer_isoc(&ep->desc) || | |
1471 | usb_endpoint_xfer_int(&ep->desc)) { | |
29cc8897 | 1472 | max_burst = (usb_endpoint_maxp(&ep->desc) |
28ccd296 ME |
1473 | & 0x1800) >> 11; |
1474 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst)); | |
f94e0186 SS |
1475 | } |
1476 | /* Fall through */ | |
1477 | case USB_SPEED_FULL: | |
1478 | case USB_SPEED_LOW: | |
29cc8897 | 1479 | max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)); |
28ccd296 | 1480 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet)); |
f94e0186 SS |
1481 | break; |
1482 | default: | |
1483 | BUG(); | |
1484 | } | |
9238f25d | 1485 | max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep); |
28ccd296 | 1486 | ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload)); |
9238f25d SS |
1487 | |
1488 | /* | |
1489 | * XXX no idea how to calculate the average TRB buffer length for bulk | |
1490 | * endpoints, as the driver gives us no clue how big each scatter gather | |
1491 | * list entry (or buffer) is going to be. | |
1492 | * | |
1493 | * For isochronous and interrupt endpoints, we set it to the max | |
1494 | * available, until we have new API in the USB core to allow drivers to | |
1495 | * declare how much bandwidth they actually need. | |
1496 | * | |
1497 | * Normally, it would be calculated by taking the total of the buffer | |
1498 | * lengths in the TD and then dividing by the number of TRBs in a TD, | |
1499 | * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't | |
1500 | * use Event Data TRBs, and we don't chain in a link TRB on short | |
1501 | * transfers, we're basically dividing by 1. | |
51eb01a7 AX |
1502 | * |
1503 | * xHCI 1.0 specification indicates that the Average TRB Length should | |
1504 | * be set to 8 for control endpoints. | |
9238f25d | 1505 | */ |
51eb01a7 AX |
1506 | if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100) |
1507 | ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8)); | |
1508 | else | |
1509 | ep_ctx->tx_info |= | |
1510 | cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload)); | |
9238f25d | 1511 | |
f94e0186 SS |
1512 | /* FIXME Debug endpoint context */ |
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | void xhci_endpoint_zero(struct xhci_hcd *xhci, | |
1517 | struct xhci_virt_device *virt_dev, | |
1518 | struct usb_host_endpoint *ep) | |
1519 | { | |
1520 | unsigned int ep_index; | |
1521 | struct xhci_ep_ctx *ep_ctx; | |
1522 | ||
1523 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
d115b048 | 1524 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index); |
f94e0186 SS |
1525 | |
1526 | ep_ctx->ep_info = 0; | |
1527 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1528 | ep_ctx->deq = 0; |
f94e0186 SS |
1529 | ep_ctx->tx_info = 0; |
1530 | /* Don't free the endpoint ring until the set interface or configuration | |
1531 | * request succeeds. | |
1532 | */ | |
1533 | } | |
1534 | ||
9af5d71d SS |
1535 | void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info) |
1536 | { | |
1537 | bw_info->ep_interval = 0; | |
1538 | bw_info->mult = 0; | |
1539 | bw_info->num_packets = 0; | |
1540 | bw_info->max_packet_size = 0; | |
1541 | bw_info->type = 0; | |
1542 | bw_info->max_esit_payload = 0; | |
1543 | } | |
1544 | ||
1545 | void xhci_update_bw_info(struct xhci_hcd *xhci, | |
1546 | struct xhci_container_ctx *in_ctx, | |
1547 | struct xhci_input_control_ctx *ctrl_ctx, | |
1548 | struct xhci_virt_device *virt_dev) | |
1549 | { | |
1550 | struct xhci_bw_info *bw_info; | |
1551 | struct xhci_ep_ctx *ep_ctx; | |
1552 | unsigned int ep_type; | |
1553 | int i; | |
1554 | ||
1555 | for (i = 1; i < 31; ++i) { | |
1556 | bw_info = &virt_dev->eps[i].bw_info; | |
1557 | ||
1558 | /* We can't tell what endpoint type is being dropped, but | |
1559 | * unconditionally clearing the bandwidth info for non-periodic | |
1560 | * endpoints should be harmless because the info will never be | |
1561 | * set in the first place. | |
1562 | */ | |
1563 | if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) { | |
1564 | /* Dropped endpoint */ | |
1565 | xhci_clear_endpoint_bw_info(bw_info); | |
1566 | continue; | |
1567 | } | |
1568 | ||
1569 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
1570 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i); | |
1571 | ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2)); | |
1572 | ||
1573 | /* Ignore non-periodic endpoints */ | |
1574 | if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
1575 | ep_type != ISOC_IN_EP && | |
1576 | ep_type != INT_IN_EP) | |
1577 | continue; | |
1578 | ||
1579 | /* Added or changed endpoint */ | |
1580 | bw_info->ep_interval = CTX_TO_EP_INTERVAL( | |
1581 | le32_to_cpu(ep_ctx->ep_info)); | |
170c0263 SS |
1582 | /* Number of packets and mult are zero-based in the |
1583 | * input context, but we want one-based for the | |
1584 | * interval table. | |
9af5d71d | 1585 | */ |
170c0263 SS |
1586 | bw_info->mult = CTX_TO_EP_MULT( |
1587 | le32_to_cpu(ep_ctx->ep_info)) + 1; | |
9af5d71d SS |
1588 | bw_info->num_packets = CTX_TO_MAX_BURST( |
1589 | le32_to_cpu(ep_ctx->ep_info2)) + 1; | |
1590 | bw_info->max_packet_size = MAX_PACKET_DECODED( | |
1591 | le32_to_cpu(ep_ctx->ep_info2)); | |
1592 | bw_info->type = ep_type; | |
1593 | bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD( | |
1594 | le32_to_cpu(ep_ctx->tx_info)); | |
1595 | } | |
1596 | } | |
1597 | } | |
1598 | ||
f2217e8e SS |
1599 | /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy. |
1600 | * Useful when you want to change one particular aspect of the endpoint and then | |
1601 | * issue a configure endpoint command. | |
1602 | */ | |
1603 | void xhci_endpoint_copy(struct xhci_hcd *xhci, | |
913a8a34 SS |
1604 | struct xhci_container_ctx *in_ctx, |
1605 | struct xhci_container_ctx *out_ctx, | |
1606 | unsigned int ep_index) | |
f2217e8e SS |
1607 | { |
1608 | struct xhci_ep_ctx *out_ep_ctx; | |
1609 | struct xhci_ep_ctx *in_ep_ctx; | |
1610 | ||
913a8a34 SS |
1611 | out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
1612 | in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); | |
f2217e8e SS |
1613 | |
1614 | in_ep_ctx->ep_info = out_ep_ctx->ep_info; | |
1615 | in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2; | |
1616 | in_ep_ctx->deq = out_ep_ctx->deq; | |
1617 | in_ep_ctx->tx_info = out_ep_ctx->tx_info; | |
1618 | } | |
1619 | ||
1620 | /* Copy output xhci_slot_ctx to the input xhci_slot_ctx. | |
1621 | * Useful when you want to change one particular aspect of the endpoint and then | |
1622 | * issue a configure endpoint command. Only the context entries field matters, | |
1623 | * but we'll copy the whole thing anyway. | |
1624 | */ | |
913a8a34 SS |
1625 | void xhci_slot_copy(struct xhci_hcd *xhci, |
1626 | struct xhci_container_ctx *in_ctx, | |
1627 | struct xhci_container_ctx *out_ctx) | |
f2217e8e SS |
1628 | { |
1629 | struct xhci_slot_ctx *in_slot_ctx; | |
1630 | struct xhci_slot_ctx *out_slot_ctx; | |
1631 | ||
913a8a34 SS |
1632 | in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx); |
1633 | out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx); | |
f2217e8e SS |
1634 | |
1635 | in_slot_ctx->dev_info = out_slot_ctx->dev_info; | |
1636 | in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2; | |
1637 | in_slot_ctx->tt_info = out_slot_ctx->tt_info; | |
1638 | in_slot_ctx->dev_state = out_slot_ctx->dev_state; | |
1639 | } | |
1640 | ||
254c80a3 JY |
1641 | /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */ |
1642 | static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags) | |
1643 | { | |
1644 | int i; | |
1645 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
1646 | int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1647 | ||
1648 | xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp); | |
1649 | ||
1650 | if (!num_sp) | |
1651 | return 0; | |
1652 | ||
1653 | xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags); | |
1654 | if (!xhci->scratchpad) | |
1655 | goto fail_sp; | |
1656 | ||
22d45f01 | 1657 | xhci->scratchpad->sp_array = dma_alloc_coherent(dev, |
254c80a3 | 1658 | num_sp * sizeof(u64), |
22d45f01 | 1659 | &xhci->scratchpad->sp_dma, flags); |
254c80a3 JY |
1660 | if (!xhci->scratchpad->sp_array) |
1661 | goto fail_sp2; | |
1662 | ||
1663 | xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags); | |
1664 | if (!xhci->scratchpad->sp_buffers) | |
1665 | goto fail_sp3; | |
1666 | ||
1667 | xhci->scratchpad->sp_dma_buffers = | |
1668 | kzalloc(sizeof(dma_addr_t) * num_sp, flags); | |
1669 | ||
1670 | if (!xhci->scratchpad->sp_dma_buffers) | |
1671 | goto fail_sp4; | |
1672 | ||
28ccd296 | 1673 | xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma); |
254c80a3 JY |
1674 | for (i = 0; i < num_sp; i++) { |
1675 | dma_addr_t dma; | |
22d45f01 SAS |
1676 | void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma, |
1677 | flags); | |
254c80a3 JY |
1678 | if (!buf) |
1679 | goto fail_sp5; | |
1680 | ||
1681 | xhci->scratchpad->sp_array[i] = dma; | |
1682 | xhci->scratchpad->sp_buffers[i] = buf; | |
1683 | xhci->scratchpad->sp_dma_buffers[i] = dma; | |
1684 | } | |
1685 | ||
1686 | return 0; | |
1687 | ||
1688 | fail_sp5: | |
1689 | for (i = i - 1; i >= 0; i--) { | |
22d45f01 | 1690 | dma_free_coherent(dev, xhci->page_size, |
254c80a3 JY |
1691 | xhci->scratchpad->sp_buffers[i], |
1692 | xhci->scratchpad->sp_dma_buffers[i]); | |
1693 | } | |
1694 | kfree(xhci->scratchpad->sp_dma_buffers); | |
1695 | ||
1696 | fail_sp4: | |
1697 | kfree(xhci->scratchpad->sp_buffers); | |
1698 | ||
1699 | fail_sp3: | |
22d45f01 | 1700 | dma_free_coherent(dev, num_sp * sizeof(u64), |
254c80a3 JY |
1701 | xhci->scratchpad->sp_array, |
1702 | xhci->scratchpad->sp_dma); | |
1703 | ||
1704 | fail_sp2: | |
1705 | kfree(xhci->scratchpad); | |
1706 | xhci->scratchpad = NULL; | |
1707 | ||
1708 | fail_sp: | |
1709 | return -ENOMEM; | |
1710 | } | |
1711 | ||
1712 | static void scratchpad_free(struct xhci_hcd *xhci) | |
1713 | { | |
1714 | int num_sp; | |
1715 | int i; | |
1716 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
1717 | ||
1718 | if (!xhci->scratchpad) | |
1719 | return; | |
1720 | ||
1721 | num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2); | |
1722 | ||
1723 | for (i = 0; i < num_sp; i++) { | |
22d45f01 | 1724 | dma_free_coherent(&pdev->dev, xhci->page_size, |
254c80a3 JY |
1725 | xhci->scratchpad->sp_buffers[i], |
1726 | xhci->scratchpad->sp_dma_buffers[i]); | |
1727 | } | |
1728 | kfree(xhci->scratchpad->sp_dma_buffers); | |
1729 | kfree(xhci->scratchpad->sp_buffers); | |
22d45f01 | 1730 | dma_free_coherent(&pdev->dev, num_sp * sizeof(u64), |
254c80a3 JY |
1731 | xhci->scratchpad->sp_array, |
1732 | xhci->scratchpad->sp_dma); | |
1733 | kfree(xhci->scratchpad); | |
1734 | xhci->scratchpad = NULL; | |
1735 | } | |
1736 | ||
913a8a34 | 1737 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
a1d78c16 SS |
1738 | bool allocate_in_ctx, bool allocate_completion, |
1739 | gfp_t mem_flags) | |
913a8a34 SS |
1740 | { |
1741 | struct xhci_command *command; | |
1742 | ||
1743 | command = kzalloc(sizeof(*command), mem_flags); | |
1744 | if (!command) | |
1745 | return NULL; | |
1746 | ||
a1d78c16 SS |
1747 | if (allocate_in_ctx) { |
1748 | command->in_ctx = | |
1749 | xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, | |
1750 | mem_flags); | |
1751 | if (!command->in_ctx) { | |
1752 | kfree(command); | |
1753 | return NULL; | |
1754 | } | |
06e18291 | 1755 | } |
913a8a34 SS |
1756 | |
1757 | if (allocate_completion) { | |
1758 | command->completion = | |
1759 | kzalloc(sizeof(struct completion), mem_flags); | |
1760 | if (!command->completion) { | |
1761 | xhci_free_container_ctx(xhci, command->in_ctx); | |
06e18291 | 1762 | kfree(command); |
913a8a34 SS |
1763 | return NULL; |
1764 | } | |
1765 | init_completion(command->completion); | |
1766 | } | |
1767 | ||
1768 | command->status = 0; | |
1769 | INIT_LIST_HEAD(&command->cmd_list); | |
1770 | return command; | |
1771 | } | |
1772 | ||
8e51adcc AX |
1773 | void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv) |
1774 | { | |
2ffdea25 AX |
1775 | if (urb_priv) { |
1776 | kfree(urb_priv->td[0]); | |
1777 | kfree(urb_priv); | |
8e51adcc | 1778 | } |
8e51adcc AX |
1779 | } |
1780 | ||
913a8a34 SS |
1781 | void xhci_free_command(struct xhci_hcd *xhci, |
1782 | struct xhci_command *command) | |
1783 | { | |
1784 | xhci_free_container_ctx(xhci, | |
1785 | command->in_ctx); | |
1786 | kfree(command->completion); | |
1787 | kfree(command); | |
1788 | } | |
1789 | ||
66d4eadd SS |
1790 | void xhci_mem_cleanup(struct xhci_hcd *xhci) |
1791 | { | |
0ebbab37 | 1792 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
9574323c | 1793 | struct dev_info *dev_info, *next; |
f8a9e72d ON |
1794 | struct list_head *tt_list_head; |
1795 | struct list_head *tt; | |
1796 | struct list_head *endpoints; | |
1797 | struct list_head *ep, *q; | |
1798 | struct xhci_tt_bw_info *tt_info; | |
1799 | struct xhci_interval_bw_table *bwt; | |
1800 | struct xhci_virt_ep *virt_ep; | |
1801 | ||
9574323c | 1802 | unsigned long flags; |
0ebbab37 | 1803 | int size; |
3ffbba95 | 1804 | int i; |
0ebbab37 SS |
1805 | |
1806 | /* Free the Event Ring Segment Table and the actual Event Ring */ | |
0ebbab37 SS |
1807 | size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries); |
1808 | if (xhci->erst.entries) | |
22d45f01 | 1809 | dma_free_coherent(&pdev->dev, size, |
0ebbab37 SS |
1810 | xhci->erst.entries, xhci->erst.erst_dma_addr); |
1811 | xhci->erst.entries = NULL; | |
1812 | xhci_dbg(xhci, "Freed ERST\n"); | |
1813 | if (xhci->event_ring) | |
1814 | xhci_ring_free(xhci, xhci->event_ring); | |
1815 | xhci->event_ring = NULL; | |
1816 | xhci_dbg(xhci, "Freed event ring\n"); | |
1817 | ||
33b2831a | 1818 | xhci->cmd_ring_reserved_trbs = 0; |
0ebbab37 SS |
1819 | if (xhci->cmd_ring) |
1820 | xhci_ring_free(xhci, xhci->cmd_ring); | |
1821 | xhci->cmd_ring = NULL; | |
1822 | xhci_dbg(xhci, "Freed command ring\n"); | |
3ffbba95 SS |
1823 | |
1824 | for (i = 1; i < MAX_HC_SLOTS; ++i) | |
1825 | xhci_free_virt_device(xhci, i); | |
1826 | ||
0ebbab37 SS |
1827 | if (xhci->segment_pool) |
1828 | dma_pool_destroy(xhci->segment_pool); | |
1829 | xhci->segment_pool = NULL; | |
1830 | xhci_dbg(xhci, "Freed segment pool\n"); | |
3ffbba95 SS |
1831 | |
1832 | if (xhci->device_pool) | |
1833 | dma_pool_destroy(xhci->device_pool); | |
1834 | xhci->device_pool = NULL; | |
1835 | xhci_dbg(xhci, "Freed device context pool\n"); | |
1836 | ||
8df75f42 SS |
1837 | if (xhci->small_streams_pool) |
1838 | dma_pool_destroy(xhci->small_streams_pool); | |
1839 | xhci->small_streams_pool = NULL; | |
1840 | xhci_dbg(xhci, "Freed small stream array pool\n"); | |
1841 | ||
1842 | if (xhci->medium_streams_pool) | |
1843 | dma_pool_destroy(xhci->medium_streams_pool); | |
1844 | xhci->medium_streams_pool = NULL; | |
1845 | xhci_dbg(xhci, "Freed medium stream array pool\n"); | |
1846 | ||
a74588f9 | 1847 | if (xhci->dcbaa) |
22d45f01 | 1848 | dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa), |
a74588f9 SS |
1849 | xhci->dcbaa, xhci->dcbaa->dma); |
1850 | xhci->dcbaa = NULL; | |
3ffbba95 | 1851 | |
5294bea4 | 1852 | scratchpad_free(xhci); |
da6699ce | 1853 | |
9574323c AX |
1854 | spin_lock_irqsave(&xhci->lock, flags); |
1855 | list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) { | |
1856 | list_del(&dev_info->list); | |
1857 | kfree(dev_info); | |
1858 | } | |
1859 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1860 | ||
f8a9e72d ON |
1861 | bwt = &xhci->rh_bw->bw_table; |
1862 | for (i = 0; i < XHCI_MAX_INTERVAL; i++) { | |
1863 | endpoints = &bwt->interval_bw[i].endpoints; | |
1864 | list_for_each_safe(ep, q, endpoints) { | |
1865 | virt_ep = list_entry(ep, struct xhci_virt_ep, bw_endpoint_list); | |
1866 | list_del(&virt_ep->bw_endpoint_list); | |
1867 | kfree(virt_ep); | |
1868 | } | |
1869 | } | |
1870 | ||
1871 | tt_list_head = &xhci->rh_bw->tts; | |
1872 | list_for_each_safe(tt, q, tt_list_head) { | |
1873 | tt_info = list_entry(tt, struct xhci_tt_bw_info, tt_list); | |
1874 | list_del(tt); | |
1875 | kfree(tt_info); | |
1876 | } | |
1877 | ||
da6699ce SS |
1878 | xhci->num_usb2_ports = 0; |
1879 | xhci->num_usb3_ports = 0; | |
f8a9e72d | 1880 | xhci->num_active_eps = 0; |
da6699ce SS |
1881 | kfree(xhci->usb2_ports); |
1882 | kfree(xhci->usb3_ports); | |
1883 | kfree(xhci->port_array); | |
839c817c | 1884 | kfree(xhci->rh_bw); |
da6699ce | 1885 | |
66d4eadd SS |
1886 | xhci->page_size = 0; |
1887 | xhci->page_shift = 0; | |
20b67cf5 | 1888 | xhci->bus_state[0].bus_suspended = 0; |
f6ff0ac8 | 1889 | xhci->bus_state[1].bus_suspended = 0; |
66d4eadd SS |
1890 | } |
1891 | ||
6648f29d SS |
1892 | static int xhci_test_trb_in_td(struct xhci_hcd *xhci, |
1893 | struct xhci_segment *input_seg, | |
1894 | union xhci_trb *start_trb, | |
1895 | union xhci_trb *end_trb, | |
1896 | dma_addr_t input_dma, | |
1897 | struct xhci_segment *result_seg, | |
1898 | char *test_name, int test_number) | |
1899 | { | |
1900 | unsigned long long start_dma; | |
1901 | unsigned long long end_dma; | |
1902 | struct xhci_segment *seg; | |
1903 | ||
1904 | start_dma = xhci_trb_virt_to_dma(input_seg, start_trb); | |
1905 | end_dma = xhci_trb_virt_to_dma(input_seg, end_trb); | |
1906 | ||
1907 | seg = trb_in_td(input_seg, start_trb, end_trb, input_dma); | |
1908 | if (seg != result_seg) { | |
1909 | xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n", | |
1910 | test_name, test_number); | |
1911 | xhci_warn(xhci, "Tested TRB math w/ seg %p and " | |
1912 | "input DMA 0x%llx\n", | |
1913 | input_seg, | |
1914 | (unsigned long long) input_dma); | |
1915 | xhci_warn(xhci, "starting TRB %p (0x%llx DMA), " | |
1916 | "ending TRB %p (0x%llx DMA)\n", | |
1917 | start_trb, start_dma, | |
1918 | end_trb, end_dma); | |
1919 | xhci_warn(xhci, "Expected seg %p, got seg %p\n", | |
1920 | result_seg, seg); | |
1921 | return -1; | |
1922 | } | |
1923 | return 0; | |
1924 | } | |
1925 | ||
1926 | /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */ | |
1927 | static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags) | |
1928 | { | |
1929 | struct { | |
1930 | dma_addr_t input_dma; | |
1931 | struct xhci_segment *result_seg; | |
1932 | } simple_test_vector [] = { | |
1933 | /* A zeroed DMA field should fail */ | |
1934 | { 0, NULL }, | |
1935 | /* One TRB before the ring start should fail */ | |
1936 | { xhci->event_ring->first_seg->dma - 16, NULL }, | |
1937 | /* One byte before the ring start should fail */ | |
1938 | { xhci->event_ring->first_seg->dma - 1, NULL }, | |
1939 | /* Starting TRB should succeed */ | |
1940 | { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg }, | |
1941 | /* Ending TRB should succeed */ | |
1942 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16, | |
1943 | xhci->event_ring->first_seg }, | |
1944 | /* One byte after the ring end should fail */ | |
1945 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL }, | |
1946 | /* One TRB after the ring end should fail */ | |
1947 | { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL }, | |
1948 | /* An address of all ones should fail */ | |
1949 | { (dma_addr_t) (~0), NULL }, | |
1950 | }; | |
1951 | struct { | |
1952 | struct xhci_segment *input_seg; | |
1953 | union xhci_trb *start_trb; | |
1954 | union xhci_trb *end_trb; | |
1955 | dma_addr_t input_dma; | |
1956 | struct xhci_segment *result_seg; | |
1957 | } complex_test_vector [] = { | |
1958 | /* Test feeding a valid DMA address from a different ring */ | |
1959 | { .input_seg = xhci->event_ring->first_seg, | |
1960 | .start_trb = xhci->event_ring->first_seg->trbs, | |
1961 | .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1962 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1963 | .result_seg = NULL, | |
1964 | }, | |
1965 | /* Test feeding a valid end TRB from a different ring */ | |
1966 | { .input_seg = xhci->event_ring->first_seg, | |
1967 | .start_trb = xhci->event_ring->first_seg->trbs, | |
1968 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1969 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1970 | .result_seg = NULL, | |
1971 | }, | |
1972 | /* Test feeding a valid start and end TRB from a different ring */ | |
1973 | { .input_seg = xhci->event_ring->first_seg, | |
1974 | .start_trb = xhci->cmd_ring->first_seg->trbs, | |
1975 | .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
1976 | .input_dma = xhci->cmd_ring->first_seg->dma, | |
1977 | .result_seg = NULL, | |
1978 | }, | |
1979 | /* TRB in this ring, but after this TD */ | |
1980 | { .input_seg = xhci->event_ring->first_seg, | |
1981 | .start_trb = &xhci->event_ring->first_seg->trbs[0], | |
1982 | .end_trb = &xhci->event_ring->first_seg->trbs[3], | |
1983 | .input_dma = xhci->event_ring->first_seg->dma + 4*16, | |
1984 | .result_seg = NULL, | |
1985 | }, | |
1986 | /* TRB in this ring, but before this TD */ | |
1987 | { .input_seg = xhci->event_ring->first_seg, | |
1988 | .start_trb = &xhci->event_ring->first_seg->trbs[3], | |
1989 | .end_trb = &xhci->event_ring->first_seg->trbs[6], | |
1990 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
1991 | .result_seg = NULL, | |
1992 | }, | |
1993 | /* TRB in this ring, but after this wrapped TD */ | |
1994 | { .input_seg = xhci->event_ring->first_seg, | |
1995 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
1996 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
1997 | .input_dma = xhci->event_ring->first_seg->dma + 2*16, | |
1998 | .result_seg = NULL, | |
1999 | }, | |
2000 | /* TRB in this ring, but before this wrapped TD */ | |
2001 | { .input_seg = xhci->event_ring->first_seg, | |
2002 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2003 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2004 | .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16, | |
2005 | .result_seg = NULL, | |
2006 | }, | |
2007 | /* TRB not in this ring, and we have a wrapped TD */ | |
2008 | { .input_seg = xhci->event_ring->first_seg, | |
2009 | .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3], | |
2010 | .end_trb = &xhci->event_ring->first_seg->trbs[1], | |
2011 | .input_dma = xhci->cmd_ring->first_seg->dma + 2*16, | |
2012 | .result_seg = NULL, | |
2013 | }, | |
2014 | }; | |
2015 | ||
2016 | unsigned int num_tests; | |
2017 | int i, ret; | |
2018 | ||
e10fa478 | 2019 | num_tests = ARRAY_SIZE(simple_test_vector); |
6648f29d SS |
2020 | for (i = 0; i < num_tests; i++) { |
2021 | ret = xhci_test_trb_in_td(xhci, | |
2022 | xhci->event_ring->first_seg, | |
2023 | xhci->event_ring->first_seg->trbs, | |
2024 | &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1], | |
2025 | simple_test_vector[i].input_dma, | |
2026 | simple_test_vector[i].result_seg, | |
2027 | "Simple", i); | |
2028 | if (ret < 0) | |
2029 | return ret; | |
2030 | } | |
2031 | ||
e10fa478 | 2032 | num_tests = ARRAY_SIZE(complex_test_vector); |
6648f29d SS |
2033 | for (i = 0; i < num_tests; i++) { |
2034 | ret = xhci_test_trb_in_td(xhci, | |
2035 | complex_test_vector[i].input_seg, | |
2036 | complex_test_vector[i].start_trb, | |
2037 | complex_test_vector[i].end_trb, | |
2038 | complex_test_vector[i].input_dma, | |
2039 | complex_test_vector[i].result_seg, | |
2040 | "Complex", i); | |
2041 | if (ret < 0) | |
2042 | return ret; | |
2043 | } | |
2044 | xhci_dbg(xhci, "TRB math tests passed.\n"); | |
2045 | return 0; | |
2046 | } | |
2047 | ||
257d585a SS |
2048 | static void xhci_set_hc_event_deq(struct xhci_hcd *xhci) |
2049 | { | |
2050 | u64 temp; | |
2051 | dma_addr_t deq; | |
2052 | ||
2053 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2054 | xhci->event_ring->dequeue); | |
2055 | if (deq == 0 && !in_interrupt()) | |
2056 | xhci_warn(xhci, "WARN something wrong with SW event ring " | |
2057 | "dequeue ptr.\n"); | |
2058 | /* Update HC event ring dequeue pointer */ | |
2059 | temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
2060 | temp &= ERST_PTR_MASK; | |
2061 | /* Don't clear the EHB bit (which is RW1C) because | |
2062 | * there might be more events to service. | |
2063 | */ | |
2064 | temp &= ~ERST_EHB; | |
2065 | xhci_dbg(xhci, "// Write event ring dequeue pointer, " | |
2066 | "preserving EHB bit\n"); | |
2067 | xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, | |
2068 | &xhci->ir_set->erst_dequeue); | |
2069 | } | |
2070 | ||
da6699ce | 2071 | static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports, |
28ccd296 | 2072 | __le32 __iomem *addr, u8 major_revision) |
da6699ce SS |
2073 | { |
2074 | u32 temp, port_offset, port_count; | |
2075 | int i; | |
2076 | ||
2077 | if (major_revision > 0x03) { | |
2078 | xhci_warn(xhci, "Ignoring unknown port speed, " | |
2079 | "Ext Cap %p, revision = 0x%x\n", | |
2080 | addr, major_revision); | |
2081 | /* Ignoring port protocol we can't understand. FIXME */ | |
2082 | return; | |
2083 | } | |
2084 | ||
2085 | /* Port offset and count in the third dword, see section 7.2 */ | |
2086 | temp = xhci_readl(xhci, addr + 2); | |
2087 | port_offset = XHCI_EXT_PORT_OFF(temp); | |
2088 | port_count = XHCI_EXT_PORT_COUNT(temp); | |
2089 | xhci_dbg(xhci, "Ext Cap %p, port offset = %u, " | |
2090 | "count = %u, revision = 0x%x\n", | |
2091 | addr, port_offset, port_count, major_revision); | |
2092 | /* Port count includes the current port offset */ | |
2093 | if (port_offset == 0 || (port_offset + port_count - 1) > num_ports) | |
2094 | /* WTF? "Valid values are ‘1’ to MaxPorts" */ | |
2095 | return; | |
fc71ff75 AX |
2096 | |
2097 | /* Check the host's USB2 LPM capability */ | |
2098 | if ((xhci->hci_version == 0x96) && (major_revision != 0x03) && | |
2099 | (temp & XHCI_L1C)) { | |
2100 | xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n"); | |
2101 | xhci->sw_lpm_support = 1; | |
2102 | } | |
2103 | ||
2104 | if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) { | |
2105 | xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n"); | |
2106 | xhci->sw_lpm_support = 1; | |
2107 | if (temp & XHCI_HLC) { | |
2108 | xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n"); | |
2109 | xhci->hw_lpm_support = 1; | |
2110 | } | |
2111 | } | |
2112 | ||
da6699ce SS |
2113 | port_offset--; |
2114 | for (i = port_offset; i < (port_offset + port_count); i++) { | |
2115 | /* Duplicate entry. Ignore the port if the revisions differ. */ | |
2116 | if (xhci->port_array[i] != 0) { | |
2117 | xhci_warn(xhci, "Duplicate port entry, Ext Cap %p," | |
2118 | " port %u\n", addr, i); | |
2119 | xhci_warn(xhci, "Port was marked as USB %u, " | |
2120 | "duplicated as USB %u\n", | |
2121 | xhci->port_array[i], major_revision); | |
2122 | /* Only adjust the roothub port counts if we haven't | |
2123 | * found a similar duplicate. | |
2124 | */ | |
2125 | if (xhci->port_array[i] != major_revision && | |
22e04870 | 2126 | xhci->port_array[i] != DUPLICATE_ENTRY) { |
da6699ce SS |
2127 | if (xhci->port_array[i] == 0x03) |
2128 | xhci->num_usb3_ports--; | |
2129 | else | |
2130 | xhci->num_usb2_ports--; | |
22e04870 | 2131 | xhci->port_array[i] = DUPLICATE_ENTRY; |
da6699ce SS |
2132 | } |
2133 | /* FIXME: Should we disable the port? */ | |
f8bbeabc | 2134 | continue; |
da6699ce SS |
2135 | } |
2136 | xhci->port_array[i] = major_revision; | |
2137 | if (major_revision == 0x03) | |
2138 | xhci->num_usb3_ports++; | |
2139 | else | |
2140 | xhci->num_usb2_ports++; | |
2141 | } | |
2142 | /* FIXME: Should we disable ports not in the Extended Capabilities? */ | |
2143 | } | |
2144 | ||
2145 | /* | |
2146 | * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that | |
2147 | * specify what speeds each port is supposed to be. We can't count on the port | |
2148 | * speed bits in the PORTSC register being correct until a device is connected, | |
2149 | * but we need to set up the two fake roothubs with the correct number of USB | |
2150 | * 3.0 and USB 2.0 ports at host controller initialization time. | |
2151 | */ | |
2152 | static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags) | |
2153 | { | |
28ccd296 | 2154 | __le32 __iomem *addr; |
da6699ce SS |
2155 | u32 offset; |
2156 | unsigned int num_ports; | |
2e27980e | 2157 | int i, j, port_index; |
da6699ce SS |
2158 | |
2159 | addr = &xhci->cap_regs->hcc_params; | |
2160 | offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr)); | |
2161 | if (offset == 0) { | |
2162 | xhci_err(xhci, "No Extended Capability registers, " | |
2163 | "unable to set up roothub.\n"); | |
2164 | return -ENODEV; | |
2165 | } | |
2166 | ||
2167 | num_ports = HCS_MAX_PORTS(xhci->hcs_params1); | |
2168 | xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags); | |
2169 | if (!xhci->port_array) | |
2170 | return -ENOMEM; | |
2171 | ||
839c817c SS |
2172 | xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags); |
2173 | if (!xhci->rh_bw) | |
2174 | return -ENOMEM; | |
2e27980e SS |
2175 | for (i = 0; i < num_ports; i++) { |
2176 | struct xhci_interval_bw_table *bw_table; | |
2177 | ||
839c817c | 2178 | INIT_LIST_HEAD(&xhci->rh_bw[i].tts); |
2e27980e SS |
2179 | bw_table = &xhci->rh_bw[i].bw_table; |
2180 | for (j = 0; j < XHCI_MAX_INTERVAL; j++) | |
2181 | INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints); | |
2182 | } | |
839c817c | 2183 | |
da6699ce SS |
2184 | /* |
2185 | * For whatever reason, the first capability offset is from the | |
2186 | * capability register base, not from the HCCPARAMS register. | |
2187 | * See section 5.3.6 for offset calculation. | |
2188 | */ | |
2189 | addr = &xhci->cap_regs->hc_capbase + offset; | |
2190 | while (1) { | |
2191 | u32 cap_id; | |
2192 | ||
2193 | cap_id = xhci_readl(xhci, addr); | |
2194 | if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL) | |
2195 | xhci_add_in_port(xhci, num_ports, addr, | |
2196 | (u8) XHCI_EXT_PORT_MAJOR(cap_id)); | |
2197 | offset = XHCI_EXT_CAPS_NEXT(cap_id); | |
2198 | if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports) | |
2199 | == num_ports) | |
2200 | break; | |
2201 | /* | |
2202 | * Once you're into the Extended Capabilities, the offset is | |
2203 | * always relative to the register holding the offset. | |
2204 | */ | |
2205 | addr += offset; | |
2206 | } | |
2207 | ||
2208 | if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) { | |
2209 | xhci_warn(xhci, "No ports on the roothubs?\n"); | |
2210 | return -ENODEV; | |
2211 | } | |
2212 | xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n", | |
2213 | xhci->num_usb2_ports, xhci->num_usb3_ports); | |
d30b2a20 SS |
2214 | |
2215 | /* Place limits on the number of roothub ports so that the hub | |
2216 | * descriptors aren't longer than the USB core will allocate. | |
2217 | */ | |
2218 | if (xhci->num_usb3_ports > 15) { | |
2219 | xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n"); | |
2220 | xhci->num_usb3_ports = 15; | |
2221 | } | |
2222 | if (xhci->num_usb2_ports > USB_MAXCHILDREN) { | |
2223 | xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n", | |
2224 | USB_MAXCHILDREN); | |
2225 | xhci->num_usb2_ports = USB_MAXCHILDREN; | |
2226 | } | |
2227 | ||
da6699ce SS |
2228 | /* |
2229 | * Note we could have all USB 3.0 ports, or all USB 2.0 ports. | |
2230 | * Not sure how the USB core will handle a hub with no ports... | |
2231 | */ | |
2232 | if (xhci->num_usb2_ports) { | |
2233 | xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)* | |
2234 | xhci->num_usb2_ports, flags); | |
2235 | if (!xhci->usb2_ports) | |
2236 | return -ENOMEM; | |
2237 | ||
2238 | port_index = 0; | |
f8bbeabc SS |
2239 | for (i = 0; i < num_ports; i++) { |
2240 | if (xhci->port_array[i] == 0x03 || | |
2241 | xhci->port_array[i] == 0 || | |
22e04870 | 2242 | xhci->port_array[i] == DUPLICATE_ENTRY) |
f8bbeabc SS |
2243 | continue; |
2244 | ||
2245 | xhci->usb2_ports[port_index] = | |
2246 | &xhci->op_regs->port_status_base + | |
2247 | NUM_PORT_REGS*i; | |
2248 | xhci_dbg(xhci, "USB 2.0 port at index %u, " | |
2249 | "addr = %p\n", i, | |
2250 | xhci->usb2_ports[port_index]); | |
2251 | port_index++; | |
d30b2a20 SS |
2252 | if (port_index == xhci->num_usb2_ports) |
2253 | break; | |
f8bbeabc | 2254 | } |
da6699ce SS |
2255 | } |
2256 | if (xhci->num_usb3_ports) { | |
2257 | xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)* | |
2258 | xhci->num_usb3_ports, flags); | |
2259 | if (!xhci->usb3_ports) | |
2260 | return -ENOMEM; | |
2261 | ||
2262 | port_index = 0; | |
2263 | for (i = 0; i < num_ports; i++) | |
2264 | if (xhci->port_array[i] == 0x03) { | |
2265 | xhci->usb3_ports[port_index] = | |
2266 | &xhci->op_regs->port_status_base + | |
2267 | NUM_PORT_REGS*i; | |
2268 | xhci_dbg(xhci, "USB 3.0 port at index %u, " | |
2269 | "addr = %p\n", i, | |
2270 | xhci->usb3_ports[port_index]); | |
2271 | port_index++; | |
d30b2a20 SS |
2272 | if (port_index == xhci->num_usb3_ports) |
2273 | break; | |
da6699ce SS |
2274 | } |
2275 | } | |
2276 | return 0; | |
2277 | } | |
6648f29d | 2278 | |
66d4eadd SS |
2279 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) |
2280 | { | |
0ebbab37 SS |
2281 | dma_addr_t dma; |
2282 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
66d4eadd | 2283 | unsigned int val, val2; |
8e595a5d | 2284 | u64 val_64; |
0ebbab37 | 2285 | struct xhci_segment *seg; |
623bef9e | 2286 | u32 page_size, temp; |
66d4eadd SS |
2287 | int i; |
2288 | ||
2289 | page_size = xhci_readl(xhci, &xhci->op_regs->page_size); | |
2290 | xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size); | |
2291 | for (i = 0; i < 16; i++) { | |
2292 | if ((0x1 & page_size) != 0) | |
2293 | break; | |
2294 | page_size = page_size >> 1; | |
2295 | } | |
2296 | if (i < 16) | |
2297 | xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024); | |
2298 | else | |
2299 | xhci_warn(xhci, "WARN: no supported page size\n"); | |
2300 | /* Use 4K pages, since that's common and the minimum the HC supports */ | |
2301 | xhci->page_shift = 12; | |
2302 | xhci->page_size = 1 << xhci->page_shift; | |
2303 | xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024); | |
2304 | ||
2305 | /* | |
2306 | * Program the Number of Device Slots Enabled field in the CONFIG | |
2307 | * register with the max value of slots the HC can handle. | |
2308 | */ | |
2309 | val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1)); | |
2310 | xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n", | |
2311 | (unsigned int) val); | |
2312 | val2 = xhci_readl(xhci, &xhci->op_regs->config_reg); | |
2313 | val |= (val2 & ~HCS_SLOTS_MASK); | |
2314 | xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n", | |
2315 | (unsigned int) val); | |
2316 | xhci_writel(xhci, val, &xhci->op_regs->config_reg); | |
2317 | ||
a74588f9 SS |
2318 | /* |
2319 | * Section 5.4.8 - doorbell array must be | |
2320 | * "physically contiguous and 64-byte (cache line) aligned". | |
2321 | */ | |
22d45f01 SAS |
2322 | xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma, |
2323 | GFP_KERNEL); | |
a74588f9 SS |
2324 | if (!xhci->dcbaa) |
2325 | goto fail; | |
2326 | memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa)); | |
2327 | xhci->dcbaa->dma = dma; | |
700e2052 GKH |
2328 | xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n", |
2329 | (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa); | |
8e595a5d | 2330 | xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr); |
a74588f9 | 2331 | |
0ebbab37 SS |
2332 | /* |
2333 | * Initialize the ring segment pool. The ring must be a contiguous | |
2334 | * structure comprised of TRBs. The TRBs must be 16 byte aligned, | |
2335 | * however, the command ring segment needs 64-byte aligned segments, | |
2336 | * so we pick the greater alignment need. | |
2337 | */ | |
2338 | xhci->segment_pool = dma_pool_create("xHCI ring segments", dev, | |
2339 | SEGMENT_SIZE, 64, xhci->page_size); | |
d115b048 | 2340 | |
3ffbba95 | 2341 | /* See Table 46 and Note on Figure 55 */ |
3ffbba95 | 2342 | xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev, |
d115b048 | 2343 | 2112, 64, xhci->page_size); |
3ffbba95 | 2344 | if (!xhci->segment_pool || !xhci->device_pool) |
0ebbab37 SS |
2345 | goto fail; |
2346 | ||
8df75f42 SS |
2347 | /* Linear stream context arrays don't have any boundary restrictions, |
2348 | * and only need to be 16-byte aligned. | |
2349 | */ | |
2350 | xhci->small_streams_pool = | |
2351 | dma_pool_create("xHCI 256 byte stream ctx arrays", | |
2352 | dev, SMALL_STREAM_ARRAY_SIZE, 16, 0); | |
2353 | xhci->medium_streams_pool = | |
2354 | dma_pool_create("xHCI 1KB stream ctx arrays", | |
2355 | dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0); | |
2356 | /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE | |
22d45f01 | 2357 | * will be allocated with dma_alloc_coherent() |
8df75f42 SS |
2358 | */ |
2359 | ||
2360 | if (!xhci->small_streams_pool || !xhci->medium_streams_pool) | |
2361 | goto fail; | |
2362 | ||
0ebbab37 | 2363 | /* Set up the command ring to have one segments for now. */ |
186a7ef1 | 2364 | xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags); |
0ebbab37 SS |
2365 | if (!xhci->cmd_ring) |
2366 | goto fail; | |
700e2052 GKH |
2367 | xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring); |
2368 | xhci_dbg(xhci, "First segment DMA is 0x%llx\n", | |
2369 | (unsigned long long)xhci->cmd_ring->first_seg->dma); | |
0ebbab37 SS |
2370 | |
2371 | /* Set the address in the Command Ring Control register */ | |
8e595a5d SS |
2372 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
2373 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | | |
2374 | (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) | | |
0ebbab37 | 2375 | xhci->cmd_ring->cycle_state; |
8e595a5d SS |
2376 | xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val); |
2377 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); | |
0ebbab37 SS |
2378 | xhci_dbg_cmd_ptrs(xhci); |
2379 | ||
2380 | val = xhci_readl(xhci, &xhci->cap_regs->db_off); | |
2381 | val &= DBOFF_MASK; | |
2382 | xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x" | |
2383 | " from cap regs base addr\n", val); | |
c50a00f8 | 2384 | xhci->dba = (void __iomem *) xhci->cap_regs + val; |
0ebbab37 SS |
2385 | xhci_dbg_regs(xhci); |
2386 | xhci_print_run_regs(xhci); | |
2387 | /* Set ir_set to interrupt register set 0 */ | |
c50a00f8 | 2388 | xhci->ir_set = &xhci->run_regs->ir_set[0]; |
0ebbab37 SS |
2389 | |
2390 | /* | |
2391 | * Event ring setup: Allocate a normal ring, but also setup | |
2392 | * the event ring segment table (ERST). Section 4.9.3. | |
2393 | */ | |
2394 | xhci_dbg(xhci, "// Allocating event ring\n"); | |
186a7ef1 | 2395 | xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT, |
7e393a83 | 2396 | flags); |
0ebbab37 SS |
2397 | if (!xhci->event_ring) |
2398 | goto fail; | |
6648f29d SS |
2399 | if (xhci_check_trb_in_td_math(xhci, flags) < 0) |
2400 | goto fail; | |
0ebbab37 | 2401 | |
22d45f01 SAS |
2402 | xhci->erst.entries = dma_alloc_coherent(dev, |
2403 | sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma, | |
2404 | GFP_KERNEL); | |
0ebbab37 SS |
2405 | if (!xhci->erst.entries) |
2406 | goto fail; | |
700e2052 GKH |
2407 | xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n", |
2408 | (unsigned long long)dma); | |
0ebbab37 SS |
2409 | |
2410 | memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS); | |
2411 | xhci->erst.num_entries = ERST_NUM_SEGS; | |
2412 | xhci->erst.erst_dma_addr = dma; | |
700e2052 | 2413 | xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n", |
0ebbab37 | 2414 | xhci->erst.num_entries, |
700e2052 GKH |
2415 | xhci->erst.entries, |
2416 | (unsigned long long)xhci->erst.erst_dma_addr); | |
0ebbab37 SS |
2417 | |
2418 | /* set ring base address and size for each segment table entry */ | |
2419 | for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) { | |
2420 | struct xhci_erst_entry *entry = &xhci->erst.entries[val]; | |
28ccd296 ME |
2421 | entry->seg_addr = cpu_to_le64(seg->dma); |
2422 | entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT); | |
0ebbab37 SS |
2423 | entry->rsvd = 0; |
2424 | seg = seg->next; | |
2425 | } | |
2426 | ||
2427 | /* set ERST count with the number of entries in the segment table */ | |
2428 | val = xhci_readl(xhci, &xhci->ir_set->erst_size); | |
2429 | val &= ERST_SIZE_MASK; | |
2430 | val |= ERST_NUM_SEGS; | |
2431 | xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n", | |
2432 | val); | |
2433 | xhci_writel(xhci, val, &xhci->ir_set->erst_size); | |
2434 | ||
2435 | xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n"); | |
2436 | /* set the segment table base address */ | |
700e2052 GKH |
2437 | xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n", |
2438 | (unsigned long long)xhci->erst.erst_dma_addr); | |
8e595a5d SS |
2439 | val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
2440 | val_64 &= ERST_PTR_MASK; | |
2441 | val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK); | |
2442 | xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base); | |
0ebbab37 SS |
2443 | |
2444 | /* Set the event ring dequeue address */ | |
23e3be11 | 2445 | xhci_set_hc_event_deq(xhci); |
0ebbab37 | 2446 | xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n"); |
09ece30e | 2447 | xhci_print_ir_set(xhci, 0); |
0ebbab37 SS |
2448 | |
2449 | /* | |
2450 | * XXX: Might need to set the Interrupter Moderation Register to | |
2451 | * something other than the default (~1ms minimum between interrupts). | |
2452 | * See section 5.5.1.2. | |
2453 | */ | |
3ffbba95 SS |
2454 | init_completion(&xhci->addr_dev); |
2455 | for (i = 0; i < MAX_HC_SLOTS; ++i) | |
326b4810 | 2456 | xhci->devs[i] = NULL; |
f6ff0ac8 | 2457 | for (i = 0; i < USB_MAXCHILDREN; ++i) { |
20b67cf5 | 2458 | xhci->bus_state[0].resume_done[i] = 0; |
f6ff0ac8 SS |
2459 | xhci->bus_state[1].resume_done[i] = 0; |
2460 | } | |
66d4eadd | 2461 | |
254c80a3 JY |
2462 | if (scratchpad_alloc(xhci, flags)) |
2463 | goto fail; | |
da6699ce SS |
2464 | if (xhci_setup_port_arrays(xhci, flags)) |
2465 | goto fail; | |
254c80a3 | 2466 | |
9574323c AX |
2467 | INIT_LIST_HEAD(&xhci->lpm_failed_devs); |
2468 | ||
623bef9e SS |
2469 | /* Enable USB 3.0 device notifications for function remote wake, which |
2470 | * is necessary for allowing USB 3.0 devices to do remote wakeup from | |
2471 | * U3 (device suspend). | |
2472 | */ | |
2473 | temp = xhci_readl(xhci, &xhci->op_regs->dev_notification); | |
2474 | temp &= ~DEV_NOTE_MASK; | |
2475 | temp |= DEV_NOTE_FWAKE; | |
2476 | xhci_writel(xhci, temp, &xhci->op_regs->dev_notification); | |
2477 | ||
66d4eadd | 2478 | return 0; |
254c80a3 | 2479 | |
66d4eadd SS |
2480 | fail: |
2481 | xhci_warn(xhci, "Couldn't initialize memory\n"); | |
159e1fcc SS |
2482 | xhci_halt(xhci); |
2483 | xhci_reset(xhci); | |
66d4eadd SS |
2484 | xhci_mem_cleanup(xhci); |
2485 | return -ENOMEM; | |
2486 | } |