Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
0f2a7930 SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
0f2a7930 SS |
9 | */ |
10 | ||
ddba5cd0 MN |
11 | |
12 | #include <linux/slab.h> | |
0f2a7930 SS |
13 | #include <asm/unaligned.h> |
14 | ||
15 | #include "xhci.h" | |
4bdfe4c3 | 16 | #include "xhci-trace.h" |
0f2a7930 | 17 | |
9777e3ce AX |
18 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
19 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ | |
20 | PORT_RC | PORT_PLC | PORT_PE) | |
21 | ||
5693e0b7 MN |
22 | /* USB 3 BOS descriptor and a capability descriptors, combined. |
23 | * Fields will be adjusted and added later in xhci_create_usb3_bos_desc() | |
24 | */ | |
48e82361 SS |
25 | static u8 usb_bos_descriptor [] = { |
26 | USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ | |
27 | USB_DT_BOS, /* __u8 bDescriptorType */ | |
28 | 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ | |
29 | 0x1, /* __u8 bNumDeviceCaps */ | |
5693e0b7 | 30 | /* First device capability, SuperSpeed */ |
48e82361 SS |
31 | USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ |
32 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ | |
33 | USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ | |
34 | 0x00, /* bmAttributes, LTM off by default */ | |
35 | USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ | |
36 | 0x03, /* bFunctionalitySupport, | |
37 | USB 3.0 speed only */ | |
38 | 0x00, /* bU1DevExitLat, set later. */ | |
5693e0b7 MN |
39 | 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */ |
40 | /* Second device capability, SuperSpeedPlus */ | |
5da665fc | 41 | 0x1c, /* bLength 28, will be adjusted later */ |
5693e0b7 MN |
42 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ |
43 | USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */ | |
44 | 0x00, /* bReserved 0 */ | |
5da665fc MN |
45 | 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */ |
46 | 0x01, 0x00, /* wFunctionalitySupport */ | |
5693e0b7 | 47 | 0x00, 0x00, /* wReserved 0 */ |
5da665fc MN |
48 | /* Default Sublink Speed Attributes, overwrite if custom PSI exists */ |
49 | 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */ | |
50 | 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */ | |
51 | 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */ | |
52 | 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */ | |
48e82361 SS |
53 | }; |
54 | ||
5693e0b7 MN |
55 | static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf, |
56 | u16 wLength) | |
57 | { | |
58 | int i, ssa_count; | |
59 | u32 temp; | |
60 | u16 desc_size, ssp_cap_size, ssa_size = 0; | |
61 | bool usb3_1 = false; | |
62 | ||
63 | desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
64 | ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size; | |
65 | ||
66 | /* does xhci support USB 3.1 Enhanced SuperSpeed */ | |
5da665fc MN |
67 | if (xhci->usb3_rhub.min_rev >= 0x01) { |
68 | /* does xhci provide a PSI table for SSA speed attributes? */ | |
69 | if (xhci->usb3_rhub.psi_count) { | |
70 | /* two SSA entries for each unique PSI ID, RX and TX */ | |
71 | ssa_count = xhci->usb3_rhub.psi_uid_count * 2; | |
72 | ssa_size = ssa_count * sizeof(u32); | |
73 | ssp_cap_size -= 16; /* skip copying the default SSA */ | |
74 | } | |
5693e0b7 MN |
75 | desc_size += ssp_cap_size; |
76 | usb3_1 = true; | |
77 | } | |
78 | memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength)); | |
79 | ||
80 | if (usb3_1) { | |
81 | /* modify bos descriptor bNumDeviceCaps and wTotalLength */ | |
82 | buf[4] += 1; | |
83 | put_unaligned_le16(desc_size + ssa_size, &buf[2]); | |
84 | } | |
85 | ||
86 | if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) | |
87 | return wLength; | |
88 | ||
89 | /* Indicate whether the host has LTM support. */ | |
90 | temp = readl(&xhci->cap_regs->hcc_params); | |
91 | if (HCC_LTC(temp)) | |
92 | buf[8] |= USB_LTM_SUPPORT; | |
93 | ||
94 | /* Set the U1 and U2 exit latencies. */ | |
95 | if ((xhci->quirks & XHCI_LPM_SUPPORT)) { | |
96 | temp = readl(&xhci->cap_regs->hcs_params3); | |
97 | buf[12] = HCS_U1_LATENCY(temp); | |
98 | put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); | |
99 | } | |
100 | ||
5da665fc MN |
101 | /* If PSI table exists, add the custom speed attributes from it */ |
102 | if (usb3_1 && xhci->usb3_rhub.psi_count) { | |
7bea22b1 | 103 | u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp; |
5693e0b7 MN |
104 | int offset; |
105 | ||
106 | ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
107 | ||
108 | if (wLength < desc_size) | |
109 | return wLength; | |
110 | buf[ssp_cap_base] = ssp_cap_size + ssa_size; | |
111 | ||
112 | /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */ | |
113 | bm_attrib = (ssa_count - 1) & 0x1f; | |
114 | bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5; | |
115 | put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]); | |
116 | ||
117 | if (wLength < desc_size + ssa_size) | |
118 | return wLength; | |
119 | /* | |
120 | * Create the Sublink Speed Attributes (SSA) array. | |
121 | * The xhci PSI field and USB 3.1 SSA fields are very similar, | |
122 | * but link type bits 7:6 differ for values 01b and 10b. | |
123 | * xhci has also only one PSI entry for a symmetric link when | |
124 | * USB 3.1 requires two SSA entries (RX and TX) for every link | |
125 | */ | |
126 | offset = desc_size; | |
127 | for (i = 0; i < xhci->usb3_rhub.psi_count; i++) { | |
128 | psi = xhci->usb3_rhub.psi[i]; | |
129 | psi &= ~USB_SSP_SUBLINK_SPEED_RSVD; | |
7bea22b1 MN |
130 | psi_exp = XHCI_EXT_PORT_PSIE(psi); |
131 | psi_mant = XHCI_EXT_PORT_PSIM(psi); | |
132 | ||
133 | /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */ | |
134 | for (; psi_exp < 3; psi_exp++) | |
135 | psi_mant /= 1000; | |
136 | if (psi_mant >= 10) | |
137 | psi |= BIT(14); | |
138 | ||
5693e0b7 MN |
139 | if ((psi & PLT_MASK) == PLT_SYM) { |
140 | /* Symmetric, create SSA RX and TX from one PSI entry */ | |
141 | put_unaligned_le32(psi, &buf[offset]); | |
142 | psi |= 1 << 7; /* turn entry to TX */ | |
143 | offset += 4; | |
144 | if (offset >= desc_size + ssa_size) | |
145 | return desc_size + ssa_size; | |
146 | } else if ((psi & PLT_MASK) == PLT_ASYM_RX) { | |
147 | /* Asymetric RX, flip bits 7:6 for SSA */ | |
148 | psi ^= PLT_MASK; | |
149 | } | |
150 | put_unaligned_le32(psi, &buf[offset]); | |
151 | offset += 4; | |
152 | if (offset >= desc_size + ssa_size) | |
153 | return desc_size + ssa_size; | |
154 | } | |
155 | } | |
156 | /* ssa_size is 0 for other than usb 3.1 hosts */ | |
157 | return desc_size + ssa_size; | |
158 | } | |
48e82361 | 159 | |
4bbb0ace SS |
160 | static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, |
161 | struct usb_hub_descriptor *desc, int ports) | |
0f2a7930 | 162 | { |
0f2a7930 SS |
163 | u16 temp; |
164 | ||
0f2a7930 SS |
165 | desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ |
166 | desc->bHubContrCurrent = 0; | |
167 | ||
168 | desc->bNbrPorts = ports; | |
0f2a7930 | 169 | temp = 0; |
c8421147 | 170 | /* Bits 1:0 - support per-port power switching, or power always on */ |
0f2a7930 | 171 | if (HCC_PPC(xhci->hcc_params)) |
c8421147 | 172 | temp |= HUB_CHAR_INDV_PORT_LPSM; |
0f2a7930 | 173 | else |
c8421147 | 174 | temp |= HUB_CHAR_NO_LPSM; |
0f2a7930 SS |
175 | /* Bit 2 - root hubs are not part of a compound device */ |
176 | /* Bits 4:3 - individual port over current protection */ | |
c8421147 | 177 | temp |= HUB_CHAR_INDV_PORT_OCPM; |
0f2a7930 SS |
178 | /* Bits 6:5 - no TTs in root ports */ |
179 | /* Bit 7 - no port indicators */ | |
28ccd296 | 180 | desc->wHubCharacteristics = cpu_to_le16(temp); |
0f2a7930 SS |
181 | } |
182 | ||
4bbb0ace SS |
183 | /* Fill in the USB 2.0 roothub descriptor */ |
184 | static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
185 | struct usb_hub_descriptor *desc) | |
186 | { | |
187 | int ports; | |
188 | u16 temp; | |
189 | __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; | |
190 | u32 portsc; | |
191 | unsigned int i; | |
e740b019 | 192 | struct xhci_hub *rhub; |
4bbb0ace | 193 | |
e740b019 MN |
194 | rhub = &xhci->usb2_rhub; |
195 | ports = rhub->num_ports; | |
4bbb0ace | 196 | xhci_common_hub_descriptor(xhci, desc, ports); |
c8421147 | 197 | desc->bDescriptorType = USB_DT_HUB; |
4bbb0ace | 198 | temp = 1 + (ports / 8); |
c8421147 | 199 | desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; |
4bbb0ace SS |
200 | |
201 | /* The Device Removable bits are reported on a byte granularity. | |
202 | * If the port doesn't exist within that byte, the bit is set to 0. | |
203 | */ | |
204 | memset(port_removable, 0, sizeof(port_removable)); | |
205 | for (i = 0; i < ports; i++) { | |
e740b019 | 206 | portsc = readl(rhub->ports[i]->addr); |
4bbb0ace SS |
207 | /* If a device is removable, PORTSC reports a 0, same as in the |
208 | * hub descriptor DeviceRemovable bits. | |
209 | */ | |
210 | if (portsc & PORT_DEV_REMOVE) | |
211 | /* This math is hairy because bit 0 of DeviceRemovable | |
212 | * is reserved, and bit 1 is for port 1, etc. | |
213 | */ | |
214 | port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); | |
215 | } | |
216 | ||
217 | /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN | |
218 | * ports on it. The USB 2.0 specification says that there are two | |
219 | * variable length fields at the end of the hub descriptor: | |
220 | * DeviceRemovable and PortPwrCtrlMask. But since we can have less than | |
221 | * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array | |
222 | * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to | |
223 | * 0xFF, so we initialize the both arrays (DeviceRemovable and | |
224 | * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each | |
225 | * set of ports that actually exist. | |
226 | */ | |
227 | memset(desc->u.hs.DeviceRemovable, 0xff, | |
228 | sizeof(desc->u.hs.DeviceRemovable)); | |
229 | memset(desc->u.hs.PortPwrCtrlMask, 0xff, | |
230 | sizeof(desc->u.hs.PortPwrCtrlMask)); | |
231 | ||
232 | for (i = 0; i < (ports + 1 + 7) / 8; i++) | |
233 | memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], | |
234 | sizeof(__u8)); | |
235 | } | |
236 | ||
237 | /* Fill in the USB 3.0 roothub descriptor */ | |
238 | static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
239 | struct usb_hub_descriptor *desc) | |
240 | { | |
241 | int ports; | |
242 | u16 port_removable; | |
243 | u32 portsc; | |
244 | unsigned int i; | |
e740b019 | 245 | struct xhci_hub *rhub; |
4bbb0ace | 246 | |
e740b019 MN |
247 | rhub = &xhci->usb3_rhub; |
248 | ports = rhub->num_ports; | |
4bbb0ace | 249 | xhci_common_hub_descriptor(xhci, desc, ports); |
c8421147 AD |
250 | desc->bDescriptorType = USB_DT_SS_HUB; |
251 | desc->bDescLength = USB_DT_SS_HUB_SIZE; | |
4bbb0ace SS |
252 | |
253 | /* header decode latency should be zero for roothubs, | |
254 | * see section 4.23.5.2. | |
255 | */ | |
256 | desc->u.ss.bHubHdrDecLat = 0; | |
257 | desc->u.ss.wHubDelay = 0; | |
258 | ||
259 | port_removable = 0; | |
260 | /* bit 0 is reserved, bit 1 is for port 1, etc. */ | |
261 | for (i = 0; i < ports; i++) { | |
e740b019 | 262 | portsc = readl(rhub->ports[i]->addr); |
4bbb0ace SS |
263 | if (portsc & PORT_DEV_REMOVE) |
264 | port_removable |= 1 << (i + 1); | |
265 | } | |
27c411c9 LT |
266 | |
267 | desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); | |
4bbb0ace SS |
268 | } |
269 | ||
270 | static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
271 | struct usb_hub_descriptor *desc) | |
272 | { | |
273 | ||
b50107bb | 274 | if (hcd->speed >= HCD_USB3) |
4bbb0ace SS |
275 | xhci_usb3_hub_descriptor(hcd, xhci, desc); |
276 | else | |
277 | xhci_usb2_hub_descriptor(hcd, xhci, desc); | |
278 | ||
279 | } | |
280 | ||
0f2a7930 SS |
281 | static unsigned int xhci_port_speed(unsigned int port_status) |
282 | { | |
283 | if (DEV_LOWSPEED(port_status)) | |
288ead45 | 284 | return USB_PORT_STAT_LOW_SPEED; |
0f2a7930 | 285 | if (DEV_HIGHSPEED(port_status)) |
288ead45 | 286 | return USB_PORT_STAT_HIGH_SPEED; |
0f2a7930 SS |
287 | /* |
288 | * FIXME: Yes, we should check for full speed, but the core uses that as | |
289 | * a default in portspeed() in usb/core/hub.c (which is the only place | |
288ead45 | 290 | * USB_PORT_STAT_*_SPEED is used). |
0f2a7930 SS |
291 | */ |
292 | return 0; | |
293 | } | |
294 | ||
295 | /* | |
296 | * These bits are Read Only (RO) and should be saved and written to the | |
297 | * registers: 0, 3, 10:13, 30 | |
298 | * connect status, over-current status, port speed, and device removable. | |
299 | * connect status and port speed are also sticky - meaning they're in | |
300 | * the AUX well and they aren't changed by a hot, warm, or cold reset. | |
301 | */ | |
302 | #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) | |
303 | /* | |
304 | * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: | |
305 | * bits 5:8, 9, 14:15, 25:27 | |
306 | * link state, port power, port indicator state, "wake on" enable state | |
307 | */ | |
308 | #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) | |
309 | /* | |
310 | * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: | |
311 | * bit 4 (port reset) | |
312 | */ | |
313 | #define XHCI_PORT_RW1S ((1<<4)) | |
314 | /* | |
315 | * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: | |
316 | * bits 1, 17, 18, 19, 20, 21, 22, 23 | |
317 | * port enable/disable, and | |
318 | * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), | |
319 | * over-current, reset, link state, and L1 change | |
320 | */ | |
321 | #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) | |
322 | /* | |
323 | * Bit 16 is RW, and writing a '1' to it causes the link state control to be | |
324 | * latched in | |
325 | */ | |
326 | #define XHCI_PORT_RW ((1<<16)) | |
327 | /* | |
328 | * These bits are Reserved Zero (RsvdZ) and zero should be written to them: | |
329 | * bits 2, 24, 28:31 | |
330 | */ | |
331 | #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) | |
332 | ||
333 | /* | |
334 | * Given a port state, this function returns a value that would result in the | |
335 | * port being in the same state, if the value was written to the port status | |
336 | * control register. | |
337 | * Save Read Only (RO) bits and save read/write bits where | |
338 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). | |
339 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. | |
340 | */ | |
56192531 | 341 | u32 xhci_port_state_to_neutral(u32 state) |
0f2a7930 SS |
342 | { |
343 | /* Save read-only status and port state */ | |
344 | return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); | |
345 | } | |
346 | ||
be88fe4f AX |
347 | /* |
348 | * find slot id based on port number. | |
f6ff0ac8 | 349 | * @port: The one-based port number from one of the two split roothubs. |
be88fe4f | 350 | */ |
5233630f SS |
351 | int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
352 | u16 port) | |
be88fe4f AX |
353 | { |
354 | int slot_id; | |
355 | int i; | |
f6ff0ac8 | 356 | enum usb_device_speed speed; |
be88fe4f AX |
357 | |
358 | slot_id = 0; | |
359 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
2278446e | 360 | if (!xhci->devs[i] || !xhci->devs[i]->udev) |
be88fe4f | 361 | continue; |
f6ff0ac8 | 362 | speed = xhci->devs[i]->udev->speed; |
b50107bb | 363 | if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3)) |
fe30182c | 364 | && xhci->devs[i]->fake_port == port) { |
be88fe4f AX |
365 | slot_id = i; |
366 | break; | |
367 | } | |
368 | } | |
369 | ||
370 | return slot_id; | |
371 | } | |
372 | ||
373 | /* | |
374 | * Stop device | |
375 | * It issues stop endpoint command for EP 0 to 30. And wait the last command | |
376 | * to complete. | |
377 | * suspend will set to 1, if suspend bit need to set in command. | |
378 | */ | |
379 | static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) | |
380 | { | |
381 | struct xhci_virt_device *virt_dev; | |
382 | struct xhci_command *cmd; | |
383 | unsigned long flags; | |
be88fe4f AX |
384 | int ret; |
385 | int i; | |
386 | ||
387 | ret = 0; | |
388 | virt_dev = xhci->devs[slot_id]; | |
88716a93 JL |
389 | if (!virt_dev) |
390 | return -ENODEV; | |
391 | ||
a711edee FB |
392 | trace_xhci_stop_device(virt_dev); |
393 | ||
103afda0 | 394 | cmd = xhci_alloc_command(xhci, true, GFP_NOIO); |
74e0b564 | 395 | if (!cmd) |
be88fe4f | 396 | return -ENOMEM; |
be88fe4f AX |
397 | |
398 | spin_lock_irqsave(&xhci->lock, flags); | |
399 | for (i = LAST_EP_INDEX; i > 0; i--) { | |
ddba5cd0 | 400 | if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { |
28a2369f | 401 | struct xhci_ep_ctx *ep_ctx; |
ddba5cd0 | 402 | struct xhci_command *command; |
28a2369f SS |
403 | |
404 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i); | |
405 | ||
406 | /* Check ep is running, required by AMD SNPS 3.1 xHC */ | |
407 | if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING) | |
408 | continue; | |
409 | ||
103afda0 | 410 | command = xhci_alloc_command(xhci, false, GFP_NOWAIT); |
ddba5cd0 MN |
411 | if (!command) { |
412 | spin_unlock_irqrestore(&xhci->lock, flags); | |
b3207c65 MR |
413 | ret = -ENOMEM; |
414 | goto cmd_cleanup; | |
415 | } | |
416 | ||
417 | ret = xhci_queue_stop_endpoint(xhci, command, slot_id, | |
418 | i, suspend); | |
419 | if (ret) { | |
420 | spin_unlock_irqrestore(&xhci->lock, flags); | |
421 | xhci_free_command(xhci, command); | |
422 | goto cmd_cleanup; | |
ddba5cd0 | 423 | } |
ddba5cd0 | 424 | } |
be88fe4f | 425 | } |
b3207c65 MR |
426 | ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); |
427 | if (ret) { | |
428 | spin_unlock_irqrestore(&xhci->lock, flags); | |
429 | goto cmd_cleanup; | |
430 | } | |
431 | ||
be88fe4f AX |
432 | xhci_ring_cmd_db(xhci); |
433 | spin_unlock_irqrestore(&xhci->lock, flags); | |
434 | ||
435 | /* Wait for last stop endpoint command to finish */ | |
c311e391 MN |
436 | wait_for_completion(cmd->completion); |
437 | ||
0b7c105a | 438 | if (cmd->status == COMP_COMMAND_ABORTED || |
604d02a2 | 439 | cmd->status == COMP_COMMAND_RING_STOPPED) { |
c311e391 | 440 | xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); |
be88fe4f | 441 | ret = -ETIME; |
be88fe4f | 442 | } |
b3207c65 MR |
443 | |
444 | cmd_cleanup: | |
be88fe4f AX |
445 | xhci_free_command(xhci, cmd); |
446 | return ret; | |
447 | } | |
448 | ||
449 | /* | |
450 | * Ring device, it rings the all doorbells unconditionally. | |
451 | */ | |
56192531 | 452 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) |
be88fe4f | 453 | { |
b7f9696b HG |
454 | int i, s; |
455 | struct xhci_virt_ep *ep; | |
456 | ||
457 | for (i = 0; i < LAST_EP_INDEX + 1; i++) { | |
458 | ep = &xhci->devs[slot_id]->eps[i]; | |
be88fe4f | 459 | |
b7f9696b HG |
460 | if (ep->ep_state & EP_HAS_STREAMS) { |
461 | for (s = 1; s < ep->stream_info->num_streams; s++) | |
462 | xhci_ring_ep_doorbell(xhci, slot_id, i, s); | |
463 | } else if (ep->ring && ep->ring->dequeue) { | |
be88fe4f | 464 | xhci_ring_ep_doorbell(xhci, slot_id, i, 0); |
b7f9696b HG |
465 | } |
466 | } | |
be88fe4f AX |
467 | |
468 | return; | |
469 | } | |
470 | ||
f6ff0ac8 | 471 | static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
28ccd296 | 472 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
6219c047 | 473 | { |
6dd0a3a7 | 474 | /* Don't allow the USB core to disable SuperSpeed ports. */ |
b50107bb | 475 | if (hcd->speed >= HCD_USB3) { |
6dd0a3a7 SS |
476 | xhci_dbg(xhci, "Ignoring request to disable " |
477 | "SuperSpeed port.\n"); | |
478 | return; | |
479 | } | |
480 | ||
41135de1 FB |
481 | if (xhci->quirks & XHCI_BROKEN_PORT_PED) { |
482 | xhci_dbg(xhci, | |
483 | "Broken Port Enabled/Disabled, ignoring port disable request.\n"); | |
484 | return; | |
485 | } | |
486 | ||
6219c047 | 487 | /* Write 1 to disable the port */ |
204b7793 | 488 | writel(port_status | PORT_PE, addr); |
b0ba9720 | 489 | port_status = readl(addr); |
d70d5a84 MN |
490 | xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n", |
491 | hcd->self.busnum, wIndex + 1, port_status); | |
6219c047 SS |
492 | } |
493 | ||
34fb562a | 494 | static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, |
28ccd296 | 495 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
34fb562a SS |
496 | { |
497 | char *port_change_bit; | |
498 | u32 status; | |
499 | ||
500 | switch (wValue) { | |
501 | case USB_PORT_FEAT_C_RESET: | |
502 | status = PORT_RC; | |
503 | port_change_bit = "reset"; | |
504 | break; | |
a11496eb AX |
505 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
506 | status = PORT_WRC; | |
507 | port_change_bit = "warm(BH) reset"; | |
508 | break; | |
34fb562a SS |
509 | case USB_PORT_FEAT_C_CONNECTION: |
510 | status = PORT_CSC; | |
511 | port_change_bit = "connect"; | |
512 | break; | |
513 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
514 | status = PORT_OCC; | |
515 | port_change_bit = "over-current"; | |
516 | break; | |
6219c047 SS |
517 | case USB_PORT_FEAT_C_ENABLE: |
518 | status = PORT_PEC; | |
519 | port_change_bit = "enable/disable"; | |
520 | break; | |
be88fe4f AX |
521 | case USB_PORT_FEAT_C_SUSPEND: |
522 | status = PORT_PLC; | |
523 | port_change_bit = "suspend/resume"; | |
524 | break; | |
85387c0e AX |
525 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
526 | status = PORT_PLC; | |
527 | port_change_bit = "link state"; | |
528 | break; | |
9425183d LB |
529 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
530 | status = PORT_CEC; | |
531 | port_change_bit = "config error"; | |
532 | break; | |
34fb562a SS |
533 | default: |
534 | /* Should never happen */ | |
535 | return; | |
536 | } | |
537 | /* Change bits are all write 1 to clear */ | |
204b7793 | 538 | writel(port_status | status, addr); |
b0ba9720 | 539 | port_status = readl(addr); |
d70d5a84 MN |
540 | |
541 | xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n", | |
542 | wIndex + 1, port_change_bit, port_status); | |
34fb562a SS |
543 | } |
544 | ||
ffd4b4fc MN |
545 | struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd) |
546 | { | |
547 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
548 | ||
549 | if (hcd->speed >= HCD_USB3) | |
550 | return &xhci->usb3_rhub; | |
551 | return &xhci->usb2_rhub; | |
552 | } | |
553 | ||
a6ff6cbf GZ |
554 | /* |
555 | * xhci_set_port_power() must be called with xhci->lock held. | |
556 | * It will release and re-aquire the lock while calling ACPI | |
557 | * method. | |
558 | */ | |
559 | static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, | |
ec1dafe8 | 560 | u16 index, bool on, unsigned long *flags) |
a6ff6cbf | 561 | { |
e740b019 MN |
562 | struct xhci_hub *rhub; |
563 | struct xhci_port *port; | |
a6ff6cbf | 564 | u32 temp; |
a6ff6cbf | 565 | |
e740b019 MN |
566 | rhub = xhci_get_rhub(hcd); |
567 | port = rhub->ports[index]; | |
568 | temp = readl(port->addr); | |
d70d5a84 MN |
569 | |
570 | xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n", | |
571 | hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); | |
572 | ||
a6ff6cbf | 573 | temp = xhci_port_state_to_neutral(temp); |
d70d5a84 | 574 | |
a6ff6cbf GZ |
575 | if (on) { |
576 | /* Power on */ | |
e740b019 | 577 | writel(temp | PORT_POWER, port->addr); |
d70d5a84 | 578 | readl(port->addr); |
a6ff6cbf GZ |
579 | } else { |
580 | /* Power off */ | |
e740b019 | 581 | writel(temp & ~PORT_POWER, port->addr); |
a6ff6cbf GZ |
582 | } |
583 | ||
ec1dafe8 | 584 | spin_unlock_irqrestore(&xhci->lock, *flags); |
a6ff6cbf GZ |
585 | temp = usb_acpi_power_manageable(hcd->self.root_hub, |
586 | index); | |
587 | if (temp) | |
588 | usb_acpi_set_power_state(hcd->self.root_hub, | |
589 | index, on); | |
ec1dafe8 | 590 | spin_lock_irqsave(&xhci->lock, *flags); |
a6ff6cbf GZ |
591 | } |
592 | ||
0f1d832e GZ |
593 | static void xhci_port_set_test_mode(struct xhci_hcd *xhci, |
594 | u16 test_mode, u16 wIndex) | |
595 | { | |
596 | u32 temp; | |
e740b019 | 597 | struct xhci_port *port; |
0f1d832e | 598 | |
e740b019 MN |
599 | /* xhci only supports test mode for usb2 ports */ |
600 | port = xhci->usb2_rhub.ports[wIndex]; | |
601 | temp = readl(port->addr + PORTPMSC); | |
0f1d832e | 602 | temp |= test_mode << PORT_TEST_MODE_SHIFT; |
e740b019 | 603 | writel(temp, port->addr + PORTPMSC); |
0f1d832e GZ |
604 | xhci->test_mode = test_mode; |
605 | if (test_mode == TEST_FORCE_EN) | |
606 | xhci_start(xhci); | |
607 | } | |
608 | ||
609 | static int xhci_enter_test_mode(struct xhci_hcd *xhci, | |
ec1dafe8 | 610 | u16 test_mode, u16 wIndex, unsigned long *flags) |
0f1d832e GZ |
611 | { |
612 | int i, retval; | |
613 | ||
614 | /* Disable all Device Slots */ | |
615 | xhci_dbg(xhci, "Disable all slots\n"); | |
576d5546 | 616 | spin_unlock_irqrestore(&xhci->lock, *flags); |
0f1d832e | 617 | for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { |
b64149ca LB |
618 | if (!xhci->devs[i]) |
619 | continue; | |
620 | ||
cd3f1790 | 621 | retval = xhci_disable_slot(xhci, i); |
0f1d832e GZ |
622 | if (retval) |
623 | xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", | |
624 | i, retval); | |
625 | } | |
576d5546 | 626 | spin_lock_irqsave(&xhci->lock, *flags); |
0f1d832e GZ |
627 | /* Put all ports to the Disable state by clear PP */ |
628 | xhci_dbg(xhci, "Disable all port (PP = 0)\n"); | |
629 | /* Power off USB3 ports*/ | |
e740b019 | 630 | for (i = 0; i < xhci->usb3_rhub.num_ports; i++) |
ec1dafe8 | 631 | xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags); |
0f1d832e | 632 | /* Power off USB2 ports*/ |
e740b019 | 633 | for (i = 0; i < xhci->usb2_rhub.num_ports; i++) |
ec1dafe8 | 634 | xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags); |
0f1d832e GZ |
635 | /* Stop the controller */ |
636 | xhci_dbg(xhci, "Stop controller\n"); | |
637 | retval = xhci_halt(xhci); | |
638 | if (retval) | |
639 | return retval; | |
640 | /* Disable runtime PM for test mode */ | |
641 | pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); | |
642 | /* Set PORTPMSC.PTC field to enter selected test mode */ | |
643 | /* Port is selected by wIndex. port_id = wIndex + 1 */ | |
644 | xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n", | |
645 | test_mode, wIndex + 1); | |
646 | xhci_port_set_test_mode(xhci, test_mode, wIndex); | |
647 | return retval; | |
648 | } | |
649 | ||
650 | static int xhci_exit_test_mode(struct xhci_hcd *xhci) | |
651 | { | |
652 | int retval; | |
653 | ||
654 | if (!xhci->test_mode) { | |
655 | xhci_err(xhci, "Not in test mode, do nothing.\n"); | |
656 | return 0; | |
657 | } | |
658 | if (xhci->test_mode == TEST_FORCE_EN && | |
659 | !(xhci->xhc_state & XHCI_STATE_HALTED)) { | |
660 | retval = xhci_halt(xhci); | |
661 | if (retval) | |
662 | return retval; | |
663 | } | |
664 | pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); | |
665 | xhci->test_mode = 0; | |
666 | return xhci_reset(xhci); | |
667 | } | |
668 | ||
6b7f40f7 MN |
669 | void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, |
670 | u32 link_state) | |
c9682dff AX |
671 | { |
672 | u32 temp; | |
d70d5a84 | 673 | u32 portsc; |
c9682dff | 674 | |
d70d5a84 MN |
675 | portsc = readl(port->addr); |
676 | temp = xhci_port_state_to_neutral(portsc); | |
c9682dff AX |
677 | temp &= ~PORT_PLS_MASK; |
678 | temp |= PORT_LINK_STROBE | link_state; | |
6b7f40f7 | 679 | writel(temp, port->addr); |
d70d5a84 MN |
680 | |
681 | xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x", | |
682 | port->rhub->hcd->self.busnum, port->hcd_portnum + 1, | |
683 | portsc, temp); | |
c9682dff AX |
684 | } |
685 | ||
ed384bd3 | 686 | static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, |
fdcf74ff | 687 | struct xhci_port *port, u16 wake_mask) |
4296c70a SS |
688 | { |
689 | u32 temp; | |
690 | ||
fdcf74ff | 691 | temp = readl(port->addr); |
4296c70a SS |
692 | temp = xhci_port_state_to_neutral(temp); |
693 | ||
694 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) | |
695 | temp |= PORT_WKCONN_E; | |
696 | else | |
697 | temp &= ~PORT_WKCONN_E; | |
698 | ||
699 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) | |
700 | temp |= PORT_WKDISC_E; | |
701 | else | |
702 | temp &= ~PORT_WKDISC_E; | |
703 | ||
704 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) | |
705 | temp |= PORT_WKOC_E; | |
706 | else | |
707 | temp &= ~PORT_WKOC_E; | |
708 | ||
fdcf74ff | 709 | writel(temp, port->addr); |
4296c70a SS |
710 | } |
711 | ||
d2f52c9e | 712 | /* Test and clear port RWC bit */ |
eaefcf24 MN |
713 | void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, |
714 | u32 port_bit) | |
d2f52c9e AX |
715 | { |
716 | u32 temp; | |
717 | ||
eaefcf24 | 718 | temp = readl(port->addr); |
d2f52c9e AX |
719 | if (temp & port_bit) { |
720 | temp = xhci_port_state_to_neutral(temp); | |
721 | temp |= port_bit; | |
eaefcf24 | 722 | writel(temp, port->addr); |
d2f52c9e AX |
723 | } |
724 | } | |
725 | ||
8bea2bd3 | 726 | /* Updates Link Status for super Speed port */ |
96908589 FB |
727 | static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, |
728 | u32 *status, u32 status_reg) | |
8bea2bd3 SL |
729 | { |
730 | u32 pls = status_reg & PORT_PLS_MASK; | |
731 | ||
732 | /* resume state is a xHCI internal state. | |
243292a2 ZJC |
733 | * Do not report it to usb core, instead, pretend to be U3, |
734 | * thus usb core knows it's not ready for transfer | |
8bea2bd3 | 735 | */ |
243292a2 ZJC |
736 | if (pls == XDEV_RESUME) { |
737 | *status |= USB_SS_PORT_LS_U3; | |
8bea2bd3 | 738 | return; |
243292a2 | 739 | } |
8bea2bd3 SL |
740 | |
741 | /* When the CAS bit is set then warm reset | |
742 | * should be performed on port | |
743 | */ | |
744 | if (status_reg & PORT_CAS) { | |
745 | /* The CAS bit can be set while the port is | |
746 | * in any link state. | |
747 | * Only roothubs have CAS bit, so we | |
748 | * pretend to be in compliance mode | |
749 | * unless we're already in compliance | |
750 | * or the inactive state. | |
751 | */ | |
752 | if (pls != USB_SS_PORT_LS_COMP_MOD && | |
753 | pls != USB_SS_PORT_LS_SS_INACTIVE) { | |
754 | pls = USB_SS_PORT_LS_COMP_MOD; | |
755 | } | |
756 | /* Return also connection bit - | |
757 | * hub state machine resets port | |
758 | * when this bit is set. | |
759 | */ | |
760 | pls |= USB_PORT_STAT_CONNECTION; | |
71c731a2 AC |
761 | } else { |
762 | /* | |
763 | * If CAS bit isn't set but the Port is already at | |
764 | * Compliance Mode, fake a connection so the USB core | |
765 | * notices the Compliance state and resets the port. | |
766 | * This resolves an issue generated by the SN65LVPE502CP | |
767 | * in which sometimes the port enters compliance mode | |
768 | * caused by a delay on the host-device negotiation. | |
769 | */ | |
96908589 FB |
770 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && |
771 | (pls == USB_SS_PORT_LS_COMP_MOD)) | |
71c731a2 | 772 | pls |= USB_PORT_STAT_CONNECTION; |
8bea2bd3 | 773 | } |
71c731a2 | 774 | |
8bea2bd3 SL |
775 | /* update status field */ |
776 | *status |= pls; | |
777 | } | |
778 | ||
71c731a2 AC |
779 | /* |
780 | * Function for Compliance Mode Quirk. | |
781 | * | |
782 | * This Function verifies if all xhc USB3 ports have entered U0, if so, | |
783 | * the compliance mode timer is deleted. A port won't enter | |
784 | * compliance mode if it has previously entered U0. | |
785 | */ | |
5f20cf12 SK |
786 | static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, |
787 | u16 wIndex) | |
71c731a2 | 788 | { |
e740b019 | 789 | u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1); |
71c731a2 AC |
790 | bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); |
791 | ||
792 | if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) | |
793 | return; | |
794 | ||
795 | if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { | |
796 | xhci->port_status_u0 |= 1 << wIndex; | |
797 | if (xhci->port_status_u0 == all_ports_seen_u0) { | |
798 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
799 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
800 | "All USB3 ports have entered U0 already!"); | |
801 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
802 | "Compliance Mode Recovery Timer Deleted."); | |
71c731a2 AC |
803 | } |
804 | } | |
805 | } | |
806 | ||
e67ebf1b MN |
807 | static int xhci_handle_usb2_port_link_resume(struct xhci_port *port, |
808 | u32 *status, u32 portsc, | |
809 | unsigned long flags) | |
810 | { | |
811 | struct xhci_bus_state *bus_state; | |
812 | struct xhci_hcd *xhci; | |
813 | struct usb_hcd *hcd; | |
814 | int slot_id; | |
815 | u32 wIndex; | |
816 | ||
817 | hcd = port->rhub->hcd; | |
818 | bus_state = &port->rhub->bus_state; | |
819 | xhci = hcd_to_xhci(hcd); | |
820 | wIndex = port->hcd_portnum; | |
821 | ||
822 | if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) { | |
823 | *status = 0xffffffff; | |
824 | return -EINVAL; | |
825 | } | |
826 | /* did port event handler already start resume timing? */ | |
827 | if (!bus_state->resume_done[wIndex]) { | |
828 | /* If not, maybe we are in a host initated resume? */ | |
829 | if (test_bit(wIndex, &bus_state->resuming_ports)) { | |
830 | /* Host initated resume doesn't time the resume | |
831 | * signalling using resume_done[]. | |
832 | * It manually sets RESUME state, sleeps 20ms | |
833 | * and sets U0 state. This should probably be | |
834 | * changed, but not right now. | |
835 | */ | |
836 | } else { | |
837 | /* port resume was discovered now and here, | |
838 | * start resume timing | |
839 | */ | |
840 | unsigned long timeout = jiffies + | |
841 | msecs_to_jiffies(USB_RESUME_TIMEOUT); | |
842 | ||
843 | set_bit(wIndex, &bus_state->resuming_ports); | |
844 | bus_state->resume_done[wIndex] = timeout; | |
845 | mod_timer(&hcd->rh_timer, timeout); | |
846 | usb_hcd_start_port_resume(&hcd->self, wIndex); | |
847 | } | |
848 | /* Has resume been signalled for USB_RESUME_TIME yet? */ | |
849 | } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) { | |
850 | int time_left; | |
851 | ||
d70d5a84 MN |
852 | xhci_dbg(xhci, "resume USB2 port %d-%d\n", |
853 | hcd->self.busnum, wIndex + 1); | |
854 | ||
e67ebf1b MN |
855 | bus_state->resume_done[wIndex] = 0; |
856 | clear_bit(wIndex, &bus_state->resuming_ports); | |
857 | ||
858 | set_bit(wIndex, &bus_state->rexit_ports); | |
859 | ||
860 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); | |
861 | xhci_set_link_state(xhci, port, XDEV_U0); | |
862 | ||
863 | spin_unlock_irqrestore(&xhci->lock, flags); | |
864 | time_left = wait_for_completion_timeout( | |
865 | &bus_state->rexit_done[wIndex], | |
866 | msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS)); | |
867 | spin_lock_irqsave(&xhci->lock, flags); | |
868 | ||
869 | if (time_left) { | |
870 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
871 | wIndex + 1); | |
872 | if (!slot_id) { | |
873 | xhci_dbg(xhci, "slot_id is zero\n"); | |
874 | *status = 0xffffffff; | |
875 | return -ENODEV; | |
876 | } | |
877 | xhci_ring_device(xhci, slot_id); | |
878 | } else { | |
879 | int port_status = readl(port->addr); | |
880 | ||
d70d5a84 MN |
881 | xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n", |
882 | hcd->self.busnum, wIndex + 1, port_status); | |
e67ebf1b MN |
883 | *status |= USB_PORT_STAT_SUSPEND; |
884 | clear_bit(wIndex, &bus_state->rexit_ports); | |
885 | } | |
886 | ||
887 | usb_hcd_end_port_resume(&hcd->self, wIndex); | |
888 | bus_state->port_c_suspend |= 1 << wIndex; | |
889 | bus_state->suspended_ports &= ~(1 << wIndex); | |
890 | } else { | |
891 | /* | |
892 | * The resume has been signaling for less than | |
893 | * USB_RESUME_TIME. Report the port status as SUSPEND, | |
894 | * let the usbcore check port status again and clear | |
895 | * resume signaling later. | |
896 | */ | |
897 | *status |= USB_PORT_STAT_SUSPEND; | |
898 | } | |
899 | return 0; | |
900 | } | |
901 | ||
395f5409 MN |
902 | static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) |
903 | { | |
904 | u32 ext_stat = 0; | |
905 | int speed_id; | |
906 | ||
907 | /* only support rx and tx lane counts of 1 in usb3.1 spec */ | |
908 | speed_id = DEV_PORT_SPEED(raw_port_status); | |
909 | ext_stat |= speed_id; /* bits 3:0, RX speed id */ | |
910 | ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ | |
911 | ||
912 | ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ | |
913 | ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ | |
914 | ||
915 | return ext_stat; | |
916 | } | |
917 | ||
5f78a54f MN |
918 | static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status, |
919 | u32 portsc) | |
920 | { | |
a231ec41 | 921 | struct xhci_bus_state *bus_state; |
5f78a54f MN |
922 | struct xhci_hcd *xhci; |
923 | u32 link_state; | |
924 | u32 portnum; | |
925 | ||
a231ec41 | 926 | bus_state = &port->rhub->bus_state; |
5f78a54f MN |
927 | xhci = hcd_to_xhci(port->rhub->hcd); |
928 | link_state = portsc & PORT_PLS_MASK; | |
929 | portnum = port->hcd_portnum; | |
930 | ||
931 | /* USB3 specific wPortChange bits | |
932 | * | |
933 | * Port link change with port in resume state should not be | |
934 | * reported to usbcore, as this is an internal state to be | |
935 | * handled by xhci driver. Reporting PLC to usbcore may | |
936 | * cause usbcore clearing PLC first and port change event | |
937 | * irq won't be generated. | |
938 | */ | |
939 | ||
940 | if (portsc & PORT_PLC && (link_state != XDEV_RESUME)) | |
941 | *status |= USB_PORT_STAT_C_LINK_STATE << 16; | |
942 | if (portsc & PORT_WRC) | |
943 | *status |= USB_PORT_STAT_C_BH_RESET << 16; | |
944 | if (portsc & PORT_CEC) | |
945 | *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; | |
946 | ||
947 | /* USB3 specific wPortStatus bits */ | |
a231ec41 | 948 | if (portsc & PORT_POWER) { |
5f78a54f | 949 | *status |= USB_SS_PORT_STAT_POWER; |
a231ec41 MN |
950 | /* link state handling */ |
951 | if (link_state == XDEV_U0) | |
952 | bus_state->suspended_ports &= ~(1 << portnum); | |
953 | } | |
5f78a54f MN |
954 | |
955 | xhci_hub_report_usb3_link_state(xhci, status, portsc); | |
956 | xhci_del_comp_mod_timer(xhci, portsc, portnum); | |
957 | } | |
958 | ||
70e9b53d | 959 | static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status, |
e67ebf1b | 960 | u32 portsc, unsigned long flags) |
70e9b53d | 961 | { |
a231ec41 | 962 | struct xhci_bus_state *bus_state; |
70e9b53d | 963 | u32 link_state; |
a231ec41 | 964 | u32 portnum; |
e67ebf1b | 965 | int ret; |
70e9b53d | 966 | |
a231ec41 | 967 | bus_state = &port->rhub->bus_state; |
70e9b53d | 968 | link_state = portsc & PORT_PLS_MASK; |
a231ec41 | 969 | portnum = port->hcd_portnum; |
70e9b53d MN |
970 | |
971 | /* USB2 wPortStatus bits */ | |
972 | if (portsc & PORT_POWER) { | |
973 | *status |= USB_PORT_STAT_POWER; | |
974 | ||
975 | /* link state is only valid if port is powered */ | |
976 | if (link_state == XDEV_U3) | |
977 | *status |= USB_PORT_STAT_SUSPEND; | |
978 | if (link_state == XDEV_U2) | |
979 | *status |= USB_PORT_STAT_L1; | |
a231ec41 MN |
980 | if (link_state == XDEV_U0) { |
981 | bus_state->resume_done[portnum] = 0; | |
982 | clear_bit(portnum, &bus_state->resuming_ports); | |
983 | if (bus_state->suspended_ports & (1 << portnum)) { | |
984 | bus_state->suspended_ports &= ~(1 << portnum); | |
985 | bus_state->port_c_suspend |= 1 << portnum; | |
986 | } | |
987 | } | |
e67ebf1b MN |
988 | if (link_state == XDEV_RESUME) { |
989 | ret = xhci_handle_usb2_port_link_resume(port, status, | |
990 | portsc, flags); | |
991 | if (ret) | |
992 | return; | |
993 | } | |
70e9b53d MN |
994 | } |
995 | } | |
996 | ||
eae5b176 SS |
997 | /* |
998 | * Converts a raw xHCI port status into the format that external USB 2.0 or USB | |
999 | * 3.0 hubs use. | |
1000 | * | |
1001 | * Possible side effects: | |
1002 | * - Mark a port as being done with device resume, | |
1003 | * and ring the endpoint doorbells. | |
1004 | * - Stop the Synopsys redriver Compliance Mode polling. | |
8b3d4570 | 1005 | * - Drop and reacquire the xHCI lock, in order to wait for port resume. |
eae5b176 SS |
1006 | */ |
1007 | static u32 xhci_get_port_status(struct usb_hcd *hcd, | |
1008 | struct xhci_bus_state *bus_state, | |
eaefcf24 | 1009 | u16 wIndex, u32 raw_port_status, |
8b3d4570 SS |
1010 | unsigned long flags) |
1011 | __releases(&xhci->lock) | |
1012 | __acquires(&xhci->lock) | |
eae5b176 | 1013 | { |
eae5b176 | 1014 | u32 status = 0; |
e740b019 MN |
1015 | struct xhci_hub *rhub; |
1016 | struct xhci_port *port; | |
1017 | ||
1018 | rhub = xhci_get_rhub(hcd); | |
1019 | port = rhub->ports[wIndex]; | |
eae5b176 | 1020 | |
3c2ddb44 | 1021 | /* common wPortChange bits */ |
eae5b176 SS |
1022 | if (raw_port_status & PORT_CSC) |
1023 | status |= USB_PORT_STAT_C_CONNECTION << 16; | |
1024 | if (raw_port_status & PORT_PEC) | |
1025 | status |= USB_PORT_STAT_C_ENABLE << 16; | |
1026 | if ((raw_port_status & PORT_OCC)) | |
1027 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; | |
1028 | if ((raw_port_status & PORT_RC)) | |
1029 | status |= USB_PORT_STAT_C_RESET << 16; | |
70e9b53d | 1030 | |
3c2ddb44 MN |
1031 | /* common wPortStatus bits */ |
1032 | if (raw_port_status & PORT_CONNECT) { | |
1033 | status |= USB_PORT_STAT_CONNECTION; | |
1034 | status |= xhci_port_speed(raw_port_status); | |
1035 | } | |
1036 | if (raw_port_status & PORT_PE) | |
1037 | status |= USB_PORT_STAT_ENABLE; | |
1038 | if (raw_port_status & PORT_OC) | |
1039 | status |= USB_PORT_STAT_OVERCURRENT; | |
1040 | if (raw_port_status & PORT_RESET) | |
1041 | status |= USB_PORT_STAT_RESET; | |
1042 | ||
1043 | /* USB2 and USB3 specific bits, including Port Link State */ | |
5f78a54f MN |
1044 | if (hcd->speed >= HCD_USB3) |
1045 | xhci_get_usb3_port_status(port, &status, raw_port_status); | |
70e9b53d | 1046 | else |
e67ebf1b MN |
1047 | xhci_get_usb2_port_status(port, &status, raw_port_status, |
1048 | flags); | |
f69115fd MN |
1049 | /* |
1050 | * Clear stale usb2 resume signalling variables in case port changed | |
1051 | * state during resume signalling. For example on error | |
1052 | */ | |
1053 | if ((bus_state->resume_done[wIndex] || | |
1054 | test_bit(wIndex, &bus_state->resuming_ports)) && | |
1055 | (raw_port_status & PORT_PLS_MASK) != XDEV_U3 && | |
1056 | (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) { | |
1057 | bus_state->resume_done[wIndex] = 0; | |
1058 | clear_bit(wIndex, &bus_state->resuming_ports); | |
330e2d61 | 1059 | usb_hcd_end_port_resume(&hcd->self, wIndex); |
f69115fd MN |
1060 | } |
1061 | ||
eae5b176 | 1062 | if (bus_state->port_c_suspend & (1 << wIndex)) |
5e6389fd | 1063 | status |= USB_PORT_STAT_C_SUSPEND << 16; |
eae5b176 SS |
1064 | |
1065 | return status; | |
1066 | } | |
1067 | ||
0f2a7930 SS |
1068 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
1069 | u16 wIndex, char *buf, u16 wLength) | |
1070 | { | |
1071 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 1072 | int max_ports; |
0f2a7930 | 1073 | unsigned long flags; |
c9682dff | 1074 | u32 temp, status; |
0f2a7930 | 1075 | int retval = 0; |
be88fe4f | 1076 | int slot_id; |
20b67cf5 | 1077 | struct xhci_bus_state *bus_state; |
2c441780 | 1078 | u16 link_state = 0; |
4296c70a | 1079 | u16 wake_mask = 0; |
797b0ca5 | 1080 | u16 timeout = 0; |
0f1d832e | 1081 | u16 test_mode = 0; |
e740b019 MN |
1082 | struct xhci_hub *rhub; |
1083 | struct xhci_port **ports; | |
0f2a7930 | 1084 | |
e740b019 MN |
1085 | rhub = xhci_get_rhub(hcd); |
1086 | ports = rhub->ports; | |
925f349d | 1087 | max_ports = rhub->num_ports; |
f6187f42 | 1088 | bus_state = &rhub->bus_state; |
0f2a7930 SS |
1089 | |
1090 | spin_lock_irqsave(&xhci->lock, flags); | |
1091 | switch (typeReq) { | |
1092 | case GetHubStatus: | |
1093 | /* No power source, over-current reported per port */ | |
1094 | memset(buf, 0, 4); | |
1095 | break; | |
1096 | case GetHubDescriptor: | |
4bbb0ace SS |
1097 | /* Check to make sure userspace is asking for the USB 3.0 hub |
1098 | * descriptor for the USB 3.0 roothub. If not, we stall the | |
1099 | * endpoint, like external hubs do. | |
1100 | */ | |
b50107bb | 1101 | if (hcd->speed >= HCD_USB3 && |
4bbb0ace SS |
1102 | (wLength < USB_DT_SS_HUB_SIZE || |
1103 | wValue != (USB_DT_SS_HUB << 8))) { | |
1104 | xhci_dbg(xhci, "Wrong hub descriptor type for " | |
1105 | "USB 3.0 roothub.\n"); | |
1106 | goto error; | |
1107 | } | |
f6ff0ac8 SS |
1108 | xhci_hub_descriptor(hcd, xhci, |
1109 | (struct usb_hub_descriptor *) buf); | |
0f2a7930 | 1110 | break; |
48e82361 SS |
1111 | case DeviceRequest | USB_REQ_GET_DESCRIPTOR: |
1112 | if ((wValue & 0xff00) != (USB_DT_BOS << 8)) | |
1113 | goto error; | |
1114 | ||
5693e0b7 | 1115 | if (hcd->speed < HCD_USB3) |
48e82361 SS |
1116 | goto error; |
1117 | ||
5693e0b7 | 1118 | retval = xhci_create_usb3_bos_desc(xhci, buf, wLength); |
48e82361 | 1119 | spin_unlock_irqrestore(&xhci->lock, flags); |
5693e0b7 | 1120 | return retval; |
0f2a7930 | 1121 | case GetPortStatus: |
a0885924 | 1122 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1123 | goto error; |
1124 | wIndex--; | |
e740b019 | 1125 | temp = readl(ports[wIndex]->addr); |
d9f11ba9 MN |
1126 | if (temp == ~(u32)0) { |
1127 | xhci_hc_died(xhci); | |
f9de8151 SS |
1128 | retval = -ENODEV; |
1129 | break; | |
1130 | } | |
28c06e58 | 1131 | trace_xhci_get_port_status(wIndex, temp); |
eaefcf24 MN |
1132 | status = xhci_get_port_status(hcd, bus_state, wIndex, temp, |
1133 | flags); | |
eae5b176 SS |
1134 | if (status == 0xffffffff) |
1135 | goto error; | |
0ed9a57e | 1136 | |
d70d5a84 MN |
1137 | xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x", |
1138 | hcd->self.busnum, wIndex + 1, temp, status); | |
eae5b176 | 1139 | |
0f2a7930 | 1140 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); |
395f5409 MN |
1141 | /* if USB 3.1 extended port status return additional 4 bytes */ |
1142 | if (wValue == 0x02) { | |
1143 | u32 port_li; | |
1144 | ||
1145 | if (hcd->speed < HCD_USB31 || wLength != 8) { | |
1146 | xhci_err(xhci, "get ext port status invalid parameter\n"); | |
1147 | retval = -EINVAL; | |
1148 | break; | |
1149 | } | |
e740b019 | 1150 | port_li = readl(ports[wIndex]->addr + PORTLI); |
395f5409 | 1151 | status = xhci_get_ext_port_status(temp, port_li); |
6269e4c7 | 1152 | put_unaligned_le32(status, &buf[4]); |
395f5409 | 1153 | } |
0f2a7930 SS |
1154 | break; |
1155 | case SetPortFeature: | |
2c441780 AX |
1156 | if (wValue == USB_PORT_FEAT_LINK_STATE) |
1157 | link_state = (wIndex & 0xff00) >> 3; | |
4296c70a SS |
1158 | if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) |
1159 | wake_mask = wIndex & 0xff00; | |
0f1d832e GZ |
1160 | if (wValue == USB_PORT_FEAT_TEST) |
1161 | test_mode = (wIndex & 0xff00) >> 8; | |
797b0ca5 SS |
1162 | /* The MSB of wIndex is the U1/U2 timeout */ |
1163 | timeout = (wIndex & 0xff00) >> 8; | |
0f2a7930 | 1164 | wIndex &= 0xff; |
a0885924 | 1165 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1166 | goto error; |
1167 | wIndex--; | |
e740b019 | 1168 | temp = readl(ports[wIndex]->addr); |
d9f11ba9 MN |
1169 | if (temp == ~(u32)0) { |
1170 | xhci_hc_died(xhci); | |
f9de8151 SS |
1171 | retval = -ENODEV; |
1172 | break; | |
1173 | } | |
0f2a7930 | 1174 | temp = xhci_port_state_to_neutral(temp); |
4bbb0ace | 1175 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 | 1176 | switch (wValue) { |
be88fe4f | 1177 | case USB_PORT_FEAT_SUSPEND: |
e740b019 | 1178 | temp = readl(ports[wIndex]->addr); |
65580b43 AX |
1179 | if ((temp & PORT_PLS_MASK) != XDEV_U0) { |
1180 | /* Resume the port to U0 first */ | |
6b7f40f7 | 1181 | xhci_set_link_state(xhci, ports[wIndex], |
65580b43 AX |
1182 | XDEV_U0); |
1183 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1184 | msleep(10); | |
1185 | spin_lock_irqsave(&xhci->lock, flags); | |
1186 | } | |
be88fe4f AX |
1187 | /* In spec software should not attempt to suspend |
1188 | * a port unless the port reports that it is in the | |
1189 | * enabled (PED = ‘1’,PLS < ‘3’) state. | |
1190 | */ | |
e740b019 | 1191 | temp = readl(ports[wIndex]->addr); |
be88fe4f AX |
1192 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) |
1193 | || (temp & PORT_PLS_MASK) >= XDEV_U3) { | |
d70d5a84 MN |
1194 | xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n", |
1195 | hcd->self.busnum, wIndex + 1); | |
be88fe4f AX |
1196 | goto error; |
1197 | } | |
1198 | ||
5233630f SS |
1199 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1200 | wIndex + 1); | |
be88fe4f AX |
1201 | if (!slot_id) { |
1202 | xhci_warn(xhci, "slot_id is zero\n"); | |
1203 | goto error; | |
1204 | } | |
1205 | /* unlock to execute stop endpoint commands */ | |
1206 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1207 | xhci_stop_device(xhci, slot_id, 1); | |
1208 | spin_lock_irqsave(&xhci->lock, flags); | |
1209 | ||
6b7f40f7 | 1210 | xhci_set_link_state(xhci, ports[wIndex], XDEV_U3); |
be88fe4f AX |
1211 | |
1212 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1213 | msleep(10); /* wait device to enter */ | |
1214 | spin_lock_irqsave(&xhci->lock, flags); | |
1215 | ||
e740b019 | 1216 | temp = readl(ports[wIndex]->addr); |
20b67cf5 | 1217 | bus_state->suspended_ports |= 1 << wIndex; |
be88fe4f | 1218 | break; |
2c441780 | 1219 | case USB_PORT_FEAT_LINK_STATE: |
e740b019 | 1220 | temp = readl(ports[wIndex]->addr); |
41e7e056 SS |
1221 | /* Disable port */ |
1222 | if (link_state == USB_SS_PORT_LS_SS_DISABLED) { | |
1223 | xhci_dbg(xhci, "Disable port %d\n", wIndex); | |
1224 | temp = xhci_port_state_to_neutral(temp); | |
1225 | /* | |
1226 | * Clear all change bits, so that we get a new | |
1227 | * connection event. | |
1228 | */ | |
1229 | temp |= PORT_CSC | PORT_PEC | PORT_WRC | | |
1230 | PORT_OCC | PORT_RC | PORT_PLC | | |
1231 | PORT_CEC; | |
e740b019 MN |
1232 | writel(temp | PORT_PE, ports[wIndex]->addr); |
1233 | temp = readl(ports[wIndex]->addr); | |
41e7e056 SS |
1234 | break; |
1235 | } | |
1236 | ||
1237 | /* Put link in RxDetect (enable port) */ | |
1238 | if (link_state == USB_SS_PORT_LS_RX_DETECT) { | |
1239 | xhci_dbg(xhci, "Enable port %d\n", wIndex); | |
6b7f40f7 MN |
1240 | xhci_set_link_state(xhci, ports[wIndex], |
1241 | link_state); | |
e740b019 | 1242 | temp = readl(ports[wIndex]->addr); |
41e7e056 SS |
1243 | break; |
1244 | } | |
1245 | ||
4b562bd2 JP |
1246 | /* |
1247 | * For xHCI 1.1 according to section 4.19.1.2.4.1 a | |
1248 | * root hub port's transition to compliance mode upon | |
1249 | * detecting LFPS timeout may be controlled by an | |
1250 | * Compliance Transition Enabled (CTE) flag (not | |
1251 | * software visible). This flag is set by writing 0xA | |
1252 | * to PORTSC PLS field which will allow transition to | |
1253 | * compliance mode the next time LFPS timeout is | |
1254 | * encountered. A warm reset will clear it. | |
1255 | * | |
1256 | * The CTE flag is only supported if the HCCPARAMS2 CTC | |
1257 | * flag is set, otherwise, the compliance substate is | |
1258 | * automatically entered as on 1.0 and prior. | |
1259 | */ | |
1260 | if (link_state == USB_SS_PORT_LS_COMP_MOD) { | |
1261 | if (!HCC2_CTC(xhci->hcc_params2)) { | |
1262 | xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n"); | |
1263 | break; | |
1264 | } | |
1265 | ||
1266 | if ((temp & PORT_CONNECT)) { | |
1267 | xhci_warn(xhci, "Can't set compliance mode when port is connected\n"); | |
1268 | goto error; | |
1269 | } | |
1270 | ||
1271 | xhci_dbg(xhci, "Enable compliance mode transition for port %d\n", | |
1272 | wIndex); | |
6b7f40f7 | 1273 | xhci_set_link_state(xhci, ports[wIndex], |
4b562bd2 | 1274 | link_state); |
6b7f40f7 | 1275 | |
e740b019 | 1276 | temp = readl(ports[wIndex]->addr); |
4b562bd2 JP |
1277 | break; |
1278 | } | |
1208d8a8 MN |
1279 | /* Port must be enabled */ |
1280 | if (!(temp & PORT_PE)) { | |
1281 | retval = -ENODEV; | |
1282 | break; | |
1283 | } | |
1284 | /* Can't set port link state above '3' (U3) */ | |
1285 | if (link_state > USB_SS_PORT_LS_U3) { | |
1286 | xhci_warn(xhci, "Cannot set port %d link state %d\n", | |
1287 | wIndex, link_state); | |
2c441780 AX |
1288 | goto error; |
1289 | } | |
2c441780 AX |
1290 | if (link_state == USB_SS_PORT_LS_U3) { |
1291 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
1292 | wIndex + 1); | |
1293 | if (slot_id) { | |
1294 | /* unlock to execute stop endpoint | |
1295 | * commands */ | |
1296 | spin_unlock_irqrestore(&xhci->lock, | |
1297 | flags); | |
1298 | xhci_stop_device(xhci, slot_id, 1); | |
1299 | spin_lock_irqsave(&xhci->lock, flags); | |
1300 | } | |
1301 | } | |
1302 | ||
6b7f40f7 | 1303 | xhci_set_link_state(xhci, ports[wIndex], link_state); |
2c441780 AX |
1304 | |
1305 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1306 | msleep(20); /* wait device to enter */ | |
1307 | spin_lock_irqsave(&xhci->lock, flags); | |
1308 | ||
e740b019 | 1309 | temp = readl(ports[wIndex]->addr); |
2c441780 AX |
1310 | if (link_state == USB_SS_PORT_LS_U3) |
1311 | bus_state->suspended_ports |= 1 << wIndex; | |
1312 | break; | |
0f2a7930 SS |
1313 | case USB_PORT_FEAT_POWER: |
1314 | /* | |
1315 | * Turn on ports, even if there isn't per-port switching. | |
1316 | * HC will report connect events even before this is set. | |
37ebb549 | 1317 | * However, hub_wq will ignore the roothub events until |
0f2a7930 SS |
1318 | * the roothub is registered. |
1319 | */ | |
ec1dafe8 | 1320 | xhci_set_port_power(xhci, hcd, wIndex, true, &flags); |
0f2a7930 SS |
1321 | break; |
1322 | case USB_PORT_FEAT_RESET: | |
1323 | temp = (temp | PORT_RESET); | |
e740b019 | 1324 | writel(temp, ports[wIndex]->addr); |
0f2a7930 | 1325 | |
e740b019 | 1326 | temp = readl(ports[wIndex]->addr); |
0f2a7930 SS |
1327 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); |
1328 | break; | |
4296c70a | 1329 | case USB_PORT_FEAT_REMOTE_WAKE_MASK: |
fdcf74ff MN |
1330 | xhci_set_remote_wake_mask(xhci, ports[wIndex], |
1331 | wake_mask); | |
e740b019 | 1332 | temp = readl(ports[wIndex]->addr); |
4296c70a SS |
1333 | xhci_dbg(xhci, "set port remote wake mask, " |
1334 | "actual port %d status = 0x%x\n", | |
1335 | wIndex, temp); | |
1336 | break; | |
a11496eb AX |
1337 | case USB_PORT_FEAT_BH_PORT_RESET: |
1338 | temp |= PORT_WR; | |
e740b019 MN |
1339 | writel(temp, ports[wIndex]->addr); |
1340 | temp = readl(ports[wIndex]->addr); | |
a11496eb | 1341 | break; |
797b0ca5 | 1342 | case USB_PORT_FEAT_U1_TIMEOUT: |
b50107bb | 1343 | if (hcd->speed < HCD_USB3) |
797b0ca5 | 1344 | goto error; |
e740b019 | 1345 | temp = readl(ports[wIndex]->addr + PORTPMSC); |
797b0ca5 SS |
1346 | temp &= ~PORT_U1_TIMEOUT_MASK; |
1347 | temp |= PORT_U1_TIMEOUT(timeout); | |
e740b019 | 1348 | writel(temp, ports[wIndex]->addr + PORTPMSC); |
797b0ca5 SS |
1349 | break; |
1350 | case USB_PORT_FEAT_U2_TIMEOUT: | |
b50107bb | 1351 | if (hcd->speed < HCD_USB3) |
797b0ca5 | 1352 | goto error; |
e740b019 | 1353 | temp = readl(ports[wIndex]->addr + PORTPMSC); |
797b0ca5 SS |
1354 | temp &= ~PORT_U2_TIMEOUT_MASK; |
1355 | temp |= PORT_U2_TIMEOUT(timeout); | |
e740b019 | 1356 | writel(temp, ports[wIndex]->addr + PORTPMSC); |
797b0ca5 | 1357 | break; |
0f1d832e GZ |
1358 | case USB_PORT_FEAT_TEST: |
1359 | /* 4.19.6 Port Test Modes (USB2 Test Mode) */ | |
1360 | if (hcd->speed != HCD_USB2) | |
1361 | goto error; | |
1362 | if (test_mode > TEST_FORCE_EN || test_mode < TEST_J) | |
1363 | goto error; | |
ec1dafe8 MN |
1364 | retval = xhci_enter_test_mode(xhci, test_mode, wIndex, |
1365 | &flags); | |
0f1d832e | 1366 | break; |
0f2a7930 SS |
1367 | default: |
1368 | goto error; | |
1369 | } | |
5308a91b | 1370 | /* unblock any posted writes */ |
e740b019 | 1371 | temp = readl(ports[wIndex]->addr); |
0f2a7930 SS |
1372 | break; |
1373 | case ClearPortFeature: | |
a0885924 | 1374 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1375 | goto error; |
1376 | wIndex--; | |
e740b019 | 1377 | temp = readl(ports[wIndex]->addr); |
d9f11ba9 MN |
1378 | if (temp == ~(u32)0) { |
1379 | xhci_hc_died(xhci); | |
f9de8151 SS |
1380 | retval = -ENODEV; |
1381 | break; | |
1382 | } | |
4bbb0ace | 1383 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 SS |
1384 | temp = xhci_port_state_to_neutral(temp); |
1385 | switch (wValue) { | |
be88fe4f | 1386 | case USB_PORT_FEAT_SUSPEND: |
e740b019 | 1387 | temp = readl(ports[wIndex]->addr); |
be88fe4f AX |
1388 | xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); |
1389 | xhci_dbg(xhci, "PORTSC %04x\n", temp); | |
1390 | if (temp & PORT_RESET) | |
1391 | goto error; | |
5ac04bf1 | 1392 | if ((temp & PORT_PLS_MASK) == XDEV_U3) { |
be88fe4f AX |
1393 | if ((temp & PORT_PE) == 0) |
1394 | goto error; | |
be88fe4f | 1395 | |
f69115fd | 1396 | set_bit(wIndex, &bus_state->resuming_ports); |
330e2d61 | 1397 | usb_hcd_start_port_resume(&hcd->self, wIndex); |
6b7f40f7 MN |
1398 | xhci_set_link_state(xhci, ports[wIndex], |
1399 | XDEV_RESUME); | |
c9682dff | 1400 | spin_unlock_irqrestore(&xhci->lock, flags); |
7d3b016a | 1401 | msleep(USB_RESUME_TIMEOUT); |
a7114230 | 1402 | spin_lock_irqsave(&xhci->lock, flags); |
6b7f40f7 | 1403 | xhci_set_link_state(xhci, ports[wIndex], |
c9682dff | 1404 | XDEV_U0); |
f69115fd | 1405 | clear_bit(wIndex, &bus_state->resuming_ports); |
330e2d61 | 1406 | usb_hcd_end_port_resume(&hcd->self, wIndex); |
be88fe4f | 1407 | } |
a7114230 | 1408 | bus_state->port_c_suspend |= 1 << wIndex; |
be88fe4f | 1409 | |
5233630f SS |
1410 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1411 | wIndex + 1); | |
be88fe4f AX |
1412 | if (!slot_id) { |
1413 | xhci_dbg(xhci, "slot_id is zero\n"); | |
1414 | goto error; | |
1415 | } | |
1416 | xhci_ring_device(xhci, slot_id); | |
1417 | break; | |
1418 | case USB_PORT_FEAT_C_SUSPEND: | |
20b67cf5 | 1419 | bus_state->port_c_suspend &= ~(1 << wIndex); |
ff504f57 | 1420 | /* fall through */ |
0f2a7930 | 1421 | case USB_PORT_FEAT_C_RESET: |
a11496eb | 1422 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
0f2a7930 | 1423 | case USB_PORT_FEAT_C_CONNECTION: |
0f2a7930 | 1424 | case USB_PORT_FEAT_C_OVER_CURRENT: |
6219c047 | 1425 | case USB_PORT_FEAT_C_ENABLE: |
85387c0e | 1426 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
9425183d | 1427 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
34fb562a | 1428 | xhci_clear_port_change_bit(xhci, wValue, wIndex, |
e740b019 | 1429 | ports[wIndex]->addr, temp); |
0f2a7930 | 1430 | break; |
6219c047 | 1431 | case USB_PORT_FEAT_ENABLE: |
f6ff0ac8 | 1432 | xhci_disable_port(hcd, xhci, wIndex, |
e740b019 | 1433 | ports[wIndex]->addr, temp); |
6219c047 | 1434 | break; |
693d8eb8 | 1435 | case USB_PORT_FEAT_POWER: |
ec1dafe8 | 1436 | xhci_set_port_power(xhci, hcd, wIndex, false, &flags); |
693d8eb8 | 1437 | break; |
0f1d832e GZ |
1438 | case USB_PORT_FEAT_TEST: |
1439 | retval = xhci_exit_test_mode(xhci); | |
1440 | break; | |
0f2a7930 SS |
1441 | default: |
1442 | goto error; | |
1443 | } | |
0f2a7930 SS |
1444 | break; |
1445 | default: | |
1446 | error: | |
1447 | /* "stall" on error */ | |
1448 | retval = -EPIPE; | |
1449 | } | |
1450 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1451 | return retval; | |
1452 | } | |
1453 | ||
1454 | /* | |
1455 | * Returns 0 if the status hasn't changed, or the number of bytes in buf. | |
1456 | * Ports are 0-indexed from the HCD point of view, | |
1457 | * and 1-indexed from the USB core pointer of view. | |
0f2a7930 SS |
1458 | * |
1459 | * Note that the status change bits will be cleared as soon as a port status | |
1460 | * change event is generated, so we use the saved status from that event. | |
1461 | */ | |
1462 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) | |
1463 | { | |
1464 | unsigned long flags; | |
1465 | u32 temp, status; | |
56192531 | 1466 | u32 mask; |
0f2a7930 SS |
1467 | int i, retval; |
1468 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 1469 | int max_ports; |
20b67cf5 | 1470 | struct xhci_bus_state *bus_state; |
c52804a4 | 1471 | bool reset_change = false; |
e740b019 MN |
1472 | struct xhci_hub *rhub; |
1473 | struct xhci_port **ports; | |
0f2a7930 | 1474 | |
e740b019 MN |
1475 | rhub = xhci_get_rhub(hcd); |
1476 | ports = rhub->ports; | |
925f349d | 1477 | max_ports = rhub->num_ports; |
f6187f42 | 1478 | bus_state = &rhub->bus_state; |
0f2a7930 SS |
1479 | |
1480 | /* Initial status is no changes */ | |
a0885924 | 1481 | retval = (max_ports + 8) / 8; |
419a8e81 | 1482 | memset(buf, 0, retval); |
f370b996 AX |
1483 | |
1484 | /* | |
1485 | * Inform the usbcore about resume-in-progress by returning | |
1486 | * a non-zero value even if there are no status changes. | |
1487 | */ | |
1488 | status = bus_state->resuming_ports; | |
0f2a7930 | 1489 | |
9425183d | 1490 | mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; |
56192531 | 1491 | |
0f2a7930 SS |
1492 | spin_lock_irqsave(&xhci->lock, flags); |
1493 | /* For each port, did anything change? If so, set that bit in buf. */ | |
a0885924 | 1494 | for (i = 0; i < max_ports; i++) { |
e740b019 | 1495 | temp = readl(ports[i]->addr); |
d9f11ba9 MN |
1496 | if (temp == ~(u32)0) { |
1497 | xhci_hc_died(xhci); | |
f9de8151 SS |
1498 | retval = -ENODEV; |
1499 | break; | |
1500 | } | |
3f8499ac MN |
1501 | trace_xhci_hub_status_data(i, temp); |
1502 | ||
56192531 | 1503 | if ((temp & mask) != 0 || |
20b67cf5 SS |
1504 | (bus_state->port_c_suspend & 1 << i) || |
1505 | (bus_state->resume_done[i] && time_after_eq( | |
1506 | jiffies, bus_state->resume_done[i]))) { | |
419a8e81 | 1507 | buf[(i + 1) / 8] |= 1 << (i + 1) % 8; |
0f2a7930 SS |
1508 | status = 1; |
1509 | } | |
c52804a4 SS |
1510 | if ((temp & PORT_RC)) |
1511 | reset_change = true; | |
1512 | } | |
1513 | if (!status && !reset_change) { | |
1514 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
1515 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1516 | } |
1517 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1518 | return status ? retval : 0; | |
1519 | } | |
9777e3ce AX |
1520 | |
1521 | #ifdef CONFIG_PM | |
1522 | ||
1523 | int xhci_bus_suspend(struct usb_hcd *hcd) | |
1524 | { | |
1525 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 1526 | int max_ports, port_index; |
20b67cf5 | 1527 | struct xhci_bus_state *bus_state; |
9777e3ce | 1528 | unsigned long flags; |
e740b019 MN |
1529 | struct xhci_hub *rhub; |
1530 | struct xhci_port **ports; | |
2f31a67f MN |
1531 | u32 portsc_buf[USB_MAXCHILDREN]; |
1532 | bool wake_enabled; | |
9777e3ce | 1533 | |
e740b019 MN |
1534 | rhub = xhci_get_rhub(hcd); |
1535 | ports = rhub->ports; | |
925f349d | 1536 | max_ports = rhub->num_ports; |
f6187f42 | 1537 | bus_state = &rhub->bus_state; |
2f31a67f | 1538 | wake_enabled = hcd->self.root_hub->do_remote_wakeup; |
9777e3ce AX |
1539 | |
1540 | spin_lock_irqsave(&xhci->lock, flags); | |
1541 | ||
2f31a67f | 1542 | if (wake_enabled) { |
fac4271d ZJC |
1543 | if (bus_state->resuming_ports || /* USB2 */ |
1544 | bus_state->port_remote_wakeup) { /* USB3 */ | |
f370b996 | 1545 | spin_unlock_irqrestore(&xhci->lock, flags); |
fac4271d | 1546 | xhci_dbg(xhci, "suspend failed because a port is resuming\n"); |
f370b996 | 1547 | return -EBUSY; |
9777e3ce AX |
1548 | } |
1549 | } | |
2f31a67f MN |
1550 | /* |
1551 | * Prepare ports for suspend, but don't write anything before all ports | |
1552 | * are checked and we know bus suspend can proceed | |
1553 | */ | |
20b67cf5 | 1554 | bus_state->bus_suspended = 0; |
2f31a67f | 1555 | port_index = max_ports; |
518e848e | 1556 | while (port_index--) { |
9777e3ce | 1557 | u32 t1, t2; |
d92f2c59 MN |
1558 | int retries = 10; |
1559 | retry: | |
e740b019 | 1560 | t1 = readl(ports[port_index]->addr); |
9777e3ce | 1561 | t2 = xhci_port_state_to_neutral(t1); |
2f31a67f | 1562 | portsc_buf[port_index] = 0; |
9777e3ce | 1563 | |
d92f2c59 MN |
1564 | /* |
1565 | * Give a USB3 port in link training time to finish, but don't | |
1566 | * prevent suspend as port might be stuck | |
1567 | */ | |
1568 | if ((hcd->speed >= HCD_USB3) && retries-- && | |
45f750c1 | 1569 | (t1 & PORT_PLS_MASK) == XDEV_POLLING) { |
2f31a67f | 1570 | spin_unlock_irqrestore(&xhci->lock, flags); |
d92f2c59 MN |
1571 | msleep(XHCI_PORT_POLLING_LFPS_TIME); |
1572 | spin_lock_irqsave(&xhci->lock, flags); | |
1573 | xhci_dbg(xhci, "port %d polling in bus suspend, waiting\n", | |
1574 | port_index); | |
1575 | goto retry; | |
2f31a67f | 1576 | } |
2f31a67f MN |
1577 | /* suspend ports in U0, or bail out for new connect changes */ |
1578 | if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) { | |
1579 | if ((t1 & PORT_CSC) && wake_enabled) { | |
1580 | bus_state->bus_suspended = 0; | |
9777e3ce | 1581 | spin_unlock_irqrestore(&xhci->lock, flags); |
2f31a67f MN |
1582 | xhci_dbg(xhci, "Bus suspend bailout, port connect change\n"); |
1583 | return -EBUSY; | |
9777e3ce | 1584 | } |
2f31a67f | 1585 | xhci_dbg(xhci, "port %d not suspended\n", port_index); |
9777e3ce AX |
1586 | t2 &= ~PORT_PLS_MASK; |
1587 | t2 |= PORT_LINK_STROBE | XDEV_U3; | |
20b67cf5 | 1588 | set_bit(port_index, &bus_state->bus_suspended); |
9777e3ce | 1589 | } |
4296c70a | 1590 | /* USB core sets remote wake mask for USB 3.0 hubs, |
ceb6c9c8 | 1591 | * including the USB 3.0 roothub, but only if CONFIG_PM |
4296c70a SS |
1592 | * is enabled, so also enable remote wake here. |
1593 | */ | |
2f31a67f | 1594 | if (wake_enabled) { |
9777e3ce AX |
1595 | if (t1 & PORT_CONNECT) { |
1596 | t2 |= PORT_WKOC_E | PORT_WKDISC_E; | |
1597 | t2 &= ~PORT_WKCONN_E; | |
1598 | } else { | |
1599 | t2 |= PORT_WKOC_E | PORT_WKCONN_E; | |
1600 | t2 &= ~PORT_WKDISC_E; | |
1601 | } | |
bde0716d JL |
1602 | |
1603 | if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) && | |
1604 | (hcd->speed < HCD_USB3)) { | |
1605 | if (usb_amd_pt_check_port(hcd->self.controller, | |
1606 | port_index)) | |
1607 | t2 &= ~PORT_WAKE_BITS; | |
1608 | } | |
9777e3ce AX |
1609 | } else |
1610 | t2 &= ~PORT_WAKE_BITS; | |
1611 | ||
1612 | t1 = xhci_port_state_to_neutral(t1); | |
1613 | if (t1 != t2) | |
2f31a67f MN |
1614 | portsc_buf[port_index] = t2; |
1615 | } | |
1616 | ||
1617 | /* write port settings, stopping and suspending ports if needed */ | |
1618 | port_index = max_ports; | |
1619 | while (port_index--) { | |
1620 | if (!portsc_buf[port_index]) | |
1621 | continue; | |
1622 | if (test_bit(port_index, &bus_state->bus_suspended)) { | |
1623 | int slot_id; | |
1624 | ||
1625 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
1626 | port_index + 1); | |
1627 | if (slot_id) { | |
1628 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1629 | xhci_stop_device(xhci, slot_id, 1); | |
1630 | spin_lock_irqsave(&xhci->lock, flags); | |
1631 | } | |
1632 | } | |
1633 | writel(portsc_buf[port_index], ports[port_index]->addr); | |
9777e3ce AX |
1634 | } |
1635 | hcd->state = HC_STATE_SUSPENDED; | |
20b67cf5 | 1636 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); |
9777e3ce AX |
1637 | spin_unlock_irqrestore(&xhci->lock, flags); |
1638 | return 0; | |
1639 | } | |
1640 | ||
346e9973 MN |
1641 | /* |
1642 | * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. | |
1643 | * warm reset a USB3 device stuck in polling or compliance mode after resume. | |
1644 | * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 | |
1645 | */ | |
fdcf74ff | 1646 | static bool xhci_port_missing_cas_quirk(struct xhci_port *port) |
346e9973 MN |
1647 | { |
1648 | u32 portsc; | |
1649 | ||
fdcf74ff | 1650 | portsc = readl(port->addr); |
346e9973 MN |
1651 | |
1652 | /* if any of these are set we are not stuck */ | |
1653 | if (portsc & (PORT_CONNECT | PORT_CAS)) | |
1654 | return false; | |
1655 | ||
1656 | if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) && | |
1657 | ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE)) | |
1658 | return false; | |
1659 | ||
1660 | /* clear wakeup/change bits, and do a warm port reset */ | |
1661 | portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | |
1662 | portsc |= PORT_WR; | |
fdcf74ff | 1663 | writel(portsc, port->addr); |
346e9973 | 1664 | /* flush write */ |
fdcf74ff | 1665 | readl(port->addr); |
346e9973 MN |
1666 | return true; |
1667 | } | |
1668 | ||
9777e3ce AX |
1669 | int xhci_bus_resume(struct usb_hcd *hcd) |
1670 | { | |
1671 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
20b67cf5 | 1672 | struct xhci_bus_state *bus_state; |
9777e3ce | 1673 | unsigned long flags; |
a85c0f8d | 1674 | int max_ports, port_index; |
41485a90 MN |
1675 | int slot_id; |
1676 | int sret; | |
a85c0f8d MN |
1677 | u32 next_state; |
1678 | u32 temp, portsc; | |
e740b019 MN |
1679 | struct xhci_hub *rhub; |
1680 | struct xhci_port **ports; | |
9777e3ce | 1681 | |
e740b019 MN |
1682 | rhub = xhci_get_rhub(hcd); |
1683 | ports = rhub->ports; | |
925f349d | 1684 | max_ports = rhub->num_ports; |
f6187f42 | 1685 | bus_state = &rhub->bus_state; |
9777e3ce | 1686 | |
20b67cf5 | 1687 | if (time_before(jiffies, bus_state->next_statechange)) |
9777e3ce AX |
1688 | msleep(5); |
1689 | ||
1690 | spin_lock_irqsave(&xhci->lock, flags); | |
1691 | if (!HCD_HW_ACCESSIBLE(hcd)) { | |
1692 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1693 | return -ESHUTDOWN; | |
1694 | } | |
1695 | ||
1696 | /* delay the irqs */ | |
b0ba9720 | 1697 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1698 | temp &= ~CMD_EIE; |
204b7793 | 1699 | writel(temp, &xhci->op_regs->command); |
9777e3ce | 1700 | |
a85c0f8d MN |
1701 | /* bus specific resume for ports we suspended at bus_suspend */ |
1702 | if (hcd->speed >= HCD_USB3) | |
1703 | next_state = XDEV_U0; | |
1704 | else | |
1705 | next_state = XDEV_RESUME; | |
1706 | ||
518e848e SS |
1707 | port_index = max_ports; |
1708 | while (port_index--) { | |
e740b019 | 1709 | portsc = readl(ports[port_index]->addr); |
346e9973 MN |
1710 | |
1711 | /* warm reset CAS limited ports stuck in polling/compliance */ | |
1712 | if ((xhci->quirks & XHCI_MISSING_CAS) && | |
1713 | (hcd->speed >= HCD_USB3) && | |
fdcf74ff | 1714 | xhci_port_missing_cas_quirk(ports[port_index])) { |
346e9973 | 1715 | xhci_dbg(xhci, "reset stuck port %d\n", port_index); |
a85c0f8d | 1716 | clear_bit(port_index, &bus_state->bus_suspended); |
346e9973 MN |
1717 | continue; |
1718 | } | |
a85c0f8d MN |
1719 | /* resume if we suspended the link, and it is still suspended */ |
1720 | if (test_bit(port_index, &bus_state->bus_suspended)) | |
1721 | switch (portsc & PORT_PLS_MASK) { | |
1722 | case XDEV_U3: | |
1723 | portsc = xhci_port_state_to_neutral(portsc); | |
1724 | portsc &= ~PORT_PLS_MASK; | |
1725 | portsc |= PORT_LINK_STROBE | next_state; | |
1726 | break; | |
1727 | case XDEV_RESUME: | |
1728 | /* resume already initiated */ | |
1729 | break; | |
1730 | default: | |
1731 | /* not in a resumeable state, ignore it */ | |
1732 | clear_bit(port_index, | |
1733 | &bus_state->bus_suspended); | |
1734 | break; | |
9777e3ce | 1735 | } |
a85c0f8d MN |
1736 | /* disable wake for all ports, write new link state if needed */ |
1737 | portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | |
e740b019 | 1738 | writel(portsc, ports[port_index]->addr); |
41485a90 MN |
1739 | } |
1740 | ||
a85c0f8d MN |
1741 | /* USB2 specific resume signaling delay and U0 link state transition */ |
1742 | if (hcd->speed < HCD_USB3) { | |
1743 | if (bus_state->bus_suspended) { | |
1744 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1745 | msleep(USB_RESUME_TIMEOUT); | |
1746 | spin_lock_irqsave(&xhci->lock, flags); | |
1747 | } | |
1748 | for_each_set_bit(port_index, &bus_state->bus_suspended, | |
1749 | BITS_PER_LONG) { | |
1750 | /* Clear PLC to poll it later for U0 transition */ | |
eaefcf24 | 1751 | xhci_test_and_clear_bit(xhci, ports[port_index], |
a85c0f8d | 1752 | PORT_PLC); |
6b7f40f7 | 1753 | xhci_set_link_state(xhci, ports[port_index], XDEV_U0); |
a85c0f8d | 1754 | } |
41485a90 MN |
1755 | } |
1756 | ||
a85c0f8d MN |
1757 | /* poll for U0 link state complete, both USB2 and USB3 */ |
1758 | for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) { | |
e740b019 | 1759 | sret = xhci_handshake(ports[port_index]->addr, PORT_PLC, |
41485a90 | 1760 | PORT_PLC, 10 * 1000); |
a85c0f8d | 1761 | if (sret) { |
41485a90 MN |
1762 | xhci_warn(xhci, "port %d resume PLC timeout\n", |
1763 | port_index); | |
a85c0f8d MN |
1764 | continue; |
1765 | } | |
eaefcf24 | 1766 | xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC); |
41485a90 MN |
1767 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1); |
1768 | if (slot_id) | |
1769 | xhci_ring_device(xhci, slot_id); | |
1770 | } | |
b0ba9720 | 1771 | (void) readl(&xhci->op_regs->command); |
9777e3ce | 1772 | |
20b67cf5 | 1773 | bus_state->next_statechange = jiffies + msecs_to_jiffies(5); |
9777e3ce | 1774 | /* re-enable irqs */ |
b0ba9720 | 1775 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1776 | temp |= CMD_EIE; |
204b7793 | 1777 | writel(temp, &xhci->op_regs->command); |
b0ba9720 | 1778 | temp = readl(&xhci->op_regs->command); |
9777e3ce AX |
1779 | |
1780 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1781 | return 0; | |
1782 | } | |
1783 | ||
8f9cc83c AS |
1784 | unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd) |
1785 | { | |
f6187f42 | 1786 | struct xhci_hub *rhub = xhci_get_rhub(hcd); |
8f9cc83c AS |
1787 | |
1788 | /* USB3 port wakeups are reported via usb_wakeup_notification() */ | |
f6187f42 | 1789 | return rhub->bus_state.resuming_ports; /* USB2 ports only */ |
8f9cc83c AS |
1790 | } |
1791 | ||
436a3890 | 1792 | #endif /* CONFIG_PM */ |