Commit | Line | Data |
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0f2a7930 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
ddba5cd0 MN |
23 | |
24 | #include <linux/slab.h> | |
0f2a7930 SS |
25 | #include <asm/unaligned.h> |
26 | ||
27 | #include "xhci.h" | |
4bdfe4c3 | 28 | #include "xhci-trace.h" |
0f2a7930 | 29 | |
9777e3ce AX |
30 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
31 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ | |
32 | PORT_RC | PORT_PLC | PORT_PE) | |
33 | ||
5693e0b7 MN |
34 | /* USB 3 BOS descriptor and a capability descriptors, combined. |
35 | * Fields will be adjusted and added later in xhci_create_usb3_bos_desc() | |
36 | */ | |
48e82361 SS |
37 | static u8 usb_bos_descriptor [] = { |
38 | USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ | |
39 | USB_DT_BOS, /* __u8 bDescriptorType */ | |
40 | 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ | |
41 | 0x1, /* __u8 bNumDeviceCaps */ | |
5693e0b7 | 42 | /* First device capability, SuperSpeed */ |
48e82361 SS |
43 | USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ |
44 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ | |
45 | USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ | |
46 | 0x00, /* bmAttributes, LTM off by default */ | |
47 | USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ | |
48 | 0x03, /* bFunctionalitySupport, | |
49 | USB 3.0 speed only */ | |
50 | 0x00, /* bU1DevExitLat, set later. */ | |
5693e0b7 MN |
51 | 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */ |
52 | /* Second device capability, SuperSpeedPlus */ | |
5da665fc | 53 | 0x1c, /* bLength 28, will be adjusted later */ |
5693e0b7 MN |
54 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ |
55 | USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */ | |
56 | 0x00, /* bReserved 0 */ | |
5da665fc MN |
57 | 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */ |
58 | 0x01, 0x00, /* wFunctionalitySupport */ | |
5693e0b7 | 59 | 0x00, 0x00, /* wReserved 0 */ |
5da665fc MN |
60 | /* Default Sublink Speed Attributes, overwrite if custom PSI exists */ |
61 | 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */ | |
62 | 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */ | |
63 | 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */ | |
64 | 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */ | |
48e82361 SS |
65 | }; |
66 | ||
5693e0b7 MN |
67 | static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf, |
68 | u16 wLength) | |
69 | { | |
70 | int i, ssa_count; | |
71 | u32 temp; | |
72 | u16 desc_size, ssp_cap_size, ssa_size = 0; | |
73 | bool usb3_1 = false; | |
74 | ||
75 | desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
76 | ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size; | |
77 | ||
78 | /* does xhci support USB 3.1 Enhanced SuperSpeed */ | |
5da665fc MN |
79 | if (xhci->usb3_rhub.min_rev >= 0x01) { |
80 | /* does xhci provide a PSI table for SSA speed attributes? */ | |
81 | if (xhci->usb3_rhub.psi_count) { | |
82 | /* two SSA entries for each unique PSI ID, RX and TX */ | |
83 | ssa_count = xhci->usb3_rhub.psi_uid_count * 2; | |
84 | ssa_size = ssa_count * sizeof(u32); | |
85 | ssp_cap_size -= 16; /* skip copying the default SSA */ | |
86 | } | |
5693e0b7 MN |
87 | desc_size += ssp_cap_size; |
88 | usb3_1 = true; | |
89 | } | |
90 | memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength)); | |
91 | ||
92 | if (usb3_1) { | |
93 | /* modify bos descriptor bNumDeviceCaps and wTotalLength */ | |
94 | buf[4] += 1; | |
95 | put_unaligned_le16(desc_size + ssa_size, &buf[2]); | |
96 | } | |
97 | ||
98 | if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) | |
99 | return wLength; | |
100 | ||
101 | /* Indicate whether the host has LTM support. */ | |
102 | temp = readl(&xhci->cap_regs->hcc_params); | |
103 | if (HCC_LTC(temp)) | |
104 | buf[8] |= USB_LTM_SUPPORT; | |
105 | ||
106 | /* Set the U1 and U2 exit latencies. */ | |
107 | if ((xhci->quirks & XHCI_LPM_SUPPORT)) { | |
108 | temp = readl(&xhci->cap_regs->hcs_params3); | |
109 | buf[12] = HCS_U1_LATENCY(temp); | |
110 | put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); | |
111 | } | |
112 | ||
5da665fc MN |
113 | /* If PSI table exists, add the custom speed attributes from it */ |
114 | if (usb3_1 && xhci->usb3_rhub.psi_count) { | |
5693e0b7 MN |
115 | u32 ssp_cap_base, bm_attrib, psi; |
116 | int offset; | |
117 | ||
118 | ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
119 | ||
120 | if (wLength < desc_size) | |
121 | return wLength; | |
122 | buf[ssp_cap_base] = ssp_cap_size + ssa_size; | |
123 | ||
124 | /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */ | |
125 | bm_attrib = (ssa_count - 1) & 0x1f; | |
126 | bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5; | |
127 | put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]); | |
128 | ||
129 | if (wLength < desc_size + ssa_size) | |
130 | return wLength; | |
131 | /* | |
132 | * Create the Sublink Speed Attributes (SSA) array. | |
133 | * The xhci PSI field and USB 3.1 SSA fields are very similar, | |
134 | * but link type bits 7:6 differ for values 01b and 10b. | |
135 | * xhci has also only one PSI entry for a symmetric link when | |
136 | * USB 3.1 requires two SSA entries (RX and TX) for every link | |
137 | */ | |
138 | offset = desc_size; | |
139 | for (i = 0; i < xhci->usb3_rhub.psi_count; i++) { | |
140 | psi = xhci->usb3_rhub.psi[i]; | |
141 | psi &= ~USB_SSP_SUBLINK_SPEED_RSVD; | |
142 | if ((psi & PLT_MASK) == PLT_SYM) { | |
143 | /* Symmetric, create SSA RX and TX from one PSI entry */ | |
144 | put_unaligned_le32(psi, &buf[offset]); | |
145 | psi |= 1 << 7; /* turn entry to TX */ | |
146 | offset += 4; | |
147 | if (offset >= desc_size + ssa_size) | |
148 | return desc_size + ssa_size; | |
149 | } else if ((psi & PLT_MASK) == PLT_ASYM_RX) { | |
150 | /* Asymetric RX, flip bits 7:6 for SSA */ | |
151 | psi ^= PLT_MASK; | |
152 | } | |
153 | put_unaligned_le32(psi, &buf[offset]); | |
154 | offset += 4; | |
155 | if (offset >= desc_size + ssa_size) | |
156 | return desc_size + ssa_size; | |
157 | } | |
158 | } | |
159 | /* ssa_size is 0 for other than usb 3.1 hosts */ | |
160 | return desc_size + ssa_size; | |
161 | } | |
48e82361 | 162 | |
4bbb0ace SS |
163 | static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, |
164 | struct usb_hub_descriptor *desc, int ports) | |
0f2a7930 | 165 | { |
0f2a7930 SS |
166 | u16 temp; |
167 | ||
0f2a7930 SS |
168 | desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ |
169 | desc->bHubContrCurrent = 0; | |
170 | ||
171 | desc->bNbrPorts = ports; | |
0f2a7930 | 172 | temp = 0; |
c8421147 | 173 | /* Bits 1:0 - support per-port power switching, or power always on */ |
0f2a7930 | 174 | if (HCC_PPC(xhci->hcc_params)) |
c8421147 | 175 | temp |= HUB_CHAR_INDV_PORT_LPSM; |
0f2a7930 | 176 | else |
c8421147 | 177 | temp |= HUB_CHAR_NO_LPSM; |
0f2a7930 SS |
178 | /* Bit 2 - root hubs are not part of a compound device */ |
179 | /* Bits 4:3 - individual port over current protection */ | |
c8421147 | 180 | temp |= HUB_CHAR_INDV_PORT_OCPM; |
0f2a7930 SS |
181 | /* Bits 6:5 - no TTs in root ports */ |
182 | /* Bit 7 - no port indicators */ | |
28ccd296 | 183 | desc->wHubCharacteristics = cpu_to_le16(temp); |
0f2a7930 SS |
184 | } |
185 | ||
4bbb0ace SS |
186 | /* Fill in the USB 2.0 roothub descriptor */ |
187 | static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
188 | struct usb_hub_descriptor *desc) | |
189 | { | |
190 | int ports; | |
191 | u16 temp; | |
192 | __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; | |
193 | u32 portsc; | |
194 | unsigned int i; | |
195 | ||
196 | ports = xhci->num_usb2_ports; | |
197 | ||
198 | xhci_common_hub_descriptor(xhci, desc, ports); | |
c8421147 | 199 | desc->bDescriptorType = USB_DT_HUB; |
4bbb0ace | 200 | temp = 1 + (ports / 8); |
c8421147 | 201 | desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; |
4bbb0ace SS |
202 | |
203 | /* The Device Removable bits are reported on a byte granularity. | |
204 | * If the port doesn't exist within that byte, the bit is set to 0. | |
205 | */ | |
206 | memset(port_removable, 0, sizeof(port_removable)); | |
207 | for (i = 0; i < ports; i++) { | |
b0ba9720 | 208 | portsc = readl(xhci->usb2_ports[i]); |
4bbb0ace SS |
209 | /* If a device is removable, PORTSC reports a 0, same as in the |
210 | * hub descriptor DeviceRemovable bits. | |
211 | */ | |
212 | if (portsc & PORT_DEV_REMOVE) | |
213 | /* This math is hairy because bit 0 of DeviceRemovable | |
214 | * is reserved, and bit 1 is for port 1, etc. | |
215 | */ | |
216 | port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); | |
217 | } | |
218 | ||
219 | /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN | |
220 | * ports on it. The USB 2.0 specification says that there are two | |
221 | * variable length fields at the end of the hub descriptor: | |
222 | * DeviceRemovable and PortPwrCtrlMask. But since we can have less than | |
223 | * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array | |
224 | * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to | |
225 | * 0xFF, so we initialize the both arrays (DeviceRemovable and | |
226 | * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each | |
227 | * set of ports that actually exist. | |
228 | */ | |
229 | memset(desc->u.hs.DeviceRemovable, 0xff, | |
230 | sizeof(desc->u.hs.DeviceRemovable)); | |
231 | memset(desc->u.hs.PortPwrCtrlMask, 0xff, | |
232 | sizeof(desc->u.hs.PortPwrCtrlMask)); | |
233 | ||
234 | for (i = 0; i < (ports + 1 + 7) / 8; i++) | |
235 | memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], | |
236 | sizeof(__u8)); | |
237 | } | |
238 | ||
239 | /* Fill in the USB 3.0 roothub descriptor */ | |
240 | static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
241 | struct usb_hub_descriptor *desc) | |
242 | { | |
243 | int ports; | |
244 | u16 port_removable; | |
245 | u32 portsc; | |
246 | unsigned int i; | |
247 | ||
248 | ports = xhci->num_usb3_ports; | |
249 | xhci_common_hub_descriptor(xhci, desc, ports); | |
c8421147 AD |
250 | desc->bDescriptorType = USB_DT_SS_HUB; |
251 | desc->bDescLength = USB_DT_SS_HUB_SIZE; | |
4bbb0ace SS |
252 | |
253 | /* header decode latency should be zero for roothubs, | |
254 | * see section 4.23.5.2. | |
255 | */ | |
256 | desc->u.ss.bHubHdrDecLat = 0; | |
257 | desc->u.ss.wHubDelay = 0; | |
258 | ||
259 | port_removable = 0; | |
260 | /* bit 0 is reserved, bit 1 is for port 1, etc. */ | |
261 | for (i = 0; i < ports; i++) { | |
b0ba9720 | 262 | portsc = readl(xhci->usb3_ports[i]); |
4bbb0ace SS |
263 | if (portsc & PORT_DEV_REMOVE) |
264 | port_removable |= 1 << (i + 1); | |
265 | } | |
27c411c9 LT |
266 | |
267 | desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); | |
4bbb0ace SS |
268 | } |
269 | ||
270 | static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
271 | struct usb_hub_descriptor *desc) | |
272 | { | |
273 | ||
b50107bb | 274 | if (hcd->speed >= HCD_USB3) |
4bbb0ace SS |
275 | xhci_usb3_hub_descriptor(hcd, xhci, desc); |
276 | else | |
277 | xhci_usb2_hub_descriptor(hcd, xhci, desc); | |
278 | ||
279 | } | |
280 | ||
0f2a7930 SS |
281 | static unsigned int xhci_port_speed(unsigned int port_status) |
282 | { | |
283 | if (DEV_LOWSPEED(port_status)) | |
288ead45 | 284 | return USB_PORT_STAT_LOW_SPEED; |
0f2a7930 | 285 | if (DEV_HIGHSPEED(port_status)) |
288ead45 | 286 | return USB_PORT_STAT_HIGH_SPEED; |
0f2a7930 SS |
287 | /* |
288 | * FIXME: Yes, we should check for full speed, but the core uses that as | |
289 | * a default in portspeed() in usb/core/hub.c (which is the only place | |
288ead45 | 290 | * USB_PORT_STAT_*_SPEED is used). |
0f2a7930 SS |
291 | */ |
292 | return 0; | |
293 | } | |
294 | ||
295 | /* | |
296 | * These bits are Read Only (RO) and should be saved and written to the | |
297 | * registers: 0, 3, 10:13, 30 | |
298 | * connect status, over-current status, port speed, and device removable. | |
299 | * connect status and port speed are also sticky - meaning they're in | |
300 | * the AUX well and they aren't changed by a hot, warm, or cold reset. | |
301 | */ | |
302 | #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) | |
303 | /* | |
304 | * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: | |
305 | * bits 5:8, 9, 14:15, 25:27 | |
306 | * link state, port power, port indicator state, "wake on" enable state | |
307 | */ | |
308 | #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) | |
309 | /* | |
310 | * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: | |
311 | * bit 4 (port reset) | |
312 | */ | |
313 | #define XHCI_PORT_RW1S ((1<<4)) | |
314 | /* | |
315 | * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: | |
316 | * bits 1, 17, 18, 19, 20, 21, 22, 23 | |
317 | * port enable/disable, and | |
318 | * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), | |
319 | * over-current, reset, link state, and L1 change | |
320 | */ | |
321 | #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) | |
322 | /* | |
323 | * Bit 16 is RW, and writing a '1' to it causes the link state control to be | |
324 | * latched in | |
325 | */ | |
326 | #define XHCI_PORT_RW ((1<<16)) | |
327 | /* | |
328 | * These bits are Reserved Zero (RsvdZ) and zero should be written to them: | |
329 | * bits 2, 24, 28:31 | |
330 | */ | |
331 | #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) | |
332 | ||
333 | /* | |
334 | * Given a port state, this function returns a value that would result in the | |
335 | * port being in the same state, if the value was written to the port status | |
336 | * control register. | |
337 | * Save Read Only (RO) bits and save read/write bits where | |
338 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). | |
339 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. | |
340 | */ | |
56192531 | 341 | u32 xhci_port_state_to_neutral(u32 state) |
0f2a7930 SS |
342 | { |
343 | /* Save read-only status and port state */ | |
344 | return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); | |
345 | } | |
346 | ||
be88fe4f AX |
347 | /* |
348 | * find slot id based on port number. | |
f6ff0ac8 | 349 | * @port: The one-based port number from one of the two split roothubs. |
be88fe4f | 350 | */ |
5233630f SS |
351 | int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
352 | u16 port) | |
be88fe4f AX |
353 | { |
354 | int slot_id; | |
355 | int i; | |
f6ff0ac8 | 356 | enum usb_device_speed speed; |
be88fe4f AX |
357 | |
358 | slot_id = 0; | |
359 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
360 | if (!xhci->devs[i]) | |
361 | continue; | |
f6ff0ac8 | 362 | speed = xhci->devs[i]->udev->speed; |
b50107bb | 363 | if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3)) |
fe30182c | 364 | && xhci->devs[i]->fake_port == port) { |
be88fe4f AX |
365 | slot_id = i; |
366 | break; | |
367 | } | |
368 | } | |
369 | ||
370 | return slot_id; | |
371 | } | |
372 | ||
373 | /* | |
374 | * Stop device | |
375 | * It issues stop endpoint command for EP 0 to 30. And wait the last command | |
376 | * to complete. | |
377 | * suspend will set to 1, if suspend bit need to set in command. | |
378 | */ | |
379 | static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) | |
380 | { | |
381 | struct xhci_virt_device *virt_dev; | |
382 | struct xhci_command *cmd; | |
383 | unsigned long flags; | |
be88fe4f AX |
384 | int ret; |
385 | int i; | |
386 | ||
387 | ret = 0; | |
388 | virt_dev = xhci->devs[slot_id]; | |
88716a93 JL |
389 | if (!virt_dev) |
390 | return -ENODEV; | |
391 | ||
a711edee FB |
392 | trace_xhci_stop_device(virt_dev); |
393 | ||
be88fe4f | 394 | cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); |
74e0b564 | 395 | if (!cmd) |
be88fe4f | 396 | return -ENOMEM; |
be88fe4f AX |
397 | |
398 | spin_lock_irqsave(&xhci->lock, flags); | |
399 | for (i = LAST_EP_INDEX; i > 0; i--) { | |
ddba5cd0 | 400 | if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { |
28a2369f | 401 | struct xhci_ep_ctx *ep_ctx; |
ddba5cd0 | 402 | struct xhci_command *command; |
28a2369f SS |
403 | |
404 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i); | |
405 | ||
406 | /* Check ep is running, required by AMD SNPS 3.1 xHC */ | |
407 | if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING) | |
408 | continue; | |
409 | ||
ddba5cd0 | 410 | command = xhci_alloc_command(xhci, false, false, |
be3de321 | 411 | GFP_NOWAIT); |
ddba5cd0 MN |
412 | if (!command) { |
413 | spin_unlock_irqrestore(&xhci->lock, flags); | |
414 | xhci_free_command(xhci, cmd); | |
415 | return -ENOMEM; | |
ddba5cd0 MN |
416 | } |
417 | xhci_queue_stop_endpoint(xhci, command, slot_id, i, | |
418 | suspend); | |
419 | } | |
be88fe4f | 420 | } |
ddba5cd0 | 421 | xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); |
be88fe4f AX |
422 | xhci_ring_cmd_db(xhci); |
423 | spin_unlock_irqrestore(&xhci->lock, flags); | |
424 | ||
425 | /* Wait for last stop endpoint command to finish */ | |
c311e391 MN |
426 | wait_for_completion(cmd->completion); |
427 | ||
0b7c105a | 428 | if (cmd->status == COMP_COMMAND_ABORTED || |
604d02a2 | 429 | cmd->status == COMP_COMMAND_RING_STOPPED) { |
c311e391 | 430 | xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); |
be88fe4f | 431 | ret = -ETIME; |
be88fe4f | 432 | } |
be88fe4f AX |
433 | xhci_free_command(xhci, cmd); |
434 | return ret; | |
435 | } | |
436 | ||
437 | /* | |
438 | * Ring device, it rings the all doorbells unconditionally. | |
439 | */ | |
56192531 | 440 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) |
be88fe4f | 441 | { |
b7f9696b HG |
442 | int i, s; |
443 | struct xhci_virt_ep *ep; | |
444 | ||
445 | for (i = 0; i < LAST_EP_INDEX + 1; i++) { | |
446 | ep = &xhci->devs[slot_id]->eps[i]; | |
be88fe4f | 447 | |
b7f9696b HG |
448 | if (ep->ep_state & EP_HAS_STREAMS) { |
449 | for (s = 1; s < ep->stream_info->num_streams; s++) | |
450 | xhci_ring_ep_doorbell(xhci, slot_id, i, s); | |
451 | } else if (ep->ring && ep->ring->dequeue) { | |
be88fe4f | 452 | xhci_ring_ep_doorbell(xhci, slot_id, i, 0); |
b7f9696b HG |
453 | } |
454 | } | |
be88fe4f AX |
455 | |
456 | return; | |
457 | } | |
458 | ||
f6ff0ac8 | 459 | static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
28ccd296 | 460 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
6219c047 | 461 | { |
6dd0a3a7 | 462 | /* Don't allow the USB core to disable SuperSpeed ports. */ |
b50107bb | 463 | if (hcd->speed >= HCD_USB3) { |
6dd0a3a7 SS |
464 | xhci_dbg(xhci, "Ignoring request to disable " |
465 | "SuperSpeed port.\n"); | |
466 | return; | |
467 | } | |
468 | ||
41135de1 FB |
469 | if (xhci->quirks & XHCI_BROKEN_PORT_PED) { |
470 | xhci_dbg(xhci, | |
471 | "Broken Port Enabled/Disabled, ignoring port disable request.\n"); | |
472 | return; | |
473 | } | |
474 | ||
6219c047 | 475 | /* Write 1 to disable the port */ |
204b7793 | 476 | writel(port_status | PORT_PE, addr); |
b0ba9720 | 477 | port_status = readl(addr); |
6219c047 SS |
478 | xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", |
479 | wIndex, port_status); | |
480 | } | |
481 | ||
34fb562a | 482 | static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, |
28ccd296 | 483 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
34fb562a SS |
484 | { |
485 | char *port_change_bit; | |
486 | u32 status; | |
487 | ||
488 | switch (wValue) { | |
489 | case USB_PORT_FEAT_C_RESET: | |
490 | status = PORT_RC; | |
491 | port_change_bit = "reset"; | |
492 | break; | |
a11496eb AX |
493 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
494 | status = PORT_WRC; | |
495 | port_change_bit = "warm(BH) reset"; | |
496 | break; | |
34fb562a SS |
497 | case USB_PORT_FEAT_C_CONNECTION: |
498 | status = PORT_CSC; | |
499 | port_change_bit = "connect"; | |
500 | break; | |
501 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
502 | status = PORT_OCC; | |
503 | port_change_bit = "over-current"; | |
504 | break; | |
6219c047 SS |
505 | case USB_PORT_FEAT_C_ENABLE: |
506 | status = PORT_PEC; | |
507 | port_change_bit = "enable/disable"; | |
508 | break; | |
be88fe4f AX |
509 | case USB_PORT_FEAT_C_SUSPEND: |
510 | status = PORT_PLC; | |
511 | port_change_bit = "suspend/resume"; | |
512 | break; | |
85387c0e AX |
513 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
514 | status = PORT_PLC; | |
515 | port_change_bit = "link state"; | |
516 | break; | |
9425183d LB |
517 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
518 | status = PORT_CEC; | |
519 | port_change_bit = "config error"; | |
520 | break; | |
34fb562a SS |
521 | default: |
522 | /* Should never happen */ | |
523 | return; | |
524 | } | |
525 | /* Change bits are all write 1 to clear */ | |
204b7793 | 526 | writel(port_status | status, addr); |
b0ba9720 | 527 | port_status = readl(addr); |
34fb562a SS |
528 | xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", |
529 | port_change_bit, wIndex, port_status); | |
530 | } | |
531 | ||
a0885924 | 532 | static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array) |
533 | { | |
534 | int max_ports; | |
535 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
536 | ||
b50107bb | 537 | if (hcd->speed >= HCD_USB3) { |
a0885924 | 538 | max_ports = xhci->num_usb3_ports; |
539 | *port_array = xhci->usb3_ports; | |
540 | } else { | |
541 | max_ports = xhci->num_usb2_ports; | |
542 | *port_array = xhci->usb2_ports; | |
543 | } | |
544 | ||
545 | return max_ports; | |
546 | } | |
547 | ||
a6ff6cbf GZ |
548 | static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index) |
549 | { | |
550 | __le32 __iomem **port_array; | |
551 | ||
552 | xhci_get_ports(hcd, &port_array); | |
553 | return port_array[index]; | |
554 | } | |
555 | ||
556 | /* | |
557 | * xhci_set_port_power() must be called with xhci->lock held. | |
558 | * It will release and re-aquire the lock while calling ACPI | |
559 | * method. | |
560 | */ | |
561 | static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, | |
ec1dafe8 | 562 | u16 index, bool on, unsigned long *flags) |
a6ff6cbf GZ |
563 | { |
564 | __le32 __iomem *addr; | |
565 | u32 temp; | |
a6ff6cbf GZ |
566 | |
567 | addr = xhci_get_port_io_addr(hcd, index); | |
568 | temp = readl(addr); | |
569 | temp = xhci_port_state_to_neutral(temp); | |
570 | if (on) { | |
571 | /* Power on */ | |
572 | writel(temp | PORT_POWER, addr); | |
573 | temp = readl(addr); | |
574 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", | |
575 | index, temp); | |
576 | } else { | |
577 | /* Power off */ | |
578 | writel(temp & ~PORT_POWER, addr); | |
579 | } | |
580 | ||
ec1dafe8 | 581 | spin_unlock_irqrestore(&xhci->lock, *flags); |
a6ff6cbf GZ |
582 | temp = usb_acpi_power_manageable(hcd->self.root_hub, |
583 | index); | |
584 | if (temp) | |
585 | usb_acpi_set_power_state(hcd->self.root_hub, | |
586 | index, on); | |
ec1dafe8 | 587 | spin_lock_irqsave(&xhci->lock, *flags); |
a6ff6cbf GZ |
588 | } |
589 | ||
0f1d832e GZ |
590 | static void xhci_port_set_test_mode(struct xhci_hcd *xhci, |
591 | u16 test_mode, u16 wIndex) | |
592 | { | |
593 | u32 temp; | |
594 | __le32 __iomem *addr; | |
595 | ||
596 | /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */ | |
597 | addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex); | |
598 | temp = readl(addr + PORTPMSC); | |
599 | temp |= test_mode << PORT_TEST_MODE_SHIFT; | |
600 | writel(temp, addr + PORTPMSC); | |
601 | xhci->test_mode = test_mode; | |
602 | if (test_mode == TEST_FORCE_EN) | |
603 | xhci_start(xhci); | |
604 | } | |
605 | ||
606 | static int xhci_enter_test_mode(struct xhci_hcd *xhci, | |
ec1dafe8 | 607 | u16 test_mode, u16 wIndex, unsigned long *flags) |
0f1d832e GZ |
608 | { |
609 | int i, retval; | |
610 | ||
611 | /* Disable all Device Slots */ | |
612 | xhci_dbg(xhci, "Disable all slots\n"); | |
613 | for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { | |
614 | retval = xhci_disable_slot(xhci, NULL, i); | |
615 | if (retval) | |
616 | xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", | |
617 | i, retval); | |
618 | } | |
619 | /* Put all ports to the Disable state by clear PP */ | |
620 | xhci_dbg(xhci, "Disable all port (PP = 0)\n"); | |
621 | /* Power off USB3 ports*/ | |
622 | for (i = 0; i < xhci->num_usb3_ports; i++) | |
ec1dafe8 | 623 | xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags); |
0f1d832e GZ |
624 | /* Power off USB2 ports*/ |
625 | for (i = 0; i < xhci->num_usb2_ports; i++) | |
ec1dafe8 | 626 | xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags); |
0f1d832e GZ |
627 | /* Stop the controller */ |
628 | xhci_dbg(xhci, "Stop controller\n"); | |
629 | retval = xhci_halt(xhci); | |
630 | if (retval) | |
631 | return retval; | |
632 | /* Disable runtime PM for test mode */ | |
633 | pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); | |
634 | /* Set PORTPMSC.PTC field to enter selected test mode */ | |
635 | /* Port is selected by wIndex. port_id = wIndex + 1 */ | |
636 | xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n", | |
637 | test_mode, wIndex + 1); | |
638 | xhci_port_set_test_mode(xhci, test_mode, wIndex); | |
639 | return retval; | |
640 | } | |
641 | ||
642 | static int xhci_exit_test_mode(struct xhci_hcd *xhci) | |
643 | { | |
644 | int retval; | |
645 | ||
646 | if (!xhci->test_mode) { | |
647 | xhci_err(xhci, "Not in test mode, do nothing.\n"); | |
648 | return 0; | |
649 | } | |
650 | if (xhci->test_mode == TEST_FORCE_EN && | |
651 | !(xhci->xhc_state & XHCI_STATE_HALTED)) { | |
652 | retval = xhci_halt(xhci); | |
653 | if (retval) | |
654 | return retval; | |
655 | } | |
656 | pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); | |
657 | xhci->test_mode = 0; | |
658 | return xhci_reset(xhci); | |
659 | } | |
660 | ||
c9682dff AX |
661 | void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, |
662 | int port_id, u32 link_state) | |
663 | { | |
664 | u32 temp; | |
665 | ||
b0ba9720 | 666 | temp = readl(port_array[port_id]); |
c9682dff AX |
667 | temp = xhci_port_state_to_neutral(temp); |
668 | temp &= ~PORT_PLS_MASK; | |
669 | temp |= PORT_LINK_STROBE | link_state; | |
204b7793 | 670 | writel(temp, port_array[port_id]); |
c9682dff AX |
671 | } |
672 | ||
ed384bd3 | 673 | static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, |
4296c70a SS |
674 | __le32 __iomem **port_array, int port_id, u16 wake_mask) |
675 | { | |
676 | u32 temp; | |
677 | ||
b0ba9720 | 678 | temp = readl(port_array[port_id]); |
4296c70a SS |
679 | temp = xhci_port_state_to_neutral(temp); |
680 | ||
681 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) | |
682 | temp |= PORT_WKCONN_E; | |
683 | else | |
684 | temp &= ~PORT_WKCONN_E; | |
685 | ||
686 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) | |
687 | temp |= PORT_WKDISC_E; | |
688 | else | |
689 | temp &= ~PORT_WKDISC_E; | |
690 | ||
691 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) | |
692 | temp |= PORT_WKOC_E; | |
693 | else | |
694 | temp &= ~PORT_WKOC_E; | |
695 | ||
204b7793 | 696 | writel(temp, port_array[port_id]); |
4296c70a SS |
697 | } |
698 | ||
d2f52c9e AX |
699 | /* Test and clear port RWC bit */ |
700 | void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, | |
701 | int port_id, u32 port_bit) | |
702 | { | |
703 | u32 temp; | |
704 | ||
b0ba9720 | 705 | temp = readl(port_array[port_id]); |
d2f52c9e AX |
706 | if (temp & port_bit) { |
707 | temp = xhci_port_state_to_neutral(temp); | |
708 | temp |= port_bit; | |
204b7793 | 709 | writel(temp, port_array[port_id]); |
d2f52c9e AX |
710 | } |
711 | } | |
712 | ||
063ebeb4 SS |
713 | /* Updates Link Status for USB 2.1 port */ |
714 | static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg) | |
715 | { | |
716 | if ((status_reg & PORT_PLS_MASK) == XDEV_U2) | |
717 | *status |= USB_PORT_STAT_L1; | |
718 | } | |
719 | ||
8bea2bd3 | 720 | /* Updates Link Status for super Speed port */ |
96908589 FB |
721 | static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, |
722 | u32 *status, u32 status_reg) | |
8bea2bd3 SL |
723 | { |
724 | u32 pls = status_reg & PORT_PLS_MASK; | |
725 | ||
726 | /* resume state is a xHCI internal state. | |
243292a2 ZJC |
727 | * Do not report it to usb core, instead, pretend to be U3, |
728 | * thus usb core knows it's not ready for transfer | |
8bea2bd3 | 729 | */ |
243292a2 ZJC |
730 | if (pls == XDEV_RESUME) { |
731 | *status |= USB_SS_PORT_LS_U3; | |
8bea2bd3 | 732 | return; |
243292a2 | 733 | } |
8bea2bd3 SL |
734 | |
735 | /* When the CAS bit is set then warm reset | |
736 | * should be performed on port | |
737 | */ | |
738 | if (status_reg & PORT_CAS) { | |
739 | /* The CAS bit can be set while the port is | |
740 | * in any link state. | |
741 | * Only roothubs have CAS bit, so we | |
742 | * pretend to be in compliance mode | |
743 | * unless we're already in compliance | |
744 | * or the inactive state. | |
745 | */ | |
746 | if (pls != USB_SS_PORT_LS_COMP_MOD && | |
747 | pls != USB_SS_PORT_LS_SS_INACTIVE) { | |
748 | pls = USB_SS_PORT_LS_COMP_MOD; | |
749 | } | |
750 | /* Return also connection bit - | |
751 | * hub state machine resets port | |
752 | * when this bit is set. | |
753 | */ | |
754 | pls |= USB_PORT_STAT_CONNECTION; | |
71c731a2 AC |
755 | } else { |
756 | /* | |
757 | * If CAS bit isn't set but the Port is already at | |
758 | * Compliance Mode, fake a connection so the USB core | |
759 | * notices the Compliance state and resets the port. | |
760 | * This resolves an issue generated by the SN65LVPE502CP | |
761 | * in which sometimes the port enters compliance mode | |
762 | * caused by a delay on the host-device negotiation. | |
763 | */ | |
96908589 FB |
764 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && |
765 | (pls == USB_SS_PORT_LS_COMP_MOD)) | |
71c731a2 | 766 | pls |= USB_PORT_STAT_CONNECTION; |
8bea2bd3 | 767 | } |
71c731a2 | 768 | |
8bea2bd3 SL |
769 | /* update status field */ |
770 | *status |= pls; | |
771 | } | |
772 | ||
71c731a2 AC |
773 | /* |
774 | * Function for Compliance Mode Quirk. | |
775 | * | |
776 | * This Function verifies if all xhc USB3 ports have entered U0, if so, | |
777 | * the compliance mode timer is deleted. A port won't enter | |
778 | * compliance mode if it has previously entered U0. | |
779 | */ | |
5f20cf12 SK |
780 | static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, |
781 | u16 wIndex) | |
71c731a2 AC |
782 | { |
783 | u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1); | |
784 | bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); | |
785 | ||
786 | if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) | |
787 | return; | |
788 | ||
789 | if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { | |
790 | xhci->port_status_u0 |= 1 << wIndex; | |
791 | if (xhci->port_status_u0 == all_ports_seen_u0) { | |
792 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
793 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
794 | "All USB3 ports have entered U0 already!"); | |
795 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
796 | "Compliance Mode Recovery Timer Deleted."); | |
71c731a2 AC |
797 | } |
798 | } | |
799 | } | |
800 | ||
395f5409 MN |
801 | static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) |
802 | { | |
803 | u32 ext_stat = 0; | |
804 | int speed_id; | |
805 | ||
806 | /* only support rx and tx lane counts of 1 in usb3.1 spec */ | |
807 | speed_id = DEV_PORT_SPEED(raw_port_status); | |
808 | ext_stat |= speed_id; /* bits 3:0, RX speed id */ | |
809 | ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ | |
810 | ||
811 | ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ | |
812 | ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ | |
813 | ||
814 | return ext_stat; | |
815 | } | |
816 | ||
eae5b176 SS |
817 | /* |
818 | * Converts a raw xHCI port status into the format that external USB 2.0 or USB | |
819 | * 3.0 hubs use. | |
820 | * | |
821 | * Possible side effects: | |
822 | * - Mark a port as being done with device resume, | |
823 | * and ring the endpoint doorbells. | |
824 | * - Stop the Synopsys redriver Compliance Mode polling. | |
8b3d4570 | 825 | * - Drop and reacquire the xHCI lock, in order to wait for port resume. |
eae5b176 SS |
826 | */ |
827 | static u32 xhci_get_port_status(struct usb_hcd *hcd, | |
828 | struct xhci_bus_state *bus_state, | |
829 | __le32 __iomem **port_array, | |
8b3d4570 SS |
830 | u16 wIndex, u32 raw_port_status, |
831 | unsigned long flags) | |
832 | __releases(&xhci->lock) | |
833 | __acquires(&xhci->lock) | |
eae5b176 SS |
834 | { |
835 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
836 | u32 status = 0; | |
837 | int slot_id; | |
838 | ||
839 | /* wPortChange bits */ | |
840 | if (raw_port_status & PORT_CSC) | |
841 | status |= USB_PORT_STAT_C_CONNECTION << 16; | |
842 | if (raw_port_status & PORT_PEC) | |
843 | status |= USB_PORT_STAT_C_ENABLE << 16; | |
844 | if ((raw_port_status & PORT_OCC)) | |
845 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; | |
846 | if ((raw_port_status & PORT_RC)) | |
847 | status |= USB_PORT_STAT_C_RESET << 16; | |
848 | /* USB3.0 only */ | |
b50107bb | 849 | if (hcd->speed >= HCD_USB3) { |
aca3a048 ZJC |
850 | /* Port link change with port in resume state should not be |
851 | * reported to usbcore, as this is an internal state to be | |
852 | * handled by xhci driver. Reporting PLC to usbcore may | |
853 | * cause usbcore clearing PLC first and port change event | |
854 | * irq won't be generated. | |
855 | */ | |
856 | if ((raw_port_status & PORT_PLC) && | |
857 | (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) | |
eae5b176 SS |
858 | status |= USB_PORT_STAT_C_LINK_STATE << 16; |
859 | if ((raw_port_status & PORT_WRC)) | |
860 | status |= USB_PORT_STAT_C_BH_RESET << 16; | |
9425183d LB |
861 | if ((raw_port_status & PORT_CEC)) |
862 | status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; | |
eae5b176 SS |
863 | } |
864 | ||
b50107bb | 865 | if (hcd->speed < HCD_USB3) { |
eae5b176 SS |
866 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3 |
867 | && (raw_port_status & PORT_POWER)) | |
868 | status |= USB_PORT_STAT_SUSPEND; | |
869 | } | |
870 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME && | |
2338b9e4 | 871 | !DEV_SUPERSPEED_ANY(raw_port_status)) { |
eae5b176 SS |
872 | if ((raw_port_status & PORT_RESET) || |
873 | !(raw_port_status & PORT_PE)) | |
874 | return 0xffffffff; | |
f69115fd MN |
875 | /* did port event handler already start resume timing? */ |
876 | if (!bus_state->resume_done[wIndex]) { | |
877 | /* If not, maybe we are in a host initated resume? */ | |
878 | if (test_bit(wIndex, &bus_state->resuming_ports)) { | |
879 | /* Host initated resume doesn't time the resume | |
880 | * signalling using resume_done[]. | |
881 | * It manually sets RESUME state, sleeps 20ms | |
882 | * and sets U0 state. This should probably be | |
883 | * changed, but not right now. | |
884 | */ | |
885 | } else { | |
886 | /* port resume was discovered now and here, | |
887 | * start resume timing | |
888 | */ | |
889 | unsigned long timeout = jiffies + | |
890 | msecs_to_jiffies(USB_RESUME_TIMEOUT); | |
891 | ||
892 | set_bit(wIndex, &bus_state->resuming_ports); | |
893 | bus_state->resume_done[wIndex] = timeout; | |
894 | mod_timer(&hcd->rh_timer, timeout); | |
895 | } | |
896 | /* Has resume been signalled for USB_RESUME_TIME yet? */ | |
897 | } else if (time_after_eq(jiffies, | |
898 | bus_state->resume_done[wIndex])) { | |
8b3d4570 SS |
899 | int time_left; |
900 | ||
eae5b176 SS |
901 | xhci_dbg(xhci, "Resume USB2 port %d\n", |
902 | wIndex + 1); | |
903 | bus_state->resume_done[wIndex] = 0; | |
904 | clear_bit(wIndex, &bus_state->resuming_ports); | |
8b3d4570 SS |
905 | |
906 | set_bit(wIndex, &bus_state->rexit_ports); | |
a54408d0 MN |
907 | |
908 | xhci_test_and_clear_bit(xhci, port_array, wIndex, | |
909 | PORT_PLC); | |
eae5b176 SS |
910 | xhci_set_link_state(xhci, port_array, wIndex, |
911 | XDEV_U0); | |
8b3d4570 SS |
912 | |
913 | spin_unlock_irqrestore(&xhci->lock, flags); | |
914 | time_left = wait_for_completion_timeout( | |
915 | &bus_state->rexit_done[wIndex], | |
916 | msecs_to_jiffies( | |
917 | XHCI_MAX_REXIT_TIMEOUT)); | |
918 | spin_lock_irqsave(&xhci->lock, flags); | |
919 | ||
920 | if (time_left) { | |
921 | slot_id = xhci_find_slot_id_by_port(hcd, | |
922 | xhci, wIndex + 1); | |
923 | if (!slot_id) { | |
924 | xhci_dbg(xhci, "slot_id is zero\n"); | |
925 | return 0xffffffff; | |
926 | } | |
927 | xhci_ring_device(xhci, slot_id); | |
928 | } else { | |
b0ba9720 | 929 | int port_status = readl(port_array[wIndex]); |
8b3d4570 SS |
930 | xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n", |
931 | XHCI_MAX_REXIT_TIMEOUT, | |
932 | port_status); | |
933 | status |= USB_PORT_STAT_SUSPEND; | |
934 | clear_bit(wIndex, &bus_state->rexit_ports); | |
eae5b176 | 935 | } |
8b3d4570 | 936 | |
eae5b176 SS |
937 | bus_state->port_c_suspend |= 1 << wIndex; |
938 | bus_state->suspended_ports &= ~(1 << wIndex); | |
939 | } else { | |
940 | /* | |
941 | * The resume has been signaling for less than | |
f69115fd MN |
942 | * USB_RESUME_TIME. Report the port status as SUSPEND, |
943 | * let the usbcore check port status again and clear | |
944 | * resume signaling later. | |
eae5b176 SS |
945 | */ |
946 | status |= USB_PORT_STAT_SUSPEND; | |
947 | } | |
948 | } | |
f69115fd MN |
949 | /* |
950 | * Clear stale usb2 resume signalling variables in case port changed | |
951 | * state during resume signalling. For example on error | |
952 | */ | |
953 | if ((bus_state->resume_done[wIndex] || | |
954 | test_bit(wIndex, &bus_state->resuming_ports)) && | |
955 | (raw_port_status & PORT_PLS_MASK) != XDEV_U3 && | |
956 | (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) { | |
957 | bus_state->resume_done[wIndex] = 0; | |
958 | clear_bit(wIndex, &bus_state->resuming_ports); | |
959 | } | |
960 | ||
961 | ||
dad67d5f MN |
962 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 && |
963 | (raw_port_status & PORT_POWER)) { | |
964 | if (bus_state->suspended_ports & (1 << wIndex)) { | |
965 | bus_state->suspended_ports &= ~(1 << wIndex); | |
966 | if (hcd->speed < HCD_USB3) | |
967 | bus_state->port_c_suspend |= 1 << wIndex; | |
968 | } | |
969 | bus_state->resume_done[wIndex] = 0; | |
970 | clear_bit(wIndex, &bus_state->resuming_ports); | |
eae5b176 SS |
971 | } |
972 | if (raw_port_status & PORT_CONNECT) { | |
973 | status |= USB_PORT_STAT_CONNECTION; | |
974 | status |= xhci_port_speed(raw_port_status); | |
975 | } | |
976 | if (raw_port_status & PORT_PE) | |
977 | status |= USB_PORT_STAT_ENABLE; | |
978 | if (raw_port_status & PORT_OC) | |
979 | status |= USB_PORT_STAT_OVERCURRENT; | |
980 | if (raw_port_status & PORT_RESET) | |
981 | status |= USB_PORT_STAT_RESET; | |
982 | if (raw_port_status & PORT_POWER) { | |
b50107bb | 983 | if (hcd->speed >= HCD_USB3) |
eae5b176 SS |
984 | status |= USB_SS_PORT_STAT_POWER; |
985 | else | |
986 | status |= USB_PORT_STAT_POWER; | |
987 | } | |
063ebeb4 | 988 | /* Update Port Link State */ |
b50107bb | 989 | if (hcd->speed >= HCD_USB3) { |
96908589 | 990 | xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status); |
eae5b176 SS |
991 | /* |
992 | * Verify if all USB3 Ports Have entered U0 already. | |
993 | * Delete Compliance Mode Timer if so. | |
994 | */ | |
995 | xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex); | |
063ebeb4 SS |
996 | } else { |
997 | xhci_hub_report_usb2_link_state(&status, raw_port_status); | |
eae5b176 SS |
998 | } |
999 | if (bus_state->port_c_suspend & (1 << wIndex)) | |
5e6389fd | 1000 | status |= USB_PORT_STAT_C_SUSPEND << 16; |
eae5b176 SS |
1001 | |
1002 | return status; | |
1003 | } | |
1004 | ||
0f2a7930 SS |
1005 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
1006 | u16 wIndex, char *buf, u16 wLength) | |
1007 | { | |
1008 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 1009 | int max_ports; |
0f2a7930 | 1010 | unsigned long flags; |
c9682dff | 1011 | u32 temp, status; |
0f2a7930 | 1012 | int retval = 0; |
28ccd296 | 1013 | __le32 __iomem **port_array; |
be88fe4f | 1014 | int slot_id; |
20b67cf5 | 1015 | struct xhci_bus_state *bus_state; |
2c441780 | 1016 | u16 link_state = 0; |
4296c70a | 1017 | u16 wake_mask = 0; |
797b0ca5 | 1018 | u16 timeout = 0; |
0f1d832e | 1019 | u16 test_mode = 0; |
0f2a7930 | 1020 | |
a0885924 | 1021 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 1022 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
0f2a7930 SS |
1023 | |
1024 | spin_lock_irqsave(&xhci->lock, flags); | |
1025 | switch (typeReq) { | |
1026 | case GetHubStatus: | |
1027 | /* No power source, over-current reported per port */ | |
1028 | memset(buf, 0, 4); | |
1029 | break; | |
1030 | case GetHubDescriptor: | |
4bbb0ace SS |
1031 | /* Check to make sure userspace is asking for the USB 3.0 hub |
1032 | * descriptor for the USB 3.0 roothub. If not, we stall the | |
1033 | * endpoint, like external hubs do. | |
1034 | */ | |
b50107bb | 1035 | if (hcd->speed >= HCD_USB3 && |
4bbb0ace SS |
1036 | (wLength < USB_DT_SS_HUB_SIZE || |
1037 | wValue != (USB_DT_SS_HUB << 8))) { | |
1038 | xhci_dbg(xhci, "Wrong hub descriptor type for " | |
1039 | "USB 3.0 roothub.\n"); | |
1040 | goto error; | |
1041 | } | |
f6ff0ac8 SS |
1042 | xhci_hub_descriptor(hcd, xhci, |
1043 | (struct usb_hub_descriptor *) buf); | |
0f2a7930 | 1044 | break; |
48e82361 SS |
1045 | case DeviceRequest | USB_REQ_GET_DESCRIPTOR: |
1046 | if ((wValue & 0xff00) != (USB_DT_BOS << 8)) | |
1047 | goto error; | |
1048 | ||
5693e0b7 | 1049 | if (hcd->speed < HCD_USB3) |
48e82361 SS |
1050 | goto error; |
1051 | ||
5693e0b7 | 1052 | retval = xhci_create_usb3_bos_desc(xhci, buf, wLength); |
48e82361 | 1053 | spin_unlock_irqrestore(&xhci->lock, flags); |
5693e0b7 | 1054 | return retval; |
0f2a7930 | 1055 | case GetPortStatus: |
a0885924 | 1056 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1057 | goto error; |
1058 | wIndex--; | |
b0ba9720 | 1059 | temp = readl(port_array[wIndex]); |
d9f11ba9 MN |
1060 | if (temp == ~(u32)0) { |
1061 | xhci_hc_died(xhci); | |
f9de8151 SS |
1062 | retval = -ENODEV; |
1063 | break; | |
1064 | } | |
eae5b176 | 1065 | status = xhci_get_port_status(hcd, bus_state, port_array, |
8b3d4570 | 1066 | wIndex, temp, flags); |
eae5b176 SS |
1067 | if (status == 0xffffffff) |
1068 | goto error; | |
0ed9a57e | 1069 | |
eae5b176 SS |
1070 | xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", |
1071 | wIndex, temp); | |
0f2a7930 | 1072 | xhci_dbg(xhci, "Get port status returned 0x%x\n", status); |
eae5b176 | 1073 | |
0f2a7930 | 1074 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); |
395f5409 MN |
1075 | /* if USB 3.1 extended port status return additional 4 bytes */ |
1076 | if (wValue == 0x02) { | |
1077 | u32 port_li; | |
1078 | ||
1079 | if (hcd->speed < HCD_USB31 || wLength != 8) { | |
1080 | xhci_err(xhci, "get ext port status invalid parameter\n"); | |
1081 | retval = -EINVAL; | |
1082 | break; | |
1083 | } | |
1084 | port_li = readl(port_array[wIndex] + PORTLI); | |
1085 | status = xhci_get_ext_port_status(temp, port_li); | |
1086 | put_unaligned_le32(cpu_to_le32(status), &buf[4]); | |
1087 | } | |
0f2a7930 SS |
1088 | break; |
1089 | case SetPortFeature: | |
2c441780 AX |
1090 | if (wValue == USB_PORT_FEAT_LINK_STATE) |
1091 | link_state = (wIndex & 0xff00) >> 3; | |
4296c70a SS |
1092 | if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) |
1093 | wake_mask = wIndex & 0xff00; | |
0f1d832e GZ |
1094 | if (wValue == USB_PORT_FEAT_TEST) |
1095 | test_mode = (wIndex & 0xff00) >> 8; | |
797b0ca5 SS |
1096 | /* The MSB of wIndex is the U1/U2 timeout */ |
1097 | timeout = (wIndex & 0xff00) >> 8; | |
0f2a7930 | 1098 | wIndex &= 0xff; |
a0885924 | 1099 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1100 | goto error; |
1101 | wIndex--; | |
b0ba9720 | 1102 | temp = readl(port_array[wIndex]); |
d9f11ba9 MN |
1103 | if (temp == ~(u32)0) { |
1104 | xhci_hc_died(xhci); | |
f9de8151 SS |
1105 | retval = -ENODEV; |
1106 | break; | |
1107 | } | |
0f2a7930 | 1108 | temp = xhci_port_state_to_neutral(temp); |
4bbb0ace | 1109 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 | 1110 | switch (wValue) { |
be88fe4f | 1111 | case USB_PORT_FEAT_SUSPEND: |
b0ba9720 | 1112 | temp = readl(port_array[wIndex]); |
65580b43 AX |
1113 | if ((temp & PORT_PLS_MASK) != XDEV_U0) { |
1114 | /* Resume the port to U0 first */ | |
1115 | xhci_set_link_state(xhci, port_array, wIndex, | |
1116 | XDEV_U0); | |
1117 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1118 | msleep(10); | |
1119 | spin_lock_irqsave(&xhci->lock, flags); | |
1120 | } | |
be88fe4f AX |
1121 | /* In spec software should not attempt to suspend |
1122 | * a port unless the port reports that it is in the | |
1123 | * enabled (PED = ‘1’,PLS < ‘3’) state. | |
1124 | */ | |
b0ba9720 | 1125 | temp = readl(port_array[wIndex]); |
be88fe4f AX |
1126 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) |
1127 | || (temp & PORT_PLS_MASK) >= XDEV_U3) { | |
52c31bd5 | 1128 | xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n"); |
be88fe4f AX |
1129 | goto error; |
1130 | } | |
1131 | ||
5233630f SS |
1132 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1133 | wIndex + 1); | |
be88fe4f AX |
1134 | if (!slot_id) { |
1135 | xhci_warn(xhci, "slot_id is zero\n"); | |
1136 | goto error; | |
1137 | } | |
1138 | /* unlock to execute stop endpoint commands */ | |
1139 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1140 | xhci_stop_device(xhci, slot_id, 1); | |
1141 | spin_lock_irqsave(&xhci->lock, flags); | |
1142 | ||
c9682dff | 1143 | xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3); |
be88fe4f AX |
1144 | |
1145 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1146 | msleep(10); /* wait device to enter */ | |
1147 | spin_lock_irqsave(&xhci->lock, flags); | |
1148 | ||
b0ba9720 | 1149 | temp = readl(port_array[wIndex]); |
20b67cf5 | 1150 | bus_state->suspended_ports |= 1 << wIndex; |
be88fe4f | 1151 | break; |
2c441780 | 1152 | case USB_PORT_FEAT_LINK_STATE: |
b0ba9720 | 1153 | temp = readl(port_array[wIndex]); |
41e7e056 SS |
1154 | |
1155 | /* Disable port */ | |
1156 | if (link_state == USB_SS_PORT_LS_SS_DISABLED) { | |
1157 | xhci_dbg(xhci, "Disable port %d\n", wIndex); | |
1158 | temp = xhci_port_state_to_neutral(temp); | |
1159 | /* | |
1160 | * Clear all change bits, so that we get a new | |
1161 | * connection event. | |
1162 | */ | |
1163 | temp |= PORT_CSC | PORT_PEC | PORT_WRC | | |
1164 | PORT_OCC | PORT_RC | PORT_PLC | | |
1165 | PORT_CEC; | |
204b7793 | 1166 | writel(temp | PORT_PE, port_array[wIndex]); |
b0ba9720 | 1167 | temp = readl(port_array[wIndex]); |
41e7e056 SS |
1168 | break; |
1169 | } | |
1170 | ||
1171 | /* Put link in RxDetect (enable port) */ | |
1172 | if (link_state == USB_SS_PORT_LS_RX_DETECT) { | |
1173 | xhci_dbg(xhci, "Enable port %d\n", wIndex); | |
1174 | xhci_set_link_state(xhci, port_array, wIndex, | |
1175 | link_state); | |
b0ba9720 | 1176 | temp = readl(port_array[wIndex]); |
41e7e056 SS |
1177 | break; |
1178 | } | |
1179 | ||
2c441780 | 1180 | /* Software should not attempt to set |
41e7e056 | 1181 | * port link state above '3' (U3) and the port |
2c441780 AX |
1182 | * must be enabled. |
1183 | */ | |
1184 | if ((temp & PORT_PE) == 0 || | |
41e7e056 | 1185 | (link_state > USB_SS_PORT_LS_U3)) { |
2c441780 AX |
1186 | xhci_warn(xhci, "Cannot set link state.\n"); |
1187 | goto error; | |
1188 | } | |
1189 | ||
1190 | if (link_state == USB_SS_PORT_LS_U3) { | |
1191 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
1192 | wIndex + 1); | |
1193 | if (slot_id) { | |
1194 | /* unlock to execute stop endpoint | |
1195 | * commands */ | |
1196 | spin_unlock_irqrestore(&xhci->lock, | |
1197 | flags); | |
1198 | xhci_stop_device(xhci, slot_id, 1); | |
1199 | spin_lock_irqsave(&xhci->lock, flags); | |
1200 | } | |
1201 | } | |
1202 | ||
c9682dff AX |
1203 | xhci_set_link_state(xhci, port_array, wIndex, |
1204 | link_state); | |
2c441780 AX |
1205 | |
1206 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1207 | msleep(20); /* wait device to enter */ | |
1208 | spin_lock_irqsave(&xhci->lock, flags); | |
1209 | ||
b0ba9720 | 1210 | temp = readl(port_array[wIndex]); |
2c441780 AX |
1211 | if (link_state == USB_SS_PORT_LS_U3) |
1212 | bus_state->suspended_ports |= 1 << wIndex; | |
1213 | break; | |
0f2a7930 SS |
1214 | case USB_PORT_FEAT_POWER: |
1215 | /* | |
1216 | * Turn on ports, even if there isn't per-port switching. | |
1217 | * HC will report connect events even before this is set. | |
37ebb549 | 1218 | * However, hub_wq will ignore the roothub events until |
0f2a7930 SS |
1219 | * the roothub is registered. |
1220 | */ | |
ec1dafe8 | 1221 | xhci_set_port_power(xhci, hcd, wIndex, true, &flags); |
0f2a7930 SS |
1222 | break; |
1223 | case USB_PORT_FEAT_RESET: | |
1224 | temp = (temp | PORT_RESET); | |
204b7793 | 1225 | writel(temp, port_array[wIndex]); |
0f2a7930 | 1226 | |
b0ba9720 | 1227 | temp = readl(port_array[wIndex]); |
0f2a7930 SS |
1228 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); |
1229 | break; | |
4296c70a SS |
1230 | case USB_PORT_FEAT_REMOTE_WAKE_MASK: |
1231 | xhci_set_remote_wake_mask(xhci, port_array, | |
1232 | wIndex, wake_mask); | |
b0ba9720 | 1233 | temp = readl(port_array[wIndex]); |
4296c70a SS |
1234 | xhci_dbg(xhci, "set port remote wake mask, " |
1235 | "actual port %d status = 0x%x\n", | |
1236 | wIndex, temp); | |
1237 | break; | |
a11496eb AX |
1238 | case USB_PORT_FEAT_BH_PORT_RESET: |
1239 | temp |= PORT_WR; | |
204b7793 | 1240 | writel(temp, port_array[wIndex]); |
a11496eb | 1241 | |
b0ba9720 | 1242 | temp = readl(port_array[wIndex]); |
a11496eb | 1243 | break; |
797b0ca5 | 1244 | case USB_PORT_FEAT_U1_TIMEOUT: |
b50107bb | 1245 | if (hcd->speed < HCD_USB3) |
797b0ca5 | 1246 | goto error; |
b0ba9720 | 1247 | temp = readl(port_array[wIndex] + PORTPMSC); |
797b0ca5 SS |
1248 | temp &= ~PORT_U1_TIMEOUT_MASK; |
1249 | temp |= PORT_U1_TIMEOUT(timeout); | |
204b7793 | 1250 | writel(temp, port_array[wIndex] + PORTPMSC); |
797b0ca5 SS |
1251 | break; |
1252 | case USB_PORT_FEAT_U2_TIMEOUT: | |
b50107bb | 1253 | if (hcd->speed < HCD_USB3) |
797b0ca5 | 1254 | goto error; |
b0ba9720 | 1255 | temp = readl(port_array[wIndex] + PORTPMSC); |
797b0ca5 SS |
1256 | temp &= ~PORT_U2_TIMEOUT_MASK; |
1257 | temp |= PORT_U2_TIMEOUT(timeout); | |
204b7793 | 1258 | writel(temp, port_array[wIndex] + PORTPMSC); |
797b0ca5 | 1259 | break; |
0f1d832e GZ |
1260 | case USB_PORT_FEAT_TEST: |
1261 | /* 4.19.6 Port Test Modes (USB2 Test Mode) */ | |
1262 | if (hcd->speed != HCD_USB2) | |
1263 | goto error; | |
1264 | if (test_mode > TEST_FORCE_EN || test_mode < TEST_J) | |
1265 | goto error; | |
ec1dafe8 MN |
1266 | retval = xhci_enter_test_mode(xhci, test_mode, wIndex, |
1267 | &flags); | |
0f1d832e | 1268 | break; |
0f2a7930 SS |
1269 | default: |
1270 | goto error; | |
1271 | } | |
5308a91b | 1272 | /* unblock any posted writes */ |
b0ba9720 | 1273 | temp = readl(port_array[wIndex]); |
0f2a7930 SS |
1274 | break; |
1275 | case ClearPortFeature: | |
a0885924 | 1276 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1277 | goto error; |
1278 | wIndex--; | |
b0ba9720 | 1279 | temp = readl(port_array[wIndex]); |
d9f11ba9 MN |
1280 | if (temp == ~(u32)0) { |
1281 | xhci_hc_died(xhci); | |
f9de8151 SS |
1282 | retval = -ENODEV; |
1283 | break; | |
1284 | } | |
4bbb0ace | 1285 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 SS |
1286 | temp = xhci_port_state_to_neutral(temp); |
1287 | switch (wValue) { | |
be88fe4f | 1288 | case USB_PORT_FEAT_SUSPEND: |
b0ba9720 | 1289 | temp = readl(port_array[wIndex]); |
be88fe4f AX |
1290 | xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); |
1291 | xhci_dbg(xhci, "PORTSC %04x\n", temp); | |
1292 | if (temp & PORT_RESET) | |
1293 | goto error; | |
5ac04bf1 | 1294 | if ((temp & PORT_PLS_MASK) == XDEV_U3) { |
be88fe4f AX |
1295 | if ((temp & PORT_PE) == 0) |
1296 | goto error; | |
be88fe4f | 1297 | |
f69115fd | 1298 | set_bit(wIndex, &bus_state->resuming_ports); |
c9682dff AX |
1299 | xhci_set_link_state(xhci, port_array, wIndex, |
1300 | XDEV_RESUME); | |
1301 | spin_unlock_irqrestore(&xhci->lock, flags); | |
7d3b016a | 1302 | msleep(USB_RESUME_TIMEOUT); |
a7114230 | 1303 | spin_lock_irqsave(&xhci->lock, flags); |
c9682dff AX |
1304 | xhci_set_link_state(xhci, port_array, wIndex, |
1305 | XDEV_U0); | |
f69115fd | 1306 | clear_bit(wIndex, &bus_state->resuming_ports); |
be88fe4f | 1307 | } |
a7114230 | 1308 | bus_state->port_c_suspend |= 1 << wIndex; |
be88fe4f | 1309 | |
5233630f SS |
1310 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1311 | wIndex + 1); | |
be88fe4f AX |
1312 | if (!slot_id) { |
1313 | xhci_dbg(xhci, "slot_id is zero\n"); | |
1314 | goto error; | |
1315 | } | |
1316 | xhci_ring_device(xhci, slot_id); | |
1317 | break; | |
1318 | case USB_PORT_FEAT_C_SUSPEND: | |
20b67cf5 | 1319 | bus_state->port_c_suspend &= ~(1 << wIndex); |
0f2a7930 | 1320 | case USB_PORT_FEAT_C_RESET: |
a11496eb | 1321 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
0f2a7930 | 1322 | case USB_PORT_FEAT_C_CONNECTION: |
0f2a7930 | 1323 | case USB_PORT_FEAT_C_OVER_CURRENT: |
6219c047 | 1324 | case USB_PORT_FEAT_C_ENABLE: |
85387c0e | 1325 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
9425183d | 1326 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
34fb562a | 1327 | xhci_clear_port_change_bit(xhci, wValue, wIndex, |
5308a91b | 1328 | port_array[wIndex], temp); |
0f2a7930 | 1329 | break; |
6219c047 | 1330 | case USB_PORT_FEAT_ENABLE: |
f6ff0ac8 | 1331 | xhci_disable_port(hcd, xhci, wIndex, |
5308a91b | 1332 | port_array[wIndex], temp); |
6219c047 | 1333 | break; |
693d8eb8 | 1334 | case USB_PORT_FEAT_POWER: |
ec1dafe8 | 1335 | xhci_set_port_power(xhci, hcd, wIndex, false, &flags); |
693d8eb8 | 1336 | break; |
0f1d832e GZ |
1337 | case USB_PORT_FEAT_TEST: |
1338 | retval = xhci_exit_test_mode(xhci); | |
1339 | break; | |
0f2a7930 SS |
1340 | default: |
1341 | goto error; | |
1342 | } | |
0f2a7930 SS |
1343 | break; |
1344 | default: | |
1345 | error: | |
1346 | /* "stall" on error */ | |
1347 | retval = -EPIPE; | |
1348 | } | |
1349 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1350 | return retval; | |
1351 | } | |
1352 | ||
1353 | /* | |
1354 | * Returns 0 if the status hasn't changed, or the number of bytes in buf. | |
1355 | * Ports are 0-indexed from the HCD point of view, | |
1356 | * and 1-indexed from the USB core pointer of view. | |
0f2a7930 SS |
1357 | * |
1358 | * Note that the status change bits will be cleared as soon as a port status | |
1359 | * change event is generated, so we use the saved status from that event. | |
1360 | */ | |
1361 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) | |
1362 | { | |
1363 | unsigned long flags; | |
1364 | u32 temp, status; | |
56192531 | 1365 | u32 mask; |
0f2a7930 SS |
1366 | int i, retval; |
1367 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 1368 | int max_ports; |
28ccd296 | 1369 | __le32 __iomem **port_array; |
20b67cf5 | 1370 | struct xhci_bus_state *bus_state; |
c52804a4 | 1371 | bool reset_change = false; |
0f2a7930 | 1372 | |
a0885924 | 1373 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 1374 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
0f2a7930 SS |
1375 | |
1376 | /* Initial status is no changes */ | |
a0885924 | 1377 | retval = (max_ports + 8) / 8; |
419a8e81 | 1378 | memset(buf, 0, retval); |
f370b996 AX |
1379 | |
1380 | /* | |
1381 | * Inform the usbcore about resume-in-progress by returning | |
1382 | * a non-zero value even if there are no status changes. | |
1383 | */ | |
1384 | status = bus_state->resuming_ports; | |
0f2a7930 | 1385 | |
9425183d | 1386 | mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; |
56192531 | 1387 | |
0f2a7930 SS |
1388 | spin_lock_irqsave(&xhci->lock, flags); |
1389 | /* For each port, did anything change? If so, set that bit in buf. */ | |
a0885924 | 1390 | for (i = 0; i < max_ports; i++) { |
b0ba9720 | 1391 | temp = readl(port_array[i]); |
d9f11ba9 MN |
1392 | if (temp == ~(u32)0) { |
1393 | xhci_hc_died(xhci); | |
f9de8151 SS |
1394 | retval = -ENODEV; |
1395 | break; | |
1396 | } | |
56192531 | 1397 | if ((temp & mask) != 0 || |
20b67cf5 SS |
1398 | (bus_state->port_c_suspend & 1 << i) || |
1399 | (bus_state->resume_done[i] && time_after_eq( | |
1400 | jiffies, bus_state->resume_done[i]))) { | |
419a8e81 | 1401 | buf[(i + 1) / 8] |= 1 << (i + 1) % 8; |
0f2a7930 SS |
1402 | status = 1; |
1403 | } | |
c52804a4 SS |
1404 | if ((temp & PORT_RC)) |
1405 | reset_change = true; | |
1406 | } | |
1407 | if (!status && !reset_change) { | |
1408 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
1409 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1410 | } |
1411 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1412 | return status ? retval : 0; | |
1413 | } | |
9777e3ce AX |
1414 | |
1415 | #ifdef CONFIG_PM | |
1416 | ||
1417 | int xhci_bus_suspend(struct usb_hcd *hcd) | |
1418 | { | |
1419 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 1420 | int max_ports, port_index; |
28ccd296 | 1421 | __le32 __iomem **port_array; |
20b67cf5 | 1422 | struct xhci_bus_state *bus_state; |
9777e3ce AX |
1423 | unsigned long flags; |
1424 | ||
a0885924 | 1425 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 1426 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
9777e3ce AX |
1427 | |
1428 | spin_lock_irqsave(&xhci->lock, flags); | |
1429 | ||
1430 | if (hcd->self.root_hub->do_remote_wakeup) { | |
fac4271d ZJC |
1431 | if (bus_state->resuming_ports || /* USB2 */ |
1432 | bus_state->port_remote_wakeup) { /* USB3 */ | |
f370b996 | 1433 | spin_unlock_irqrestore(&xhci->lock, flags); |
fac4271d | 1434 | xhci_dbg(xhci, "suspend failed because a port is resuming\n"); |
f370b996 | 1435 | return -EBUSY; |
9777e3ce AX |
1436 | } |
1437 | } | |
1438 | ||
518e848e | 1439 | port_index = max_ports; |
20b67cf5 | 1440 | bus_state->bus_suspended = 0; |
518e848e | 1441 | while (port_index--) { |
9777e3ce | 1442 | /* suspend the port if the port is not suspended */ |
9777e3ce AX |
1443 | u32 t1, t2; |
1444 | int slot_id; | |
1445 | ||
b0ba9720 | 1446 | t1 = readl(port_array[port_index]); |
9777e3ce AX |
1447 | t2 = xhci_port_state_to_neutral(t1); |
1448 | ||
1449 | if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) { | |
518e848e | 1450 | xhci_dbg(xhci, "port %d not suspended\n", port_index); |
5233630f | 1451 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
518e848e | 1452 | port_index + 1); |
9777e3ce AX |
1453 | if (slot_id) { |
1454 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1455 | xhci_stop_device(xhci, slot_id, 1); | |
1456 | spin_lock_irqsave(&xhci->lock, flags); | |
1457 | } | |
1458 | t2 &= ~PORT_PLS_MASK; | |
1459 | t2 |= PORT_LINK_STROBE | XDEV_U3; | |
20b67cf5 | 1460 | set_bit(port_index, &bus_state->bus_suspended); |
9777e3ce | 1461 | } |
4296c70a | 1462 | /* USB core sets remote wake mask for USB 3.0 hubs, |
ceb6c9c8 | 1463 | * including the USB 3.0 roothub, but only if CONFIG_PM |
4296c70a SS |
1464 | * is enabled, so also enable remote wake here. |
1465 | */ | |
9b41ebd3 | 1466 | if (hcd->self.root_hub->do_remote_wakeup) { |
9777e3ce AX |
1467 | if (t1 & PORT_CONNECT) { |
1468 | t2 |= PORT_WKOC_E | PORT_WKDISC_E; | |
1469 | t2 &= ~PORT_WKCONN_E; | |
1470 | } else { | |
1471 | t2 |= PORT_WKOC_E | PORT_WKCONN_E; | |
1472 | t2 &= ~PORT_WKDISC_E; | |
1473 | } | |
dec08194 JC |
1474 | if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) && |
1475 | (hcd->speed < HCD_USB3)) | |
1476 | t2 &= ~PORT_WAKE_BITS; | |
9777e3ce AX |
1477 | } else |
1478 | t2 &= ~PORT_WAKE_BITS; | |
1479 | ||
1480 | t1 = xhci_port_state_to_neutral(t1); | |
1481 | if (t1 != t2) | |
204b7793 | 1482 | writel(t2, port_array[port_index]); |
9777e3ce AX |
1483 | } |
1484 | hcd->state = HC_STATE_SUSPENDED; | |
20b67cf5 | 1485 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); |
9777e3ce AX |
1486 | spin_unlock_irqrestore(&xhci->lock, flags); |
1487 | return 0; | |
1488 | } | |
1489 | ||
346e9973 MN |
1490 | /* |
1491 | * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. | |
1492 | * warm reset a USB3 device stuck in polling or compliance mode after resume. | |
1493 | * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 | |
1494 | */ | |
1495 | static bool xhci_port_missing_cas_quirk(int port_index, | |
1496 | __le32 __iomem **port_array) | |
1497 | { | |
1498 | u32 portsc; | |
1499 | ||
1500 | portsc = readl(port_array[port_index]); | |
1501 | ||
1502 | /* if any of these are set we are not stuck */ | |
1503 | if (portsc & (PORT_CONNECT | PORT_CAS)) | |
1504 | return false; | |
1505 | ||
1506 | if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) && | |
1507 | ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE)) | |
1508 | return false; | |
1509 | ||
1510 | /* clear wakeup/change bits, and do a warm port reset */ | |
1511 | portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | |
1512 | portsc |= PORT_WR; | |
1513 | writel(portsc, port_array[port_index]); | |
1514 | /* flush write */ | |
1515 | readl(port_array[port_index]); | |
1516 | return true; | |
1517 | } | |
1518 | ||
9777e3ce AX |
1519 | int xhci_bus_resume(struct usb_hcd *hcd) |
1520 | { | |
1521 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 1522 | int max_ports, port_index; |
28ccd296 | 1523 | __le32 __iomem **port_array; |
20b67cf5 | 1524 | struct xhci_bus_state *bus_state; |
9777e3ce AX |
1525 | u32 temp; |
1526 | unsigned long flags; | |
41485a90 MN |
1527 | unsigned long port_was_suspended = 0; |
1528 | bool need_usb2_u3_exit = false; | |
1529 | int slot_id; | |
1530 | int sret; | |
9777e3ce | 1531 | |
a0885924 | 1532 | max_ports = xhci_get_ports(hcd, &port_array); |
20b67cf5 | 1533 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
9777e3ce | 1534 | |
20b67cf5 | 1535 | if (time_before(jiffies, bus_state->next_statechange)) |
9777e3ce AX |
1536 | msleep(5); |
1537 | ||
1538 | spin_lock_irqsave(&xhci->lock, flags); | |
1539 | if (!HCD_HW_ACCESSIBLE(hcd)) { | |
1540 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1541 | return -ESHUTDOWN; | |
1542 | } | |
1543 | ||
1544 | /* delay the irqs */ | |
b0ba9720 | 1545 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1546 | temp &= ~CMD_EIE; |
204b7793 | 1547 | writel(temp, &xhci->op_regs->command); |
9777e3ce | 1548 | |
518e848e SS |
1549 | port_index = max_ports; |
1550 | while (port_index--) { | |
9777e3ce AX |
1551 | /* Check whether need resume ports. If needed |
1552 | resume port and disable remote wakeup */ | |
9777e3ce | 1553 | u32 temp; |
9777e3ce | 1554 | |
b0ba9720 | 1555 | temp = readl(port_array[port_index]); |
346e9973 MN |
1556 | |
1557 | /* warm reset CAS limited ports stuck in polling/compliance */ | |
1558 | if ((xhci->quirks & XHCI_MISSING_CAS) && | |
1559 | (hcd->speed >= HCD_USB3) && | |
1560 | xhci_port_missing_cas_quirk(port_index, port_array)) { | |
1561 | xhci_dbg(xhci, "reset stuck port %d\n", port_index); | |
1562 | continue; | |
1563 | } | |
2338b9e4 | 1564 | if (DEV_SUPERSPEED_ANY(temp)) |
9777e3ce AX |
1565 | temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); |
1566 | else | |
1567 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | |
20b67cf5 | 1568 | if (test_bit(port_index, &bus_state->bus_suspended) && |
9777e3ce | 1569 | (temp & PORT_PLS_MASK)) { |
41485a90 | 1570 | set_bit(port_index, &port_was_suspended); |
2338b9e4 | 1571 | if (!DEV_SUPERSPEED_ANY(temp)) { |
c9682dff AX |
1572 | xhci_set_link_state(xhci, port_array, |
1573 | port_index, XDEV_RESUME); | |
41485a90 | 1574 | need_usb2_u3_exit = true; |
9777e3ce | 1575 | } |
9777e3ce | 1576 | } else |
204b7793 | 1577 | writel(temp, port_array[port_index]); |
9777e3ce AX |
1578 | } |
1579 | ||
41485a90 MN |
1580 | if (need_usb2_u3_exit) { |
1581 | spin_unlock_irqrestore(&xhci->lock, flags); | |
7d3b016a | 1582 | msleep(USB_RESUME_TIMEOUT); |
41485a90 MN |
1583 | spin_lock_irqsave(&xhci->lock, flags); |
1584 | } | |
1585 | ||
1586 | port_index = max_ports; | |
1587 | while (port_index--) { | |
1588 | if (!(port_was_suspended & BIT(port_index))) | |
1589 | continue; | |
1590 | /* Clear PLC to poll it later after XDEV_U0 */ | |
1591 | xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC); | |
1592 | xhci_set_link_state(xhci, port_array, port_index, XDEV_U0); | |
1593 | } | |
1594 | ||
1595 | port_index = max_ports; | |
1596 | while (port_index--) { | |
1597 | if (!(port_was_suspended & BIT(port_index))) | |
1598 | continue; | |
1599 | /* Poll and Clear PLC */ | |
1600 | sret = xhci_handshake(port_array[port_index], PORT_PLC, | |
1601 | PORT_PLC, 10 * 1000); | |
1602 | if (sret) | |
1603 | xhci_warn(xhci, "port %d resume PLC timeout\n", | |
1604 | port_index); | |
1605 | xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC); | |
1606 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1); | |
1607 | if (slot_id) | |
1608 | xhci_ring_device(xhci, slot_id); | |
1609 | } | |
1610 | ||
b0ba9720 | 1611 | (void) readl(&xhci->op_regs->command); |
9777e3ce | 1612 | |
20b67cf5 | 1613 | bus_state->next_statechange = jiffies + msecs_to_jiffies(5); |
9777e3ce | 1614 | /* re-enable irqs */ |
b0ba9720 | 1615 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1616 | temp |= CMD_EIE; |
204b7793 | 1617 | writel(temp, &xhci->op_regs->command); |
b0ba9720 | 1618 | temp = readl(&xhci->op_regs->command); |
9777e3ce AX |
1619 | |
1620 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1621 | return 0; | |
1622 | } | |
1623 | ||
436a3890 | 1624 | #endif /* CONFIG_PM */ |