Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
0f2a7930 SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
0f2a7930 SS |
9 | */ |
10 | ||
ddba5cd0 MN |
11 | |
12 | #include <linux/slab.h> | |
0f2a7930 SS |
13 | #include <asm/unaligned.h> |
14 | ||
15 | #include "xhci.h" | |
4bdfe4c3 | 16 | #include "xhci-trace.h" |
0f2a7930 | 17 | |
9777e3ce AX |
18 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
19 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ | |
20 | PORT_RC | PORT_PLC | PORT_PE) | |
21 | ||
5693e0b7 MN |
22 | /* USB 3 BOS descriptor and a capability descriptors, combined. |
23 | * Fields will be adjusted and added later in xhci_create_usb3_bos_desc() | |
24 | */ | |
48e82361 SS |
25 | static u8 usb_bos_descriptor [] = { |
26 | USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ | |
27 | USB_DT_BOS, /* __u8 bDescriptorType */ | |
28 | 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ | |
29 | 0x1, /* __u8 bNumDeviceCaps */ | |
5693e0b7 | 30 | /* First device capability, SuperSpeed */ |
48e82361 SS |
31 | USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ |
32 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ | |
33 | USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ | |
34 | 0x00, /* bmAttributes, LTM off by default */ | |
35 | USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ | |
36 | 0x03, /* bFunctionalitySupport, | |
37 | USB 3.0 speed only */ | |
38 | 0x00, /* bU1DevExitLat, set later. */ | |
5693e0b7 MN |
39 | 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */ |
40 | /* Second device capability, SuperSpeedPlus */ | |
5da665fc | 41 | 0x1c, /* bLength 28, will be adjusted later */ |
5693e0b7 MN |
42 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ |
43 | USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */ | |
44 | 0x00, /* bReserved 0 */ | |
5da665fc MN |
45 | 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */ |
46 | 0x01, 0x00, /* wFunctionalitySupport */ | |
5693e0b7 | 47 | 0x00, 0x00, /* wReserved 0 */ |
5da665fc MN |
48 | /* Default Sublink Speed Attributes, overwrite if custom PSI exists */ |
49 | 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */ | |
50 | 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */ | |
51 | 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */ | |
52 | 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */ | |
48e82361 SS |
53 | }; |
54 | ||
5693e0b7 MN |
55 | static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf, |
56 | u16 wLength) | |
57 | { | |
cf0ee7c6 | 58 | struct xhci_port_cap *port_cap = NULL; |
5693e0b7 MN |
59 | int i, ssa_count; |
60 | u32 temp; | |
61 | u16 desc_size, ssp_cap_size, ssa_size = 0; | |
62 | bool usb3_1 = false; | |
63 | ||
64 | desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
65 | ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size; | |
66 | ||
67 | /* does xhci support USB 3.1 Enhanced SuperSpeed */ | |
cf0ee7c6 MN |
68 | for (i = 0; i < xhci->num_port_caps; i++) { |
69 | if (xhci->port_caps[i].maj_rev == 0x03 && | |
70 | xhci->port_caps[i].min_rev >= 0x01) { | |
71 | usb3_1 = true; | |
72 | port_cap = &xhci->port_caps[i]; | |
73 | break; | |
74 | } | |
75 | } | |
76 | ||
77 | if (usb3_1) { | |
5da665fc | 78 | /* does xhci provide a PSI table for SSA speed attributes? */ |
cf0ee7c6 | 79 | if (port_cap->psi_count) { |
5da665fc | 80 | /* two SSA entries for each unique PSI ID, RX and TX */ |
cf0ee7c6 | 81 | ssa_count = port_cap->psi_uid_count * 2; |
5da665fc MN |
82 | ssa_size = ssa_count * sizeof(u32); |
83 | ssp_cap_size -= 16; /* skip copying the default SSA */ | |
84 | } | |
5693e0b7 | 85 | desc_size += ssp_cap_size; |
5693e0b7 MN |
86 | } |
87 | memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength)); | |
88 | ||
89 | if (usb3_1) { | |
90 | /* modify bos descriptor bNumDeviceCaps and wTotalLength */ | |
91 | buf[4] += 1; | |
92 | put_unaligned_le16(desc_size + ssa_size, &buf[2]); | |
93 | } | |
94 | ||
95 | if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) | |
96 | return wLength; | |
97 | ||
98 | /* Indicate whether the host has LTM support. */ | |
99 | temp = readl(&xhci->cap_regs->hcc_params); | |
100 | if (HCC_LTC(temp)) | |
101 | buf[8] |= USB_LTM_SUPPORT; | |
102 | ||
103 | /* Set the U1 and U2 exit latencies. */ | |
104 | if ((xhci->quirks & XHCI_LPM_SUPPORT)) { | |
105 | temp = readl(&xhci->cap_regs->hcs_params3); | |
106 | buf[12] = HCS_U1_LATENCY(temp); | |
107 | put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); | |
108 | } | |
109 | ||
5da665fc | 110 | /* If PSI table exists, add the custom speed attributes from it */ |
cf0ee7c6 | 111 | if (usb3_1 && port_cap->psi_count) { |
7bea22b1 | 112 | u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp; |
5693e0b7 MN |
113 | int offset; |
114 | ||
115 | ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
116 | ||
117 | if (wLength < desc_size) | |
118 | return wLength; | |
119 | buf[ssp_cap_base] = ssp_cap_size + ssa_size; | |
120 | ||
121 | /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */ | |
122 | bm_attrib = (ssa_count - 1) & 0x1f; | |
cf0ee7c6 | 123 | bm_attrib |= (port_cap->psi_uid_count - 1) << 5; |
5693e0b7 MN |
124 | put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]); |
125 | ||
126 | if (wLength < desc_size + ssa_size) | |
127 | return wLength; | |
128 | /* | |
129 | * Create the Sublink Speed Attributes (SSA) array. | |
130 | * The xhci PSI field and USB 3.1 SSA fields are very similar, | |
131 | * but link type bits 7:6 differ for values 01b and 10b. | |
132 | * xhci has also only one PSI entry for a symmetric link when | |
133 | * USB 3.1 requires two SSA entries (RX and TX) for every link | |
134 | */ | |
135 | offset = desc_size; | |
cf0ee7c6 MN |
136 | for (i = 0; i < port_cap->psi_count; i++) { |
137 | psi = port_cap->psi[i]; | |
5693e0b7 | 138 | psi &= ~USB_SSP_SUBLINK_SPEED_RSVD; |
7bea22b1 MN |
139 | psi_exp = XHCI_EXT_PORT_PSIE(psi); |
140 | psi_mant = XHCI_EXT_PORT_PSIM(psi); | |
141 | ||
142 | /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */ | |
143 | for (; psi_exp < 3; psi_exp++) | |
144 | psi_mant /= 1000; | |
145 | if (psi_mant >= 10) | |
146 | psi |= BIT(14); | |
147 | ||
5693e0b7 MN |
148 | if ((psi & PLT_MASK) == PLT_SYM) { |
149 | /* Symmetric, create SSA RX and TX from one PSI entry */ | |
150 | put_unaligned_le32(psi, &buf[offset]); | |
151 | psi |= 1 << 7; /* turn entry to TX */ | |
152 | offset += 4; | |
153 | if (offset >= desc_size + ssa_size) | |
154 | return desc_size + ssa_size; | |
155 | } else if ((psi & PLT_MASK) == PLT_ASYM_RX) { | |
156 | /* Asymetric RX, flip bits 7:6 for SSA */ | |
157 | psi ^= PLT_MASK; | |
158 | } | |
159 | put_unaligned_le32(psi, &buf[offset]); | |
160 | offset += 4; | |
161 | if (offset >= desc_size + ssa_size) | |
162 | return desc_size + ssa_size; | |
163 | } | |
164 | } | |
165 | /* ssa_size is 0 for other than usb 3.1 hosts */ | |
166 | return desc_size + ssa_size; | |
167 | } | |
48e82361 | 168 | |
4bbb0ace SS |
169 | static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, |
170 | struct usb_hub_descriptor *desc, int ports) | |
0f2a7930 | 171 | { |
0f2a7930 SS |
172 | u16 temp; |
173 | ||
0f2a7930 SS |
174 | desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ |
175 | desc->bHubContrCurrent = 0; | |
176 | ||
177 | desc->bNbrPorts = ports; | |
0f2a7930 | 178 | temp = 0; |
c8421147 | 179 | /* Bits 1:0 - support per-port power switching, or power always on */ |
0f2a7930 | 180 | if (HCC_PPC(xhci->hcc_params)) |
c8421147 | 181 | temp |= HUB_CHAR_INDV_PORT_LPSM; |
0f2a7930 | 182 | else |
c8421147 | 183 | temp |= HUB_CHAR_NO_LPSM; |
0f2a7930 SS |
184 | /* Bit 2 - root hubs are not part of a compound device */ |
185 | /* Bits 4:3 - individual port over current protection */ | |
c8421147 | 186 | temp |= HUB_CHAR_INDV_PORT_OCPM; |
0f2a7930 SS |
187 | /* Bits 6:5 - no TTs in root ports */ |
188 | /* Bit 7 - no port indicators */ | |
28ccd296 | 189 | desc->wHubCharacteristics = cpu_to_le16(temp); |
0f2a7930 SS |
190 | } |
191 | ||
4bbb0ace SS |
192 | /* Fill in the USB 2.0 roothub descriptor */ |
193 | static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
194 | struct usb_hub_descriptor *desc) | |
195 | { | |
196 | int ports; | |
197 | u16 temp; | |
198 | __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; | |
199 | u32 portsc; | |
200 | unsigned int i; | |
e740b019 | 201 | struct xhci_hub *rhub; |
4bbb0ace | 202 | |
e740b019 MN |
203 | rhub = &xhci->usb2_rhub; |
204 | ports = rhub->num_ports; | |
4bbb0ace | 205 | xhci_common_hub_descriptor(xhci, desc, ports); |
c8421147 | 206 | desc->bDescriptorType = USB_DT_HUB; |
4bbb0ace | 207 | temp = 1 + (ports / 8); |
c8421147 | 208 | desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; |
4bbb0ace SS |
209 | |
210 | /* The Device Removable bits are reported on a byte granularity. | |
211 | * If the port doesn't exist within that byte, the bit is set to 0. | |
212 | */ | |
213 | memset(port_removable, 0, sizeof(port_removable)); | |
214 | for (i = 0; i < ports; i++) { | |
e740b019 | 215 | portsc = readl(rhub->ports[i]->addr); |
4bbb0ace SS |
216 | /* If a device is removable, PORTSC reports a 0, same as in the |
217 | * hub descriptor DeviceRemovable bits. | |
218 | */ | |
219 | if (portsc & PORT_DEV_REMOVE) | |
220 | /* This math is hairy because bit 0 of DeviceRemovable | |
221 | * is reserved, and bit 1 is for port 1, etc. | |
222 | */ | |
223 | port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); | |
224 | } | |
225 | ||
226 | /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN | |
227 | * ports on it. The USB 2.0 specification says that there are two | |
228 | * variable length fields at the end of the hub descriptor: | |
229 | * DeviceRemovable and PortPwrCtrlMask. But since we can have less than | |
230 | * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array | |
231 | * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to | |
232 | * 0xFF, so we initialize the both arrays (DeviceRemovable and | |
233 | * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each | |
234 | * set of ports that actually exist. | |
235 | */ | |
236 | memset(desc->u.hs.DeviceRemovable, 0xff, | |
237 | sizeof(desc->u.hs.DeviceRemovable)); | |
238 | memset(desc->u.hs.PortPwrCtrlMask, 0xff, | |
239 | sizeof(desc->u.hs.PortPwrCtrlMask)); | |
240 | ||
241 | for (i = 0; i < (ports + 1 + 7) / 8; i++) | |
242 | memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], | |
243 | sizeof(__u8)); | |
244 | } | |
245 | ||
246 | /* Fill in the USB 3.0 roothub descriptor */ | |
247 | static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
248 | struct usb_hub_descriptor *desc) | |
249 | { | |
250 | int ports; | |
251 | u16 port_removable; | |
252 | u32 portsc; | |
253 | unsigned int i; | |
e740b019 | 254 | struct xhci_hub *rhub; |
4bbb0ace | 255 | |
e740b019 MN |
256 | rhub = &xhci->usb3_rhub; |
257 | ports = rhub->num_ports; | |
4bbb0ace | 258 | xhci_common_hub_descriptor(xhci, desc, ports); |
c8421147 AD |
259 | desc->bDescriptorType = USB_DT_SS_HUB; |
260 | desc->bDescLength = USB_DT_SS_HUB_SIZE; | |
4bbb0ace SS |
261 | |
262 | /* header decode latency should be zero for roothubs, | |
263 | * see section 4.23.5.2. | |
264 | */ | |
265 | desc->u.ss.bHubHdrDecLat = 0; | |
266 | desc->u.ss.wHubDelay = 0; | |
267 | ||
268 | port_removable = 0; | |
269 | /* bit 0 is reserved, bit 1 is for port 1, etc. */ | |
270 | for (i = 0; i < ports; i++) { | |
e740b019 | 271 | portsc = readl(rhub->ports[i]->addr); |
4bbb0ace SS |
272 | if (portsc & PORT_DEV_REMOVE) |
273 | port_removable |= 1 << (i + 1); | |
274 | } | |
27c411c9 LT |
275 | |
276 | desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); | |
4bbb0ace SS |
277 | } |
278 | ||
279 | static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
280 | struct usb_hub_descriptor *desc) | |
281 | { | |
282 | ||
b50107bb | 283 | if (hcd->speed >= HCD_USB3) |
4bbb0ace SS |
284 | xhci_usb3_hub_descriptor(hcd, xhci, desc); |
285 | else | |
286 | xhci_usb2_hub_descriptor(hcd, xhci, desc); | |
287 | ||
288 | } | |
289 | ||
0f2a7930 SS |
290 | static unsigned int xhci_port_speed(unsigned int port_status) |
291 | { | |
292 | if (DEV_LOWSPEED(port_status)) | |
288ead45 | 293 | return USB_PORT_STAT_LOW_SPEED; |
0f2a7930 | 294 | if (DEV_HIGHSPEED(port_status)) |
288ead45 | 295 | return USB_PORT_STAT_HIGH_SPEED; |
0f2a7930 SS |
296 | /* |
297 | * FIXME: Yes, we should check for full speed, but the core uses that as | |
298 | * a default in portspeed() in usb/core/hub.c (which is the only place | |
288ead45 | 299 | * USB_PORT_STAT_*_SPEED is used). |
0f2a7930 SS |
300 | */ |
301 | return 0; | |
302 | } | |
303 | ||
304 | /* | |
305 | * These bits are Read Only (RO) and should be saved and written to the | |
306 | * registers: 0, 3, 10:13, 30 | |
307 | * connect status, over-current status, port speed, and device removable. | |
308 | * connect status and port speed are also sticky - meaning they're in | |
309 | * the AUX well and they aren't changed by a hot, warm, or cold reset. | |
310 | */ | |
311 | #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) | |
312 | /* | |
313 | * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: | |
314 | * bits 5:8, 9, 14:15, 25:27 | |
315 | * link state, port power, port indicator state, "wake on" enable state | |
316 | */ | |
317 | #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) | |
318 | /* | |
319 | * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: | |
320 | * bit 4 (port reset) | |
321 | */ | |
322 | #define XHCI_PORT_RW1S ((1<<4)) | |
323 | /* | |
324 | * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: | |
325 | * bits 1, 17, 18, 19, 20, 21, 22, 23 | |
326 | * port enable/disable, and | |
327 | * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), | |
328 | * over-current, reset, link state, and L1 change | |
329 | */ | |
330 | #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) | |
331 | /* | |
332 | * Bit 16 is RW, and writing a '1' to it causes the link state control to be | |
333 | * latched in | |
334 | */ | |
335 | #define XHCI_PORT_RW ((1<<16)) | |
336 | /* | |
337 | * These bits are Reserved Zero (RsvdZ) and zero should be written to them: | |
338 | * bits 2, 24, 28:31 | |
339 | */ | |
340 | #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) | |
341 | ||
342 | /* | |
343 | * Given a port state, this function returns a value that would result in the | |
344 | * port being in the same state, if the value was written to the port status | |
345 | * control register. | |
346 | * Save Read Only (RO) bits and save read/write bits where | |
347 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). | |
348 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. | |
349 | */ | |
56192531 | 350 | u32 xhci_port_state_to_neutral(u32 state) |
0f2a7930 SS |
351 | { |
352 | /* Save read-only status and port state */ | |
353 | return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); | |
354 | } | |
355 | ||
be88fe4f AX |
356 | /* |
357 | * find slot id based on port number. | |
f6ff0ac8 | 358 | * @port: The one-based port number from one of the two split roothubs. |
be88fe4f | 359 | */ |
5233630f SS |
360 | int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
361 | u16 port) | |
be88fe4f AX |
362 | { |
363 | int slot_id; | |
364 | int i; | |
f6ff0ac8 | 365 | enum usb_device_speed speed; |
be88fe4f AX |
366 | |
367 | slot_id = 0; | |
368 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
2278446e | 369 | if (!xhci->devs[i] || !xhci->devs[i]->udev) |
be88fe4f | 370 | continue; |
f6ff0ac8 | 371 | speed = xhci->devs[i]->udev->speed; |
b50107bb | 372 | if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3)) |
fe30182c | 373 | && xhci->devs[i]->fake_port == port) { |
be88fe4f AX |
374 | slot_id = i; |
375 | break; | |
376 | } | |
377 | } | |
378 | ||
379 | return slot_id; | |
380 | } | |
381 | ||
382 | /* | |
383 | * Stop device | |
384 | * It issues stop endpoint command for EP 0 to 30. And wait the last command | |
385 | * to complete. | |
386 | * suspend will set to 1, if suspend bit need to set in command. | |
387 | */ | |
388 | static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) | |
389 | { | |
390 | struct xhci_virt_device *virt_dev; | |
391 | struct xhci_command *cmd; | |
392 | unsigned long flags; | |
be88fe4f AX |
393 | int ret; |
394 | int i; | |
395 | ||
396 | ret = 0; | |
397 | virt_dev = xhci->devs[slot_id]; | |
88716a93 JL |
398 | if (!virt_dev) |
399 | return -ENODEV; | |
400 | ||
a711edee FB |
401 | trace_xhci_stop_device(virt_dev); |
402 | ||
103afda0 | 403 | cmd = xhci_alloc_command(xhci, true, GFP_NOIO); |
74e0b564 | 404 | if (!cmd) |
be88fe4f | 405 | return -ENOMEM; |
be88fe4f AX |
406 | |
407 | spin_lock_irqsave(&xhci->lock, flags); | |
408 | for (i = LAST_EP_INDEX; i > 0; i--) { | |
ddba5cd0 | 409 | if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { |
28a2369f | 410 | struct xhci_ep_ctx *ep_ctx; |
ddba5cd0 | 411 | struct xhci_command *command; |
28a2369f SS |
412 | |
413 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i); | |
414 | ||
415 | /* Check ep is running, required by AMD SNPS 3.1 xHC */ | |
416 | if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING) | |
417 | continue; | |
418 | ||
103afda0 | 419 | command = xhci_alloc_command(xhci, false, GFP_NOWAIT); |
ddba5cd0 MN |
420 | if (!command) { |
421 | spin_unlock_irqrestore(&xhci->lock, flags); | |
b3207c65 MR |
422 | ret = -ENOMEM; |
423 | goto cmd_cleanup; | |
424 | } | |
425 | ||
426 | ret = xhci_queue_stop_endpoint(xhci, command, slot_id, | |
427 | i, suspend); | |
428 | if (ret) { | |
429 | spin_unlock_irqrestore(&xhci->lock, flags); | |
430 | xhci_free_command(xhci, command); | |
431 | goto cmd_cleanup; | |
ddba5cd0 | 432 | } |
ddba5cd0 | 433 | } |
be88fe4f | 434 | } |
b3207c65 MR |
435 | ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); |
436 | if (ret) { | |
437 | spin_unlock_irqrestore(&xhci->lock, flags); | |
438 | goto cmd_cleanup; | |
439 | } | |
440 | ||
be88fe4f AX |
441 | xhci_ring_cmd_db(xhci); |
442 | spin_unlock_irqrestore(&xhci->lock, flags); | |
443 | ||
444 | /* Wait for last stop endpoint command to finish */ | |
c311e391 MN |
445 | wait_for_completion(cmd->completion); |
446 | ||
0b7c105a | 447 | if (cmd->status == COMP_COMMAND_ABORTED || |
604d02a2 | 448 | cmd->status == COMP_COMMAND_RING_STOPPED) { |
c311e391 | 449 | xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); |
be88fe4f | 450 | ret = -ETIME; |
be88fe4f | 451 | } |
b3207c65 MR |
452 | |
453 | cmd_cleanup: | |
be88fe4f AX |
454 | xhci_free_command(xhci, cmd); |
455 | return ret; | |
456 | } | |
457 | ||
458 | /* | |
459 | * Ring device, it rings the all doorbells unconditionally. | |
460 | */ | |
56192531 | 461 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) |
be88fe4f | 462 | { |
b7f9696b HG |
463 | int i, s; |
464 | struct xhci_virt_ep *ep; | |
465 | ||
466 | for (i = 0; i < LAST_EP_INDEX + 1; i++) { | |
467 | ep = &xhci->devs[slot_id]->eps[i]; | |
be88fe4f | 468 | |
b7f9696b HG |
469 | if (ep->ep_state & EP_HAS_STREAMS) { |
470 | for (s = 1; s < ep->stream_info->num_streams; s++) | |
471 | xhci_ring_ep_doorbell(xhci, slot_id, i, s); | |
472 | } else if (ep->ring && ep->ring->dequeue) { | |
be88fe4f | 473 | xhci_ring_ep_doorbell(xhci, slot_id, i, 0); |
b7f9696b HG |
474 | } |
475 | } | |
be88fe4f AX |
476 | |
477 | return; | |
478 | } | |
479 | ||
f6ff0ac8 | 480 | static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
28ccd296 | 481 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
6219c047 | 482 | { |
6dd0a3a7 | 483 | /* Don't allow the USB core to disable SuperSpeed ports. */ |
b50107bb | 484 | if (hcd->speed >= HCD_USB3) { |
6dd0a3a7 SS |
485 | xhci_dbg(xhci, "Ignoring request to disable " |
486 | "SuperSpeed port.\n"); | |
487 | return; | |
488 | } | |
489 | ||
41135de1 FB |
490 | if (xhci->quirks & XHCI_BROKEN_PORT_PED) { |
491 | xhci_dbg(xhci, | |
492 | "Broken Port Enabled/Disabled, ignoring port disable request.\n"); | |
493 | return; | |
494 | } | |
495 | ||
6219c047 | 496 | /* Write 1 to disable the port */ |
204b7793 | 497 | writel(port_status | PORT_PE, addr); |
b0ba9720 | 498 | port_status = readl(addr); |
d70d5a84 MN |
499 | xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n", |
500 | hcd->self.busnum, wIndex + 1, port_status); | |
6219c047 SS |
501 | } |
502 | ||
34fb562a | 503 | static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, |
28ccd296 | 504 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
34fb562a SS |
505 | { |
506 | char *port_change_bit; | |
507 | u32 status; | |
508 | ||
509 | switch (wValue) { | |
510 | case USB_PORT_FEAT_C_RESET: | |
511 | status = PORT_RC; | |
512 | port_change_bit = "reset"; | |
513 | break; | |
a11496eb AX |
514 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
515 | status = PORT_WRC; | |
516 | port_change_bit = "warm(BH) reset"; | |
517 | break; | |
34fb562a SS |
518 | case USB_PORT_FEAT_C_CONNECTION: |
519 | status = PORT_CSC; | |
520 | port_change_bit = "connect"; | |
521 | break; | |
522 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
523 | status = PORT_OCC; | |
524 | port_change_bit = "over-current"; | |
525 | break; | |
6219c047 SS |
526 | case USB_PORT_FEAT_C_ENABLE: |
527 | status = PORT_PEC; | |
528 | port_change_bit = "enable/disable"; | |
529 | break; | |
be88fe4f AX |
530 | case USB_PORT_FEAT_C_SUSPEND: |
531 | status = PORT_PLC; | |
532 | port_change_bit = "suspend/resume"; | |
533 | break; | |
85387c0e AX |
534 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
535 | status = PORT_PLC; | |
536 | port_change_bit = "link state"; | |
537 | break; | |
9425183d LB |
538 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
539 | status = PORT_CEC; | |
540 | port_change_bit = "config error"; | |
541 | break; | |
34fb562a SS |
542 | default: |
543 | /* Should never happen */ | |
544 | return; | |
545 | } | |
546 | /* Change bits are all write 1 to clear */ | |
204b7793 | 547 | writel(port_status | status, addr); |
b0ba9720 | 548 | port_status = readl(addr); |
d70d5a84 MN |
549 | |
550 | xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n", | |
551 | wIndex + 1, port_change_bit, port_status); | |
34fb562a SS |
552 | } |
553 | ||
ffd4b4fc MN |
554 | struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd) |
555 | { | |
556 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
557 | ||
558 | if (hcd->speed >= HCD_USB3) | |
559 | return &xhci->usb3_rhub; | |
560 | return &xhci->usb2_rhub; | |
561 | } | |
562 | ||
a6ff6cbf GZ |
563 | /* |
564 | * xhci_set_port_power() must be called with xhci->lock held. | |
565 | * It will release and re-aquire the lock while calling ACPI | |
566 | * method. | |
567 | */ | |
568 | static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, | |
ec1dafe8 | 569 | u16 index, bool on, unsigned long *flags) |
dce174e0 | 570 | __must_hold(&xhci->lock) |
a6ff6cbf | 571 | { |
e740b019 MN |
572 | struct xhci_hub *rhub; |
573 | struct xhci_port *port; | |
a6ff6cbf | 574 | u32 temp; |
a6ff6cbf | 575 | |
e740b019 MN |
576 | rhub = xhci_get_rhub(hcd); |
577 | port = rhub->ports[index]; | |
578 | temp = readl(port->addr); | |
d70d5a84 MN |
579 | |
580 | xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n", | |
581 | hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); | |
582 | ||
a6ff6cbf | 583 | temp = xhci_port_state_to_neutral(temp); |
d70d5a84 | 584 | |
a6ff6cbf GZ |
585 | if (on) { |
586 | /* Power on */ | |
e740b019 | 587 | writel(temp | PORT_POWER, port->addr); |
d70d5a84 | 588 | readl(port->addr); |
a6ff6cbf GZ |
589 | } else { |
590 | /* Power off */ | |
e740b019 | 591 | writel(temp & ~PORT_POWER, port->addr); |
a6ff6cbf GZ |
592 | } |
593 | ||
ec1dafe8 | 594 | spin_unlock_irqrestore(&xhci->lock, *flags); |
a6ff6cbf GZ |
595 | temp = usb_acpi_power_manageable(hcd->self.root_hub, |
596 | index); | |
597 | if (temp) | |
598 | usb_acpi_set_power_state(hcd->self.root_hub, | |
599 | index, on); | |
ec1dafe8 | 600 | spin_lock_irqsave(&xhci->lock, *flags); |
a6ff6cbf GZ |
601 | } |
602 | ||
0f1d832e GZ |
603 | static void xhci_port_set_test_mode(struct xhci_hcd *xhci, |
604 | u16 test_mode, u16 wIndex) | |
605 | { | |
606 | u32 temp; | |
e740b019 | 607 | struct xhci_port *port; |
0f1d832e | 608 | |
e740b019 MN |
609 | /* xhci only supports test mode for usb2 ports */ |
610 | port = xhci->usb2_rhub.ports[wIndex]; | |
611 | temp = readl(port->addr + PORTPMSC); | |
0f1d832e | 612 | temp |= test_mode << PORT_TEST_MODE_SHIFT; |
e740b019 | 613 | writel(temp, port->addr + PORTPMSC); |
0f1d832e | 614 | xhci->test_mode = test_mode; |
62fb45d3 | 615 | if (test_mode == USB_TEST_FORCE_ENABLE) |
0f1d832e GZ |
616 | xhci_start(xhci); |
617 | } | |
618 | ||
619 | static int xhci_enter_test_mode(struct xhci_hcd *xhci, | |
ec1dafe8 | 620 | u16 test_mode, u16 wIndex, unsigned long *flags) |
055b185a | 621 | __must_hold(&xhci->lock) |
0f1d832e GZ |
622 | { |
623 | int i, retval; | |
624 | ||
625 | /* Disable all Device Slots */ | |
626 | xhci_dbg(xhci, "Disable all slots\n"); | |
576d5546 | 627 | spin_unlock_irqrestore(&xhci->lock, *flags); |
0f1d832e | 628 | for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { |
b64149ca LB |
629 | if (!xhci->devs[i]) |
630 | continue; | |
631 | ||
cd3f1790 | 632 | retval = xhci_disable_slot(xhci, i); |
0f1d832e GZ |
633 | if (retval) |
634 | xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", | |
635 | i, retval); | |
636 | } | |
576d5546 | 637 | spin_lock_irqsave(&xhci->lock, *flags); |
0f1d832e GZ |
638 | /* Put all ports to the Disable state by clear PP */ |
639 | xhci_dbg(xhci, "Disable all port (PP = 0)\n"); | |
640 | /* Power off USB3 ports*/ | |
e740b019 | 641 | for (i = 0; i < xhci->usb3_rhub.num_ports; i++) |
ec1dafe8 | 642 | xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags); |
0f1d832e | 643 | /* Power off USB2 ports*/ |
e740b019 | 644 | for (i = 0; i < xhci->usb2_rhub.num_ports; i++) |
ec1dafe8 | 645 | xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags); |
0f1d832e GZ |
646 | /* Stop the controller */ |
647 | xhci_dbg(xhci, "Stop controller\n"); | |
648 | retval = xhci_halt(xhci); | |
649 | if (retval) | |
650 | return retval; | |
651 | /* Disable runtime PM for test mode */ | |
652 | pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); | |
653 | /* Set PORTPMSC.PTC field to enter selected test mode */ | |
654 | /* Port is selected by wIndex. port_id = wIndex + 1 */ | |
655 | xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n", | |
656 | test_mode, wIndex + 1); | |
657 | xhci_port_set_test_mode(xhci, test_mode, wIndex); | |
658 | return retval; | |
659 | } | |
660 | ||
661 | static int xhci_exit_test_mode(struct xhci_hcd *xhci) | |
662 | { | |
663 | int retval; | |
664 | ||
665 | if (!xhci->test_mode) { | |
666 | xhci_err(xhci, "Not in test mode, do nothing.\n"); | |
667 | return 0; | |
668 | } | |
62fb45d3 | 669 | if (xhci->test_mode == USB_TEST_FORCE_ENABLE && |
0f1d832e GZ |
670 | !(xhci->xhc_state & XHCI_STATE_HALTED)) { |
671 | retval = xhci_halt(xhci); | |
672 | if (retval) | |
673 | return retval; | |
674 | } | |
675 | pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); | |
676 | xhci->test_mode = 0; | |
677 | return xhci_reset(xhci); | |
678 | } | |
679 | ||
6b7f40f7 MN |
680 | void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, |
681 | u32 link_state) | |
c9682dff AX |
682 | { |
683 | u32 temp; | |
d70d5a84 | 684 | u32 portsc; |
c9682dff | 685 | |
d70d5a84 MN |
686 | portsc = readl(port->addr); |
687 | temp = xhci_port_state_to_neutral(portsc); | |
c9682dff AX |
688 | temp &= ~PORT_PLS_MASK; |
689 | temp |= PORT_LINK_STROBE | link_state; | |
6b7f40f7 | 690 | writel(temp, port->addr); |
d70d5a84 MN |
691 | |
692 | xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x", | |
693 | port->rhub->hcd->self.busnum, port->hcd_portnum + 1, | |
694 | portsc, temp); | |
c9682dff AX |
695 | } |
696 | ||
ed384bd3 | 697 | static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, |
fdcf74ff | 698 | struct xhci_port *port, u16 wake_mask) |
4296c70a SS |
699 | { |
700 | u32 temp; | |
701 | ||
fdcf74ff | 702 | temp = readl(port->addr); |
4296c70a SS |
703 | temp = xhci_port_state_to_neutral(temp); |
704 | ||
705 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) | |
706 | temp |= PORT_WKCONN_E; | |
707 | else | |
708 | temp &= ~PORT_WKCONN_E; | |
709 | ||
710 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) | |
711 | temp |= PORT_WKDISC_E; | |
712 | else | |
713 | temp &= ~PORT_WKDISC_E; | |
714 | ||
715 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) | |
716 | temp |= PORT_WKOC_E; | |
717 | else | |
718 | temp &= ~PORT_WKOC_E; | |
719 | ||
fdcf74ff | 720 | writel(temp, port->addr); |
4296c70a SS |
721 | } |
722 | ||
d2f52c9e | 723 | /* Test and clear port RWC bit */ |
eaefcf24 MN |
724 | void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, |
725 | u32 port_bit) | |
d2f52c9e AX |
726 | { |
727 | u32 temp; | |
728 | ||
eaefcf24 | 729 | temp = readl(port->addr); |
d2f52c9e AX |
730 | if (temp & port_bit) { |
731 | temp = xhci_port_state_to_neutral(temp); | |
732 | temp |= port_bit; | |
eaefcf24 | 733 | writel(temp, port->addr); |
d2f52c9e AX |
734 | } |
735 | } | |
736 | ||
8bea2bd3 | 737 | /* Updates Link Status for super Speed port */ |
96908589 FB |
738 | static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, |
739 | u32 *status, u32 status_reg) | |
8bea2bd3 SL |
740 | { |
741 | u32 pls = status_reg & PORT_PLS_MASK; | |
742 | ||
8bea2bd3 SL |
743 | /* When the CAS bit is set then warm reset |
744 | * should be performed on port | |
745 | */ | |
746 | if (status_reg & PORT_CAS) { | |
747 | /* The CAS bit can be set while the port is | |
748 | * in any link state. | |
749 | * Only roothubs have CAS bit, so we | |
750 | * pretend to be in compliance mode | |
751 | * unless we're already in compliance | |
752 | * or the inactive state. | |
753 | */ | |
754 | if (pls != USB_SS_PORT_LS_COMP_MOD && | |
755 | pls != USB_SS_PORT_LS_SS_INACTIVE) { | |
756 | pls = USB_SS_PORT_LS_COMP_MOD; | |
757 | } | |
758 | /* Return also connection bit - | |
759 | * hub state machine resets port | |
760 | * when this bit is set. | |
761 | */ | |
762 | pls |= USB_PORT_STAT_CONNECTION; | |
71c731a2 | 763 | } else { |
904df64a KHF |
764 | /* |
765 | * Resume state is an xHCI internal state. Do not report it to | |
766 | * usb core, instead, pretend to be U3, thus usb core knows | |
767 | * it's not ready for transfer. | |
768 | */ | |
769 | if (pls == XDEV_RESUME) { | |
770 | *status |= USB_SS_PORT_LS_U3; | |
771 | return; | |
772 | } | |
773 | ||
71c731a2 AC |
774 | /* |
775 | * If CAS bit isn't set but the Port is already at | |
776 | * Compliance Mode, fake a connection so the USB core | |
777 | * notices the Compliance state and resets the port. | |
778 | * This resolves an issue generated by the SN65LVPE502CP | |
779 | * in which sometimes the port enters compliance mode | |
780 | * caused by a delay on the host-device negotiation. | |
781 | */ | |
96908589 FB |
782 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && |
783 | (pls == USB_SS_PORT_LS_COMP_MOD)) | |
71c731a2 | 784 | pls |= USB_PORT_STAT_CONNECTION; |
8bea2bd3 | 785 | } |
71c731a2 | 786 | |
8bea2bd3 SL |
787 | /* update status field */ |
788 | *status |= pls; | |
789 | } | |
790 | ||
71c731a2 AC |
791 | /* |
792 | * Function for Compliance Mode Quirk. | |
793 | * | |
794 | * This Function verifies if all xhc USB3 ports have entered U0, if so, | |
795 | * the compliance mode timer is deleted. A port won't enter | |
796 | * compliance mode if it has previously entered U0. | |
797 | */ | |
5f20cf12 SK |
798 | static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, |
799 | u16 wIndex) | |
71c731a2 | 800 | { |
e740b019 | 801 | u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1); |
71c731a2 AC |
802 | bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); |
803 | ||
804 | if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) | |
805 | return; | |
806 | ||
807 | if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { | |
808 | xhci->port_status_u0 |= 1 << wIndex; | |
809 | if (xhci->port_status_u0 == all_ports_seen_u0) { | |
810 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
811 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
812 | "All USB3 ports have entered U0 already!"); | |
813 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
814 | "Compliance Mode Recovery Timer Deleted."); | |
71c731a2 AC |
815 | } |
816 | } | |
817 | } | |
818 | ||
e67ebf1b MN |
819 | static int xhci_handle_usb2_port_link_resume(struct xhci_port *port, |
820 | u32 *status, u32 portsc, | |
bd82873f | 821 | unsigned long *flags) |
e67ebf1b MN |
822 | { |
823 | struct xhci_bus_state *bus_state; | |
824 | struct xhci_hcd *xhci; | |
825 | struct usb_hcd *hcd; | |
826 | int slot_id; | |
827 | u32 wIndex; | |
828 | ||
829 | hcd = port->rhub->hcd; | |
830 | bus_state = &port->rhub->bus_state; | |
831 | xhci = hcd_to_xhci(hcd); | |
832 | wIndex = port->hcd_portnum; | |
833 | ||
834 | if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) { | |
835 | *status = 0xffffffff; | |
836 | return -EINVAL; | |
837 | } | |
838 | /* did port event handler already start resume timing? */ | |
839 | if (!bus_state->resume_done[wIndex]) { | |
840 | /* If not, maybe we are in a host initated resume? */ | |
841 | if (test_bit(wIndex, &bus_state->resuming_ports)) { | |
842 | /* Host initated resume doesn't time the resume | |
843 | * signalling using resume_done[]. | |
844 | * It manually sets RESUME state, sleeps 20ms | |
845 | * and sets U0 state. This should probably be | |
846 | * changed, but not right now. | |
847 | */ | |
848 | } else { | |
849 | /* port resume was discovered now and here, | |
850 | * start resume timing | |
851 | */ | |
852 | unsigned long timeout = jiffies + | |
853 | msecs_to_jiffies(USB_RESUME_TIMEOUT); | |
854 | ||
855 | set_bit(wIndex, &bus_state->resuming_ports); | |
856 | bus_state->resume_done[wIndex] = timeout; | |
857 | mod_timer(&hcd->rh_timer, timeout); | |
858 | usb_hcd_start_port_resume(&hcd->self, wIndex); | |
859 | } | |
860 | /* Has resume been signalled for USB_RESUME_TIME yet? */ | |
861 | } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) { | |
862 | int time_left; | |
863 | ||
d70d5a84 MN |
864 | xhci_dbg(xhci, "resume USB2 port %d-%d\n", |
865 | hcd->self.busnum, wIndex + 1); | |
866 | ||
e67ebf1b MN |
867 | bus_state->resume_done[wIndex] = 0; |
868 | clear_bit(wIndex, &bus_state->resuming_ports); | |
869 | ||
870 | set_bit(wIndex, &bus_state->rexit_ports); | |
871 | ||
872 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); | |
873 | xhci_set_link_state(xhci, port, XDEV_U0); | |
874 | ||
bd82873f | 875 | spin_unlock_irqrestore(&xhci->lock, *flags); |
e67ebf1b MN |
876 | time_left = wait_for_completion_timeout( |
877 | &bus_state->rexit_done[wIndex], | |
878 | msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS)); | |
bd82873f | 879 | spin_lock_irqsave(&xhci->lock, *flags); |
e67ebf1b MN |
880 | |
881 | if (time_left) { | |
882 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
883 | wIndex + 1); | |
884 | if (!slot_id) { | |
885 | xhci_dbg(xhci, "slot_id is zero\n"); | |
886 | *status = 0xffffffff; | |
887 | return -ENODEV; | |
888 | } | |
889 | xhci_ring_device(xhci, slot_id); | |
890 | } else { | |
891 | int port_status = readl(port->addr); | |
892 | ||
d70d5a84 MN |
893 | xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n", |
894 | hcd->self.busnum, wIndex + 1, port_status); | |
e67ebf1b MN |
895 | *status |= USB_PORT_STAT_SUSPEND; |
896 | clear_bit(wIndex, &bus_state->rexit_ports); | |
897 | } | |
898 | ||
899 | usb_hcd_end_port_resume(&hcd->self, wIndex); | |
900 | bus_state->port_c_suspend |= 1 << wIndex; | |
901 | bus_state->suspended_ports &= ~(1 << wIndex); | |
902 | } else { | |
903 | /* | |
904 | * The resume has been signaling for less than | |
905 | * USB_RESUME_TIME. Report the port status as SUSPEND, | |
906 | * let the usbcore check port status again and clear | |
907 | * resume signaling later. | |
908 | */ | |
909 | *status |= USB_PORT_STAT_SUSPEND; | |
910 | } | |
911 | return 0; | |
912 | } | |
913 | ||
395f5409 MN |
914 | static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) |
915 | { | |
916 | u32 ext_stat = 0; | |
917 | int speed_id; | |
918 | ||
919 | /* only support rx and tx lane counts of 1 in usb3.1 spec */ | |
920 | speed_id = DEV_PORT_SPEED(raw_port_status); | |
921 | ext_stat |= speed_id; /* bits 3:0, RX speed id */ | |
922 | ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ | |
923 | ||
924 | ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ | |
925 | ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ | |
926 | ||
927 | return ext_stat; | |
928 | } | |
929 | ||
5f78a54f MN |
930 | static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status, |
931 | u32 portsc) | |
932 | { | |
a231ec41 | 933 | struct xhci_bus_state *bus_state; |
5f78a54f | 934 | struct xhci_hcd *xhci; |
057d476f | 935 | struct usb_hcd *hcd; |
5f78a54f MN |
936 | u32 link_state; |
937 | u32 portnum; | |
938 | ||
a231ec41 | 939 | bus_state = &port->rhub->bus_state; |
5f78a54f | 940 | xhci = hcd_to_xhci(port->rhub->hcd); |
057d476f | 941 | hcd = port->rhub->hcd; |
5f78a54f MN |
942 | link_state = portsc & PORT_PLS_MASK; |
943 | portnum = port->hcd_portnum; | |
944 | ||
945 | /* USB3 specific wPortChange bits | |
946 | * | |
947 | * Port link change with port in resume state should not be | |
948 | * reported to usbcore, as this is an internal state to be | |
949 | * handled by xhci driver. Reporting PLC to usbcore may | |
950 | * cause usbcore clearing PLC first and port change event | |
951 | * irq won't be generated. | |
952 | */ | |
953 | ||
954 | if (portsc & PORT_PLC && (link_state != XDEV_RESUME)) | |
955 | *status |= USB_PORT_STAT_C_LINK_STATE << 16; | |
956 | if (portsc & PORT_WRC) | |
957 | *status |= USB_PORT_STAT_C_BH_RESET << 16; | |
958 | if (portsc & PORT_CEC) | |
959 | *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; | |
960 | ||
961 | /* USB3 specific wPortStatus bits */ | |
a231ec41 | 962 | if (portsc & PORT_POWER) { |
5f78a54f | 963 | *status |= USB_SS_PORT_STAT_POWER; |
a231ec41 MN |
964 | /* link state handling */ |
965 | if (link_state == XDEV_U0) | |
966 | bus_state->suspended_ports &= ~(1 << portnum); | |
967 | } | |
5f78a54f | 968 | |
057d476f MN |
969 | /* remote wake resume signaling complete */ |
970 | if (bus_state->port_remote_wakeup & (1 << portnum) && | |
971 | link_state != XDEV_RESUME && | |
972 | link_state != XDEV_RECOVERY) { | |
973 | bus_state->port_remote_wakeup &= ~(1 << portnum); | |
974 | usb_hcd_end_port_resume(&hcd->self, portnum); | |
975 | } | |
976 | ||
5f78a54f MN |
977 | xhci_hub_report_usb3_link_state(xhci, status, portsc); |
978 | xhci_del_comp_mod_timer(xhci, portsc, portnum); | |
979 | } | |
980 | ||
70e9b53d | 981 | static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status, |
bd82873f | 982 | u32 portsc, unsigned long *flags) |
70e9b53d | 983 | { |
a231ec41 | 984 | struct xhci_bus_state *bus_state; |
70e9b53d | 985 | u32 link_state; |
a231ec41 | 986 | u32 portnum; |
e67ebf1b | 987 | int ret; |
70e9b53d | 988 | |
a231ec41 | 989 | bus_state = &port->rhub->bus_state; |
70e9b53d | 990 | link_state = portsc & PORT_PLS_MASK; |
a231ec41 | 991 | portnum = port->hcd_portnum; |
70e9b53d MN |
992 | |
993 | /* USB2 wPortStatus bits */ | |
994 | if (portsc & PORT_POWER) { | |
995 | *status |= USB_PORT_STAT_POWER; | |
996 | ||
997 | /* link state is only valid if port is powered */ | |
998 | if (link_state == XDEV_U3) | |
999 | *status |= USB_PORT_STAT_SUSPEND; | |
1000 | if (link_state == XDEV_U2) | |
1001 | *status |= USB_PORT_STAT_L1; | |
a231ec41 MN |
1002 | if (link_state == XDEV_U0) { |
1003 | bus_state->resume_done[portnum] = 0; | |
1004 | clear_bit(portnum, &bus_state->resuming_ports); | |
1005 | if (bus_state->suspended_ports & (1 << portnum)) { | |
1006 | bus_state->suspended_ports &= ~(1 << portnum); | |
1007 | bus_state->port_c_suspend |= 1 << portnum; | |
1008 | } | |
1009 | } | |
e67ebf1b MN |
1010 | if (link_state == XDEV_RESUME) { |
1011 | ret = xhci_handle_usb2_port_link_resume(port, status, | |
1012 | portsc, flags); | |
1013 | if (ret) | |
1014 | return; | |
1015 | } | |
70e9b53d MN |
1016 | } |
1017 | } | |
1018 | ||
eae5b176 SS |
1019 | /* |
1020 | * Converts a raw xHCI port status into the format that external USB 2.0 or USB | |
1021 | * 3.0 hubs use. | |
1022 | * | |
1023 | * Possible side effects: | |
1024 | * - Mark a port as being done with device resume, | |
1025 | * and ring the endpoint doorbells. | |
1026 | * - Stop the Synopsys redriver Compliance Mode polling. | |
8b3d4570 | 1027 | * - Drop and reacquire the xHCI lock, in order to wait for port resume. |
eae5b176 SS |
1028 | */ |
1029 | static u32 xhci_get_port_status(struct usb_hcd *hcd, | |
1030 | struct xhci_bus_state *bus_state, | |
eaefcf24 | 1031 | u16 wIndex, u32 raw_port_status, |
bd82873f | 1032 | unsigned long *flags) |
8b3d4570 SS |
1033 | __releases(&xhci->lock) |
1034 | __acquires(&xhci->lock) | |
eae5b176 | 1035 | { |
eae5b176 | 1036 | u32 status = 0; |
e740b019 MN |
1037 | struct xhci_hub *rhub; |
1038 | struct xhci_port *port; | |
1039 | ||
1040 | rhub = xhci_get_rhub(hcd); | |
1041 | port = rhub->ports[wIndex]; | |
eae5b176 | 1042 | |
3c2ddb44 | 1043 | /* common wPortChange bits */ |
eae5b176 SS |
1044 | if (raw_port_status & PORT_CSC) |
1045 | status |= USB_PORT_STAT_C_CONNECTION << 16; | |
1046 | if (raw_port_status & PORT_PEC) | |
1047 | status |= USB_PORT_STAT_C_ENABLE << 16; | |
1048 | if ((raw_port_status & PORT_OCC)) | |
1049 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; | |
1050 | if ((raw_port_status & PORT_RC)) | |
1051 | status |= USB_PORT_STAT_C_RESET << 16; | |
70e9b53d | 1052 | |
3c2ddb44 MN |
1053 | /* common wPortStatus bits */ |
1054 | if (raw_port_status & PORT_CONNECT) { | |
1055 | status |= USB_PORT_STAT_CONNECTION; | |
1056 | status |= xhci_port_speed(raw_port_status); | |
1057 | } | |
1058 | if (raw_port_status & PORT_PE) | |
1059 | status |= USB_PORT_STAT_ENABLE; | |
1060 | if (raw_port_status & PORT_OC) | |
1061 | status |= USB_PORT_STAT_OVERCURRENT; | |
1062 | if (raw_port_status & PORT_RESET) | |
1063 | status |= USB_PORT_STAT_RESET; | |
1064 | ||
1065 | /* USB2 and USB3 specific bits, including Port Link State */ | |
5f78a54f MN |
1066 | if (hcd->speed >= HCD_USB3) |
1067 | xhci_get_usb3_port_status(port, &status, raw_port_status); | |
70e9b53d | 1068 | else |
e67ebf1b MN |
1069 | xhci_get_usb2_port_status(port, &status, raw_port_status, |
1070 | flags); | |
f69115fd MN |
1071 | /* |
1072 | * Clear stale usb2 resume signalling variables in case port changed | |
1073 | * state during resume signalling. For example on error | |
1074 | */ | |
1075 | if ((bus_state->resume_done[wIndex] || | |
1076 | test_bit(wIndex, &bus_state->resuming_ports)) && | |
1077 | (raw_port_status & PORT_PLS_MASK) != XDEV_U3 && | |
1078 | (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) { | |
1079 | bus_state->resume_done[wIndex] = 0; | |
1080 | clear_bit(wIndex, &bus_state->resuming_ports); | |
330e2d61 | 1081 | usb_hcd_end_port_resume(&hcd->self, wIndex); |
f69115fd MN |
1082 | } |
1083 | ||
eae5b176 | 1084 | if (bus_state->port_c_suspend & (1 << wIndex)) |
5e6389fd | 1085 | status |= USB_PORT_STAT_C_SUSPEND << 16; |
eae5b176 SS |
1086 | |
1087 | return status; | |
1088 | } | |
1089 | ||
0f2a7930 SS |
1090 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
1091 | u16 wIndex, char *buf, u16 wLength) | |
1092 | { | |
1093 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 1094 | int max_ports; |
0f2a7930 | 1095 | unsigned long flags; |
c9682dff | 1096 | u32 temp, status; |
0f2a7930 | 1097 | int retval = 0; |
be88fe4f | 1098 | int slot_id; |
20b67cf5 | 1099 | struct xhci_bus_state *bus_state; |
2c441780 | 1100 | u16 link_state = 0; |
4296c70a | 1101 | u16 wake_mask = 0; |
797b0ca5 | 1102 | u16 timeout = 0; |
0f1d832e | 1103 | u16 test_mode = 0; |
e740b019 MN |
1104 | struct xhci_hub *rhub; |
1105 | struct xhci_port **ports; | |
0f2a7930 | 1106 | |
e740b019 MN |
1107 | rhub = xhci_get_rhub(hcd); |
1108 | ports = rhub->ports; | |
925f349d | 1109 | max_ports = rhub->num_ports; |
f6187f42 | 1110 | bus_state = &rhub->bus_state; |
0f2a7930 SS |
1111 | |
1112 | spin_lock_irqsave(&xhci->lock, flags); | |
1113 | switch (typeReq) { | |
1114 | case GetHubStatus: | |
1115 | /* No power source, over-current reported per port */ | |
1116 | memset(buf, 0, 4); | |
1117 | break; | |
1118 | case GetHubDescriptor: | |
4bbb0ace SS |
1119 | /* Check to make sure userspace is asking for the USB 3.0 hub |
1120 | * descriptor for the USB 3.0 roothub. If not, we stall the | |
1121 | * endpoint, like external hubs do. | |
1122 | */ | |
b50107bb | 1123 | if (hcd->speed >= HCD_USB3 && |
4bbb0ace SS |
1124 | (wLength < USB_DT_SS_HUB_SIZE || |
1125 | wValue != (USB_DT_SS_HUB << 8))) { | |
1126 | xhci_dbg(xhci, "Wrong hub descriptor type for " | |
1127 | "USB 3.0 roothub.\n"); | |
1128 | goto error; | |
1129 | } | |
f6ff0ac8 SS |
1130 | xhci_hub_descriptor(hcd, xhci, |
1131 | (struct usb_hub_descriptor *) buf); | |
0f2a7930 | 1132 | break; |
48e82361 SS |
1133 | case DeviceRequest | USB_REQ_GET_DESCRIPTOR: |
1134 | if ((wValue & 0xff00) != (USB_DT_BOS << 8)) | |
1135 | goto error; | |
1136 | ||
5693e0b7 | 1137 | if (hcd->speed < HCD_USB3) |
48e82361 SS |
1138 | goto error; |
1139 | ||
5693e0b7 | 1140 | retval = xhci_create_usb3_bos_desc(xhci, buf, wLength); |
48e82361 | 1141 | spin_unlock_irqrestore(&xhci->lock, flags); |
5693e0b7 | 1142 | return retval; |
0f2a7930 | 1143 | case GetPortStatus: |
a0885924 | 1144 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1145 | goto error; |
1146 | wIndex--; | |
e740b019 | 1147 | temp = readl(ports[wIndex]->addr); |
d9f11ba9 MN |
1148 | if (temp == ~(u32)0) { |
1149 | xhci_hc_died(xhci); | |
f9de8151 SS |
1150 | retval = -ENODEV; |
1151 | break; | |
1152 | } | |
28c06e58 | 1153 | trace_xhci_get_port_status(wIndex, temp); |
eaefcf24 | 1154 | status = xhci_get_port_status(hcd, bus_state, wIndex, temp, |
bd82873f | 1155 | &flags); |
eae5b176 SS |
1156 | if (status == 0xffffffff) |
1157 | goto error; | |
0ed9a57e | 1158 | |
d70d5a84 MN |
1159 | xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x", |
1160 | hcd->self.busnum, wIndex + 1, temp, status); | |
eae5b176 | 1161 | |
0f2a7930 | 1162 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); |
395f5409 MN |
1163 | /* if USB 3.1 extended port status return additional 4 bytes */ |
1164 | if (wValue == 0x02) { | |
1165 | u32 port_li; | |
1166 | ||
1167 | if (hcd->speed < HCD_USB31 || wLength != 8) { | |
1168 | xhci_err(xhci, "get ext port status invalid parameter\n"); | |
1169 | retval = -EINVAL; | |
1170 | break; | |
1171 | } | |
e740b019 | 1172 | port_li = readl(ports[wIndex]->addr + PORTLI); |
395f5409 | 1173 | status = xhci_get_ext_port_status(temp, port_li); |
6269e4c7 | 1174 | put_unaligned_le32(status, &buf[4]); |
395f5409 | 1175 | } |
0f2a7930 SS |
1176 | break; |
1177 | case SetPortFeature: | |
2c441780 AX |
1178 | if (wValue == USB_PORT_FEAT_LINK_STATE) |
1179 | link_state = (wIndex & 0xff00) >> 3; | |
4296c70a SS |
1180 | if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) |
1181 | wake_mask = wIndex & 0xff00; | |
0f1d832e GZ |
1182 | if (wValue == USB_PORT_FEAT_TEST) |
1183 | test_mode = (wIndex & 0xff00) >> 8; | |
797b0ca5 SS |
1184 | /* The MSB of wIndex is the U1/U2 timeout */ |
1185 | timeout = (wIndex & 0xff00) >> 8; | |
0f2a7930 | 1186 | wIndex &= 0xff; |
a0885924 | 1187 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1188 | goto error; |
1189 | wIndex--; | |
e740b019 | 1190 | temp = readl(ports[wIndex]->addr); |
d9f11ba9 MN |
1191 | if (temp == ~(u32)0) { |
1192 | xhci_hc_died(xhci); | |
f9de8151 SS |
1193 | retval = -ENODEV; |
1194 | break; | |
1195 | } | |
0f2a7930 | 1196 | temp = xhci_port_state_to_neutral(temp); |
4bbb0ace | 1197 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 | 1198 | switch (wValue) { |
be88fe4f | 1199 | case USB_PORT_FEAT_SUSPEND: |
e740b019 | 1200 | temp = readl(ports[wIndex]->addr); |
65580b43 AX |
1201 | if ((temp & PORT_PLS_MASK) != XDEV_U0) { |
1202 | /* Resume the port to U0 first */ | |
6b7f40f7 | 1203 | xhci_set_link_state(xhci, ports[wIndex], |
65580b43 AX |
1204 | XDEV_U0); |
1205 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1206 | msleep(10); | |
1207 | spin_lock_irqsave(&xhci->lock, flags); | |
1208 | } | |
be88fe4f AX |
1209 | /* In spec software should not attempt to suspend |
1210 | * a port unless the port reports that it is in the | |
1211 | * enabled (PED = ‘1’,PLS < ‘3’) state. | |
1212 | */ | |
e740b019 | 1213 | temp = readl(ports[wIndex]->addr); |
be88fe4f AX |
1214 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) |
1215 | || (temp & PORT_PLS_MASK) >= XDEV_U3) { | |
d70d5a84 MN |
1216 | xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n", |
1217 | hcd->self.busnum, wIndex + 1); | |
be88fe4f AX |
1218 | goto error; |
1219 | } | |
1220 | ||
5233630f SS |
1221 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1222 | wIndex + 1); | |
be88fe4f AX |
1223 | if (!slot_id) { |
1224 | xhci_warn(xhci, "slot_id is zero\n"); | |
1225 | goto error; | |
1226 | } | |
1227 | /* unlock to execute stop endpoint commands */ | |
1228 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1229 | xhci_stop_device(xhci, slot_id, 1); | |
1230 | spin_lock_irqsave(&xhci->lock, flags); | |
1231 | ||
6b7f40f7 | 1232 | xhci_set_link_state(xhci, ports[wIndex], XDEV_U3); |
be88fe4f AX |
1233 | |
1234 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1235 | msleep(10); /* wait device to enter */ | |
1236 | spin_lock_irqsave(&xhci->lock, flags); | |
1237 | ||
e740b019 | 1238 | temp = readl(ports[wIndex]->addr); |
20b67cf5 | 1239 | bus_state->suspended_ports |= 1 << wIndex; |
be88fe4f | 1240 | break; |
2c441780 | 1241 | case USB_PORT_FEAT_LINK_STATE: |
e740b019 | 1242 | temp = readl(ports[wIndex]->addr); |
41e7e056 SS |
1243 | /* Disable port */ |
1244 | if (link_state == USB_SS_PORT_LS_SS_DISABLED) { | |
8aaf19b8 KHF |
1245 | xhci_dbg(xhci, "Disable port %d-%d\n", |
1246 | hcd->self.busnum, wIndex + 1); | |
41e7e056 SS |
1247 | temp = xhci_port_state_to_neutral(temp); |
1248 | /* | |
1249 | * Clear all change bits, so that we get a new | |
1250 | * connection event. | |
1251 | */ | |
1252 | temp |= PORT_CSC | PORT_PEC | PORT_WRC | | |
1253 | PORT_OCC | PORT_RC | PORT_PLC | | |
1254 | PORT_CEC; | |
e740b019 MN |
1255 | writel(temp | PORT_PE, ports[wIndex]->addr); |
1256 | temp = readl(ports[wIndex]->addr); | |
41e7e056 SS |
1257 | break; |
1258 | } | |
1259 | ||
1260 | /* Put link in RxDetect (enable port) */ | |
1261 | if (link_state == USB_SS_PORT_LS_RX_DETECT) { | |
8aaf19b8 KHF |
1262 | xhci_dbg(xhci, "Enable port %d-%d\n", |
1263 | hcd->self.busnum, wIndex + 1); | |
6b7f40f7 MN |
1264 | xhci_set_link_state(xhci, ports[wIndex], |
1265 | link_state); | |
e740b019 | 1266 | temp = readl(ports[wIndex]->addr); |
41e7e056 SS |
1267 | break; |
1268 | } | |
1269 | ||
4b562bd2 JP |
1270 | /* |
1271 | * For xHCI 1.1 according to section 4.19.1.2.4.1 a | |
1272 | * root hub port's transition to compliance mode upon | |
1273 | * detecting LFPS timeout may be controlled by an | |
1274 | * Compliance Transition Enabled (CTE) flag (not | |
1275 | * software visible). This flag is set by writing 0xA | |
1276 | * to PORTSC PLS field which will allow transition to | |
1277 | * compliance mode the next time LFPS timeout is | |
1278 | * encountered. A warm reset will clear it. | |
1279 | * | |
1280 | * The CTE flag is only supported if the HCCPARAMS2 CTC | |
1281 | * flag is set, otherwise, the compliance substate is | |
1282 | * automatically entered as on 1.0 and prior. | |
1283 | */ | |
1284 | if (link_state == USB_SS_PORT_LS_COMP_MOD) { | |
1285 | if (!HCC2_CTC(xhci->hcc_params2)) { | |
1286 | xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n"); | |
1287 | break; | |
1288 | } | |
1289 | ||
1290 | if ((temp & PORT_CONNECT)) { | |
1291 | xhci_warn(xhci, "Can't set compliance mode when port is connected\n"); | |
1292 | goto error; | |
1293 | } | |
1294 | ||
8aaf19b8 KHF |
1295 | xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n", |
1296 | hcd->self.busnum, wIndex + 1); | |
6b7f40f7 | 1297 | xhci_set_link_state(xhci, ports[wIndex], |
4b562bd2 | 1298 | link_state); |
6b7f40f7 | 1299 | |
e740b019 | 1300 | temp = readl(ports[wIndex]->addr); |
4b562bd2 JP |
1301 | break; |
1302 | } | |
1208d8a8 MN |
1303 | /* Port must be enabled */ |
1304 | if (!(temp & PORT_PE)) { | |
1305 | retval = -ENODEV; | |
1306 | break; | |
1307 | } | |
1308 | /* Can't set port link state above '3' (U3) */ | |
1309 | if (link_state > USB_SS_PORT_LS_U3) { | |
8aaf19b8 KHF |
1310 | xhci_warn(xhci, "Cannot set port %d-%d link state %d\n", |
1311 | hcd->self.busnum, wIndex + 1, | |
1312 | link_state); | |
2c441780 AX |
1313 | goto error; |
1314 | } | |
0200b9f7 | 1315 | |
ceca4938 MN |
1316 | /* |
1317 | * set link to U0, steps depend on current link state. | |
1318 | * U3: set link to U0 and wait for u3exit completion. | |
1319 | * U1/U2: no PLC complete event, only set link to U0. | |
1320 | * Resume/Recovery: device initiated U0, only wait for | |
1321 | * completion | |
1322 | */ | |
0200b9f7 | 1323 | if (link_state == USB_SS_PORT_LS_U0) { |
ceca4938 MN |
1324 | u32 pls = temp & PORT_PLS_MASK; |
1325 | bool wait_u0 = false; | |
0200b9f7 | 1326 | |
ceca4938 MN |
1327 | /* already in U0 */ |
1328 | if (pls == XDEV_U0) | |
1329 | break; | |
1330 | if (pls == XDEV_U3 || | |
1331 | pls == XDEV_RESUME || | |
1332 | pls == XDEV_RECOVERY) { | |
1333 | wait_u0 = true; | |
1334 | reinit_completion(&bus_state->u3exit_done[wIndex]); | |
1335 | } | |
1336 | if (pls <= XDEV_U3) /* U1, U2, U3 */ | |
1337 | xhci_set_link_state(xhci, ports[wIndex], | |
1338 | USB_SS_PORT_LS_U0); | |
1339 | if (!wait_u0) { | |
1340 | if (pls > XDEV_U3) | |
1341 | goto error; | |
1342 | break; | |
0200b9f7 | 1343 | } |
0200b9f7 KHF |
1344 | spin_unlock_irqrestore(&xhci->lock, flags); |
1345 | if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex], | |
1346 | msecs_to_jiffies(100))) | |
8aaf19b8 KHF |
1347 | xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n", |
1348 | hcd->self.busnum, wIndex + 1); | |
0200b9f7 KHF |
1349 | spin_lock_irqsave(&xhci->lock, flags); |
1350 | temp = readl(ports[wIndex]->addr); | |
1351 | break; | |
1352 | } | |
1353 | ||
2c441780 | 1354 | if (link_state == USB_SS_PORT_LS_U3) { |
0200b9f7 | 1355 | int retries = 16; |
2c441780 AX |
1356 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1357 | wIndex + 1); | |
1358 | if (slot_id) { | |
1359 | /* unlock to execute stop endpoint | |
1360 | * commands */ | |
1361 | spin_unlock_irqrestore(&xhci->lock, | |
1362 | flags); | |
1363 | xhci_stop_device(xhci, slot_id, 1); | |
1364 | spin_lock_irqsave(&xhci->lock, flags); | |
1365 | } | |
0200b9f7 KHF |
1366 | xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3); |
1367 | spin_unlock_irqrestore(&xhci->lock, flags); | |
eb002726 KHF |
1368 | while (retries--) { |
1369 | usleep_range(4000, 8000); | |
1370 | temp = readl(ports[wIndex]->addr); | |
1371 | if ((temp & PORT_PLS_MASK) == XDEV_U3) | |
1372 | break; | |
1373 | } | |
0200b9f7 KHF |
1374 | spin_lock_irqsave(&xhci->lock, flags); |
1375 | temp = readl(ports[wIndex]->addr); | |
2c441780 | 1376 | bus_state->suspended_ports |= 1 << wIndex; |
0200b9f7 | 1377 | } |
2c441780 | 1378 | break; |
0f2a7930 SS |
1379 | case USB_PORT_FEAT_POWER: |
1380 | /* | |
1381 | * Turn on ports, even if there isn't per-port switching. | |
1382 | * HC will report connect events even before this is set. | |
37ebb549 | 1383 | * However, hub_wq will ignore the roothub events until |
0f2a7930 SS |
1384 | * the roothub is registered. |
1385 | */ | |
ec1dafe8 | 1386 | xhci_set_port_power(xhci, hcd, wIndex, true, &flags); |
0f2a7930 SS |
1387 | break; |
1388 | case USB_PORT_FEAT_RESET: | |
1389 | temp = (temp | PORT_RESET); | |
e740b019 | 1390 | writel(temp, ports[wIndex]->addr); |
0f2a7930 | 1391 | |
e740b019 | 1392 | temp = readl(ports[wIndex]->addr); |
8aaf19b8 KHF |
1393 | xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n", |
1394 | hcd->self.busnum, wIndex + 1, temp); | |
0f2a7930 | 1395 | break; |
4296c70a | 1396 | case USB_PORT_FEAT_REMOTE_WAKE_MASK: |
fdcf74ff MN |
1397 | xhci_set_remote_wake_mask(xhci, ports[wIndex], |
1398 | wake_mask); | |
e740b019 | 1399 | temp = readl(ports[wIndex]->addr); |
8aaf19b8 KHF |
1400 | xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n", |
1401 | hcd->self.busnum, wIndex + 1, temp); | |
4296c70a | 1402 | break; |
a11496eb AX |
1403 | case USB_PORT_FEAT_BH_PORT_RESET: |
1404 | temp |= PORT_WR; | |
e740b019 MN |
1405 | writel(temp, ports[wIndex]->addr); |
1406 | temp = readl(ports[wIndex]->addr); | |
a11496eb | 1407 | break; |
797b0ca5 | 1408 | case USB_PORT_FEAT_U1_TIMEOUT: |
b50107bb | 1409 | if (hcd->speed < HCD_USB3) |
797b0ca5 | 1410 | goto error; |
e740b019 | 1411 | temp = readl(ports[wIndex]->addr + PORTPMSC); |
797b0ca5 SS |
1412 | temp &= ~PORT_U1_TIMEOUT_MASK; |
1413 | temp |= PORT_U1_TIMEOUT(timeout); | |
e740b019 | 1414 | writel(temp, ports[wIndex]->addr + PORTPMSC); |
797b0ca5 SS |
1415 | break; |
1416 | case USB_PORT_FEAT_U2_TIMEOUT: | |
b50107bb | 1417 | if (hcd->speed < HCD_USB3) |
797b0ca5 | 1418 | goto error; |
e740b019 | 1419 | temp = readl(ports[wIndex]->addr + PORTPMSC); |
797b0ca5 SS |
1420 | temp &= ~PORT_U2_TIMEOUT_MASK; |
1421 | temp |= PORT_U2_TIMEOUT(timeout); | |
e740b019 | 1422 | writel(temp, ports[wIndex]->addr + PORTPMSC); |
797b0ca5 | 1423 | break; |
0f1d832e GZ |
1424 | case USB_PORT_FEAT_TEST: |
1425 | /* 4.19.6 Port Test Modes (USB2 Test Mode) */ | |
1426 | if (hcd->speed != HCD_USB2) | |
1427 | goto error; | |
62fb45d3 GKH |
1428 | if (test_mode > USB_TEST_FORCE_ENABLE || |
1429 | test_mode < USB_TEST_J) | |
0f1d832e | 1430 | goto error; |
ec1dafe8 MN |
1431 | retval = xhci_enter_test_mode(xhci, test_mode, wIndex, |
1432 | &flags); | |
0f1d832e | 1433 | break; |
0f2a7930 SS |
1434 | default: |
1435 | goto error; | |
1436 | } | |
5308a91b | 1437 | /* unblock any posted writes */ |
e740b019 | 1438 | temp = readl(ports[wIndex]->addr); |
0f2a7930 SS |
1439 | break; |
1440 | case ClearPortFeature: | |
a0885924 | 1441 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1442 | goto error; |
1443 | wIndex--; | |
e740b019 | 1444 | temp = readl(ports[wIndex]->addr); |
d9f11ba9 MN |
1445 | if (temp == ~(u32)0) { |
1446 | xhci_hc_died(xhci); | |
f9de8151 SS |
1447 | retval = -ENODEV; |
1448 | break; | |
1449 | } | |
4bbb0ace | 1450 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 SS |
1451 | temp = xhci_port_state_to_neutral(temp); |
1452 | switch (wValue) { | |
be88fe4f | 1453 | case USB_PORT_FEAT_SUSPEND: |
e740b019 | 1454 | temp = readl(ports[wIndex]->addr); |
be88fe4f AX |
1455 | xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); |
1456 | xhci_dbg(xhci, "PORTSC %04x\n", temp); | |
1457 | if (temp & PORT_RESET) | |
1458 | goto error; | |
5ac04bf1 | 1459 | if ((temp & PORT_PLS_MASK) == XDEV_U3) { |
be88fe4f AX |
1460 | if ((temp & PORT_PE) == 0) |
1461 | goto error; | |
be88fe4f | 1462 | |
f69115fd | 1463 | set_bit(wIndex, &bus_state->resuming_ports); |
330e2d61 | 1464 | usb_hcd_start_port_resume(&hcd->self, wIndex); |
6b7f40f7 MN |
1465 | xhci_set_link_state(xhci, ports[wIndex], |
1466 | XDEV_RESUME); | |
c9682dff | 1467 | spin_unlock_irqrestore(&xhci->lock, flags); |
7d3b016a | 1468 | msleep(USB_RESUME_TIMEOUT); |
a7114230 | 1469 | spin_lock_irqsave(&xhci->lock, flags); |
6b7f40f7 | 1470 | xhci_set_link_state(xhci, ports[wIndex], |
c9682dff | 1471 | XDEV_U0); |
f69115fd | 1472 | clear_bit(wIndex, &bus_state->resuming_ports); |
330e2d61 | 1473 | usb_hcd_end_port_resume(&hcd->self, wIndex); |
be88fe4f | 1474 | } |
a7114230 | 1475 | bus_state->port_c_suspend |= 1 << wIndex; |
be88fe4f | 1476 | |
5233630f SS |
1477 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1478 | wIndex + 1); | |
be88fe4f AX |
1479 | if (!slot_id) { |
1480 | xhci_dbg(xhci, "slot_id is zero\n"); | |
1481 | goto error; | |
1482 | } | |
1483 | xhci_ring_device(xhci, slot_id); | |
1484 | break; | |
1485 | case USB_PORT_FEAT_C_SUSPEND: | |
20b67cf5 | 1486 | bus_state->port_c_suspend &= ~(1 << wIndex); |
ff504f57 | 1487 | /* fall through */ |
0f2a7930 | 1488 | case USB_PORT_FEAT_C_RESET: |
a11496eb | 1489 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
0f2a7930 | 1490 | case USB_PORT_FEAT_C_CONNECTION: |
0f2a7930 | 1491 | case USB_PORT_FEAT_C_OVER_CURRENT: |
6219c047 | 1492 | case USB_PORT_FEAT_C_ENABLE: |
85387c0e | 1493 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
9425183d | 1494 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
34fb562a | 1495 | xhci_clear_port_change_bit(xhci, wValue, wIndex, |
e740b019 | 1496 | ports[wIndex]->addr, temp); |
0f2a7930 | 1497 | break; |
6219c047 | 1498 | case USB_PORT_FEAT_ENABLE: |
f6ff0ac8 | 1499 | xhci_disable_port(hcd, xhci, wIndex, |
e740b019 | 1500 | ports[wIndex]->addr, temp); |
6219c047 | 1501 | break; |
693d8eb8 | 1502 | case USB_PORT_FEAT_POWER: |
ec1dafe8 | 1503 | xhci_set_port_power(xhci, hcd, wIndex, false, &flags); |
693d8eb8 | 1504 | break; |
0f1d832e GZ |
1505 | case USB_PORT_FEAT_TEST: |
1506 | retval = xhci_exit_test_mode(xhci); | |
1507 | break; | |
0f2a7930 SS |
1508 | default: |
1509 | goto error; | |
1510 | } | |
0f2a7930 SS |
1511 | break; |
1512 | default: | |
1513 | error: | |
1514 | /* "stall" on error */ | |
1515 | retval = -EPIPE; | |
1516 | } | |
1517 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1518 | return retval; | |
1519 | } | |
1520 | ||
1521 | /* | |
1522 | * Returns 0 if the status hasn't changed, or the number of bytes in buf. | |
1523 | * Ports are 0-indexed from the HCD point of view, | |
1524 | * and 1-indexed from the USB core pointer of view. | |
0f2a7930 SS |
1525 | * |
1526 | * Note that the status change bits will be cleared as soon as a port status | |
1527 | * change event is generated, so we use the saved status from that event. | |
1528 | */ | |
1529 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) | |
1530 | { | |
1531 | unsigned long flags; | |
1532 | u32 temp, status; | |
56192531 | 1533 | u32 mask; |
0f2a7930 SS |
1534 | int i, retval; |
1535 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 1536 | int max_ports; |
20b67cf5 | 1537 | struct xhci_bus_state *bus_state; |
c52804a4 | 1538 | bool reset_change = false; |
e740b019 MN |
1539 | struct xhci_hub *rhub; |
1540 | struct xhci_port **ports; | |
0f2a7930 | 1541 | |
e740b019 MN |
1542 | rhub = xhci_get_rhub(hcd); |
1543 | ports = rhub->ports; | |
925f349d | 1544 | max_ports = rhub->num_ports; |
f6187f42 | 1545 | bus_state = &rhub->bus_state; |
0f2a7930 SS |
1546 | |
1547 | /* Initial status is no changes */ | |
a0885924 | 1548 | retval = (max_ports + 8) / 8; |
419a8e81 | 1549 | memset(buf, 0, retval); |
f370b996 AX |
1550 | |
1551 | /* | |
1552 | * Inform the usbcore about resume-in-progress by returning | |
1553 | * a non-zero value even if there are no status changes. | |
1554 | */ | |
1555 | status = bus_state->resuming_ports; | |
0f2a7930 | 1556 | |
9425183d | 1557 | mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; |
56192531 | 1558 | |
0f2a7930 SS |
1559 | spin_lock_irqsave(&xhci->lock, flags); |
1560 | /* For each port, did anything change? If so, set that bit in buf. */ | |
a0885924 | 1561 | for (i = 0; i < max_ports; i++) { |
e740b019 | 1562 | temp = readl(ports[i]->addr); |
d9f11ba9 MN |
1563 | if (temp == ~(u32)0) { |
1564 | xhci_hc_died(xhci); | |
f9de8151 SS |
1565 | retval = -ENODEV; |
1566 | break; | |
1567 | } | |
3f8499ac MN |
1568 | trace_xhci_hub_status_data(i, temp); |
1569 | ||
56192531 | 1570 | if ((temp & mask) != 0 || |
20b67cf5 SS |
1571 | (bus_state->port_c_suspend & 1 << i) || |
1572 | (bus_state->resume_done[i] && time_after_eq( | |
1573 | jiffies, bus_state->resume_done[i]))) { | |
419a8e81 | 1574 | buf[(i + 1) / 8] |= 1 << (i + 1) % 8; |
0f2a7930 SS |
1575 | status = 1; |
1576 | } | |
c52804a4 SS |
1577 | if ((temp & PORT_RC)) |
1578 | reset_change = true; | |
e9fb08d6 MN |
1579 | if (temp & PORT_OC) |
1580 | status = 1; | |
c52804a4 SS |
1581 | } |
1582 | if (!status && !reset_change) { | |
1583 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
1584 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1585 | } |
1586 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1587 | return status ? retval : 0; | |
1588 | } | |
9777e3ce AX |
1589 | |
1590 | #ifdef CONFIG_PM | |
1591 | ||
1592 | int xhci_bus_suspend(struct usb_hcd *hcd) | |
1593 | { | |
1594 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 1595 | int max_ports, port_index; |
20b67cf5 | 1596 | struct xhci_bus_state *bus_state; |
9777e3ce | 1597 | unsigned long flags; |
e740b019 MN |
1598 | struct xhci_hub *rhub; |
1599 | struct xhci_port **ports; | |
2f31a67f MN |
1600 | u32 portsc_buf[USB_MAXCHILDREN]; |
1601 | bool wake_enabled; | |
9777e3ce | 1602 | |
e740b019 MN |
1603 | rhub = xhci_get_rhub(hcd); |
1604 | ports = rhub->ports; | |
925f349d | 1605 | max_ports = rhub->num_ports; |
f6187f42 | 1606 | bus_state = &rhub->bus_state; |
2f31a67f | 1607 | wake_enabled = hcd->self.root_hub->do_remote_wakeup; |
9777e3ce AX |
1608 | |
1609 | spin_lock_irqsave(&xhci->lock, flags); | |
1610 | ||
2f31a67f | 1611 | if (wake_enabled) { |
fac4271d ZJC |
1612 | if (bus_state->resuming_ports || /* USB2 */ |
1613 | bus_state->port_remote_wakeup) { /* USB3 */ | |
f370b996 | 1614 | spin_unlock_irqrestore(&xhci->lock, flags); |
fac4271d | 1615 | xhci_dbg(xhci, "suspend failed because a port is resuming\n"); |
f370b996 | 1616 | return -EBUSY; |
9777e3ce AX |
1617 | } |
1618 | } | |
2f31a67f MN |
1619 | /* |
1620 | * Prepare ports for suspend, but don't write anything before all ports | |
1621 | * are checked and we know bus suspend can proceed | |
1622 | */ | |
20b67cf5 | 1623 | bus_state->bus_suspended = 0; |
2f31a67f | 1624 | port_index = max_ports; |
518e848e | 1625 | while (port_index--) { |
9777e3ce | 1626 | u32 t1, t2; |
d92f2c59 MN |
1627 | int retries = 10; |
1628 | retry: | |
e740b019 | 1629 | t1 = readl(ports[port_index]->addr); |
9777e3ce | 1630 | t2 = xhci_port_state_to_neutral(t1); |
2f31a67f | 1631 | portsc_buf[port_index] = 0; |
9777e3ce | 1632 | |
d92f2c59 MN |
1633 | /* |
1634 | * Give a USB3 port in link training time to finish, but don't | |
1635 | * prevent suspend as port might be stuck | |
1636 | */ | |
1637 | if ((hcd->speed >= HCD_USB3) && retries-- && | |
45f750c1 | 1638 | (t1 & PORT_PLS_MASK) == XDEV_POLLING) { |
2f31a67f | 1639 | spin_unlock_irqrestore(&xhci->lock, flags); |
d92f2c59 MN |
1640 | msleep(XHCI_PORT_POLLING_LFPS_TIME); |
1641 | spin_lock_irqsave(&xhci->lock, flags); | |
8aaf19b8 KHF |
1642 | xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n", |
1643 | hcd->self.busnum, port_index + 1); | |
d92f2c59 | 1644 | goto retry; |
2f31a67f | 1645 | } |
e9fb08d6 MN |
1646 | /* bail out if port detected a over-current condition */ |
1647 | if (t1 & PORT_OC) { | |
1648 | bus_state->bus_suspended = 0; | |
1649 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1650 | xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n"); | |
1651 | return -EBUSY; | |
1652 | } | |
2f31a67f MN |
1653 | /* suspend ports in U0, or bail out for new connect changes */ |
1654 | if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) { | |
1655 | if ((t1 & PORT_CSC) && wake_enabled) { | |
1656 | bus_state->bus_suspended = 0; | |
9777e3ce | 1657 | spin_unlock_irqrestore(&xhci->lock, flags); |
2f31a67f MN |
1658 | xhci_dbg(xhci, "Bus suspend bailout, port connect change\n"); |
1659 | return -EBUSY; | |
9777e3ce | 1660 | } |
8aaf19b8 KHF |
1661 | xhci_dbg(xhci, "port %d-%d not suspended\n", |
1662 | hcd->self.busnum, port_index + 1); | |
9777e3ce AX |
1663 | t2 &= ~PORT_PLS_MASK; |
1664 | t2 |= PORT_LINK_STROBE | XDEV_U3; | |
20b67cf5 | 1665 | set_bit(port_index, &bus_state->bus_suspended); |
9777e3ce | 1666 | } |
4296c70a | 1667 | /* USB core sets remote wake mask for USB 3.0 hubs, |
ceb6c9c8 | 1668 | * including the USB 3.0 roothub, but only if CONFIG_PM |
4296c70a SS |
1669 | * is enabled, so also enable remote wake here. |
1670 | */ | |
2f31a67f | 1671 | if (wake_enabled) { |
9777e3ce AX |
1672 | if (t1 & PORT_CONNECT) { |
1673 | t2 |= PORT_WKOC_E | PORT_WKDISC_E; | |
1674 | t2 &= ~PORT_WKCONN_E; | |
1675 | } else { | |
1676 | t2 |= PORT_WKOC_E | PORT_WKCONN_E; | |
1677 | t2 &= ~PORT_WKDISC_E; | |
1678 | } | |
bde0716d JL |
1679 | |
1680 | if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) && | |
1681 | (hcd->speed < HCD_USB3)) { | |
1682 | if (usb_amd_pt_check_port(hcd->self.controller, | |
1683 | port_index)) | |
1684 | t2 &= ~PORT_WAKE_BITS; | |
1685 | } | |
9777e3ce AX |
1686 | } else |
1687 | t2 &= ~PORT_WAKE_BITS; | |
1688 | ||
1689 | t1 = xhci_port_state_to_neutral(t1); | |
1690 | if (t1 != t2) | |
2f31a67f MN |
1691 | portsc_buf[port_index] = t2; |
1692 | } | |
1693 | ||
1694 | /* write port settings, stopping and suspending ports if needed */ | |
1695 | port_index = max_ports; | |
1696 | while (port_index--) { | |
1697 | if (!portsc_buf[port_index]) | |
1698 | continue; | |
1699 | if (test_bit(port_index, &bus_state->bus_suspended)) { | |
1700 | int slot_id; | |
1701 | ||
1702 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
1703 | port_index + 1); | |
1704 | if (slot_id) { | |
1705 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1706 | xhci_stop_device(xhci, slot_id, 1); | |
1707 | spin_lock_irqsave(&xhci->lock, flags); | |
1708 | } | |
1709 | } | |
1710 | writel(portsc_buf[port_index], ports[port_index]->addr); | |
9777e3ce AX |
1711 | } |
1712 | hcd->state = HC_STATE_SUSPENDED; | |
20b67cf5 | 1713 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); |
9777e3ce AX |
1714 | spin_unlock_irqrestore(&xhci->lock, flags); |
1715 | return 0; | |
1716 | } | |
1717 | ||
346e9973 MN |
1718 | /* |
1719 | * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. | |
1720 | * warm reset a USB3 device stuck in polling or compliance mode after resume. | |
1721 | * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 | |
1722 | */ | |
fdcf74ff | 1723 | static bool xhci_port_missing_cas_quirk(struct xhci_port *port) |
346e9973 MN |
1724 | { |
1725 | u32 portsc; | |
1726 | ||
fdcf74ff | 1727 | portsc = readl(port->addr); |
346e9973 MN |
1728 | |
1729 | /* if any of these are set we are not stuck */ | |
1730 | if (portsc & (PORT_CONNECT | PORT_CAS)) | |
1731 | return false; | |
1732 | ||
1733 | if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) && | |
1734 | ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE)) | |
1735 | return false; | |
1736 | ||
1737 | /* clear wakeup/change bits, and do a warm port reset */ | |
1738 | portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | |
1739 | portsc |= PORT_WR; | |
fdcf74ff | 1740 | writel(portsc, port->addr); |
346e9973 | 1741 | /* flush write */ |
fdcf74ff | 1742 | readl(port->addr); |
346e9973 MN |
1743 | return true; |
1744 | } | |
1745 | ||
9777e3ce AX |
1746 | int xhci_bus_resume(struct usb_hcd *hcd) |
1747 | { | |
1748 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
20b67cf5 | 1749 | struct xhci_bus_state *bus_state; |
9777e3ce | 1750 | unsigned long flags; |
a85c0f8d | 1751 | int max_ports, port_index; |
41485a90 MN |
1752 | int slot_id; |
1753 | int sret; | |
a85c0f8d MN |
1754 | u32 next_state; |
1755 | u32 temp, portsc; | |
e740b019 MN |
1756 | struct xhci_hub *rhub; |
1757 | struct xhci_port **ports; | |
9777e3ce | 1758 | |
e740b019 MN |
1759 | rhub = xhci_get_rhub(hcd); |
1760 | ports = rhub->ports; | |
925f349d | 1761 | max_ports = rhub->num_ports; |
f6187f42 | 1762 | bus_state = &rhub->bus_state; |
9777e3ce | 1763 | |
20b67cf5 | 1764 | if (time_before(jiffies, bus_state->next_statechange)) |
9777e3ce AX |
1765 | msleep(5); |
1766 | ||
1767 | spin_lock_irqsave(&xhci->lock, flags); | |
1768 | if (!HCD_HW_ACCESSIBLE(hcd)) { | |
1769 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1770 | return -ESHUTDOWN; | |
1771 | } | |
1772 | ||
1773 | /* delay the irqs */ | |
b0ba9720 | 1774 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1775 | temp &= ~CMD_EIE; |
204b7793 | 1776 | writel(temp, &xhci->op_regs->command); |
9777e3ce | 1777 | |
a85c0f8d MN |
1778 | /* bus specific resume for ports we suspended at bus_suspend */ |
1779 | if (hcd->speed >= HCD_USB3) | |
1780 | next_state = XDEV_U0; | |
1781 | else | |
1782 | next_state = XDEV_RESUME; | |
1783 | ||
518e848e SS |
1784 | port_index = max_ports; |
1785 | while (port_index--) { | |
e740b019 | 1786 | portsc = readl(ports[port_index]->addr); |
346e9973 MN |
1787 | |
1788 | /* warm reset CAS limited ports stuck in polling/compliance */ | |
1789 | if ((xhci->quirks & XHCI_MISSING_CAS) && | |
1790 | (hcd->speed >= HCD_USB3) && | |
fdcf74ff | 1791 | xhci_port_missing_cas_quirk(ports[port_index])) { |
8aaf19b8 KHF |
1792 | xhci_dbg(xhci, "reset stuck port %d-%d\n", |
1793 | hcd->self.busnum, port_index + 1); | |
a85c0f8d | 1794 | clear_bit(port_index, &bus_state->bus_suspended); |
346e9973 MN |
1795 | continue; |
1796 | } | |
a85c0f8d MN |
1797 | /* resume if we suspended the link, and it is still suspended */ |
1798 | if (test_bit(port_index, &bus_state->bus_suspended)) | |
1799 | switch (portsc & PORT_PLS_MASK) { | |
1800 | case XDEV_U3: | |
1801 | portsc = xhci_port_state_to_neutral(portsc); | |
1802 | portsc &= ~PORT_PLS_MASK; | |
1803 | portsc |= PORT_LINK_STROBE | next_state; | |
1804 | break; | |
1805 | case XDEV_RESUME: | |
1806 | /* resume already initiated */ | |
1807 | break; | |
1808 | default: | |
1809 | /* not in a resumeable state, ignore it */ | |
1810 | clear_bit(port_index, | |
1811 | &bus_state->bus_suspended); | |
1812 | break; | |
9777e3ce | 1813 | } |
a85c0f8d MN |
1814 | /* disable wake for all ports, write new link state if needed */ |
1815 | portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | |
e740b019 | 1816 | writel(portsc, ports[port_index]->addr); |
41485a90 MN |
1817 | } |
1818 | ||
a85c0f8d MN |
1819 | /* USB2 specific resume signaling delay and U0 link state transition */ |
1820 | if (hcd->speed < HCD_USB3) { | |
1821 | if (bus_state->bus_suspended) { | |
1822 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1823 | msleep(USB_RESUME_TIMEOUT); | |
1824 | spin_lock_irqsave(&xhci->lock, flags); | |
1825 | } | |
1826 | for_each_set_bit(port_index, &bus_state->bus_suspended, | |
1827 | BITS_PER_LONG) { | |
1828 | /* Clear PLC to poll it later for U0 transition */ | |
eaefcf24 | 1829 | xhci_test_and_clear_bit(xhci, ports[port_index], |
a85c0f8d | 1830 | PORT_PLC); |
6b7f40f7 | 1831 | xhci_set_link_state(xhci, ports[port_index], XDEV_U0); |
a85c0f8d | 1832 | } |
41485a90 MN |
1833 | } |
1834 | ||
a85c0f8d MN |
1835 | /* poll for U0 link state complete, both USB2 and USB3 */ |
1836 | for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) { | |
e740b019 | 1837 | sret = xhci_handshake(ports[port_index]->addr, PORT_PLC, |
41485a90 | 1838 | PORT_PLC, 10 * 1000); |
a85c0f8d | 1839 | if (sret) { |
8aaf19b8 KHF |
1840 | xhci_warn(xhci, "port %d-%d resume PLC timeout\n", |
1841 | hcd->self.busnum, port_index + 1); | |
a85c0f8d MN |
1842 | continue; |
1843 | } | |
eaefcf24 | 1844 | xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC); |
41485a90 MN |
1845 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1); |
1846 | if (slot_id) | |
1847 | xhci_ring_device(xhci, slot_id); | |
1848 | } | |
b0ba9720 | 1849 | (void) readl(&xhci->op_regs->command); |
9777e3ce | 1850 | |
20b67cf5 | 1851 | bus_state->next_statechange = jiffies + msecs_to_jiffies(5); |
9777e3ce | 1852 | /* re-enable irqs */ |
b0ba9720 | 1853 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1854 | temp |= CMD_EIE; |
204b7793 | 1855 | writel(temp, &xhci->op_regs->command); |
b0ba9720 | 1856 | temp = readl(&xhci->op_regs->command); |
9777e3ce AX |
1857 | |
1858 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1859 | return 0; | |
1860 | } | |
1861 | ||
8f9cc83c AS |
1862 | unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd) |
1863 | { | |
f6187f42 | 1864 | struct xhci_hub *rhub = xhci_get_rhub(hcd); |
8f9cc83c AS |
1865 | |
1866 | /* USB3 port wakeups are reported via usb_wakeup_notification() */ | |
f6187f42 | 1867 | return rhub->bus_state.resuming_ports; /* USB2 ports only */ |
8f9cc83c AS |
1868 | } |
1869 | ||
436a3890 | 1870 | #endif /* CONFIG_PM */ |