Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
0f2a7930 SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
0f2a7930 SS |
9 | */ |
10 | ||
ddba5cd0 MN |
11 | |
12 | #include <linux/slab.h> | |
0f2a7930 SS |
13 | #include <asm/unaligned.h> |
14 | ||
15 | #include "xhci.h" | |
4bdfe4c3 | 16 | #include "xhci-trace.h" |
0f2a7930 | 17 | |
9777e3ce AX |
18 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
19 | #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \ | |
20 | PORT_RC | PORT_PLC | PORT_PE) | |
21 | ||
5693e0b7 MN |
22 | /* USB 3 BOS descriptor and a capability descriptors, combined. |
23 | * Fields will be adjusted and added later in xhci_create_usb3_bos_desc() | |
24 | */ | |
48e82361 SS |
25 | static u8 usb_bos_descriptor [] = { |
26 | USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */ | |
27 | USB_DT_BOS, /* __u8 bDescriptorType */ | |
28 | 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */ | |
29 | 0x1, /* __u8 bNumDeviceCaps */ | |
5693e0b7 | 30 | /* First device capability, SuperSpeed */ |
48e82361 SS |
31 | USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */ |
32 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ | |
33 | USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */ | |
34 | 0x00, /* bmAttributes, LTM off by default */ | |
35 | USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */ | |
36 | 0x03, /* bFunctionalitySupport, | |
37 | USB 3.0 speed only */ | |
38 | 0x00, /* bU1DevExitLat, set later. */ | |
5693e0b7 MN |
39 | 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */ |
40 | /* Second device capability, SuperSpeedPlus */ | |
5da665fc | 41 | 0x1c, /* bLength 28, will be adjusted later */ |
5693e0b7 MN |
42 | USB_DT_DEVICE_CAPABILITY, /* Device Capability */ |
43 | USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */ | |
44 | 0x00, /* bReserved 0 */ | |
5da665fc MN |
45 | 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */ |
46 | 0x01, 0x00, /* wFunctionalitySupport */ | |
5693e0b7 | 47 | 0x00, 0x00, /* wReserved 0 */ |
5da665fc MN |
48 | /* Default Sublink Speed Attributes, overwrite if custom PSI exists */ |
49 | 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */ | |
50 | 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */ | |
51 | 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */ | |
52 | 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */ | |
48e82361 SS |
53 | }; |
54 | ||
5693e0b7 MN |
55 | static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf, |
56 | u16 wLength) | |
57 | { | |
58 | int i, ssa_count; | |
59 | u32 temp; | |
60 | u16 desc_size, ssp_cap_size, ssa_size = 0; | |
61 | bool usb3_1 = false; | |
62 | ||
63 | desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
64 | ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size; | |
65 | ||
66 | /* does xhci support USB 3.1 Enhanced SuperSpeed */ | |
5da665fc MN |
67 | if (xhci->usb3_rhub.min_rev >= 0x01) { |
68 | /* does xhci provide a PSI table for SSA speed attributes? */ | |
69 | if (xhci->usb3_rhub.psi_count) { | |
70 | /* two SSA entries for each unique PSI ID, RX and TX */ | |
71 | ssa_count = xhci->usb3_rhub.psi_uid_count * 2; | |
72 | ssa_size = ssa_count * sizeof(u32); | |
73 | ssp_cap_size -= 16; /* skip copying the default SSA */ | |
74 | } | |
5693e0b7 MN |
75 | desc_size += ssp_cap_size; |
76 | usb3_1 = true; | |
77 | } | |
78 | memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength)); | |
79 | ||
80 | if (usb3_1) { | |
81 | /* modify bos descriptor bNumDeviceCaps and wTotalLength */ | |
82 | buf[4] += 1; | |
83 | put_unaligned_le16(desc_size + ssa_size, &buf[2]); | |
84 | } | |
85 | ||
86 | if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE) | |
87 | return wLength; | |
88 | ||
89 | /* Indicate whether the host has LTM support. */ | |
90 | temp = readl(&xhci->cap_regs->hcc_params); | |
91 | if (HCC_LTC(temp)) | |
92 | buf[8] |= USB_LTM_SUPPORT; | |
93 | ||
94 | /* Set the U1 and U2 exit latencies. */ | |
95 | if ((xhci->quirks & XHCI_LPM_SUPPORT)) { | |
96 | temp = readl(&xhci->cap_regs->hcs_params3); | |
97 | buf[12] = HCS_U1_LATENCY(temp); | |
98 | put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); | |
99 | } | |
100 | ||
5da665fc MN |
101 | /* If PSI table exists, add the custom speed attributes from it */ |
102 | if (usb3_1 && xhci->usb3_rhub.psi_count) { | |
7bea22b1 | 103 | u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp; |
5693e0b7 MN |
104 | int offset; |
105 | ||
106 | ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE; | |
107 | ||
108 | if (wLength < desc_size) | |
109 | return wLength; | |
110 | buf[ssp_cap_base] = ssp_cap_size + ssa_size; | |
111 | ||
112 | /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */ | |
113 | bm_attrib = (ssa_count - 1) & 0x1f; | |
114 | bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5; | |
115 | put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]); | |
116 | ||
117 | if (wLength < desc_size + ssa_size) | |
118 | return wLength; | |
119 | /* | |
120 | * Create the Sublink Speed Attributes (SSA) array. | |
121 | * The xhci PSI field and USB 3.1 SSA fields are very similar, | |
122 | * but link type bits 7:6 differ for values 01b and 10b. | |
123 | * xhci has also only one PSI entry for a symmetric link when | |
124 | * USB 3.1 requires two SSA entries (RX and TX) for every link | |
125 | */ | |
126 | offset = desc_size; | |
127 | for (i = 0; i < xhci->usb3_rhub.psi_count; i++) { | |
128 | psi = xhci->usb3_rhub.psi[i]; | |
129 | psi &= ~USB_SSP_SUBLINK_SPEED_RSVD; | |
7bea22b1 MN |
130 | psi_exp = XHCI_EXT_PORT_PSIE(psi); |
131 | psi_mant = XHCI_EXT_PORT_PSIM(psi); | |
132 | ||
133 | /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */ | |
134 | for (; psi_exp < 3; psi_exp++) | |
135 | psi_mant /= 1000; | |
136 | if (psi_mant >= 10) | |
137 | psi |= BIT(14); | |
138 | ||
5693e0b7 MN |
139 | if ((psi & PLT_MASK) == PLT_SYM) { |
140 | /* Symmetric, create SSA RX and TX from one PSI entry */ | |
141 | put_unaligned_le32(psi, &buf[offset]); | |
142 | psi |= 1 << 7; /* turn entry to TX */ | |
143 | offset += 4; | |
144 | if (offset >= desc_size + ssa_size) | |
145 | return desc_size + ssa_size; | |
146 | } else if ((psi & PLT_MASK) == PLT_ASYM_RX) { | |
147 | /* Asymetric RX, flip bits 7:6 for SSA */ | |
148 | psi ^= PLT_MASK; | |
149 | } | |
150 | put_unaligned_le32(psi, &buf[offset]); | |
151 | offset += 4; | |
152 | if (offset >= desc_size + ssa_size) | |
153 | return desc_size + ssa_size; | |
154 | } | |
155 | } | |
156 | /* ssa_size is 0 for other than usb 3.1 hosts */ | |
157 | return desc_size + ssa_size; | |
158 | } | |
48e82361 | 159 | |
4bbb0ace SS |
160 | static void xhci_common_hub_descriptor(struct xhci_hcd *xhci, |
161 | struct usb_hub_descriptor *desc, int ports) | |
0f2a7930 | 162 | { |
0f2a7930 SS |
163 | u16 temp; |
164 | ||
0f2a7930 SS |
165 | desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */ |
166 | desc->bHubContrCurrent = 0; | |
167 | ||
168 | desc->bNbrPorts = ports; | |
0f2a7930 | 169 | temp = 0; |
c8421147 | 170 | /* Bits 1:0 - support per-port power switching, or power always on */ |
0f2a7930 | 171 | if (HCC_PPC(xhci->hcc_params)) |
c8421147 | 172 | temp |= HUB_CHAR_INDV_PORT_LPSM; |
0f2a7930 | 173 | else |
c8421147 | 174 | temp |= HUB_CHAR_NO_LPSM; |
0f2a7930 SS |
175 | /* Bit 2 - root hubs are not part of a compound device */ |
176 | /* Bits 4:3 - individual port over current protection */ | |
c8421147 | 177 | temp |= HUB_CHAR_INDV_PORT_OCPM; |
0f2a7930 SS |
178 | /* Bits 6:5 - no TTs in root ports */ |
179 | /* Bit 7 - no port indicators */ | |
28ccd296 | 180 | desc->wHubCharacteristics = cpu_to_le16(temp); |
0f2a7930 SS |
181 | } |
182 | ||
4bbb0ace SS |
183 | /* Fill in the USB 2.0 roothub descriptor */ |
184 | static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
185 | struct usb_hub_descriptor *desc) | |
186 | { | |
187 | int ports; | |
188 | u16 temp; | |
189 | __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8]; | |
190 | u32 portsc; | |
191 | unsigned int i; | |
e740b019 | 192 | struct xhci_hub *rhub; |
4bbb0ace | 193 | |
e740b019 MN |
194 | rhub = &xhci->usb2_rhub; |
195 | ports = rhub->num_ports; | |
4bbb0ace | 196 | xhci_common_hub_descriptor(xhci, desc, ports); |
c8421147 | 197 | desc->bDescriptorType = USB_DT_HUB; |
4bbb0ace | 198 | temp = 1 + (ports / 8); |
c8421147 | 199 | desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; |
4bbb0ace SS |
200 | |
201 | /* The Device Removable bits are reported on a byte granularity. | |
202 | * If the port doesn't exist within that byte, the bit is set to 0. | |
203 | */ | |
204 | memset(port_removable, 0, sizeof(port_removable)); | |
205 | for (i = 0; i < ports; i++) { | |
e740b019 | 206 | portsc = readl(rhub->ports[i]->addr); |
4bbb0ace SS |
207 | /* If a device is removable, PORTSC reports a 0, same as in the |
208 | * hub descriptor DeviceRemovable bits. | |
209 | */ | |
210 | if (portsc & PORT_DEV_REMOVE) | |
211 | /* This math is hairy because bit 0 of DeviceRemovable | |
212 | * is reserved, and bit 1 is for port 1, etc. | |
213 | */ | |
214 | port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8); | |
215 | } | |
216 | ||
217 | /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN | |
218 | * ports on it. The USB 2.0 specification says that there are two | |
219 | * variable length fields at the end of the hub descriptor: | |
220 | * DeviceRemovable and PortPwrCtrlMask. But since we can have less than | |
221 | * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array | |
222 | * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to | |
223 | * 0xFF, so we initialize the both arrays (DeviceRemovable and | |
224 | * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each | |
225 | * set of ports that actually exist. | |
226 | */ | |
227 | memset(desc->u.hs.DeviceRemovable, 0xff, | |
228 | sizeof(desc->u.hs.DeviceRemovable)); | |
229 | memset(desc->u.hs.PortPwrCtrlMask, 0xff, | |
230 | sizeof(desc->u.hs.PortPwrCtrlMask)); | |
231 | ||
232 | for (i = 0; i < (ports + 1 + 7) / 8; i++) | |
233 | memset(&desc->u.hs.DeviceRemovable[i], port_removable[i], | |
234 | sizeof(__u8)); | |
235 | } | |
236 | ||
237 | /* Fill in the USB 3.0 roothub descriptor */ | |
238 | static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
239 | struct usb_hub_descriptor *desc) | |
240 | { | |
241 | int ports; | |
242 | u16 port_removable; | |
243 | u32 portsc; | |
244 | unsigned int i; | |
e740b019 | 245 | struct xhci_hub *rhub; |
4bbb0ace | 246 | |
e740b019 MN |
247 | rhub = &xhci->usb3_rhub; |
248 | ports = rhub->num_ports; | |
4bbb0ace | 249 | xhci_common_hub_descriptor(xhci, desc, ports); |
c8421147 AD |
250 | desc->bDescriptorType = USB_DT_SS_HUB; |
251 | desc->bDescLength = USB_DT_SS_HUB_SIZE; | |
4bbb0ace SS |
252 | |
253 | /* header decode latency should be zero for roothubs, | |
254 | * see section 4.23.5.2. | |
255 | */ | |
256 | desc->u.ss.bHubHdrDecLat = 0; | |
257 | desc->u.ss.wHubDelay = 0; | |
258 | ||
259 | port_removable = 0; | |
260 | /* bit 0 is reserved, bit 1 is for port 1, etc. */ | |
261 | for (i = 0; i < ports; i++) { | |
e740b019 | 262 | portsc = readl(rhub->ports[i]->addr); |
4bbb0ace SS |
263 | if (portsc & PORT_DEV_REMOVE) |
264 | port_removable |= 1 << (i + 1); | |
265 | } | |
27c411c9 LT |
266 | |
267 | desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable); | |
4bbb0ace SS |
268 | } |
269 | ||
270 | static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci, | |
271 | struct usb_hub_descriptor *desc) | |
272 | { | |
273 | ||
b50107bb | 274 | if (hcd->speed >= HCD_USB3) |
4bbb0ace SS |
275 | xhci_usb3_hub_descriptor(hcd, xhci, desc); |
276 | else | |
277 | xhci_usb2_hub_descriptor(hcd, xhci, desc); | |
278 | ||
279 | } | |
280 | ||
0f2a7930 SS |
281 | static unsigned int xhci_port_speed(unsigned int port_status) |
282 | { | |
283 | if (DEV_LOWSPEED(port_status)) | |
288ead45 | 284 | return USB_PORT_STAT_LOW_SPEED; |
0f2a7930 | 285 | if (DEV_HIGHSPEED(port_status)) |
288ead45 | 286 | return USB_PORT_STAT_HIGH_SPEED; |
0f2a7930 SS |
287 | /* |
288 | * FIXME: Yes, we should check for full speed, but the core uses that as | |
289 | * a default in portspeed() in usb/core/hub.c (which is the only place | |
288ead45 | 290 | * USB_PORT_STAT_*_SPEED is used). |
0f2a7930 SS |
291 | */ |
292 | return 0; | |
293 | } | |
294 | ||
295 | /* | |
296 | * These bits are Read Only (RO) and should be saved and written to the | |
297 | * registers: 0, 3, 10:13, 30 | |
298 | * connect status, over-current status, port speed, and device removable. | |
299 | * connect status and port speed are also sticky - meaning they're in | |
300 | * the AUX well and they aren't changed by a hot, warm, or cold reset. | |
301 | */ | |
302 | #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30)) | |
303 | /* | |
304 | * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit: | |
305 | * bits 5:8, 9, 14:15, 25:27 | |
306 | * link state, port power, port indicator state, "wake on" enable state | |
307 | */ | |
308 | #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25)) | |
309 | /* | |
310 | * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect: | |
311 | * bit 4 (port reset) | |
312 | */ | |
313 | #define XHCI_PORT_RW1S ((1<<4)) | |
314 | /* | |
315 | * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect: | |
316 | * bits 1, 17, 18, 19, 20, 21, 22, 23 | |
317 | * port enable/disable, and | |
318 | * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports), | |
319 | * over-current, reset, link state, and L1 change | |
320 | */ | |
321 | #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17)) | |
322 | /* | |
323 | * Bit 16 is RW, and writing a '1' to it causes the link state control to be | |
324 | * latched in | |
325 | */ | |
326 | #define XHCI_PORT_RW ((1<<16)) | |
327 | /* | |
328 | * These bits are Reserved Zero (RsvdZ) and zero should be written to them: | |
329 | * bits 2, 24, 28:31 | |
330 | */ | |
331 | #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28)) | |
332 | ||
333 | /* | |
334 | * Given a port state, this function returns a value that would result in the | |
335 | * port being in the same state, if the value was written to the port status | |
336 | * control register. | |
337 | * Save Read Only (RO) bits and save read/write bits where | |
338 | * writing a 0 clears the bit and writing a 1 sets the bit (RWS). | |
339 | * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. | |
340 | */ | |
56192531 | 341 | u32 xhci_port_state_to_neutral(u32 state) |
0f2a7930 SS |
342 | { |
343 | /* Save read-only status and port state */ | |
344 | return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); | |
345 | } | |
346 | ||
be88fe4f AX |
347 | /* |
348 | * find slot id based on port number. | |
f6ff0ac8 | 349 | * @port: The one-based port number from one of the two split roothubs. |
be88fe4f | 350 | */ |
5233630f SS |
351 | int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
352 | u16 port) | |
be88fe4f AX |
353 | { |
354 | int slot_id; | |
355 | int i; | |
f6ff0ac8 | 356 | enum usb_device_speed speed; |
be88fe4f AX |
357 | |
358 | slot_id = 0; | |
359 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
2278446e | 360 | if (!xhci->devs[i] || !xhci->devs[i]->udev) |
be88fe4f | 361 | continue; |
f6ff0ac8 | 362 | speed = xhci->devs[i]->udev->speed; |
b50107bb | 363 | if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3)) |
fe30182c | 364 | && xhci->devs[i]->fake_port == port) { |
be88fe4f AX |
365 | slot_id = i; |
366 | break; | |
367 | } | |
368 | } | |
369 | ||
370 | return slot_id; | |
371 | } | |
372 | ||
373 | /* | |
374 | * Stop device | |
375 | * It issues stop endpoint command for EP 0 to 30. And wait the last command | |
376 | * to complete. | |
377 | * suspend will set to 1, if suspend bit need to set in command. | |
378 | */ | |
379 | static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend) | |
380 | { | |
381 | struct xhci_virt_device *virt_dev; | |
382 | struct xhci_command *cmd; | |
383 | unsigned long flags; | |
be88fe4f AX |
384 | int ret; |
385 | int i; | |
386 | ||
387 | ret = 0; | |
388 | virt_dev = xhci->devs[slot_id]; | |
88716a93 JL |
389 | if (!virt_dev) |
390 | return -ENODEV; | |
391 | ||
a711edee FB |
392 | trace_xhci_stop_device(virt_dev); |
393 | ||
103afda0 | 394 | cmd = xhci_alloc_command(xhci, true, GFP_NOIO); |
74e0b564 | 395 | if (!cmd) |
be88fe4f | 396 | return -ENOMEM; |
be88fe4f AX |
397 | |
398 | spin_lock_irqsave(&xhci->lock, flags); | |
399 | for (i = LAST_EP_INDEX; i > 0; i--) { | |
ddba5cd0 | 400 | if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) { |
28a2369f | 401 | struct xhci_ep_ctx *ep_ctx; |
ddba5cd0 | 402 | struct xhci_command *command; |
28a2369f SS |
403 | |
404 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i); | |
405 | ||
406 | /* Check ep is running, required by AMD SNPS 3.1 xHC */ | |
407 | if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING) | |
408 | continue; | |
409 | ||
103afda0 | 410 | command = xhci_alloc_command(xhci, false, GFP_NOWAIT); |
ddba5cd0 MN |
411 | if (!command) { |
412 | spin_unlock_irqrestore(&xhci->lock, flags); | |
b3207c65 MR |
413 | ret = -ENOMEM; |
414 | goto cmd_cleanup; | |
415 | } | |
416 | ||
417 | ret = xhci_queue_stop_endpoint(xhci, command, slot_id, | |
418 | i, suspend); | |
419 | if (ret) { | |
420 | spin_unlock_irqrestore(&xhci->lock, flags); | |
421 | xhci_free_command(xhci, command); | |
422 | goto cmd_cleanup; | |
ddba5cd0 | 423 | } |
ddba5cd0 | 424 | } |
be88fe4f | 425 | } |
b3207c65 MR |
426 | ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend); |
427 | if (ret) { | |
428 | spin_unlock_irqrestore(&xhci->lock, flags); | |
429 | goto cmd_cleanup; | |
430 | } | |
431 | ||
be88fe4f AX |
432 | xhci_ring_cmd_db(xhci); |
433 | spin_unlock_irqrestore(&xhci->lock, flags); | |
434 | ||
435 | /* Wait for last stop endpoint command to finish */ | |
c311e391 MN |
436 | wait_for_completion(cmd->completion); |
437 | ||
0b7c105a | 438 | if (cmd->status == COMP_COMMAND_ABORTED || |
604d02a2 | 439 | cmd->status == COMP_COMMAND_RING_STOPPED) { |
c311e391 | 440 | xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n"); |
be88fe4f | 441 | ret = -ETIME; |
be88fe4f | 442 | } |
b3207c65 MR |
443 | |
444 | cmd_cleanup: | |
be88fe4f AX |
445 | xhci_free_command(xhci, cmd); |
446 | return ret; | |
447 | } | |
448 | ||
449 | /* | |
450 | * Ring device, it rings the all doorbells unconditionally. | |
451 | */ | |
56192531 | 452 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id) |
be88fe4f | 453 | { |
b7f9696b HG |
454 | int i, s; |
455 | struct xhci_virt_ep *ep; | |
456 | ||
457 | for (i = 0; i < LAST_EP_INDEX + 1; i++) { | |
458 | ep = &xhci->devs[slot_id]->eps[i]; | |
be88fe4f | 459 | |
b7f9696b HG |
460 | if (ep->ep_state & EP_HAS_STREAMS) { |
461 | for (s = 1; s < ep->stream_info->num_streams; s++) | |
462 | xhci_ring_ep_doorbell(xhci, slot_id, i, s); | |
463 | } else if (ep->ring && ep->ring->dequeue) { | |
be88fe4f | 464 | xhci_ring_ep_doorbell(xhci, slot_id, i, 0); |
b7f9696b HG |
465 | } |
466 | } | |
be88fe4f AX |
467 | |
468 | return; | |
469 | } | |
470 | ||
f6ff0ac8 | 471 | static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
28ccd296 | 472 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
6219c047 | 473 | { |
6dd0a3a7 | 474 | /* Don't allow the USB core to disable SuperSpeed ports. */ |
b50107bb | 475 | if (hcd->speed >= HCD_USB3) { |
6dd0a3a7 SS |
476 | xhci_dbg(xhci, "Ignoring request to disable " |
477 | "SuperSpeed port.\n"); | |
478 | return; | |
479 | } | |
480 | ||
41135de1 FB |
481 | if (xhci->quirks & XHCI_BROKEN_PORT_PED) { |
482 | xhci_dbg(xhci, | |
483 | "Broken Port Enabled/Disabled, ignoring port disable request.\n"); | |
484 | return; | |
485 | } | |
486 | ||
6219c047 | 487 | /* Write 1 to disable the port */ |
204b7793 | 488 | writel(port_status | PORT_PE, addr); |
b0ba9720 | 489 | port_status = readl(addr); |
6219c047 SS |
490 | xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n", |
491 | wIndex, port_status); | |
492 | } | |
493 | ||
34fb562a | 494 | static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue, |
28ccd296 | 495 | u16 wIndex, __le32 __iomem *addr, u32 port_status) |
34fb562a SS |
496 | { |
497 | char *port_change_bit; | |
498 | u32 status; | |
499 | ||
500 | switch (wValue) { | |
501 | case USB_PORT_FEAT_C_RESET: | |
502 | status = PORT_RC; | |
503 | port_change_bit = "reset"; | |
504 | break; | |
a11496eb AX |
505 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
506 | status = PORT_WRC; | |
507 | port_change_bit = "warm(BH) reset"; | |
508 | break; | |
34fb562a SS |
509 | case USB_PORT_FEAT_C_CONNECTION: |
510 | status = PORT_CSC; | |
511 | port_change_bit = "connect"; | |
512 | break; | |
513 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
514 | status = PORT_OCC; | |
515 | port_change_bit = "over-current"; | |
516 | break; | |
6219c047 SS |
517 | case USB_PORT_FEAT_C_ENABLE: |
518 | status = PORT_PEC; | |
519 | port_change_bit = "enable/disable"; | |
520 | break; | |
be88fe4f AX |
521 | case USB_PORT_FEAT_C_SUSPEND: |
522 | status = PORT_PLC; | |
523 | port_change_bit = "suspend/resume"; | |
524 | break; | |
85387c0e AX |
525 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
526 | status = PORT_PLC; | |
527 | port_change_bit = "link state"; | |
528 | break; | |
9425183d LB |
529 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
530 | status = PORT_CEC; | |
531 | port_change_bit = "config error"; | |
532 | break; | |
34fb562a SS |
533 | default: |
534 | /* Should never happen */ | |
535 | return; | |
536 | } | |
537 | /* Change bits are all write 1 to clear */ | |
204b7793 | 538 | writel(port_status | status, addr); |
b0ba9720 | 539 | port_status = readl(addr); |
34fb562a SS |
540 | xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n", |
541 | port_change_bit, wIndex, port_status); | |
542 | } | |
543 | ||
ffd4b4fc MN |
544 | struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd) |
545 | { | |
546 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
547 | ||
548 | if (hcd->speed >= HCD_USB3) | |
549 | return &xhci->usb3_rhub; | |
550 | return &xhci->usb2_rhub; | |
551 | } | |
552 | ||
a6ff6cbf GZ |
553 | /* |
554 | * xhci_set_port_power() must be called with xhci->lock held. | |
555 | * It will release and re-aquire the lock while calling ACPI | |
556 | * method. | |
557 | */ | |
558 | static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd, | |
ec1dafe8 | 559 | u16 index, bool on, unsigned long *flags) |
a6ff6cbf | 560 | { |
e740b019 MN |
561 | struct xhci_hub *rhub; |
562 | struct xhci_port *port; | |
a6ff6cbf | 563 | u32 temp; |
a6ff6cbf | 564 | |
e740b019 MN |
565 | rhub = xhci_get_rhub(hcd); |
566 | port = rhub->ports[index]; | |
567 | temp = readl(port->addr); | |
a6ff6cbf GZ |
568 | temp = xhci_port_state_to_neutral(temp); |
569 | if (on) { | |
570 | /* Power on */ | |
e740b019 MN |
571 | writel(temp | PORT_POWER, port->addr); |
572 | temp = readl(port->addr); | |
a6ff6cbf GZ |
573 | xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", |
574 | index, temp); | |
575 | } else { | |
576 | /* Power off */ | |
e740b019 | 577 | writel(temp & ~PORT_POWER, port->addr); |
a6ff6cbf GZ |
578 | } |
579 | ||
ec1dafe8 | 580 | spin_unlock_irqrestore(&xhci->lock, *flags); |
a6ff6cbf GZ |
581 | temp = usb_acpi_power_manageable(hcd->self.root_hub, |
582 | index); | |
583 | if (temp) | |
584 | usb_acpi_set_power_state(hcd->self.root_hub, | |
585 | index, on); | |
ec1dafe8 | 586 | spin_lock_irqsave(&xhci->lock, *flags); |
a6ff6cbf GZ |
587 | } |
588 | ||
0f1d832e GZ |
589 | static void xhci_port_set_test_mode(struct xhci_hcd *xhci, |
590 | u16 test_mode, u16 wIndex) | |
591 | { | |
592 | u32 temp; | |
e740b019 | 593 | struct xhci_port *port; |
0f1d832e | 594 | |
e740b019 MN |
595 | /* xhci only supports test mode for usb2 ports */ |
596 | port = xhci->usb2_rhub.ports[wIndex]; | |
597 | temp = readl(port->addr + PORTPMSC); | |
0f1d832e | 598 | temp |= test_mode << PORT_TEST_MODE_SHIFT; |
e740b019 | 599 | writel(temp, port->addr + PORTPMSC); |
0f1d832e GZ |
600 | xhci->test_mode = test_mode; |
601 | if (test_mode == TEST_FORCE_EN) | |
602 | xhci_start(xhci); | |
603 | } | |
604 | ||
605 | static int xhci_enter_test_mode(struct xhci_hcd *xhci, | |
ec1dafe8 | 606 | u16 test_mode, u16 wIndex, unsigned long *flags) |
0f1d832e GZ |
607 | { |
608 | int i, retval; | |
609 | ||
610 | /* Disable all Device Slots */ | |
611 | xhci_dbg(xhci, "Disable all slots\n"); | |
576d5546 | 612 | spin_unlock_irqrestore(&xhci->lock, *flags); |
0f1d832e | 613 | for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { |
b64149ca LB |
614 | if (!xhci->devs[i]) |
615 | continue; | |
616 | ||
cd3f1790 | 617 | retval = xhci_disable_slot(xhci, i); |
0f1d832e GZ |
618 | if (retval) |
619 | xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n", | |
620 | i, retval); | |
621 | } | |
576d5546 | 622 | spin_lock_irqsave(&xhci->lock, *flags); |
0f1d832e GZ |
623 | /* Put all ports to the Disable state by clear PP */ |
624 | xhci_dbg(xhci, "Disable all port (PP = 0)\n"); | |
625 | /* Power off USB3 ports*/ | |
e740b019 | 626 | for (i = 0; i < xhci->usb3_rhub.num_ports; i++) |
ec1dafe8 | 627 | xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags); |
0f1d832e | 628 | /* Power off USB2 ports*/ |
e740b019 | 629 | for (i = 0; i < xhci->usb2_rhub.num_ports; i++) |
ec1dafe8 | 630 | xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags); |
0f1d832e GZ |
631 | /* Stop the controller */ |
632 | xhci_dbg(xhci, "Stop controller\n"); | |
633 | retval = xhci_halt(xhci); | |
634 | if (retval) | |
635 | return retval; | |
636 | /* Disable runtime PM for test mode */ | |
637 | pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller); | |
638 | /* Set PORTPMSC.PTC field to enter selected test mode */ | |
639 | /* Port is selected by wIndex. port_id = wIndex + 1 */ | |
640 | xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n", | |
641 | test_mode, wIndex + 1); | |
642 | xhci_port_set_test_mode(xhci, test_mode, wIndex); | |
643 | return retval; | |
644 | } | |
645 | ||
646 | static int xhci_exit_test_mode(struct xhci_hcd *xhci) | |
647 | { | |
648 | int retval; | |
649 | ||
650 | if (!xhci->test_mode) { | |
651 | xhci_err(xhci, "Not in test mode, do nothing.\n"); | |
652 | return 0; | |
653 | } | |
654 | if (xhci->test_mode == TEST_FORCE_EN && | |
655 | !(xhci->xhc_state & XHCI_STATE_HALTED)) { | |
656 | retval = xhci_halt(xhci); | |
657 | if (retval) | |
658 | return retval; | |
659 | } | |
660 | pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); | |
661 | xhci->test_mode = 0; | |
662 | return xhci_reset(xhci); | |
663 | } | |
664 | ||
6b7f40f7 MN |
665 | void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, |
666 | u32 link_state) | |
c9682dff AX |
667 | { |
668 | u32 temp; | |
669 | ||
6b7f40f7 | 670 | temp = readl(port->addr); |
c9682dff AX |
671 | temp = xhci_port_state_to_neutral(temp); |
672 | temp &= ~PORT_PLS_MASK; | |
673 | temp |= PORT_LINK_STROBE | link_state; | |
6b7f40f7 | 674 | writel(temp, port->addr); |
c9682dff AX |
675 | } |
676 | ||
ed384bd3 | 677 | static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci, |
fdcf74ff | 678 | struct xhci_port *port, u16 wake_mask) |
4296c70a SS |
679 | { |
680 | u32 temp; | |
681 | ||
fdcf74ff | 682 | temp = readl(port->addr); |
4296c70a SS |
683 | temp = xhci_port_state_to_neutral(temp); |
684 | ||
685 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT) | |
686 | temp |= PORT_WKCONN_E; | |
687 | else | |
688 | temp &= ~PORT_WKCONN_E; | |
689 | ||
690 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT) | |
691 | temp |= PORT_WKDISC_E; | |
692 | else | |
693 | temp &= ~PORT_WKDISC_E; | |
694 | ||
695 | if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT) | |
696 | temp |= PORT_WKOC_E; | |
697 | else | |
698 | temp &= ~PORT_WKOC_E; | |
699 | ||
fdcf74ff | 700 | writel(temp, port->addr); |
4296c70a SS |
701 | } |
702 | ||
d2f52c9e | 703 | /* Test and clear port RWC bit */ |
eaefcf24 MN |
704 | void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port, |
705 | u32 port_bit) | |
d2f52c9e AX |
706 | { |
707 | u32 temp; | |
708 | ||
eaefcf24 | 709 | temp = readl(port->addr); |
d2f52c9e AX |
710 | if (temp & port_bit) { |
711 | temp = xhci_port_state_to_neutral(temp); | |
712 | temp |= port_bit; | |
eaefcf24 | 713 | writel(temp, port->addr); |
d2f52c9e AX |
714 | } |
715 | } | |
716 | ||
8bea2bd3 | 717 | /* Updates Link Status for super Speed port */ |
96908589 FB |
718 | static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci, |
719 | u32 *status, u32 status_reg) | |
8bea2bd3 SL |
720 | { |
721 | u32 pls = status_reg & PORT_PLS_MASK; | |
722 | ||
723 | /* resume state is a xHCI internal state. | |
243292a2 ZJC |
724 | * Do not report it to usb core, instead, pretend to be U3, |
725 | * thus usb core knows it's not ready for transfer | |
8bea2bd3 | 726 | */ |
243292a2 ZJC |
727 | if (pls == XDEV_RESUME) { |
728 | *status |= USB_SS_PORT_LS_U3; | |
8bea2bd3 | 729 | return; |
243292a2 | 730 | } |
8bea2bd3 SL |
731 | |
732 | /* When the CAS bit is set then warm reset | |
733 | * should be performed on port | |
734 | */ | |
735 | if (status_reg & PORT_CAS) { | |
736 | /* The CAS bit can be set while the port is | |
737 | * in any link state. | |
738 | * Only roothubs have CAS bit, so we | |
739 | * pretend to be in compliance mode | |
740 | * unless we're already in compliance | |
741 | * or the inactive state. | |
742 | */ | |
743 | if (pls != USB_SS_PORT_LS_COMP_MOD && | |
744 | pls != USB_SS_PORT_LS_SS_INACTIVE) { | |
745 | pls = USB_SS_PORT_LS_COMP_MOD; | |
746 | } | |
747 | /* Return also connection bit - | |
748 | * hub state machine resets port | |
749 | * when this bit is set. | |
750 | */ | |
751 | pls |= USB_PORT_STAT_CONNECTION; | |
71c731a2 AC |
752 | } else { |
753 | /* | |
754 | * If CAS bit isn't set but the Port is already at | |
755 | * Compliance Mode, fake a connection so the USB core | |
756 | * notices the Compliance state and resets the port. | |
757 | * This resolves an issue generated by the SN65LVPE502CP | |
758 | * in which sometimes the port enters compliance mode | |
759 | * caused by a delay on the host-device negotiation. | |
760 | */ | |
96908589 FB |
761 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && |
762 | (pls == USB_SS_PORT_LS_COMP_MOD)) | |
71c731a2 | 763 | pls |= USB_PORT_STAT_CONNECTION; |
8bea2bd3 | 764 | } |
71c731a2 | 765 | |
8bea2bd3 SL |
766 | /* update status field */ |
767 | *status |= pls; | |
768 | } | |
769 | ||
71c731a2 AC |
770 | /* |
771 | * Function for Compliance Mode Quirk. | |
772 | * | |
773 | * This Function verifies if all xhc USB3 ports have entered U0, if so, | |
774 | * the compliance mode timer is deleted. A port won't enter | |
775 | * compliance mode if it has previously entered U0. | |
776 | */ | |
5f20cf12 SK |
777 | static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status, |
778 | u16 wIndex) | |
71c731a2 | 779 | { |
e740b019 | 780 | u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1); |
71c731a2 AC |
781 | bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0); |
782 | ||
783 | if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK)) | |
784 | return; | |
785 | ||
786 | if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) { | |
787 | xhci->port_status_u0 |= 1 << wIndex; | |
788 | if (xhci->port_status_u0 == all_ports_seen_u0) { | |
789 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
790 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
791 | "All USB3 ports have entered U0 already!"); | |
792 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
793 | "Compliance Mode Recovery Timer Deleted."); | |
71c731a2 AC |
794 | } |
795 | } | |
796 | } | |
797 | ||
395f5409 MN |
798 | static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li) |
799 | { | |
800 | u32 ext_stat = 0; | |
801 | int speed_id; | |
802 | ||
803 | /* only support rx and tx lane counts of 1 in usb3.1 spec */ | |
804 | speed_id = DEV_PORT_SPEED(raw_port_status); | |
805 | ext_stat |= speed_id; /* bits 3:0, RX speed id */ | |
806 | ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */ | |
807 | ||
808 | ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */ | |
809 | ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */ | |
810 | ||
811 | return ext_stat; | |
812 | } | |
813 | ||
5f78a54f MN |
814 | static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status, |
815 | u32 portsc) | |
816 | { | |
817 | struct xhci_hcd *xhci; | |
818 | u32 link_state; | |
819 | u32 portnum; | |
820 | ||
821 | xhci = hcd_to_xhci(port->rhub->hcd); | |
822 | link_state = portsc & PORT_PLS_MASK; | |
823 | portnum = port->hcd_portnum; | |
824 | ||
825 | /* USB3 specific wPortChange bits | |
826 | * | |
827 | * Port link change with port in resume state should not be | |
828 | * reported to usbcore, as this is an internal state to be | |
829 | * handled by xhci driver. Reporting PLC to usbcore may | |
830 | * cause usbcore clearing PLC first and port change event | |
831 | * irq won't be generated. | |
832 | */ | |
833 | ||
834 | if (portsc & PORT_PLC && (link_state != XDEV_RESUME)) | |
835 | *status |= USB_PORT_STAT_C_LINK_STATE << 16; | |
836 | if (portsc & PORT_WRC) | |
837 | *status |= USB_PORT_STAT_C_BH_RESET << 16; | |
838 | if (portsc & PORT_CEC) | |
839 | *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16; | |
840 | ||
841 | /* USB3 specific wPortStatus bits */ | |
842 | if (portsc & PORT_POWER) | |
843 | *status |= USB_SS_PORT_STAT_POWER; | |
844 | ||
845 | xhci_hub_report_usb3_link_state(xhci, status, portsc); | |
846 | xhci_del_comp_mod_timer(xhci, portsc, portnum); | |
847 | } | |
848 | ||
70e9b53d MN |
849 | static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status, |
850 | u32 portsc) | |
851 | { | |
852 | u32 link_state; | |
853 | ||
854 | link_state = portsc & PORT_PLS_MASK; | |
855 | ||
856 | /* USB2 wPortStatus bits */ | |
857 | if (portsc & PORT_POWER) { | |
858 | *status |= USB_PORT_STAT_POWER; | |
859 | ||
860 | /* link state is only valid if port is powered */ | |
861 | if (link_state == XDEV_U3) | |
862 | *status |= USB_PORT_STAT_SUSPEND; | |
863 | if (link_state == XDEV_U2) | |
864 | *status |= USB_PORT_STAT_L1; | |
865 | } | |
866 | } | |
867 | ||
eae5b176 SS |
868 | /* |
869 | * Converts a raw xHCI port status into the format that external USB 2.0 or USB | |
870 | * 3.0 hubs use. | |
871 | * | |
872 | * Possible side effects: | |
873 | * - Mark a port as being done with device resume, | |
874 | * and ring the endpoint doorbells. | |
875 | * - Stop the Synopsys redriver Compliance Mode polling. | |
8b3d4570 | 876 | * - Drop and reacquire the xHCI lock, in order to wait for port resume. |
eae5b176 SS |
877 | */ |
878 | static u32 xhci_get_port_status(struct usb_hcd *hcd, | |
879 | struct xhci_bus_state *bus_state, | |
eaefcf24 | 880 | u16 wIndex, u32 raw_port_status, |
8b3d4570 SS |
881 | unsigned long flags) |
882 | __releases(&xhci->lock) | |
883 | __acquires(&xhci->lock) | |
eae5b176 SS |
884 | { |
885 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
886 | u32 status = 0; | |
887 | int slot_id; | |
e740b019 MN |
888 | struct xhci_hub *rhub; |
889 | struct xhci_port *port; | |
890 | ||
891 | rhub = xhci_get_rhub(hcd); | |
892 | port = rhub->ports[wIndex]; | |
eae5b176 | 893 | |
3c2ddb44 | 894 | /* common wPortChange bits */ |
eae5b176 SS |
895 | if (raw_port_status & PORT_CSC) |
896 | status |= USB_PORT_STAT_C_CONNECTION << 16; | |
897 | if (raw_port_status & PORT_PEC) | |
898 | status |= USB_PORT_STAT_C_ENABLE << 16; | |
899 | if ((raw_port_status & PORT_OCC)) | |
900 | status |= USB_PORT_STAT_C_OVERCURRENT << 16; | |
901 | if ((raw_port_status & PORT_RC)) | |
902 | status |= USB_PORT_STAT_C_RESET << 16; | |
70e9b53d | 903 | |
3c2ddb44 MN |
904 | /* common wPortStatus bits */ |
905 | if (raw_port_status & PORT_CONNECT) { | |
906 | status |= USB_PORT_STAT_CONNECTION; | |
907 | status |= xhci_port_speed(raw_port_status); | |
908 | } | |
909 | if (raw_port_status & PORT_PE) | |
910 | status |= USB_PORT_STAT_ENABLE; | |
911 | if (raw_port_status & PORT_OC) | |
912 | status |= USB_PORT_STAT_OVERCURRENT; | |
913 | if (raw_port_status & PORT_RESET) | |
914 | status |= USB_PORT_STAT_RESET; | |
915 | ||
916 | /* USB2 and USB3 specific bits, including Port Link State */ | |
5f78a54f MN |
917 | if (hcd->speed >= HCD_USB3) |
918 | xhci_get_usb3_port_status(port, &status, raw_port_status); | |
70e9b53d MN |
919 | else |
920 | xhci_get_usb2_port_status(port, &status, raw_port_status); | |
921 | ||
eae5b176 | 922 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME && |
958c0bd8 | 923 | !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) { |
eae5b176 SS |
924 | if ((raw_port_status & PORT_RESET) || |
925 | !(raw_port_status & PORT_PE)) | |
926 | return 0xffffffff; | |
f69115fd MN |
927 | /* did port event handler already start resume timing? */ |
928 | if (!bus_state->resume_done[wIndex]) { | |
929 | /* If not, maybe we are in a host initated resume? */ | |
930 | if (test_bit(wIndex, &bus_state->resuming_ports)) { | |
931 | /* Host initated resume doesn't time the resume | |
932 | * signalling using resume_done[]. | |
933 | * It manually sets RESUME state, sleeps 20ms | |
934 | * and sets U0 state. This should probably be | |
935 | * changed, but not right now. | |
936 | */ | |
937 | } else { | |
938 | /* port resume was discovered now and here, | |
939 | * start resume timing | |
940 | */ | |
941 | unsigned long timeout = jiffies + | |
942 | msecs_to_jiffies(USB_RESUME_TIMEOUT); | |
943 | ||
944 | set_bit(wIndex, &bus_state->resuming_ports); | |
945 | bus_state->resume_done[wIndex] = timeout; | |
946 | mod_timer(&hcd->rh_timer, timeout); | |
330e2d61 | 947 | usb_hcd_start_port_resume(&hcd->self, wIndex); |
f69115fd MN |
948 | } |
949 | /* Has resume been signalled for USB_RESUME_TIME yet? */ | |
950 | } else if (time_after_eq(jiffies, | |
951 | bus_state->resume_done[wIndex])) { | |
8b3d4570 SS |
952 | int time_left; |
953 | ||
eae5b176 SS |
954 | xhci_dbg(xhci, "Resume USB2 port %d\n", |
955 | wIndex + 1); | |
956 | bus_state->resume_done[wIndex] = 0; | |
957 | clear_bit(wIndex, &bus_state->resuming_ports); | |
8b3d4570 SS |
958 | |
959 | set_bit(wIndex, &bus_state->rexit_ports); | |
a54408d0 | 960 | |
eaefcf24 | 961 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); |
6b7f40f7 | 962 | xhci_set_link_state(xhci, port, XDEV_U0); |
8b3d4570 SS |
963 | |
964 | spin_unlock_irqrestore(&xhci->lock, flags); | |
965 | time_left = wait_for_completion_timeout( | |
966 | &bus_state->rexit_done[wIndex], | |
967 | msecs_to_jiffies( | |
a5baeaea | 968 | XHCI_MAX_REXIT_TIMEOUT_MS)); |
8b3d4570 SS |
969 | spin_lock_irqsave(&xhci->lock, flags); |
970 | ||
971 | if (time_left) { | |
972 | slot_id = xhci_find_slot_id_by_port(hcd, | |
973 | xhci, wIndex + 1); | |
974 | if (!slot_id) { | |
975 | xhci_dbg(xhci, "slot_id is zero\n"); | |
976 | return 0xffffffff; | |
977 | } | |
978 | xhci_ring_device(xhci, slot_id); | |
979 | } else { | |
e740b019 | 980 | int port_status = readl(port->addr); |
8b3d4570 | 981 | xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n", |
a5baeaea | 982 | XHCI_MAX_REXIT_TIMEOUT_MS, |
8b3d4570 SS |
983 | port_status); |
984 | status |= USB_PORT_STAT_SUSPEND; | |
985 | clear_bit(wIndex, &bus_state->rexit_ports); | |
eae5b176 | 986 | } |
8b3d4570 | 987 | |
330e2d61 | 988 | usb_hcd_end_port_resume(&hcd->self, wIndex); |
eae5b176 SS |
989 | bus_state->port_c_suspend |= 1 << wIndex; |
990 | bus_state->suspended_ports &= ~(1 << wIndex); | |
991 | } else { | |
992 | /* | |
993 | * The resume has been signaling for less than | |
f69115fd MN |
994 | * USB_RESUME_TIME. Report the port status as SUSPEND, |
995 | * let the usbcore check port status again and clear | |
996 | * resume signaling later. | |
eae5b176 SS |
997 | */ |
998 | status |= USB_PORT_STAT_SUSPEND; | |
999 | } | |
1000 | } | |
f69115fd MN |
1001 | /* |
1002 | * Clear stale usb2 resume signalling variables in case port changed | |
1003 | * state during resume signalling. For example on error | |
1004 | */ | |
1005 | if ((bus_state->resume_done[wIndex] || | |
1006 | test_bit(wIndex, &bus_state->resuming_ports)) && | |
1007 | (raw_port_status & PORT_PLS_MASK) != XDEV_U3 && | |
1008 | (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) { | |
1009 | bus_state->resume_done[wIndex] = 0; | |
1010 | clear_bit(wIndex, &bus_state->resuming_ports); | |
330e2d61 | 1011 | usb_hcd_end_port_resume(&hcd->self, wIndex); |
f69115fd MN |
1012 | } |
1013 | ||
1014 | ||
dad67d5f MN |
1015 | if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 && |
1016 | (raw_port_status & PORT_POWER)) { | |
1017 | if (bus_state->suspended_ports & (1 << wIndex)) { | |
1018 | bus_state->suspended_ports &= ~(1 << wIndex); | |
1019 | if (hcd->speed < HCD_USB3) | |
1020 | bus_state->port_c_suspend |= 1 << wIndex; | |
1021 | } | |
1022 | bus_state->resume_done[wIndex] = 0; | |
1023 | clear_bit(wIndex, &bus_state->resuming_ports); | |
eae5b176 | 1024 | } |
5f78a54f | 1025 | |
eae5b176 | 1026 | if (bus_state->port_c_suspend & (1 << wIndex)) |
5e6389fd | 1027 | status |= USB_PORT_STAT_C_SUSPEND << 16; |
eae5b176 SS |
1028 | |
1029 | return status; | |
1030 | } | |
1031 | ||
0f2a7930 SS |
1032 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
1033 | u16 wIndex, char *buf, u16 wLength) | |
1034 | { | |
1035 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 1036 | int max_ports; |
0f2a7930 | 1037 | unsigned long flags; |
c9682dff | 1038 | u32 temp, status; |
0f2a7930 | 1039 | int retval = 0; |
be88fe4f | 1040 | int slot_id; |
20b67cf5 | 1041 | struct xhci_bus_state *bus_state; |
2c441780 | 1042 | u16 link_state = 0; |
4296c70a | 1043 | u16 wake_mask = 0; |
797b0ca5 | 1044 | u16 timeout = 0; |
0f1d832e | 1045 | u16 test_mode = 0; |
e740b019 MN |
1046 | struct xhci_hub *rhub; |
1047 | struct xhci_port **ports; | |
0f2a7930 | 1048 | |
e740b019 MN |
1049 | rhub = xhci_get_rhub(hcd); |
1050 | ports = rhub->ports; | |
925f349d | 1051 | max_ports = rhub->num_ports; |
f6187f42 | 1052 | bus_state = &rhub->bus_state; |
0f2a7930 SS |
1053 | |
1054 | spin_lock_irqsave(&xhci->lock, flags); | |
1055 | switch (typeReq) { | |
1056 | case GetHubStatus: | |
1057 | /* No power source, over-current reported per port */ | |
1058 | memset(buf, 0, 4); | |
1059 | break; | |
1060 | case GetHubDescriptor: | |
4bbb0ace SS |
1061 | /* Check to make sure userspace is asking for the USB 3.0 hub |
1062 | * descriptor for the USB 3.0 roothub. If not, we stall the | |
1063 | * endpoint, like external hubs do. | |
1064 | */ | |
b50107bb | 1065 | if (hcd->speed >= HCD_USB3 && |
4bbb0ace SS |
1066 | (wLength < USB_DT_SS_HUB_SIZE || |
1067 | wValue != (USB_DT_SS_HUB << 8))) { | |
1068 | xhci_dbg(xhci, "Wrong hub descriptor type for " | |
1069 | "USB 3.0 roothub.\n"); | |
1070 | goto error; | |
1071 | } | |
f6ff0ac8 SS |
1072 | xhci_hub_descriptor(hcd, xhci, |
1073 | (struct usb_hub_descriptor *) buf); | |
0f2a7930 | 1074 | break; |
48e82361 SS |
1075 | case DeviceRequest | USB_REQ_GET_DESCRIPTOR: |
1076 | if ((wValue & 0xff00) != (USB_DT_BOS << 8)) | |
1077 | goto error; | |
1078 | ||
5693e0b7 | 1079 | if (hcd->speed < HCD_USB3) |
48e82361 SS |
1080 | goto error; |
1081 | ||
5693e0b7 | 1082 | retval = xhci_create_usb3_bos_desc(xhci, buf, wLength); |
48e82361 | 1083 | spin_unlock_irqrestore(&xhci->lock, flags); |
5693e0b7 | 1084 | return retval; |
0f2a7930 | 1085 | case GetPortStatus: |
a0885924 | 1086 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1087 | goto error; |
1088 | wIndex--; | |
e740b019 | 1089 | temp = readl(ports[wIndex]->addr); |
d9f11ba9 MN |
1090 | if (temp == ~(u32)0) { |
1091 | xhci_hc_died(xhci); | |
f9de8151 SS |
1092 | retval = -ENODEV; |
1093 | break; | |
1094 | } | |
28c06e58 | 1095 | trace_xhci_get_port_status(wIndex, temp); |
eaefcf24 MN |
1096 | status = xhci_get_port_status(hcd, bus_state, wIndex, temp, |
1097 | flags); | |
eae5b176 SS |
1098 | if (status == 0xffffffff) |
1099 | goto error; | |
0ed9a57e | 1100 | |
eae5b176 SS |
1101 | xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", |
1102 | wIndex, temp); | |
0f2a7930 | 1103 | xhci_dbg(xhci, "Get port status returned 0x%x\n", status); |
eae5b176 | 1104 | |
0f2a7930 | 1105 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); |
395f5409 MN |
1106 | /* if USB 3.1 extended port status return additional 4 bytes */ |
1107 | if (wValue == 0x02) { | |
1108 | u32 port_li; | |
1109 | ||
1110 | if (hcd->speed < HCD_USB31 || wLength != 8) { | |
1111 | xhci_err(xhci, "get ext port status invalid parameter\n"); | |
1112 | retval = -EINVAL; | |
1113 | break; | |
1114 | } | |
e740b019 | 1115 | port_li = readl(ports[wIndex]->addr + PORTLI); |
395f5409 MN |
1116 | status = xhci_get_ext_port_status(temp, port_li); |
1117 | put_unaligned_le32(cpu_to_le32(status), &buf[4]); | |
1118 | } | |
0f2a7930 SS |
1119 | break; |
1120 | case SetPortFeature: | |
2c441780 AX |
1121 | if (wValue == USB_PORT_FEAT_LINK_STATE) |
1122 | link_state = (wIndex & 0xff00) >> 3; | |
4296c70a SS |
1123 | if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK) |
1124 | wake_mask = wIndex & 0xff00; | |
0f1d832e GZ |
1125 | if (wValue == USB_PORT_FEAT_TEST) |
1126 | test_mode = (wIndex & 0xff00) >> 8; | |
797b0ca5 SS |
1127 | /* The MSB of wIndex is the U1/U2 timeout */ |
1128 | timeout = (wIndex & 0xff00) >> 8; | |
0f2a7930 | 1129 | wIndex &= 0xff; |
a0885924 | 1130 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1131 | goto error; |
1132 | wIndex--; | |
e740b019 | 1133 | temp = readl(ports[wIndex]->addr); |
d9f11ba9 MN |
1134 | if (temp == ~(u32)0) { |
1135 | xhci_hc_died(xhci); | |
f9de8151 SS |
1136 | retval = -ENODEV; |
1137 | break; | |
1138 | } | |
0f2a7930 | 1139 | temp = xhci_port_state_to_neutral(temp); |
4bbb0ace | 1140 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 | 1141 | switch (wValue) { |
be88fe4f | 1142 | case USB_PORT_FEAT_SUSPEND: |
e740b019 | 1143 | temp = readl(ports[wIndex]->addr); |
65580b43 AX |
1144 | if ((temp & PORT_PLS_MASK) != XDEV_U0) { |
1145 | /* Resume the port to U0 first */ | |
6b7f40f7 | 1146 | xhci_set_link_state(xhci, ports[wIndex], |
65580b43 AX |
1147 | XDEV_U0); |
1148 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1149 | msleep(10); | |
1150 | spin_lock_irqsave(&xhci->lock, flags); | |
1151 | } | |
be88fe4f AX |
1152 | /* In spec software should not attempt to suspend |
1153 | * a port unless the port reports that it is in the | |
1154 | * enabled (PED = ‘1’,PLS < ‘3’) state. | |
1155 | */ | |
e740b019 | 1156 | temp = readl(ports[wIndex]->addr); |
be88fe4f AX |
1157 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) |
1158 | || (temp & PORT_PLS_MASK) >= XDEV_U3) { | |
52c31bd5 | 1159 | xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n"); |
be88fe4f AX |
1160 | goto error; |
1161 | } | |
1162 | ||
5233630f SS |
1163 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1164 | wIndex + 1); | |
be88fe4f AX |
1165 | if (!slot_id) { |
1166 | xhci_warn(xhci, "slot_id is zero\n"); | |
1167 | goto error; | |
1168 | } | |
1169 | /* unlock to execute stop endpoint commands */ | |
1170 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1171 | xhci_stop_device(xhci, slot_id, 1); | |
1172 | spin_lock_irqsave(&xhci->lock, flags); | |
1173 | ||
6b7f40f7 | 1174 | xhci_set_link_state(xhci, ports[wIndex], XDEV_U3); |
be88fe4f AX |
1175 | |
1176 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1177 | msleep(10); /* wait device to enter */ | |
1178 | spin_lock_irqsave(&xhci->lock, flags); | |
1179 | ||
e740b019 | 1180 | temp = readl(ports[wIndex]->addr); |
20b67cf5 | 1181 | bus_state->suspended_ports |= 1 << wIndex; |
be88fe4f | 1182 | break; |
2c441780 | 1183 | case USB_PORT_FEAT_LINK_STATE: |
e740b019 | 1184 | temp = readl(ports[wIndex]->addr); |
41e7e056 SS |
1185 | /* Disable port */ |
1186 | if (link_state == USB_SS_PORT_LS_SS_DISABLED) { | |
1187 | xhci_dbg(xhci, "Disable port %d\n", wIndex); | |
1188 | temp = xhci_port_state_to_neutral(temp); | |
1189 | /* | |
1190 | * Clear all change bits, so that we get a new | |
1191 | * connection event. | |
1192 | */ | |
1193 | temp |= PORT_CSC | PORT_PEC | PORT_WRC | | |
1194 | PORT_OCC | PORT_RC | PORT_PLC | | |
1195 | PORT_CEC; | |
e740b019 MN |
1196 | writel(temp | PORT_PE, ports[wIndex]->addr); |
1197 | temp = readl(ports[wIndex]->addr); | |
41e7e056 SS |
1198 | break; |
1199 | } | |
1200 | ||
1201 | /* Put link in RxDetect (enable port) */ | |
1202 | if (link_state == USB_SS_PORT_LS_RX_DETECT) { | |
1203 | xhci_dbg(xhci, "Enable port %d\n", wIndex); | |
6b7f40f7 MN |
1204 | xhci_set_link_state(xhci, ports[wIndex], |
1205 | link_state); | |
e740b019 | 1206 | temp = readl(ports[wIndex]->addr); |
41e7e056 SS |
1207 | break; |
1208 | } | |
1209 | ||
4b562bd2 JP |
1210 | /* |
1211 | * For xHCI 1.1 according to section 4.19.1.2.4.1 a | |
1212 | * root hub port's transition to compliance mode upon | |
1213 | * detecting LFPS timeout may be controlled by an | |
1214 | * Compliance Transition Enabled (CTE) flag (not | |
1215 | * software visible). This flag is set by writing 0xA | |
1216 | * to PORTSC PLS field which will allow transition to | |
1217 | * compliance mode the next time LFPS timeout is | |
1218 | * encountered. A warm reset will clear it. | |
1219 | * | |
1220 | * The CTE flag is only supported if the HCCPARAMS2 CTC | |
1221 | * flag is set, otherwise, the compliance substate is | |
1222 | * automatically entered as on 1.0 and prior. | |
1223 | */ | |
1224 | if (link_state == USB_SS_PORT_LS_COMP_MOD) { | |
1225 | if (!HCC2_CTC(xhci->hcc_params2)) { | |
1226 | xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n"); | |
1227 | break; | |
1228 | } | |
1229 | ||
1230 | if ((temp & PORT_CONNECT)) { | |
1231 | xhci_warn(xhci, "Can't set compliance mode when port is connected\n"); | |
1232 | goto error; | |
1233 | } | |
1234 | ||
1235 | xhci_dbg(xhci, "Enable compliance mode transition for port %d\n", | |
1236 | wIndex); | |
6b7f40f7 | 1237 | xhci_set_link_state(xhci, ports[wIndex], |
4b562bd2 | 1238 | link_state); |
6b7f40f7 | 1239 | |
e740b019 | 1240 | temp = readl(ports[wIndex]->addr); |
4b562bd2 JP |
1241 | break; |
1242 | } | |
1208d8a8 MN |
1243 | /* Port must be enabled */ |
1244 | if (!(temp & PORT_PE)) { | |
1245 | retval = -ENODEV; | |
1246 | break; | |
1247 | } | |
1248 | /* Can't set port link state above '3' (U3) */ | |
1249 | if (link_state > USB_SS_PORT_LS_U3) { | |
1250 | xhci_warn(xhci, "Cannot set port %d link state %d\n", | |
1251 | wIndex, link_state); | |
2c441780 AX |
1252 | goto error; |
1253 | } | |
2c441780 AX |
1254 | if (link_state == USB_SS_PORT_LS_U3) { |
1255 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
1256 | wIndex + 1); | |
1257 | if (slot_id) { | |
1258 | /* unlock to execute stop endpoint | |
1259 | * commands */ | |
1260 | spin_unlock_irqrestore(&xhci->lock, | |
1261 | flags); | |
1262 | xhci_stop_device(xhci, slot_id, 1); | |
1263 | spin_lock_irqsave(&xhci->lock, flags); | |
1264 | } | |
1265 | } | |
1266 | ||
6b7f40f7 | 1267 | xhci_set_link_state(xhci, ports[wIndex], link_state); |
2c441780 AX |
1268 | |
1269 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1270 | msleep(20); /* wait device to enter */ | |
1271 | spin_lock_irqsave(&xhci->lock, flags); | |
1272 | ||
e740b019 | 1273 | temp = readl(ports[wIndex]->addr); |
2c441780 AX |
1274 | if (link_state == USB_SS_PORT_LS_U3) |
1275 | bus_state->suspended_ports |= 1 << wIndex; | |
1276 | break; | |
0f2a7930 SS |
1277 | case USB_PORT_FEAT_POWER: |
1278 | /* | |
1279 | * Turn on ports, even if there isn't per-port switching. | |
1280 | * HC will report connect events even before this is set. | |
37ebb549 | 1281 | * However, hub_wq will ignore the roothub events until |
0f2a7930 SS |
1282 | * the roothub is registered. |
1283 | */ | |
ec1dafe8 | 1284 | xhci_set_port_power(xhci, hcd, wIndex, true, &flags); |
0f2a7930 SS |
1285 | break; |
1286 | case USB_PORT_FEAT_RESET: | |
1287 | temp = (temp | PORT_RESET); | |
e740b019 | 1288 | writel(temp, ports[wIndex]->addr); |
0f2a7930 | 1289 | |
e740b019 | 1290 | temp = readl(ports[wIndex]->addr); |
0f2a7930 SS |
1291 | xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp); |
1292 | break; | |
4296c70a | 1293 | case USB_PORT_FEAT_REMOTE_WAKE_MASK: |
fdcf74ff MN |
1294 | xhci_set_remote_wake_mask(xhci, ports[wIndex], |
1295 | wake_mask); | |
e740b019 | 1296 | temp = readl(ports[wIndex]->addr); |
4296c70a SS |
1297 | xhci_dbg(xhci, "set port remote wake mask, " |
1298 | "actual port %d status = 0x%x\n", | |
1299 | wIndex, temp); | |
1300 | break; | |
a11496eb AX |
1301 | case USB_PORT_FEAT_BH_PORT_RESET: |
1302 | temp |= PORT_WR; | |
e740b019 MN |
1303 | writel(temp, ports[wIndex]->addr); |
1304 | temp = readl(ports[wIndex]->addr); | |
a11496eb | 1305 | break; |
797b0ca5 | 1306 | case USB_PORT_FEAT_U1_TIMEOUT: |
b50107bb | 1307 | if (hcd->speed < HCD_USB3) |
797b0ca5 | 1308 | goto error; |
e740b019 | 1309 | temp = readl(ports[wIndex]->addr + PORTPMSC); |
797b0ca5 SS |
1310 | temp &= ~PORT_U1_TIMEOUT_MASK; |
1311 | temp |= PORT_U1_TIMEOUT(timeout); | |
e740b019 | 1312 | writel(temp, ports[wIndex]->addr + PORTPMSC); |
797b0ca5 SS |
1313 | break; |
1314 | case USB_PORT_FEAT_U2_TIMEOUT: | |
b50107bb | 1315 | if (hcd->speed < HCD_USB3) |
797b0ca5 | 1316 | goto error; |
e740b019 | 1317 | temp = readl(ports[wIndex]->addr + PORTPMSC); |
797b0ca5 SS |
1318 | temp &= ~PORT_U2_TIMEOUT_MASK; |
1319 | temp |= PORT_U2_TIMEOUT(timeout); | |
e740b019 | 1320 | writel(temp, ports[wIndex]->addr + PORTPMSC); |
797b0ca5 | 1321 | break; |
0f1d832e GZ |
1322 | case USB_PORT_FEAT_TEST: |
1323 | /* 4.19.6 Port Test Modes (USB2 Test Mode) */ | |
1324 | if (hcd->speed != HCD_USB2) | |
1325 | goto error; | |
1326 | if (test_mode > TEST_FORCE_EN || test_mode < TEST_J) | |
1327 | goto error; | |
ec1dafe8 MN |
1328 | retval = xhci_enter_test_mode(xhci, test_mode, wIndex, |
1329 | &flags); | |
0f1d832e | 1330 | break; |
0f2a7930 SS |
1331 | default: |
1332 | goto error; | |
1333 | } | |
5308a91b | 1334 | /* unblock any posted writes */ |
e740b019 | 1335 | temp = readl(ports[wIndex]->addr); |
0f2a7930 SS |
1336 | break; |
1337 | case ClearPortFeature: | |
a0885924 | 1338 | if (!wIndex || wIndex > max_ports) |
0f2a7930 SS |
1339 | goto error; |
1340 | wIndex--; | |
e740b019 | 1341 | temp = readl(ports[wIndex]->addr); |
d9f11ba9 MN |
1342 | if (temp == ~(u32)0) { |
1343 | xhci_hc_died(xhci); | |
f9de8151 SS |
1344 | retval = -ENODEV; |
1345 | break; | |
1346 | } | |
4bbb0ace | 1347 | /* FIXME: What new port features do we need to support? */ |
0f2a7930 SS |
1348 | temp = xhci_port_state_to_neutral(temp); |
1349 | switch (wValue) { | |
be88fe4f | 1350 | case USB_PORT_FEAT_SUSPEND: |
e740b019 | 1351 | temp = readl(ports[wIndex]->addr); |
be88fe4f AX |
1352 | xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n"); |
1353 | xhci_dbg(xhci, "PORTSC %04x\n", temp); | |
1354 | if (temp & PORT_RESET) | |
1355 | goto error; | |
5ac04bf1 | 1356 | if ((temp & PORT_PLS_MASK) == XDEV_U3) { |
be88fe4f AX |
1357 | if ((temp & PORT_PE) == 0) |
1358 | goto error; | |
be88fe4f | 1359 | |
f69115fd | 1360 | set_bit(wIndex, &bus_state->resuming_ports); |
330e2d61 | 1361 | usb_hcd_start_port_resume(&hcd->self, wIndex); |
6b7f40f7 MN |
1362 | xhci_set_link_state(xhci, ports[wIndex], |
1363 | XDEV_RESUME); | |
c9682dff | 1364 | spin_unlock_irqrestore(&xhci->lock, flags); |
7d3b016a | 1365 | msleep(USB_RESUME_TIMEOUT); |
a7114230 | 1366 | spin_lock_irqsave(&xhci->lock, flags); |
6b7f40f7 | 1367 | xhci_set_link_state(xhci, ports[wIndex], |
c9682dff | 1368 | XDEV_U0); |
f69115fd | 1369 | clear_bit(wIndex, &bus_state->resuming_ports); |
330e2d61 | 1370 | usb_hcd_end_port_resume(&hcd->self, wIndex); |
be88fe4f | 1371 | } |
a7114230 | 1372 | bus_state->port_c_suspend |= 1 << wIndex; |
be88fe4f | 1373 | |
5233630f SS |
1374 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1375 | wIndex + 1); | |
be88fe4f AX |
1376 | if (!slot_id) { |
1377 | xhci_dbg(xhci, "slot_id is zero\n"); | |
1378 | goto error; | |
1379 | } | |
1380 | xhci_ring_device(xhci, slot_id); | |
1381 | break; | |
1382 | case USB_PORT_FEAT_C_SUSPEND: | |
20b67cf5 | 1383 | bus_state->port_c_suspend &= ~(1 << wIndex); |
ff504f57 | 1384 | /* fall through */ |
0f2a7930 | 1385 | case USB_PORT_FEAT_C_RESET: |
a11496eb | 1386 | case USB_PORT_FEAT_C_BH_PORT_RESET: |
0f2a7930 | 1387 | case USB_PORT_FEAT_C_CONNECTION: |
0f2a7930 | 1388 | case USB_PORT_FEAT_C_OVER_CURRENT: |
6219c047 | 1389 | case USB_PORT_FEAT_C_ENABLE: |
85387c0e | 1390 | case USB_PORT_FEAT_C_PORT_LINK_STATE: |
9425183d | 1391 | case USB_PORT_FEAT_C_PORT_CONFIG_ERROR: |
34fb562a | 1392 | xhci_clear_port_change_bit(xhci, wValue, wIndex, |
e740b019 | 1393 | ports[wIndex]->addr, temp); |
0f2a7930 | 1394 | break; |
6219c047 | 1395 | case USB_PORT_FEAT_ENABLE: |
f6ff0ac8 | 1396 | xhci_disable_port(hcd, xhci, wIndex, |
e740b019 | 1397 | ports[wIndex]->addr, temp); |
6219c047 | 1398 | break; |
693d8eb8 | 1399 | case USB_PORT_FEAT_POWER: |
ec1dafe8 | 1400 | xhci_set_port_power(xhci, hcd, wIndex, false, &flags); |
693d8eb8 | 1401 | break; |
0f1d832e GZ |
1402 | case USB_PORT_FEAT_TEST: |
1403 | retval = xhci_exit_test_mode(xhci); | |
1404 | break; | |
0f2a7930 SS |
1405 | default: |
1406 | goto error; | |
1407 | } | |
0f2a7930 SS |
1408 | break; |
1409 | default: | |
1410 | error: | |
1411 | /* "stall" on error */ | |
1412 | retval = -EPIPE; | |
1413 | } | |
1414 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1415 | return retval; | |
1416 | } | |
1417 | ||
1418 | /* | |
1419 | * Returns 0 if the status hasn't changed, or the number of bytes in buf. | |
1420 | * Ports are 0-indexed from the HCD point of view, | |
1421 | * and 1-indexed from the USB core pointer of view. | |
0f2a7930 SS |
1422 | * |
1423 | * Note that the status change bits will be cleared as soon as a port status | |
1424 | * change event is generated, so we use the saved status from that event. | |
1425 | */ | |
1426 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf) | |
1427 | { | |
1428 | unsigned long flags; | |
1429 | u32 temp, status; | |
56192531 | 1430 | u32 mask; |
0f2a7930 SS |
1431 | int i, retval; |
1432 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
a0885924 | 1433 | int max_ports; |
20b67cf5 | 1434 | struct xhci_bus_state *bus_state; |
c52804a4 | 1435 | bool reset_change = false; |
e740b019 MN |
1436 | struct xhci_hub *rhub; |
1437 | struct xhci_port **ports; | |
0f2a7930 | 1438 | |
e740b019 MN |
1439 | rhub = xhci_get_rhub(hcd); |
1440 | ports = rhub->ports; | |
925f349d | 1441 | max_ports = rhub->num_ports; |
f6187f42 | 1442 | bus_state = &rhub->bus_state; |
0f2a7930 SS |
1443 | |
1444 | /* Initial status is no changes */ | |
a0885924 | 1445 | retval = (max_ports + 8) / 8; |
419a8e81 | 1446 | memset(buf, 0, retval); |
f370b996 AX |
1447 | |
1448 | /* | |
1449 | * Inform the usbcore about resume-in-progress by returning | |
1450 | * a non-zero value even if there are no status changes. | |
1451 | */ | |
1452 | status = bus_state->resuming_ports; | |
0f2a7930 | 1453 | |
9425183d | 1454 | mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC; |
56192531 | 1455 | |
0f2a7930 SS |
1456 | spin_lock_irqsave(&xhci->lock, flags); |
1457 | /* For each port, did anything change? If so, set that bit in buf. */ | |
a0885924 | 1458 | for (i = 0; i < max_ports; i++) { |
e740b019 | 1459 | temp = readl(ports[i]->addr); |
d9f11ba9 MN |
1460 | if (temp == ~(u32)0) { |
1461 | xhci_hc_died(xhci); | |
f9de8151 SS |
1462 | retval = -ENODEV; |
1463 | break; | |
1464 | } | |
3f8499ac MN |
1465 | trace_xhci_hub_status_data(i, temp); |
1466 | ||
56192531 | 1467 | if ((temp & mask) != 0 || |
20b67cf5 SS |
1468 | (bus_state->port_c_suspend & 1 << i) || |
1469 | (bus_state->resume_done[i] && time_after_eq( | |
1470 | jiffies, bus_state->resume_done[i]))) { | |
419a8e81 | 1471 | buf[(i + 1) / 8] |= 1 << (i + 1) % 8; |
0f2a7930 SS |
1472 | status = 1; |
1473 | } | |
c52804a4 SS |
1474 | if ((temp & PORT_RC)) |
1475 | reset_change = true; | |
1476 | } | |
1477 | if (!status && !reset_change) { | |
1478 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
1479 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1480 | } |
1481 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1482 | return status ? retval : 0; | |
1483 | } | |
9777e3ce AX |
1484 | |
1485 | #ifdef CONFIG_PM | |
1486 | ||
1487 | int xhci_bus_suspend(struct usb_hcd *hcd) | |
1488 | { | |
1489 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
518e848e | 1490 | int max_ports, port_index; |
20b67cf5 | 1491 | struct xhci_bus_state *bus_state; |
9777e3ce | 1492 | unsigned long flags; |
e740b019 MN |
1493 | struct xhci_hub *rhub; |
1494 | struct xhci_port **ports; | |
2f31a67f MN |
1495 | u32 portsc_buf[USB_MAXCHILDREN]; |
1496 | bool wake_enabled; | |
9777e3ce | 1497 | |
e740b019 MN |
1498 | rhub = xhci_get_rhub(hcd); |
1499 | ports = rhub->ports; | |
925f349d | 1500 | max_ports = rhub->num_ports; |
f6187f42 | 1501 | bus_state = &rhub->bus_state; |
2f31a67f | 1502 | wake_enabled = hcd->self.root_hub->do_remote_wakeup; |
9777e3ce AX |
1503 | |
1504 | spin_lock_irqsave(&xhci->lock, flags); | |
1505 | ||
2f31a67f | 1506 | if (wake_enabled) { |
fac4271d ZJC |
1507 | if (bus_state->resuming_ports || /* USB2 */ |
1508 | bus_state->port_remote_wakeup) { /* USB3 */ | |
f370b996 | 1509 | spin_unlock_irqrestore(&xhci->lock, flags); |
fac4271d | 1510 | xhci_dbg(xhci, "suspend failed because a port is resuming\n"); |
f370b996 | 1511 | return -EBUSY; |
9777e3ce AX |
1512 | } |
1513 | } | |
2f31a67f MN |
1514 | /* |
1515 | * Prepare ports for suspend, but don't write anything before all ports | |
1516 | * are checked and we know bus suspend can proceed | |
1517 | */ | |
20b67cf5 | 1518 | bus_state->bus_suspended = 0; |
2f31a67f | 1519 | port_index = max_ports; |
518e848e | 1520 | while (port_index--) { |
9777e3ce | 1521 | u32 t1, t2; |
9777e3ce | 1522 | |
e740b019 | 1523 | t1 = readl(ports[port_index]->addr); |
9777e3ce | 1524 | t2 = xhci_port_state_to_neutral(t1); |
2f31a67f | 1525 | portsc_buf[port_index] = 0; |
9777e3ce | 1526 | |
2f31a67f MN |
1527 | /* Bail out if a USB3 port has a new device in link training */ |
1528 | if ((t1 & PORT_PLS_MASK) == XDEV_POLLING) { | |
1529 | bus_state->bus_suspended = 0; | |
1530 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1531 | xhci_dbg(xhci, "Bus suspend bailout, port in polling\n"); | |
1532 | return -EBUSY; | |
1533 | } | |
1534 | ||
1535 | /* suspend ports in U0, or bail out for new connect changes */ | |
1536 | if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) { | |
1537 | if ((t1 & PORT_CSC) && wake_enabled) { | |
1538 | bus_state->bus_suspended = 0; | |
9777e3ce | 1539 | spin_unlock_irqrestore(&xhci->lock, flags); |
2f31a67f MN |
1540 | xhci_dbg(xhci, "Bus suspend bailout, port connect change\n"); |
1541 | return -EBUSY; | |
9777e3ce | 1542 | } |
2f31a67f | 1543 | xhci_dbg(xhci, "port %d not suspended\n", port_index); |
9777e3ce AX |
1544 | t2 &= ~PORT_PLS_MASK; |
1545 | t2 |= PORT_LINK_STROBE | XDEV_U3; | |
20b67cf5 | 1546 | set_bit(port_index, &bus_state->bus_suspended); |
9777e3ce | 1547 | } |
4296c70a | 1548 | /* USB core sets remote wake mask for USB 3.0 hubs, |
ceb6c9c8 | 1549 | * including the USB 3.0 roothub, but only if CONFIG_PM |
4296c70a SS |
1550 | * is enabled, so also enable remote wake here. |
1551 | */ | |
2f31a67f | 1552 | if (wake_enabled) { |
9777e3ce AX |
1553 | if (t1 & PORT_CONNECT) { |
1554 | t2 |= PORT_WKOC_E | PORT_WKDISC_E; | |
1555 | t2 &= ~PORT_WKCONN_E; | |
1556 | } else { | |
1557 | t2 |= PORT_WKOC_E | PORT_WKCONN_E; | |
1558 | t2 &= ~PORT_WKDISC_E; | |
1559 | } | |
bde0716d JL |
1560 | |
1561 | if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) && | |
1562 | (hcd->speed < HCD_USB3)) { | |
1563 | if (usb_amd_pt_check_port(hcd->self.controller, | |
1564 | port_index)) | |
1565 | t2 &= ~PORT_WAKE_BITS; | |
1566 | } | |
9777e3ce AX |
1567 | } else |
1568 | t2 &= ~PORT_WAKE_BITS; | |
1569 | ||
1570 | t1 = xhci_port_state_to_neutral(t1); | |
1571 | if (t1 != t2) | |
2f31a67f MN |
1572 | portsc_buf[port_index] = t2; |
1573 | } | |
1574 | ||
1575 | /* write port settings, stopping and suspending ports if needed */ | |
1576 | port_index = max_ports; | |
1577 | while (port_index--) { | |
1578 | if (!portsc_buf[port_index]) | |
1579 | continue; | |
1580 | if (test_bit(port_index, &bus_state->bus_suspended)) { | |
1581 | int slot_id; | |
1582 | ||
1583 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, | |
1584 | port_index + 1); | |
1585 | if (slot_id) { | |
1586 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1587 | xhci_stop_device(xhci, slot_id, 1); | |
1588 | spin_lock_irqsave(&xhci->lock, flags); | |
1589 | } | |
1590 | } | |
1591 | writel(portsc_buf[port_index], ports[port_index]->addr); | |
9777e3ce AX |
1592 | } |
1593 | hcd->state = HC_STATE_SUSPENDED; | |
20b67cf5 | 1594 | bus_state->next_statechange = jiffies + msecs_to_jiffies(10); |
9777e3ce AX |
1595 | spin_unlock_irqrestore(&xhci->lock, flags); |
1596 | return 0; | |
1597 | } | |
1598 | ||
346e9973 MN |
1599 | /* |
1600 | * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3. | |
1601 | * warm reset a USB3 device stuck in polling or compliance mode after resume. | |
1602 | * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8 | |
1603 | */ | |
fdcf74ff | 1604 | static bool xhci_port_missing_cas_quirk(struct xhci_port *port) |
346e9973 MN |
1605 | { |
1606 | u32 portsc; | |
1607 | ||
fdcf74ff | 1608 | portsc = readl(port->addr); |
346e9973 MN |
1609 | |
1610 | /* if any of these are set we are not stuck */ | |
1611 | if (portsc & (PORT_CONNECT | PORT_CAS)) | |
1612 | return false; | |
1613 | ||
1614 | if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) && | |
1615 | ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE)) | |
1616 | return false; | |
1617 | ||
1618 | /* clear wakeup/change bits, and do a warm port reset */ | |
1619 | portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | |
1620 | portsc |= PORT_WR; | |
fdcf74ff | 1621 | writel(portsc, port->addr); |
346e9973 | 1622 | /* flush write */ |
fdcf74ff | 1623 | readl(port->addr); |
346e9973 MN |
1624 | return true; |
1625 | } | |
1626 | ||
9777e3ce AX |
1627 | int xhci_bus_resume(struct usb_hcd *hcd) |
1628 | { | |
1629 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
20b67cf5 | 1630 | struct xhci_bus_state *bus_state; |
9777e3ce | 1631 | unsigned long flags; |
a85c0f8d | 1632 | int max_ports, port_index; |
41485a90 MN |
1633 | int slot_id; |
1634 | int sret; | |
a85c0f8d MN |
1635 | u32 next_state; |
1636 | u32 temp, portsc; | |
e740b019 MN |
1637 | struct xhci_hub *rhub; |
1638 | struct xhci_port **ports; | |
9777e3ce | 1639 | |
e740b019 MN |
1640 | rhub = xhci_get_rhub(hcd); |
1641 | ports = rhub->ports; | |
925f349d | 1642 | max_ports = rhub->num_ports; |
f6187f42 | 1643 | bus_state = &rhub->bus_state; |
9777e3ce | 1644 | |
20b67cf5 | 1645 | if (time_before(jiffies, bus_state->next_statechange)) |
9777e3ce AX |
1646 | msleep(5); |
1647 | ||
1648 | spin_lock_irqsave(&xhci->lock, flags); | |
1649 | if (!HCD_HW_ACCESSIBLE(hcd)) { | |
1650 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1651 | return -ESHUTDOWN; | |
1652 | } | |
1653 | ||
1654 | /* delay the irqs */ | |
b0ba9720 | 1655 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1656 | temp &= ~CMD_EIE; |
204b7793 | 1657 | writel(temp, &xhci->op_regs->command); |
9777e3ce | 1658 | |
a85c0f8d MN |
1659 | /* bus specific resume for ports we suspended at bus_suspend */ |
1660 | if (hcd->speed >= HCD_USB3) | |
1661 | next_state = XDEV_U0; | |
1662 | else | |
1663 | next_state = XDEV_RESUME; | |
1664 | ||
518e848e SS |
1665 | port_index = max_ports; |
1666 | while (port_index--) { | |
e740b019 | 1667 | portsc = readl(ports[port_index]->addr); |
346e9973 MN |
1668 | |
1669 | /* warm reset CAS limited ports stuck in polling/compliance */ | |
1670 | if ((xhci->quirks & XHCI_MISSING_CAS) && | |
1671 | (hcd->speed >= HCD_USB3) && | |
fdcf74ff | 1672 | xhci_port_missing_cas_quirk(ports[port_index])) { |
346e9973 | 1673 | xhci_dbg(xhci, "reset stuck port %d\n", port_index); |
a85c0f8d | 1674 | clear_bit(port_index, &bus_state->bus_suspended); |
346e9973 MN |
1675 | continue; |
1676 | } | |
a85c0f8d MN |
1677 | /* resume if we suspended the link, and it is still suspended */ |
1678 | if (test_bit(port_index, &bus_state->bus_suspended)) | |
1679 | switch (portsc & PORT_PLS_MASK) { | |
1680 | case XDEV_U3: | |
1681 | portsc = xhci_port_state_to_neutral(portsc); | |
1682 | portsc &= ~PORT_PLS_MASK; | |
1683 | portsc |= PORT_LINK_STROBE | next_state; | |
1684 | break; | |
1685 | case XDEV_RESUME: | |
1686 | /* resume already initiated */ | |
1687 | break; | |
1688 | default: | |
1689 | /* not in a resumeable state, ignore it */ | |
1690 | clear_bit(port_index, | |
1691 | &bus_state->bus_suspended); | |
1692 | break; | |
9777e3ce | 1693 | } |
a85c0f8d MN |
1694 | /* disable wake for all ports, write new link state if needed */ |
1695 | portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS); | |
e740b019 | 1696 | writel(portsc, ports[port_index]->addr); |
41485a90 MN |
1697 | } |
1698 | ||
a85c0f8d MN |
1699 | /* USB2 specific resume signaling delay and U0 link state transition */ |
1700 | if (hcd->speed < HCD_USB3) { | |
1701 | if (bus_state->bus_suspended) { | |
1702 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1703 | msleep(USB_RESUME_TIMEOUT); | |
1704 | spin_lock_irqsave(&xhci->lock, flags); | |
1705 | } | |
1706 | for_each_set_bit(port_index, &bus_state->bus_suspended, | |
1707 | BITS_PER_LONG) { | |
1708 | /* Clear PLC to poll it later for U0 transition */ | |
eaefcf24 | 1709 | xhci_test_and_clear_bit(xhci, ports[port_index], |
a85c0f8d | 1710 | PORT_PLC); |
6b7f40f7 | 1711 | xhci_set_link_state(xhci, ports[port_index], XDEV_U0); |
a85c0f8d | 1712 | } |
41485a90 MN |
1713 | } |
1714 | ||
a85c0f8d MN |
1715 | /* poll for U0 link state complete, both USB2 and USB3 */ |
1716 | for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) { | |
e740b019 | 1717 | sret = xhci_handshake(ports[port_index]->addr, PORT_PLC, |
41485a90 | 1718 | PORT_PLC, 10 * 1000); |
a85c0f8d | 1719 | if (sret) { |
41485a90 MN |
1720 | xhci_warn(xhci, "port %d resume PLC timeout\n", |
1721 | port_index); | |
a85c0f8d MN |
1722 | continue; |
1723 | } | |
eaefcf24 | 1724 | xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC); |
41485a90 MN |
1725 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1); |
1726 | if (slot_id) | |
1727 | xhci_ring_device(xhci, slot_id); | |
1728 | } | |
b0ba9720 | 1729 | (void) readl(&xhci->op_regs->command); |
9777e3ce | 1730 | |
20b67cf5 | 1731 | bus_state->next_statechange = jiffies + msecs_to_jiffies(5); |
9777e3ce | 1732 | /* re-enable irqs */ |
b0ba9720 | 1733 | temp = readl(&xhci->op_regs->command); |
9777e3ce | 1734 | temp |= CMD_EIE; |
204b7793 | 1735 | writel(temp, &xhci->op_regs->command); |
b0ba9720 | 1736 | temp = readl(&xhci->op_regs->command); |
9777e3ce AX |
1737 | |
1738 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1739 | return 0; | |
1740 | } | |
1741 | ||
8f9cc83c AS |
1742 | unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd) |
1743 | { | |
f6187f42 | 1744 | struct xhci_hub *rhub = xhci_get_rhub(hcd); |
8f9cc83c AS |
1745 | |
1746 | /* USB3 port wakeups are reported via usb_wakeup_notification() */ | |
f6187f42 | 1747 | return rhub->bus_state.resuming_ports; /* USB2 ports only */ |
8f9cc83c AS |
1748 | } |
1749 | ||
436a3890 | 1750 | #endif /* CONFIG_PM */ |