[linux-block.git] / drivers / usb / host / uhci-hcd.h

#ifndef __LINUX_UHCI_HCD_H
#define __LINUX_UHCI_HCD_H

#include <linux/list.h>
#include <linux/usb.h>

#define usb_packetid(pipe)	(usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
#define PIPE_DEVEP_MASK		0x0007ff00


/*
 * Universal Host Controller Interface data structures and defines
 */

/* Command register */
#define USBCMD		0
#define   USBCMD_RS		0x0001	/* Run/Stop */
#define   USBCMD_HCRESET	0x0002	/* Host reset */
#define   USBCMD_GRESET		0x0004	/* Global reset */
#define   USBCMD_EGSM		0x0008	/* Global Suspend Mode */
#define   USBCMD_FGR		0x0010	/* Force Global Resume */
#define   USBCMD_SWDBG		0x0020	/* SW Debug mode */
#define   USBCMD_CF		0x0040	/* Config Flag (sw only) */
#define   USBCMD_MAXP		0x0080	/* Max Packet (0 = 32, 1 = 64) */

/* Status register */
#define USBSTS		2
#define   USBSTS_USBINT		0x0001	/* Interrupt due to IOC */
#define   USBSTS_ERROR		0x0002	/* Interrupt due to error */
#define   USBSTS_RD		0x0004	/* Resume Detect */
#define   USBSTS_HSE		0x0008	/* Host System Error: PCI problems */
#define   USBSTS_HCPE		0x0010	/* Host Controller Process Error:
					 * the schedule is buggy */
#define   USBSTS_HCH		0x0020	/* HC Halted */

/* Interrupt enable register */
#define USBINTR		4
#define   USBINTR_TIMEOUT	0x0001	/* Timeout/CRC error enable */
#define   USBINTR_RESUME	0x0002	/* Resume interrupt enable */
#define   USBINTR_IOC		0x0004	/* Interrupt On Complete enable */
#define   USBINTR_SP		0x0008	/* Short packet interrupt enable */

#define USBFRNUM	6
#define USBFLBASEADD	8
#define USBSOF		12
#define   USBSOF_DEFAULT	64	/* Frame length is exactly 1 ms */

/* USB port status and control registers */
#define USBPORTSC1	16
#define USBPORTSC2	18
#define   USBPORTSC_CCS		0x0001	/* Current Connect Status
					 * ("device present") */
#define   USBPORTSC_CSC		0x0002	/* Connect Status Change */
#define   USBPORTSC_PE		0x0004	/* Port Enable */
#define   USBPORTSC_PEC		0x0008	/* Port Enable Change */
#define   USBPORTSC_DPLUS	0x0010	/* D+ high (line status) */
#define   USBPORTSC_DMINUS	0x0020	/* D- high (line status) */
#define   USBPORTSC_RD		0x0040	/* Resume Detect */
#define   USBPORTSC_RES1	0x0080	/* reserved, always 1 */
#define   USBPORTSC_LSDA	0x0100	/* Low Speed Device Attached */
#define   USBPORTSC_PR		0x0200	/* Port Reset */
/* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
#define   USBPORTSC_OC		0x0400	/* Over Current condition */
#define   USBPORTSC_OCC		0x0800	/* Over Current Change R/WC */
#define   USBPORTSC_SUSP	0x1000	/* Suspend */
#define   USBPORTSC_RES2	0x2000	/* reserved, write zeroes */
#define   USBPORTSC_RES3	0x4000	/* reserved, write zeroes */
#define   USBPORTSC_RES4	0x8000	/* reserved, write zeroes */

/* Legacy support register */
#define USBLEGSUP		0xc0
#define   USBLEGSUP_DEFAULT	0x2000	/* only PIRQ enable set */
#define   USBLEGSUP_RWC		0x8f00	/* the R/WC bits */
#define   USBLEGSUP_RO		0x5040	/* R/O and reserved bits */

#define UHCI_PTR_BITS		__constant_cpu_to_le32(0x000F)
#define UHCI_PTR_TERM		__constant_cpu_to_le32(0x0001)
#define UHCI_PTR_QH		__constant_cpu_to_le32(0x0002)
#define UHCI_PTR_DEPTH		__constant_cpu_to_le32(0x0004)
#define UHCI_PTR_BREADTH	__constant_cpu_to_le32(0x0000)

#define UHCI_NUMFRAMES		1024	/* in the frame list [array] */
#define UHCI_MAX_SOF_NUMBER	2047	/* in an SOF packet */
#define CAN_SCHEDULE_FRAMES	1000	/* how far in the future frames
					 * can be scheduled */


/*
 *	Queue Headers
 */

/*
 * One role of a QH is to hold a queue of TDs for some endpoint.  One QH goes
 * with each endpoint, and qh->element (updated by the HC) is either:
 *   - the next unprocessed TD in the endpoint's queue, or
 *   - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
 *
 * The other role of a QH is to serve as a "skeleton" framelist entry, so we
 * can easily splice a QH for some endpoint into the schedule at the right
 * place.  Then qh->element is UHCI_PTR_TERM.
 *
 * In the schedule, qh->link maintains a list of QHs seen by the HC:
 *     skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
 *
 * qh->node is the software equivalent of qh->link.  The differences
 * are that the software list is doubly-linked and QHs in the UNLINKING
 * state are on the software list but not the hardware schedule.
 *
 * For bookkeeping purposes we maintain QHs even for Isochronous endpoints,
 * but they never get added to the hardware schedule.
 */
#define QH_STATE_IDLE		1	/* QH is not being used */
#define QH_STATE_UNLINKING	2	/* QH has been removed from the
					 * schedule but the hardware may
					 * still be using it */
#define QH_STATE_ACTIVE		3	/* QH is on the schedule */

struct uhci_qh {
	/* Hardware fields */
	__le32 link;			/* Next QH in the schedule */
	__le32 element;			/* Queue element (TD) pointer */

	/* Software fields */
	dma_addr_t dma_handle;

	struct list_head node;		/* Node in the list of QHs */
	struct usb_host_endpoint *hep;	/* Endpoint information */
	struct usb_device *udev;
	struct list_head queue;		/* Queue of urbps for this QH */
	struct uhci_qh *skel;		/* Skeleton for this QH */
	struct uhci_td *dummy_td;	/* Dummy TD to end the queue */

	unsigned int unlink_frame;	/* When the QH was unlinked */
	int state;			/* QH_STATE_xxx; see above */
	int type;			/* Queue type (control, bulk, etc) */

	unsigned int initial_toggle:1;	/* Endpoint's current toggle value */
	unsigned int needs_fixup:1;	/* Must fix the TD toggle values */
	unsigned int is_stopped:1;	/* Queue was stopped by an error */
} __attribute__((aligned(16)));

/*
 * We need a special accessor for the element pointer because it is
 * subject to asynchronous updates by the controller.
 */
static inline __le32 qh_element(struct uhci_qh *qh) {
	__le32 element = qh->element;

	barrier();
	return element;
}


/*
 *	Transfer Descriptors
 */

/*
 * for TD <status>:
 */
#define TD_CTRL_SPD		(1 << 29)	/* Short Packet Detect */
#define TD_CTRL_C_ERR_MASK	(3 << 27)	/* Error Counter bits */
#define TD_CTRL_C_ERR_SHIFT	27
#define TD_CTRL_LS		(1 << 26)	/* Low Speed Device */
#define TD_CTRL_IOS		(1 << 25)	/* Isochronous Select */
#define TD_CTRL_IOC		(1 << 24)	/* Interrupt on Complete */
#define TD_CTRL_ACTIVE		(1 << 23)	/* TD Active */
#define TD_CTRL_STALLED		(1 << 22)	/* TD Stalled */
#define TD_CTRL_DBUFERR		(1 << 21)	/* Data Buffer Error */
#define TD_CTRL_BABBLE		(1 << 20)	/* Babble Detected */
#define TD_CTRL_NAK		(1 << 19)	/* NAK Received */
#define TD_CTRL_CRCTIMEO	(1 << 18)	/* CRC/Time Out Error */
#define TD_CTRL_BITSTUFF	(1 << 17)	/* Bit Stuff Error */
#define TD_CTRL_ACTLEN_MASK	0x7FF	/* actual length, encoded as n - 1 */

#define TD_CTRL_ANY_ERROR	(TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
				 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \
				 TD_CTRL_BITSTUFF)

#define uhci_maxerr(err)		((err) << TD_CTRL_C_ERR_SHIFT)
#define uhci_status_bits(ctrl_sts)	((ctrl_sts) & 0xF60000)
#define uhci_actual_length(ctrl_sts)	(((ctrl_sts) + 1) & \
			TD_CTRL_ACTLEN_MASK)	/* 1-based */

/*
 * for TD <info>: (a.k.a. Token)
 */
#define td_token(td)		le32_to_cpu((td)->token)
#define TD_TOKEN_DEVADDR_SHIFT	8
#define TD_TOKEN_TOGGLE_SHIFT	19
#define TD_TOKEN_TOGGLE		(1 << 19)
#define TD_TOKEN_EXPLEN_SHIFT	21
#define TD_TOKEN_EXPLEN_MASK	0x7FF	/* expected length, encoded as n-1 */
#define TD_TOKEN_PID_MASK	0xFF

#define uhci_explen(len)	((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
					TD_TOKEN_EXPLEN_SHIFT)

#define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
					1) & TD_TOKEN_EXPLEN_MASK)
#define uhci_toggle(token)	(((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
#define uhci_endpoint(token)	(((token) >> 15) & 0xf)
#define uhci_devaddr(token)	(((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
#define uhci_devep(token)	(((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
#define uhci_packetid(token)	((token) & TD_TOKEN_PID_MASK)
#define uhci_packetout(token)	(uhci_packetid(token) != USB_PID_IN)
#define uhci_packetin(token)	(uhci_packetid(token) == USB_PID_IN)

/*
 * The documentation says "4 words for hardware, 4 words for software".
 *
 * That's silly, the hardware doesn't care. The hardware only cares that
 * the hardware words are 16-byte aligned, and we can have any amount of
 * sw space after the TD entry.
 *
 * td->link points to either another TD (not necessarily for the same urb or
 * even the same endpoint), or nothing (PTR_TERM), or a QH.
 */
struct uhci_td {
	/* Hardware fields */
	__le32 link;
	__le32 status;
	__le32 token;
	__le32 buffer;

	/* Software fields */
	dma_addr_t dma_handle;

	struct list_head list;
	struct list_head remove_list;

	int frame;			/* for iso: what frame? */
	struct list_head fl_list;
} __attribute__((aligned(16)));

/*
 * We need a special accessor for the control/status word because it is
 * subject to asynchronous updates by the controller.
 */
static inline u32 td_status(struct uhci_td *td) {
	__le32 status = td->status;

	barrier();
	return le32_to_cpu(status);
}


/*
 *	Skeleton Queue Headers
 */

/*
 * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for
 * automatic queuing. To make it easy to insert entries into the schedule,
 * we have a skeleton of QHs for each predefined Interrupt latency,
 * low-speed control, full-speed control, bulk, and terminating QH
 * (see explanation for the terminating QH below).
 *
 * When we want to add a new QH, we add it to the end of the list for the
 * skeleton QH.  For instance, the schedule list can look like this:
 *
 * skel int128 QH
 * dev 1 interrupt QH
 * dev 5 interrupt QH
 * skel int64 QH
 * skel int32 QH
 * ...
 * skel int1 QH
 * skel low-speed control QH
 * dev 5 control QH
 * skel full-speed control QH
 * skel bulk QH
 * dev 1 bulk QH
 * dev 2 bulk QH
 * skel terminating QH
 *
 * The terminating QH is used for 2 reasons:
 * - To place a terminating TD which is used to workaround a PIIX bug
 *   (see Intel errata for explanation), and
 * - To loop back to the full-speed control queue for full-speed bandwidth
 *   reclamation.
 *
 * There's a special skeleton QH for Isochronous QHs.  It never appears
 * on the schedule, and Isochronous TDs go on the schedule before the
 * the skeleton QHs.  The hardware accesses them directly rather than
 * through their QH, which is used only for bookkeeping purposes.
 * While the UHCI spec doesn't forbid the use of QHs for Isochronous,
 * it doesn't use them either.  And the spec says that queues never
 * advance on an error completion status, which makes them totally
 * unsuitable for Isochronous transfers.
 */

#define UHCI_NUM_SKELQH		14
#define skel_unlink_qh		skelqh[0]
#define skel_iso_qh		skelqh[1]
#define skel_int128_qh		skelqh[2]
#define skel_int64_qh		skelqh[3]
#define skel_int32_qh		skelqh[4]
#define skel_int16_qh		skelqh[5]
#define skel_int8_qh		skelqh[6]
#define skel_int4_qh		skelqh[7]
#define skel_int2_qh		skelqh[8]
#define skel_int1_qh		skelqh[9]
#define skel_ls_control_qh	skelqh[10]
#define skel_fs_control_qh	skelqh[11]
#define skel_bulk_qh		skelqh[12]
#define skel_term_qh		skelqh[13]

/*
 * Search tree for determining where <interval> fits in the skelqh[]
 * skeleton.
 *
 * An interrupt request should be placed into the slowest skelqh[]
 * which meets the interval/period/frequency requirement.
 * An interrupt request is allowed to be faster than <interval> but not slower.
 *
 * For a given <interval>, this function returns the appropriate/matching
 * skelqh[] index value.
 */
static inline int __interval_to_skel(int interval)
{
	if (interval < 16) {
		if (interval < 4) {
			if (interval < 2)
				return 9;	/* int1 for 0-1 ms */
			return 8;		/* int2 for 2-3 ms */
		}
		if (interval < 8)
			return 7;		/* int4 for 4-7 ms */
		return 6;			/* int8 for 8-15 ms */
	}
	if (interval < 64) {
		if (interval < 32)
			return 5;		/* int16 for 16-31 ms */
		return 4;			/* int32 for 32-63 ms */
	}
	if (interval < 128)
		return 3;			/* int64 for 64-127 ms */
	return 2;				/* int128 for 128-255 ms (Max.) */
}


/*
 *	The UHCI controller and root hub
 */

/*
 * States for the root hub:
 *
 * To prevent "bouncing" in the presence of electrical noise,
 * when there are no devices attached we delay for 1 second in the
 * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
 * 
 * (Note that the AUTO_STOPPED state won't be necessary once the hub
 * driver learns to autosuspend.)
 */
enum uhci_rh_state {
	/* In the following states the HC must be halted.
	 * These two must come first. */
	UHCI_RH_RESET,
	UHCI_RH_SUSPENDED,

	UHCI_RH_AUTO_STOPPED,
	UHCI_RH_RESUMING,

	/* In this state the HC changes from running to halted,
	 * so it can legally appear either way. */
	UHCI_RH_SUSPENDING,

	/* In the following states it's an error if the HC is halted.
	 * These two must come last. */
	UHCI_RH_RUNNING,		/* The normal state */
	UHCI_RH_RUNNING_NODEVS,		/* Running with no devices attached */
};

/*
 * The full UHCI controller information:
 */
struct uhci_hcd {

	/* debugfs */
	struct dentry *dentry;

	/* Grabbed from PCI */
	unsigned long io_addr;

	struct dma_pool *qh_pool;
	struct dma_pool *td_pool;

	struct uhci_td *term_td;	/* Terminating TD, see UHCI bug */
	struct uhci_qh *skelqh[UHCI_NUM_SKELQH];	/* Skeleton QHs */
	struct uhci_qh *next_qh;	/* Next QH to scan */

	spinlock_t lock;

	dma_addr_t frame_dma_handle;	/* Hardware frame list */
	__le32 *frame;
	void **frame_cpu;		/* CPU's frame list */

	int fsbr;			/* Full-speed bandwidth reclamation */
	unsigned long fsbrtimeout;	/* FSBR delay */

	enum uhci_rh_state rh_state;
	unsigned long auto_stop_time;		/* When to AUTO_STOP */

	unsigned int frame_number;		/* As of last check */
	unsigned int is_stopped;
#define UHCI_IS_STOPPED		9999		/* Larger than a frame # */

	unsigned int scan_in_progress:1;	/* Schedule scan is running */
	unsigned int need_rescan:1;		/* Redo the schedule scan */
	unsigned int hc_inaccessible:1;		/* HC is suspended or dead */
	unsigned int working_RD:1;		/* Suspended root hub doesn't
						   need to be polled */
	unsigned int is_initialized:1;		/* Data structure is usable */

	/* Support for port suspend/resume/reset */
	unsigned long port_c_suspend;		/* Bit-arrays of ports */
	unsigned long resuming_ports;
	unsigned long ports_timeout;		/* Time to stop signalling */

	/* List of TDs that are done, but waiting to be freed (race) */
	struct list_head td_remove_list;
	unsigned int td_remove_age;		/* Age in frames */

	struct list_head idle_qh_list;		/* Where the idle QHs live */

	int rh_numports;			/* Number of root-hub ports */

	wait_queue_head_t waitqh;		/* endpoint_disable waiters */
	int num_waiting;			/* Number of waiters */
};

/* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
{
	return (struct uhci_hcd *) (hcd->hcd_priv);
}
static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
{
	return container_of((void *) uhci, struct usb_hcd, hcd_priv);
}

#define uhci_dev(u)	(uhci_to_hcd(u)->self.controller)


/*
 *	Private per-URB data
 */
struct urb_priv {
	struct list_head node;		/* Node in the QH's urbp list */

	struct urb *urb;

	struct uhci_qh *qh;		/* QH for this URB */
	struct list_head td_list;

	unsigned fsbr : 1;		/* URB turned on FSBR */
	unsigned short_transfer : 1;	/* URB got a short transfer, no
					 * need to rescan */
};


/*
 * Locking in uhci.c
 *
 * Almost everything relating to the hardware schedule and processing
 * of URBs is protected by uhci->lock.  urb->status is protected by
 * urb->lock; that's the one exception.
 *
 * To prevent deadlocks, never lock uhci->lock while holding urb->lock.
 * The safe order of locking is:
 *
 * #1 uhci->lock
 * #2 urb->lock
 */


/* Some special IDs */

#define PCI_VENDOR_ID_GENESYS		0x17a0
#define PCI_DEVICE_ID_GL880S_UHCI	0x8083

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef __LINUX_UHCI_HCD_H
	2	#define __LINUX_UHCI_HCD_H
	3
	4	#include <linux/list.h>
	5	#include <linux/usb.h>
	6
	7	#define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
	8	#define PIPE_DEVEP_MASK 0x0007ff00
	9
8b262bd2	10
1da177e4 LT	11	/*
	12	* Universal Host Controller Interface data structures and defines
	13	*/
	14
	15	/* Command register */
	16	#define USBCMD 0
	17	#define USBCMD_RS 0x0001 /* Run/Stop */
	18	#define USBCMD_HCRESET 0x0002 /* Host reset */
	19	#define USBCMD_GRESET 0x0004 /* Global reset */
	20	#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
	21	#define USBCMD_FGR 0x0010 /* Force Global Resume */
	22	#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
	23	#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
	24	#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
	25
	26	/* Status register */
	27	#define USBSTS 2
	28	#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
	29	#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
	30	#define USBSTS_RD 0x0004 /* Resume Detect */
dccf4a48 AS	31	#define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */
	32	#define USBSTS_HCPE 0x0010 /* Host Controller Process Error:
	33	* the schedule is buggy */
1da177e4 LT	34	#define USBSTS_HCH 0x0020 /* HC Halted */
	35
	36	/* Interrupt enable register */
	37	#define USBINTR 4
	38	#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
	39	#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
	40	#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
	41	#define USBINTR_SP 0x0008 /* Short packet interrupt enable */
	42
	43	#define USBFRNUM 6
	44	#define USBFLBASEADD 8
	45	#define USBSOF 12
a8bed8b6	46	#define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */
1da177e4 LT	47
	48	/* USB port status and control registers */
	49	#define USBPORTSC1 16
	50	#define USBPORTSC2 18
dccf4a48 AS	51	#define USBPORTSC_CCS 0x0001 /* Current Connect Status
dccf4a48 AS	52	* ("device present") */
1da177e4 LT	53	#define USBPORTSC_CSC 0x0002 /* Connect Status Change */
	54	#define USBPORTSC_PE 0x0004 /* Port Enable */
	55	#define USBPORTSC_PEC 0x0008 /* Port Enable Change */
	56	#define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */
	57	#define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
	58	#define USBPORTSC_RD 0x0040 /* Resume Detect */
	59	#define USBPORTSC_RES1 0x0080 /* reserved, always 1 */
	60	#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
	61	#define USBPORTSC_PR 0x0200 /* Port Reset */
	62	/* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
	63	#define USBPORTSC_OC 0x0400 /* Over Current condition */
	64	#define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */
	65	#define USBPORTSC_SUSP 0x1000 /* Suspend */
	66	#define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */
	67	#define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */
	68	#define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */
	69
	70	/* Legacy support register */
	71	#define USBLEGSUP 0xc0
	72	#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
a8bed8b6 AS	73	#define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
a8bed8b6 AS	74	#define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
1da177e4	75
dccf4a48 AS	76	#define UHCI_PTR_BITS __constant_cpu_to_le32(0x000F)
	77	#define UHCI_PTR_TERM __constant_cpu_to_le32(0x0001)
	78	#define UHCI_PTR_QH __constant_cpu_to_le32(0x0002)
	79	#define UHCI_PTR_DEPTH __constant_cpu_to_le32(0x0004)
	80	#define UHCI_PTR_BREADTH __constant_cpu_to_le32(0x0000)
1da177e4 LT	81
	82	#define UHCI_NUMFRAMES 1024 /* in the frame list [array] */
	83	#define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */
dccf4a48 AS	84	#define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames
dccf4a48 AS	85	* can be scheduled */
1da177e4	86
1da177e4	87
8b262bd2 AS	88	/*
	89	* Queue Headers
	90	*/
1da177e4 LT	91
1da177e4 LT	92	/*
dccf4a48 AS	93	* One role of a QH is to hold a queue of TDs for some endpoint. One QH goes
	94	* with each endpoint, and qh->element (updated by the HC) is either:
	95	* - the next unprocessed TD in the endpoint's queue, or
	96	* - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
1da177e4 LT	97	*
	98	* The other role of a QH is to serve as a "skeleton" framelist entry, so we
	99	* can easily splice a QH for some endpoint into the schedule at the right
	100	* place. Then qh->element is UHCI_PTR_TERM.
	101	*
dccf4a48	102	* In the schedule, qh->link maintains a list of QHs seen by the HC:
1da177e4	103	* skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
dccf4a48 AS	104	*
	105	* qh->node is the software equivalent of qh->link. The differences
	106	* are that the software list is doubly-linked and QHs in the UNLINKING
	107	* state are on the software list but not the hardware schedule.
	108	*
	109	* For bookkeeping purposes we maintain QHs even for Isochronous endpoints,
	110	* but they never get added to the hardware schedule.
1da177e4	111	*/
dccf4a48 AS	112	#define QH_STATE_IDLE 1 /* QH is not being used */
	113	#define QH_STATE_UNLINKING 2 /* QH has been removed from the
	114	* schedule but the hardware may
	115	* still be using it */
	116	#define QH_STATE_ACTIVE 3 /* QH is on the schedule */
	117
1da177e4 LT	118	struct uhci_qh {
1da177e4 LT	119	/* Hardware fields */
dccf4a48 AS	120	__le32 link; /* Next QH in the schedule */
dccf4a48 AS	121	__le32 element; /* Queue element (TD) pointer */
1da177e4 LT	122
	123	/* Software fields */
	124	dma_addr_t dma_handle;
	125
dccf4a48 AS	126	struct list_head node; /* Node in the list of QHs */
	127	struct usb_host_endpoint hep; / Endpoint information */
	128	struct usb_device *udev;
	129	struct list_head queue; /* Queue of urbps for this QH */
	130	struct uhci_qh skel; / Skeleton for this QH */
af0bb599	131	struct uhci_td dummy_td; / Dummy TD to end the queue */
1da177e4	132
dccf4a48 AS	133	unsigned int unlink_frame; /* When the QH was unlinked */
dccf4a48 AS	134	int state; /* QH_STATE_xxx; see above */
4de7d2c2	135	int type; /* Queue type (control, bulk, etc) */
0ed8fee1 AS	136
	137	unsigned int initial_toggle:1; /* Endpoint's current toggle value */
	138	unsigned int needs_fixup:1; /* Must fix the TD toggle values */
	139	unsigned int is_stopped:1; /* Queue was stopped by an error */
1da177e4 LT	140	} __attribute__((aligned(16)));
	141
	142	/*
	143	* We need a special accessor for the element pointer because it is
8b262bd2	144	* subject to asynchronous updates by the controller.
1da177e4	145	*/
dccf4a48	146	static inline __le32 qh_element(struct uhci_qh *qh) {
1da177e4 LT	147	__le32 element = qh->element;
	148
	149	barrier();
	150	return element;
	151	}
	152
8b262bd2 AS	153
	154	/*
	155	* Transfer Descriptors
	156	*/
	157
1da177e4 LT	158	/*
	159	* for TD <status>:
	160	*/
	161	#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
	162	#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
	163	#define TD_CTRL_C_ERR_SHIFT 27
	164	#define TD_CTRL_LS (1 << 26) /* Low Speed Device */
	165	#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
	166	#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
	167	#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
	168	#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
	169	#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
	170	#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
	171	#define TD_CTRL_NAK (1 << 19) /* NAK Received */
	172	#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
	173	#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
	174	#define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
	175
	176	#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED \| TD_CTRL_DBUFERR \| \
dccf4a48 AS	177	TD_CTRL_BABBLE \| TD_CTRL_CRCTIME \| \
dccf4a48 AS	178	TD_CTRL_BITSTUFF)
1da177e4 LT	179
	180	#define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
	181	#define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
dccf4a48 AS	182	#define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \
dccf4a48 AS	183	TD_CTRL_ACTLEN_MASK) /* 1-based */
1da177e4 LT	184
	185	/*
	186	* for TD <info>: (a.k.a. Token)
	187	*/
	188	#define td_token(td) le32_to_cpu((td)->token)
	189	#define TD_TOKEN_DEVADDR_SHIFT 8
	190	#define TD_TOKEN_TOGGLE_SHIFT 19
	191	#define TD_TOKEN_TOGGLE (1 << 19)
	192	#define TD_TOKEN_EXPLEN_SHIFT 21
dccf4a48	193	#define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */
1da177e4 LT	194	#define TD_TOKEN_PID_MASK 0xFF
1da177e4 LT	195
fa346568 AS	196	#define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
fa346568 AS	197	TD_TOKEN_EXPLEN_SHIFT)
1da177e4	198
fa346568 AS	199	#define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
fa346568 AS	200	1) & TD_TOKEN_EXPLEN_MASK)
1da177e4 LT	201	#define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
	202	#define uhci_endpoint(token) (((token) >> 15) & 0xf)
	203	#define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
	204	#define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
	205	#define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
	206	#define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
	207	#define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
	208
	209	/*
	210	* The documentation says "4 words for hardware, 4 words for software".
	211	*
	212	* That's silly, the hardware doesn't care. The hardware only cares that
	213	* the hardware words are 16-byte aligned, and we can have any amount of
8b262bd2	214	* sw space after the TD entry.
1da177e4 LT	215	*
1da177e4 LT	216	* td->link points to either another TD (not necessarily for the same urb or
dccf4a48	217	* even the same endpoint), or nothing (PTR_TERM), or a QH.
1da177e4 LT	218	*/
	219	struct uhci_td {
	220	/* Hardware fields */
	221	__le32 link;
	222	__le32 status;
	223	__le32 token;
	224	__le32 buffer;
	225
	226	/* Software fields */
	227	dma_addr_t dma_handle;
	228
8b262bd2 AS	229	struct list_head list;
8b262bd2 AS	230	struct list_head remove_list;
1da177e4 LT	231
1da177e4 LT	232	int frame; /* for iso: what frame? */
8b262bd2	233	struct list_head fl_list;
1da177e4 LT	234	} __attribute__((aligned(16)));
	235
	236	/*
	237	* We need a special accessor for the control/status word because it is
8b262bd2	238	* subject to asynchronous updates by the controller.
1da177e4	239	*/
dccf4a48	240	static inline u32 td_status(struct uhci_td *td) {
1da177e4 LT	241	__le32 status = td->status;
	242
	243	barrier();
	244	return le32_to_cpu(status);
	245	}
	246
	247
8b262bd2 AS	248	/*
	249	* Skeleton Queue Headers
	250	*/
	251
1da177e4	252	/*
dccf4a48 AS	253	* The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for
	254	* automatic queuing. To make it easy to insert entries into the schedule,
	255	* we have a skeleton of QHs for each predefined Interrupt latency,
	256	* low-speed control, full-speed control, bulk, and terminating QH
	257	* (see explanation for the terminating QH below).
1da177e4 LT	258	*
1da177e4 LT	259	* When we want to add a new QH, we add it to the end of the list for the
dccf4a48	260	* skeleton QH. For instance, the schedule list can look like this:
1da177e4 LT	261	*
	262	* skel int128 QH
	263	* dev 1 interrupt QH
	264	* dev 5 interrupt QH
	265	* skel int64 QH
	266	* skel int32 QH
	267	* ...
	268	* skel int1 QH
	269	* skel low-speed control QH
	270	* dev 5 control QH
	271	* skel full-speed control QH
	272	* skel bulk QH
	273	* dev 1 bulk QH
	274	* dev 2 bulk QH
	275	* skel terminating QH
	276	*
	277	* The terminating QH is used for 2 reasons:
	278	* - To place a terminating TD which is used to workaround a PIIX bug
8b262bd2	279	* (see Intel errata for explanation), and
1da177e4	280	* - To loop back to the full-speed control queue for full-speed bandwidth
8b262bd2	281	* reclamation.
1da177e4	282	*
dccf4a48 AS	283	* There's a special skeleton QH for Isochronous QHs. It never appears
	284	* on the schedule, and Isochronous TDs go on the schedule before the
	285	* the skeleton QHs. The hardware accesses them directly rather than
	286	* through their QH, which is used only for bookkeeping purposes.
	287	* While the UHCI spec doesn't forbid the use of QHs for Isochronous,
	288	* it doesn't use them either. And the spec says that queues never
	289	* advance on an error completion status, which makes them totally
	290	* unsuitable for Isochronous transfers.
1da177e4 LT	291	*/
1da177e4 LT	292
dccf4a48 AS	293	#define UHCI_NUM_SKELQH 14
	294	#define skel_unlink_qh skelqh[0]
	295	#define skel_iso_qh skelqh[1]
	296	#define skel_int128_qh skelqh[2]
	297	#define skel_int64_qh skelqh[3]
	298	#define skel_int32_qh skelqh[4]
	299	#define skel_int16_qh skelqh[5]
	300	#define skel_int8_qh skelqh[6]
	301	#define skel_int4_qh skelqh[7]
	302	#define skel_int2_qh skelqh[8]
	303	#define skel_int1_qh skelqh[9]
	304	#define skel_ls_control_qh skelqh[10]
	305	#define skel_fs_control_qh skelqh[11]
	306	#define skel_bulk_qh skelqh[12]
	307	#define skel_term_qh skelqh[13]
1da177e4 LT	308
	309	/*
	310	* Search tree for determining where <interval> fits in the skelqh[]
	311	* skeleton.
	312	*
	313	* An interrupt request should be placed into the slowest skelqh[]
	314	* which meets the interval/period/frequency requirement.
	315	* An interrupt request is allowed to be faster than <interval> but not slower.
	316	*
	317	* For a given <interval>, this function returns the appropriate/matching
	318	* skelqh[] index value.
	319	*/
	320	static inline int __interval_to_skel(int interval)
	321	{
	322	if (interval < 16) {
	323	if (interval < 4) {
	324	if (interval < 2)
dccf4a48 AS	325	return 9; /* int1 for 0-1 ms */
dccf4a48 AS	326	return 8; /* int2 for 2-3 ms */
1da177e4 LT	327	}
1da177e4 LT	328	if (interval < 8)
dccf4a48 AS	329	return 7; /* int4 for 4-7 ms */
dccf4a48 AS	330	return 6; /* int8 for 8-15 ms */
1da177e4 LT	331	}
	332	if (interval < 64) {
	333	if (interval < 32)
dccf4a48 AS	334	return 5; /* int16 for 16-31 ms */
dccf4a48 AS	335	return 4; /* int32 for 32-63 ms */
1da177e4 LT	336	}
1da177e4 LT	337	if (interval < 128)
dccf4a48 AS	338	return 3; /* int64 for 64-127 ms */
dccf4a48 AS	339	return 2; /* int128 for 128-255 ms (Max.) */
1da177e4 LT	340	}
1da177e4 LT	341
8b262bd2 AS	342
	343	/*
	344	* The UHCI controller and root hub
	345	*/
	346
1da177e4	347	/*
8b262bd2	348	* States for the root hub:
1da177e4 LT	349	*
1da177e4 LT	350	* To prevent "bouncing" in the presence of electrical noise,
c8f4fe43 AS	351	* when there are no devices attached we delay for 1 second in the
	352	* RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
	353	*
	354	* (Note that the AUTO_STOPPED state won't be necessary once the hub
	355	* driver learns to autosuspend.)
1da177e4	356	*/
c8f4fe43	357	enum uhci_rh_state {
6c1b445c	358	/* In the following states the HC must be halted.
8b262bd2	359	* These two must come first. */
6c1b445c	360	UHCI_RH_RESET,
c8f4fe43	361	UHCI_RH_SUSPENDED,
a8bed8b6	362
c8f4fe43 AS	363	UHCI_RH_AUTO_STOPPED,
	364	UHCI_RH_RESUMING,
	365
6c1b445c AS	366	/* In this state the HC changes from running to halted,
6c1b445c AS	367	* so it can legally appear either way. */
c8f4fe43 AS	368	UHCI_RH_SUSPENDING,
c8f4fe43 AS	369
6c1b445c	370	/* In the following states it's an error if the HC is halted.
8b262bd2	371	* These two must come last. */
c8f4fe43 AS	372	UHCI_RH_RUNNING, /* The normal state */
c8f4fe43 AS	373	UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */
1da177e4 LT	374	};
	375
	376	/*
8b262bd2	377	* The full UHCI controller information:
1da177e4 LT	378	*/
	379	struct uhci_hcd {
	380
	381	/* debugfs */
	382	struct dentry *dentry;
	383
	384	/* Grabbed from PCI */
	385	unsigned long io_addr;
	386
	387	struct dma_pool *qh_pool;
	388	struct dma_pool *td_pool;
	389
1da177e4	390	struct uhci_td term_td; / Terminating TD, see UHCI bug */
687f5f34	391	struct uhci_qh skelqh[UHCI_NUM_SKELQH]; / Skeleton QHs */
0ed8fee1	392	struct uhci_qh next_qh; / Next QH to scan */
1da177e4 LT	393
1da177e4 LT	394	spinlock_t lock;
a1d59ce8	395
dccf4a48	396	dma_addr_t frame_dma_handle; /* Hardware frame list */
8b262bd2	397	__le32 *frame;
dccf4a48	398	void *frame_cpu; / CPU's frame list */
a1d59ce8	399
dccf4a48 AS	400	int fsbr; /* Full-speed bandwidth reclamation */
dccf4a48 AS	401	unsigned long fsbrtimeout; /* FSBR delay */
1da177e4	402
c8f4fe43 AS	403	enum uhci_rh_state rh_state;
	404	unsigned long auto_stop_time; /* When to AUTO_STOP */
	405
1da177e4 LT	406	unsigned int frame_number; /* As of last check */
	407	unsigned int is_stopped;
	408	#define UHCI_IS_STOPPED 9999 /* Larger than a frame # */
	409
	410	unsigned int scan_in_progress:1; /* Schedule scan is running */
	411	unsigned int need_rescan:1; /* Redo the schedule scan */
a8bed8b6	412	unsigned int hc_inaccessible:1; /* HC is suspended or dead */
1f09df8b AS	413	unsigned int working_RD:1; /* Suspended root hub doesn't
1f09df8b AS	414	need to be polled */
8d402e1a	415	unsigned int is_initialized:1; /* Data structure is usable */
1da177e4 LT	416
	417	/* Support for port suspend/resume/reset */
	418	unsigned long port_c_suspend; /* Bit-arrays of ports */
1da177e4 LT	419	unsigned long resuming_ports;
	420	unsigned long ports_timeout; /* Time to stop signalling */
	421
687f5f34	422	/* List of TDs that are done, but waiting to be freed (race) */
8b262bd2	423	struct list_head td_remove_list;
1da177e4 LT	424	unsigned int td_remove_age; /* Age in frames */
1da177e4 LT	425
dccf4a48 AS	426	struct list_head idle_qh_list; /* Where the idle QHs live */
dccf4a48 AS	427
1f09df8b	428	int rh_numports; /* Number of root-hub ports */
1da177e4 LT	429
1da177e4 LT	430	wait_queue_head_t waitqh; /* endpoint_disable waiters */
dccf4a48	431	int num_waiting; /* Number of waiters */
1da177e4 LT	432	};
	433
	434	/* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
	435	static inline struct uhci_hcd hcd_to_uhci(struct usb_hcd hcd)
	436	{
	437	return (struct uhci_hcd *) (hcd->hcd_priv);
	438	}
	439	static inline struct usb_hcd uhci_to_hcd(struct uhci_hcd uhci)
	440	{
	441	return container_of((void *) uhci, struct usb_hcd, hcd_priv);
	442	}
	443
	444	#define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
	445
8b262bd2 AS	446
	447	/*
	448	* Private per-URB data
	449	*/
1da177e4	450	struct urb_priv {
dccf4a48	451	struct list_head node; /* Node in the QH's urbp list */
1da177e4 LT	452
	453	struct urb *urb;
	454
	455	struct uhci_qh qh; / QH for this URB */
8b262bd2	456	struct list_head td_list;
1da177e4	457
dccf4a48	458	unsigned fsbr : 1; /* URB turned on FSBR */
dccf4a48 AS	459	unsigned short_transfer : 1; /* URB got a short transfer, no
dccf4a48 AS	460	* need to rescan */
1da177e4 LT	461	};
1da177e4 LT	462
8b262bd2	463
1da177e4 LT	464	/*
	465	* Locking in uhci.c
	466	*
	467	* Almost everything relating to the hardware schedule and processing
	468	* of URBs is protected by uhci->lock. urb->status is protected by
	469	* urb->lock; that's the one exception.
	470	*
	471	* To prevent deadlocks, never lock uhci->lock while holding urb->lock.
	472	* The safe order of locking is:
	473	*
	474	* #1 uhci->lock
	475	* #2 urb->lock
	476	*/
	477
c8f4fe43 AS	478
	479	/* Some special IDs */
	480
	481	#define PCI_VENDOR_ID_GENESYS 0x17a0
	482	#define PCI_DEVICE_ID_GL880S_UHCI 0x8083
c8f4fe43	483
1da177e4	484	#endif