Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Universal Host Controller Interface driver for USB. | |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
6 | * (C) Copyright 1999 Linus Torvalds | |
7 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
8 | * (C) Copyright 1999 Randy Dunlap | |
9 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
10 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
11 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
12 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
13 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
14 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
15 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
c4334726 | 16 | * (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu |
1da177e4 LT |
17 | * |
18 | * Intel documents this fairly well, and as far as I know there | |
19 | * are no royalties or anything like that, but even so there are | |
20 | * people who decided that they want to do the same thing in a | |
21 | * completely different way. | |
22 | * | |
1da177e4 LT |
23 | */ |
24 | ||
1da177e4 LT |
25 | #include <linux/module.h> |
26 | #include <linux/pci.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/slab.h> | |
1da177e4 LT |
33 | #include <linux/errno.h> |
34 | #include <linux/unistd.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/debugfs.h> | |
38 | #include <linux/pm.h> | |
39 | #include <linux/dmapool.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/usb.h> | |
42 | #include <linux/bitops.h> | |
43 | ||
44 | #include <asm/uaccess.h> | |
45 | #include <asm/io.h> | |
46 | #include <asm/irq.h> | |
47 | #include <asm/system.h> | |
48 | ||
49 | #include "../core/hcd.h" | |
50 | #include "uhci-hcd.h" | |
75e2df60 | 51 | #include "pci-quirks.h" |
1da177e4 LT |
52 | |
53 | /* | |
54 | * Version Information | |
55 | */ | |
dccf4a48 | 56 | #define DRIVER_VERSION "v3.0" |
1da177e4 LT |
57 | #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \ |
58 | Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \ | |
59 | Alan Stern" | |
60 | #define DRIVER_DESC "USB Universal Host Controller Interface driver" | |
61 | ||
62 | /* | |
63 | * debug = 0, no debugging messages | |
687f5f34 AS |
64 | * debug = 1, dump failed URBs except for stalls |
65 | * debug = 2, dump all failed URBs (including stalls) | |
1da177e4 | 66 | * show all queues in /debug/uhci/[pci_addr] |
687f5f34 | 67 | * debug = 3, show all TDs in URBs when dumping |
1da177e4 LT |
68 | */ |
69 | #ifdef DEBUG | |
8d402e1a | 70 | #define DEBUG_CONFIGURED 1 |
1da177e4 | 71 | static int debug = 1; |
1da177e4 LT |
72 | module_param(debug, int, S_IRUGO | S_IWUSR); |
73 | MODULE_PARM_DESC(debug, "Debug level"); | |
8d402e1a AS |
74 | |
75 | #else | |
76 | #define DEBUG_CONFIGURED 0 | |
77 | #define debug 0 | |
78 | #endif | |
79 | ||
1da177e4 LT |
80 | static char *errbuf; |
81 | #define ERRBUF_LEN (32 * 1024) | |
82 | ||
83 | static kmem_cache_t *uhci_up_cachep; /* urb_priv */ | |
84 | ||
6c1b445c AS |
85 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state); |
86 | static void wakeup_rh(struct uhci_hcd *uhci); | |
1da177e4 | 87 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci); |
1da177e4 | 88 | |
1da177e4 LT |
89 | #include "uhci-debug.c" |
90 | #include "uhci-q.c" | |
1f09df8b | 91 | #include "uhci-hub.c" |
1da177e4 | 92 | |
a8bed8b6 | 93 | /* |
bb200f6e | 94 | * Finish up a host controller reset and update the recorded state. |
a8bed8b6 | 95 | */ |
bb200f6e | 96 | static void finish_reset(struct uhci_hcd *uhci) |
1da177e4 | 97 | { |
c074b416 AS |
98 | int port; |
99 | ||
c074b416 AS |
100 | /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect |
101 | * bits in the port status and control registers. | |
102 | * We have to clear them by hand. | |
103 | */ | |
104 | for (port = 0; port < uhci->rh_numports; ++port) | |
105 | outw(0, uhci->io_addr + USBPORTSC1 + (port * 2)); | |
106 | ||
8e326406 | 107 | uhci->port_c_suspend = uhci->resuming_ports = 0; |
c8f4fe43 | 108 | uhci->rh_state = UHCI_RH_RESET; |
a8bed8b6 AS |
109 | uhci->is_stopped = UHCI_IS_STOPPED; |
110 | uhci_to_hcd(uhci)->state = HC_STATE_HALT; | |
6c1b445c | 111 | uhci_to_hcd(uhci)->poll_rh = 0; |
e323de46 AS |
112 | |
113 | uhci->dead = 0; /* Full reset resurrects the controller */ | |
1da177e4 LT |
114 | } |
115 | ||
4daaa87c AS |
116 | /* |
117 | * Last rites for a defunct/nonfunctional controller | |
02597d2d | 118 | * or one we don't want to use any more. |
4daaa87c | 119 | */ |
e323de46 | 120 | static void uhci_hc_died(struct uhci_hcd *uhci) |
4daaa87c | 121 | { |
e323de46 | 122 | uhci_get_current_frame_number(uhci); |
bb200f6e AS |
123 | uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr); |
124 | finish_reset(uhci); | |
e323de46 AS |
125 | uhci->dead = 1; |
126 | ||
127 | /* The current frame may already be partway finished */ | |
128 | ++uhci->frame_number; | |
4daaa87c AS |
129 | } |
130 | ||
a8bed8b6 | 131 | /* |
be3cbc5f DB |
132 | * Initialize a controller that was newly discovered or has lost power |
133 | * or otherwise been reset while it was suspended. In none of these cases | |
134 | * can we be sure of its previous state. | |
a8bed8b6 AS |
135 | */ |
136 | static void check_and_reset_hc(struct uhci_hcd *uhci) | |
137 | { | |
bb200f6e AS |
138 | if (uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr)) |
139 | finish_reset(uhci); | |
a8bed8b6 AS |
140 | } |
141 | ||
142 | /* | |
143 | * Store the basic register settings needed by the controller. | |
144 | */ | |
145 | static void configure_hc(struct uhci_hcd *uhci) | |
146 | { | |
147 | /* Set the frame length to the default: 1 ms exactly */ | |
148 | outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF); | |
149 | ||
150 | /* Store the frame list base address */ | |
a1d59ce8 | 151 | outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD); |
a8bed8b6 AS |
152 | |
153 | /* Set the current frame number */ | |
c4334726 AS |
154 | outw(uhci->frame_number & UHCI_MAX_SOF_NUMBER, |
155 | uhci->io_addr + USBFRNUM); | |
a8bed8b6 | 156 | |
f37be9b9 AS |
157 | /* Mark controller as not halted before we enable interrupts */ |
158 | uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED; | |
a8bed8b6 AS |
159 | mb(); |
160 | ||
161 | /* Enable PIRQ */ | |
162 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, | |
163 | USBLEGSUP_DEFAULT); | |
164 | } | |
165 | ||
166 | ||
c8f4fe43 | 167 | static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) |
1da177e4 | 168 | { |
c8f4fe43 | 169 | int port; |
1da177e4 | 170 | |
c8f4fe43 AS |
171 | switch (to_pci_dev(uhci_dev(uhci))->vendor) { |
172 | default: | |
173 | break; | |
174 | ||
175 | case PCI_VENDOR_ID_GENESYS: | |
176 | /* Genesys Logic's GL880S controllers don't generate | |
177 | * resume-detect interrupts. | |
178 | */ | |
179 | return 1; | |
180 | ||
181 | case PCI_VENDOR_ID_INTEL: | |
182 | /* Some of Intel's USB controllers have a bug that causes | |
183 | * resume-detect interrupts if any port has an over-current | |
184 | * condition. To make matters worse, some motherboards | |
185 | * hardwire unused USB ports' over-current inputs active! | |
186 | * To prevent problems, we will not enable resume-detect | |
187 | * interrupts if any ports are OC. | |
188 | */ | |
189 | for (port = 0; port < uhci->rh_numports; ++port) { | |
190 | if (inw(uhci->io_addr + USBPORTSC1 + port * 2) & | |
191 | USBPORTSC_OC) | |
192 | return 1; | |
193 | } | |
194 | break; | |
195 | } | |
196 | return 0; | |
197 | } | |
198 | ||
a8bed8b6 | 199 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) |
c8f4fe43 AS |
200 | __releases(uhci->lock) |
201 | __acquires(uhci->lock) | |
202 | { | |
203 | int auto_stop; | |
204 | int int_enable; | |
205 | ||
206 | auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); | |
be3cbc5f DB |
207 | dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, |
208 | "%s%s\n", __FUNCTION__, | |
c8f4fe43 AS |
209 | (auto_stop ? " (auto-stop)" : "")); |
210 | ||
211 | /* If we get a suspend request when we're already auto-stopped | |
212 | * then there's nothing to do. | |
213 | */ | |
214 | if (uhci->rh_state == UHCI_RH_AUTO_STOPPED) { | |
215 | uhci->rh_state = new_state; | |
216 | return; | |
217 | } | |
218 | ||
219 | /* Enable resume-detect interrupts if they work. | |
220 | * Then enter Global Suspend mode, still configured. | |
221 | */ | |
1f09df8b AS |
222 | uhci->working_RD = 1; |
223 | int_enable = USBINTR_RESUME; | |
224 | if (resume_detect_interrupts_are_broken(uhci)) { | |
225 | uhci->working_RD = int_enable = 0; | |
226 | } | |
c8f4fe43 AS |
227 | outw(int_enable, uhci->io_addr + USBINTR); |
228 | outw(USBCMD_EGSM | USBCMD_CF, uhci->io_addr + USBCMD); | |
a8bed8b6 | 229 | mb(); |
c8f4fe43 AS |
230 | udelay(5); |
231 | ||
232 | /* If we're auto-stopping then no devices have been attached | |
233 | * for a while, so there shouldn't be any active URBs and the | |
234 | * controller should stop after a few microseconds. Otherwise | |
235 | * we will give the controller one frame to stop. | |
236 | */ | |
237 | if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) { | |
238 | uhci->rh_state = UHCI_RH_SUSPENDING; | |
239 | spin_unlock_irq(&uhci->lock); | |
240 | msleep(1); | |
241 | spin_lock_irq(&uhci->lock); | |
e323de46 | 242 | if (uhci->dead) |
4daaa87c | 243 | return; |
c8f4fe43 AS |
244 | } |
245 | if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) | |
be3cbc5f DB |
246 | dev_warn(&uhci_to_hcd(uhci)->self.root_hub->dev, |
247 | "Controller not stopped yet!\n"); | |
1da177e4 | 248 | |
1da177e4 | 249 | uhci_get_current_frame_number(uhci); |
c8f4fe43 AS |
250 | |
251 | uhci->rh_state = new_state; | |
1da177e4 | 252 | uhci->is_stopped = UHCI_IS_STOPPED; |
6c1b445c | 253 | uhci_to_hcd(uhci)->poll_rh = !int_enable; |
1da177e4 LT |
254 | |
255 | uhci_scan_schedule(uhci, NULL); | |
84afddd7 | 256 | uhci_fsbr_off(uhci); |
1da177e4 LT |
257 | } |
258 | ||
a8bed8b6 AS |
259 | static void start_rh(struct uhci_hcd *uhci) |
260 | { | |
f37be9b9 | 261 | uhci_to_hcd(uhci)->state = HC_STATE_RUNNING; |
a8bed8b6 | 262 | uhci->is_stopped = 0; |
a8bed8b6 AS |
263 | |
264 | /* Mark it configured and running with a 64-byte max packet. | |
265 | * All interrupts are enabled, even though RESUME won't do anything. | |
266 | */ | |
267 | outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD); | |
268 | outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP, | |
269 | uhci->io_addr + USBINTR); | |
270 | mb(); | |
6c1b445c AS |
271 | uhci->rh_state = UHCI_RH_RUNNING; |
272 | uhci_to_hcd(uhci)->poll_rh = 1; | |
a8bed8b6 AS |
273 | } |
274 | ||
275 | static void wakeup_rh(struct uhci_hcd *uhci) | |
c8f4fe43 AS |
276 | __releases(uhci->lock) |
277 | __acquires(uhci->lock) | |
1da177e4 | 278 | { |
be3cbc5f DB |
279 | dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, |
280 | "%s%s\n", __FUNCTION__, | |
c8f4fe43 AS |
281 | uhci->rh_state == UHCI_RH_AUTO_STOPPED ? |
282 | " (auto-start)" : ""); | |
1da177e4 | 283 | |
c8f4fe43 AS |
284 | /* If we are auto-stopped then no devices are attached so there's |
285 | * no need for wakeup signals. Otherwise we send Global Resume | |
286 | * for 20 ms. | |
287 | */ | |
288 | if (uhci->rh_state == UHCI_RH_SUSPENDED) { | |
289 | uhci->rh_state = UHCI_RH_RESUMING; | |
290 | outw(USBCMD_FGR | USBCMD_EGSM | USBCMD_CF, | |
291 | uhci->io_addr + USBCMD); | |
292 | spin_unlock_irq(&uhci->lock); | |
293 | msleep(20); | |
294 | spin_lock_irq(&uhci->lock); | |
e323de46 | 295 | if (uhci->dead) |
4daaa87c | 296 | return; |
1da177e4 | 297 | |
c8f4fe43 AS |
298 | /* End Global Resume and wait for EOP to be sent */ |
299 | outw(USBCMD_CF, uhci->io_addr + USBCMD); | |
a8bed8b6 | 300 | mb(); |
c8f4fe43 AS |
301 | udelay(4); |
302 | if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR) | |
303 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); | |
304 | } | |
1da177e4 | 305 | |
a8bed8b6 | 306 | start_rh(uhci); |
c8f4fe43 | 307 | |
6c1b445c AS |
308 | /* Restart root hub polling */ |
309 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); | |
1da177e4 LT |
310 | } |
311 | ||
014e73c9 AS |
312 | static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs) |
313 | { | |
314 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
014e73c9 | 315 | unsigned short status; |
4daaa87c | 316 | unsigned long flags; |
1da177e4 LT |
317 | |
318 | /* | |
014e73c9 AS |
319 | * Read the interrupt status, and write it back to clear the |
320 | * interrupt cause. Contrary to the UHCI specification, the | |
321 | * "HC Halted" status bit is persistent: it is RO, not R/WC. | |
1da177e4 | 322 | */ |
a8bed8b6 | 323 | status = inw(uhci->io_addr + USBSTS); |
014e73c9 AS |
324 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ |
325 | return IRQ_NONE; | |
a8bed8b6 | 326 | outw(status, uhci->io_addr + USBSTS); /* Clear it */ |
014e73c9 AS |
327 | |
328 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { | |
329 | if (status & USBSTS_HSE) | |
330 | dev_err(uhci_dev(uhci), "host system error, " | |
331 | "PCI problems?\n"); | |
332 | if (status & USBSTS_HCPE) | |
333 | dev_err(uhci_dev(uhci), "host controller process " | |
334 | "error, something bad happened!\n"); | |
4daaa87c AS |
335 | if (status & USBSTS_HCH) { |
336 | spin_lock_irqsave(&uhci->lock, flags); | |
337 | if (uhci->rh_state >= UHCI_RH_RUNNING) { | |
338 | dev_err(uhci_dev(uhci), | |
339 | "host controller halted, " | |
014e73c9 | 340 | "very bad!\n"); |
8d402e1a AS |
341 | if (debug > 1 && errbuf) { |
342 | /* Print the schedule for debugging */ | |
343 | uhci_sprint_schedule(uhci, | |
344 | errbuf, ERRBUF_LEN); | |
345 | lprintk(errbuf); | |
346 | } | |
e323de46 | 347 | uhci_hc_died(uhci); |
1f09df8b AS |
348 | |
349 | /* Force a callback in case there are | |
350 | * pending unlinks */ | |
351 | mod_timer(&hcd->rh_timer, jiffies); | |
4daaa87c AS |
352 | } |
353 | spin_unlock_irqrestore(&uhci->lock, flags); | |
1da177e4 | 354 | } |
1da177e4 LT |
355 | } |
356 | ||
014e73c9 | 357 | if (status & USBSTS_RD) |
6c1b445c | 358 | usb_hcd_poll_rh_status(hcd); |
1f09df8b AS |
359 | else { |
360 | spin_lock_irqsave(&uhci->lock, flags); | |
361 | uhci_scan_schedule(uhci, regs); | |
362 | spin_unlock_irqrestore(&uhci->lock, flags); | |
363 | } | |
1da177e4 | 364 | |
014e73c9 AS |
365 | return IRQ_HANDLED; |
366 | } | |
1da177e4 | 367 | |
014e73c9 AS |
368 | /* |
369 | * Store the current frame number in uhci->frame_number if the controller | |
c4334726 AS |
370 | * is runnning. Expand from 11 bits (of which we use only 10) to a |
371 | * full-sized integer. | |
372 | * | |
373 | * Like many other parts of the driver, this code relies on being polled | |
374 | * more than once per second as long as the controller is running. | |
014e73c9 AS |
375 | */ |
376 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci) | |
377 | { | |
c4334726 AS |
378 | if (!uhci->is_stopped) { |
379 | unsigned delta; | |
380 | ||
381 | delta = (inw(uhci->io_addr + USBFRNUM) - uhci->frame_number) & | |
382 | (UHCI_NUMFRAMES - 1); | |
383 | uhci->frame_number += delta; | |
384 | } | |
1da177e4 LT |
385 | } |
386 | ||
387 | /* | |
388 | * De-allocate all resources | |
389 | */ | |
390 | static void release_uhci(struct uhci_hcd *uhci) | |
391 | { | |
392 | int i; | |
393 | ||
8d402e1a AS |
394 | if (DEBUG_CONFIGURED) { |
395 | spin_lock_irq(&uhci->lock); | |
396 | uhci->is_initialized = 0; | |
397 | spin_unlock_irq(&uhci->lock); | |
398 | ||
399 | debugfs_remove(uhci->dentry); | |
400 | } | |
401 | ||
1da177e4 | 402 | for (i = 0; i < UHCI_NUM_SKELQH; i++) |
8b4cd421 | 403 | uhci_free_qh(uhci, uhci->skelqh[i]); |
1da177e4 | 404 | |
8b4cd421 | 405 | uhci_free_td(uhci, uhci->term_td); |
1da177e4 | 406 | |
8b4cd421 | 407 | dma_pool_destroy(uhci->qh_pool); |
1da177e4 | 408 | |
8b4cd421 | 409 | dma_pool_destroy(uhci->td_pool); |
1da177e4 | 410 | |
a1d59ce8 AS |
411 | kfree(uhci->frame_cpu); |
412 | ||
413 | dma_free_coherent(uhci_dev(uhci), | |
414 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
415 | uhci->frame, uhci->frame_dma_handle); | |
1da177e4 LT |
416 | } |
417 | ||
be3cbc5f | 418 | static int uhci_init(struct usb_hcd *hcd) |
1da177e4 LT |
419 | { |
420 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
c074b416 AS |
421 | unsigned io_size = (unsigned) hcd->rsrc_len; |
422 | int port; | |
1da177e4 LT |
423 | |
424 | uhci->io_addr = (unsigned long) hcd->rsrc_start; | |
425 | ||
c074b416 AS |
426 | /* The UHCI spec says devices must have 2 ports, and goes on to say |
427 | * they may have more but gives no way to determine how many there | |
e07fefa6 | 428 | * are. However according to the UHCI spec, Bit 7 of the port |
c074b416 | 429 | * status and control register is always set to 1. So we try to |
e07fefa6 AS |
430 | * use this to our advantage. Another common failure mode when |
431 | * a nonexistent register is addressed is to return all ones, so | |
432 | * we test for that also. | |
c074b416 AS |
433 | */ |
434 | for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { | |
435 | unsigned int portstatus; | |
436 | ||
437 | portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2)); | |
e07fefa6 | 438 | if (!(portstatus & 0x0080) || portstatus == 0xffff) |
c074b416 AS |
439 | break; |
440 | } | |
441 | if (debug) | |
442 | dev_info(uhci_dev(uhci), "detected %d ports\n", port); | |
443 | ||
e07fefa6 AS |
444 | /* Anything greater than 7 is weird so we'll ignore it. */ |
445 | if (port > UHCI_RH_MAXCHILD) { | |
c074b416 AS |
446 | dev_info(uhci_dev(uhci), "port count misdetected? " |
447 | "forcing to 2 ports\n"); | |
448 | port = 2; | |
449 | } | |
450 | uhci->rh_numports = port; | |
451 | ||
a8bed8b6 AS |
452 | /* Kick BIOS off this hardware and reset if the controller |
453 | * isn't already safely quiescent. | |
1da177e4 | 454 | */ |
a8bed8b6 | 455 | check_and_reset_hc(uhci); |
1da177e4 LT |
456 | return 0; |
457 | } | |
458 | ||
02597d2d AS |
459 | /* Make sure the controller is quiescent and that we're not using it |
460 | * any more. This is mainly for the benefit of programs which, like kexec, | |
461 | * expect the hardware to be idle: not doing DMA or generating IRQs. | |
462 | * | |
463 | * This routine may be called in a damaged or failing kernel. Hence we | |
464 | * do not acquire the spinlock before shutting down the controller. | |
465 | */ | |
466 | static void uhci_shutdown(struct pci_dev *pdev) | |
467 | { | |
468 | struct usb_hcd *hcd = (struct usb_hcd *) pci_get_drvdata(pdev); | |
469 | ||
e323de46 | 470 | uhci_hc_died(hcd_to_uhci(hcd)); |
02597d2d AS |
471 | } |
472 | ||
1da177e4 LT |
473 | /* |
474 | * Allocate a frame list, and then setup the skeleton | |
475 | * | |
476 | * The hardware doesn't really know any difference | |
477 | * in the queues, but the order does matter for the | |
478 | * protocols higher up. The order is: | |
479 | * | |
480 | * - any isochronous events handled before any | |
481 | * of the queues. We don't do that here, because | |
482 | * we'll create the actual TD entries on demand. | |
483 | * - The first queue is the interrupt queue. | |
484 | * - The second queue is the control queue, split into low- and full-speed | |
485 | * - The third queue is bulk queue. | |
486 | * - The fourth queue is the bandwidth reclamation queue, which loops back | |
487 | * to the full-speed control queue. | |
488 | */ | |
489 | static int uhci_start(struct usb_hcd *hcd) | |
490 | { | |
491 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
492 | int retval = -EBUSY; | |
c074b416 | 493 | int i; |
1da177e4 LT |
494 | struct dentry *dentry; |
495 | ||
6c1b445c | 496 | hcd->uses_new_polling = 1; |
1da177e4 | 497 | |
1da177e4 | 498 | spin_lock_init(&uhci->lock); |
c5e3b741 AS |
499 | setup_timer(&uhci->fsbr_timer, uhci_fsbr_timeout, |
500 | (unsigned long) uhci); | |
dccf4a48 | 501 | INIT_LIST_HEAD(&uhci->idle_qh_list); |
1da177e4 LT |
502 | init_waitqueue_head(&uhci->waitqh); |
503 | ||
8d402e1a AS |
504 | if (DEBUG_CONFIGURED) { |
505 | dentry = debugfs_create_file(hcd->self.bus_name, | |
506 | S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, | |
507 | uhci, &uhci_debug_operations); | |
508 | if (!dentry) { | |
509 | dev_err(uhci_dev(uhci), "couldn't create uhci " | |
510 | "debugfs entry\n"); | |
511 | retval = -ENOMEM; | |
512 | goto err_create_debug_entry; | |
513 | } | |
514 | uhci->dentry = dentry; | |
515 | } | |
516 | ||
a1d59ce8 AS |
517 | uhci->frame = dma_alloc_coherent(uhci_dev(uhci), |
518 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
519 | &uhci->frame_dma_handle, 0); | |
520 | if (!uhci->frame) { | |
1da177e4 LT |
521 | dev_err(uhci_dev(uhci), "unable to allocate " |
522 | "consistent memory for frame list\n"); | |
a1d59ce8 | 523 | goto err_alloc_frame; |
1da177e4 | 524 | } |
a1d59ce8 | 525 | memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame)); |
1da177e4 | 526 | |
a1d59ce8 AS |
527 | uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu), |
528 | GFP_KERNEL); | |
529 | if (!uhci->frame_cpu) { | |
530 | dev_err(uhci_dev(uhci), "unable to allocate " | |
531 | "memory for frame pointers\n"); | |
532 | goto err_alloc_frame_cpu; | |
533 | } | |
1da177e4 LT |
534 | |
535 | uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), | |
536 | sizeof(struct uhci_td), 16, 0); | |
537 | if (!uhci->td_pool) { | |
538 | dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); | |
539 | goto err_create_td_pool; | |
540 | } | |
541 | ||
542 | uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), | |
543 | sizeof(struct uhci_qh), 16, 0); | |
544 | if (!uhci->qh_pool) { | |
545 | dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); | |
546 | goto err_create_qh_pool; | |
547 | } | |
548 | ||
2532178a | 549 | uhci->term_td = uhci_alloc_td(uhci); |
1da177e4 LT |
550 | if (!uhci->term_td) { |
551 | dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); | |
552 | goto err_alloc_term_td; | |
553 | } | |
554 | ||
555 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { | |
dccf4a48 | 556 | uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL); |
1da177e4 LT |
557 | if (!uhci->skelqh[i]) { |
558 | dev_err(uhci_dev(uhci), "unable to allocate QH\n"); | |
559 | goto err_alloc_skelqh; | |
560 | } | |
561 | } | |
562 | ||
563 | /* | |
564 | * 8 Interrupt queues; link all higher int queues to int1, | |
565 | * then link int1 to control and control to bulk | |
566 | */ | |
567 | uhci->skel_int128_qh->link = | |
568 | uhci->skel_int64_qh->link = | |
569 | uhci->skel_int32_qh->link = | |
570 | uhci->skel_int16_qh->link = | |
571 | uhci->skel_int8_qh->link = | |
572 | uhci->skel_int4_qh->link = | |
dccf4a48 AS |
573 | uhci->skel_int2_qh->link = UHCI_PTR_QH | |
574 | cpu_to_le32(uhci->skel_int1_qh->dma_handle); | |
575 | ||
576 | uhci->skel_int1_qh->link = UHCI_PTR_QH | | |
577 | cpu_to_le32(uhci->skel_ls_control_qh->dma_handle); | |
578 | uhci->skel_ls_control_qh->link = UHCI_PTR_QH | | |
579 | cpu_to_le32(uhci->skel_fs_control_qh->dma_handle); | |
580 | uhci->skel_fs_control_qh->link = UHCI_PTR_QH | | |
581 | cpu_to_le32(uhci->skel_bulk_qh->dma_handle); | |
582 | uhci->skel_bulk_qh->link = UHCI_PTR_QH | | |
583 | cpu_to_le32(uhci->skel_term_qh->dma_handle); | |
1da177e4 LT |
584 | |
585 | /* This dummy TD is to work around a bug in Intel PIIX controllers */ | |
fa346568 | 586 | uhci_fill_td(uhci->term_td, 0, uhci_explen(0) | |
1da177e4 LT |
587 | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); |
588 | uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle); | |
589 | ||
590 | uhci->skel_term_qh->link = UHCI_PTR_TERM; | |
591 | uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle); | |
592 | ||
593 | /* | |
594 | * Fill the frame list: make all entries point to the proper | |
595 | * interrupt queue. | |
596 | * | |
597 | * The interrupt queues will be interleaved as evenly as possible. | |
598 | * There's not much to be done about period-1 interrupts; they have | |
599 | * to occur in every frame. But we can schedule period-2 interrupts | |
600 | * in odd-numbered frames, period-4 interrupts in frames congruent | |
601 | * to 2 (mod 4), and so on. This way each frame only has two | |
602 | * interrupt QHs, which will help spread out bandwidth utilization. | |
603 | */ | |
604 | for (i = 0; i < UHCI_NUMFRAMES; i++) { | |
605 | int irq; | |
606 | ||
607 | /* | |
608 | * ffs (Find First bit Set) does exactly what we need: | |
dccf4a48 AS |
609 | * 1,3,5,... => ffs = 0 => use skel_int2_qh = skelqh[8], |
610 | * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[7], etc. | |
611 | * ffs >= 7 => not on any high-period queue, so use | |
612 | * skel_int1_qh = skelqh[9]. | |
1da177e4 LT |
613 | * Add UHCI_NUMFRAMES to insure at least one bit is set. |
614 | */ | |
dccf4a48 AS |
615 | irq = 8 - (int) __ffs(i + UHCI_NUMFRAMES); |
616 | if (irq <= 1) | |
617 | irq = 9; | |
1da177e4 LT |
618 | |
619 | /* Only place we don't use the frame list routines */ | |
a1d59ce8 | 620 | uhci->frame[i] = UHCI_PTR_QH | |
1da177e4 LT |
621 | cpu_to_le32(uhci->skelqh[irq]->dma_handle); |
622 | } | |
623 | ||
624 | /* | |
625 | * Some architectures require a full mb() to enforce completion of | |
a8bed8b6 | 626 | * the memory writes above before the I/O transfers in configure_hc(). |
1da177e4 LT |
627 | */ |
628 | mb(); | |
a8bed8b6 AS |
629 | |
630 | configure_hc(uhci); | |
8d402e1a | 631 | uhci->is_initialized = 1; |
a8bed8b6 | 632 | start_rh(uhci); |
1da177e4 LT |
633 | return 0; |
634 | ||
635 | /* | |
636 | * error exits: | |
637 | */ | |
1da177e4 | 638 | err_alloc_skelqh: |
8b4cd421 AS |
639 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { |
640 | if (uhci->skelqh[i]) | |
1da177e4 | 641 | uhci_free_qh(uhci, uhci->skelqh[i]); |
8b4cd421 | 642 | } |
1da177e4 LT |
643 | |
644 | uhci_free_td(uhci, uhci->term_td); | |
1da177e4 LT |
645 | |
646 | err_alloc_term_td: | |
1da177e4 | 647 | dma_pool_destroy(uhci->qh_pool); |
1da177e4 LT |
648 | |
649 | err_create_qh_pool: | |
650 | dma_pool_destroy(uhci->td_pool); | |
1da177e4 LT |
651 | |
652 | err_create_td_pool: | |
a1d59ce8 AS |
653 | kfree(uhci->frame_cpu); |
654 | ||
655 | err_alloc_frame_cpu: | |
656 | dma_free_coherent(uhci_dev(uhci), | |
657 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
658 | uhci->frame, uhci->frame_dma_handle); | |
1da177e4 | 659 | |
a1d59ce8 | 660 | err_alloc_frame: |
1da177e4 | 661 | debugfs_remove(uhci->dentry); |
1da177e4 LT |
662 | |
663 | err_create_debug_entry: | |
664 | return retval; | |
665 | } | |
666 | ||
667 | static void uhci_stop(struct usb_hcd *hcd) | |
668 | { | |
669 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
670 | ||
1da177e4 | 671 | spin_lock_irq(&uhci->lock); |
e323de46 AS |
672 | if (test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) && !uhci->dead) |
673 | uhci_hc_died(uhci); | |
1da177e4 LT |
674 | uhci_scan_schedule(uhci, NULL); |
675 | spin_unlock_irq(&uhci->lock); | |
6c1b445c | 676 | |
c5e3b741 | 677 | del_timer_sync(&uhci->fsbr_timer); |
1da177e4 LT |
678 | release_uhci(uhci); |
679 | } | |
680 | ||
681 | #ifdef CONFIG_PM | |
a8bed8b6 AS |
682 | static int uhci_rh_suspend(struct usb_hcd *hcd) |
683 | { | |
684 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
be3cbc5f | 685 | int rc = 0; |
a8bed8b6 AS |
686 | |
687 | spin_lock_irq(&uhci->lock); | |
be3cbc5f DB |
688 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) |
689 | rc = -ESHUTDOWN; | |
e323de46 | 690 | else if (!uhci->dead) |
4daaa87c | 691 | suspend_rh(uhci, UHCI_RH_SUSPENDED); |
a8bed8b6 | 692 | spin_unlock_irq(&uhci->lock); |
be3cbc5f | 693 | return rc; |
a8bed8b6 AS |
694 | } |
695 | ||
696 | static int uhci_rh_resume(struct usb_hcd *hcd) | |
697 | { | |
698 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
4daaa87c | 699 | int rc = 0; |
a8bed8b6 AS |
700 | |
701 | spin_lock_irq(&uhci->lock); | |
be3cbc5f DB |
702 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { |
703 | dev_warn(&hcd->self.root_hub->dev, "HC isn't running!\n"); | |
704 | rc = -ESHUTDOWN; | |
e323de46 | 705 | } else if (!uhci->dead) |
4daaa87c | 706 | wakeup_rh(uhci); |
a8bed8b6 | 707 | spin_unlock_irq(&uhci->lock); |
4daaa87c | 708 | return rc; |
a8bed8b6 AS |
709 | } |
710 | ||
9a5d3e98 | 711 | static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message) |
1da177e4 LT |
712 | { |
713 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
4daaa87c | 714 | int rc = 0; |
1da177e4 | 715 | |
a8bed8b6 AS |
716 | dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); |
717 | ||
1da177e4 | 718 | spin_lock_irq(&uhci->lock); |
e323de46 AS |
719 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags) || uhci->dead) |
720 | goto done_okay; /* Already suspended or dead */ | |
a8bed8b6 | 721 | |
4daaa87c AS |
722 | if (uhci->rh_state > UHCI_RH_SUSPENDED) { |
723 | dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n"); | |
4daaa87c AS |
724 | rc = -EBUSY; |
725 | goto done; | |
726 | }; | |
727 | ||
a8bed8b6 AS |
728 | /* All PCI host controllers are required to disable IRQ generation |
729 | * at the source, so we must turn off PIRQ. | |
730 | */ | |
731 | pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0); | |
42245e65 | 732 | mb(); |
1f09df8b | 733 | hcd->poll_rh = 0; |
a8bed8b6 AS |
734 | |
735 | /* FIXME: Enable non-PME# remote wakeup? */ | |
736 | ||
18584999 DB |
737 | /* make sure snapshot being resumed re-enumerates everything */ |
738 | if (message.event == PM_EVENT_PRETHAW) | |
739 | uhci_hc_died(uhci); | |
740 | ||
e323de46 AS |
741 | done_okay: |
742 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
4daaa87c | 743 | done: |
1da177e4 | 744 | spin_unlock_irq(&uhci->lock); |
4daaa87c | 745 | return rc; |
1da177e4 LT |
746 | } |
747 | ||
748 | static int uhci_resume(struct usb_hcd *hcd) | |
749 | { | |
750 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
1da177e4 | 751 | |
a8bed8b6 AS |
752 | dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__); |
753 | ||
687f5f34 | 754 | /* Since we aren't in D3 any more, it's safe to set this flag |
e323de46 | 755 | * even if the controller was dead. |
8de98402 BH |
756 | */ |
757 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
42245e65 | 758 | mb(); |
8de98402 | 759 | |
1da177e4 | 760 | spin_lock_irq(&uhci->lock); |
1da177e4 | 761 | |
a8bed8b6 AS |
762 | /* FIXME: Disable non-PME# remote wakeup? */ |
763 | ||
e323de46 AS |
764 | /* The firmware or a boot kernel may have changed the controller |
765 | * settings during a system wakeup. Check it and reconfigure | |
766 | * to avoid problems. | |
a8bed8b6 AS |
767 | */ |
768 | check_and_reset_hc(uhci); | |
e323de46 AS |
769 | |
770 | /* If the controller was dead before, it's back alive now */ | |
a8bed8b6 AS |
771 | configure_hc(uhci); |
772 | ||
1c50c317 AS |
773 | if (uhci->rh_state == UHCI_RH_RESET) { |
774 | ||
775 | /* The controller had to be reset */ | |
776 | usb_root_hub_lost_power(hcd->self.root_hub); | |
a8bed8b6 | 777 | suspend_rh(uhci, UHCI_RH_SUSPENDED); |
1c50c317 | 778 | } |
c8f4fe43 | 779 | |
a8bed8b6 | 780 | spin_unlock_irq(&uhci->lock); |
6c1b445c | 781 | |
1f09df8b AS |
782 | if (!uhci->working_RD) { |
783 | /* Suspended root hub needs to be polled */ | |
784 | hcd->poll_rh = 1; | |
6c1b445c | 785 | usb_hcd_poll_rh_status(hcd); |
1f09df8b | 786 | } |
1da177e4 LT |
787 | return 0; |
788 | } | |
789 | #endif | |
790 | ||
dccf4a48 | 791 | /* Wait until a particular device/endpoint's QH is idle, and free it */ |
1da177e4 | 792 | static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, |
dccf4a48 | 793 | struct usb_host_endpoint *hep) |
1da177e4 LT |
794 | { |
795 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
dccf4a48 AS |
796 | struct uhci_qh *qh; |
797 | ||
798 | spin_lock_irq(&uhci->lock); | |
799 | qh = (struct uhci_qh *) hep->hcpriv; | |
800 | if (qh == NULL) | |
801 | goto done; | |
1da177e4 | 802 | |
dccf4a48 AS |
803 | while (qh->state != QH_STATE_IDLE) { |
804 | ++uhci->num_waiting; | |
805 | spin_unlock_irq(&uhci->lock); | |
806 | wait_event_interruptible(uhci->waitqh, | |
807 | qh->state == QH_STATE_IDLE); | |
808 | spin_lock_irq(&uhci->lock); | |
809 | --uhci->num_waiting; | |
810 | } | |
811 | ||
812 | uhci_free_qh(uhci, qh); | |
813 | done: | |
814 | spin_unlock_irq(&uhci->lock); | |
1da177e4 LT |
815 | } |
816 | ||
817 | static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) | |
818 | { | |
819 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
c4334726 AS |
820 | unsigned frame_number; |
821 | unsigned delta; | |
1da177e4 LT |
822 | |
823 | /* Minimize latency by avoiding the spinlock */ | |
c4334726 AS |
824 | frame_number = uhci->frame_number; |
825 | barrier(); | |
826 | delta = (inw(uhci->io_addr + USBFRNUM) - frame_number) & | |
827 | (UHCI_NUMFRAMES - 1); | |
828 | return frame_number + delta; | |
1da177e4 LT |
829 | } |
830 | ||
831 | static const char hcd_name[] = "uhci_hcd"; | |
832 | ||
833 | static const struct hc_driver uhci_driver = { | |
834 | .description = hcd_name, | |
835 | .product_desc = "UHCI Host Controller", | |
836 | .hcd_priv_size = sizeof(struct uhci_hcd), | |
837 | ||
838 | /* Generic hardware linkage */ | |
839 | .irq = uhci_irq, | |
840 | .flags = HCD_USB11, | |
841 | ||
842 | /* Basic lifecycle operations */ | |
be3cbc5f | 843 | .reset = uhci_init, |
1da177e4 LT |
844 | .start = uhci_start, |
845 | #ifdef CONFIG_PM | |
846 | .suspend = uhci_suspend, | |
847 | .resume = uhci_resume, | |
0c0382e3 AS |
848 | .bus_suspend = uhci_rh_suspend, |
849 | .bus_resume = uhci_rh_resume, | |
1da177e4 LT |
850 | #endif |
851 | .stop = uhci_stop, | |
852 | ||
853 | .urb_enqueue = uhci_urb_enqueue, | |
854 | .urb_dequeue = uhci_urb_dequeue, | |
855 | ||
856 | .endpoint_disable = uhci_hcd_endpoint_disable, | |
857 | .get_frame_number = uhci_hcd_get_frame_number, | |
858 | ||
859 | .hub_status_data = uhci_hub_status_data, | |
860 | .hub_control = uhci_hub_control, | |
861 | }; | |
862 | ||
863 | static const struct pci_device_id uhci_pci_ids[] = { { | |
864 | /* handle any USB UHCI controller */ | |
c67808ee | 865 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0), |
1da177e4 LT |
866 | .driver_data = (unsigned long) &uhci_driver, |
867 | }, { /* end: all zeroes */ } | |
868 | }; | |
869 | ||
870 | MODULE_DEVICE_TABLE(pci, uhci_pci_ids); | |
871 | ||
872 | static struct pci_driver uhci_pci_driver = { | |
873 | .name = (char *)hcd_name, | |
874 | .id_table = uhci_pci_ids, | |
875 | ||
876 | .probe = usb_hcd_pci_probe, | |
877 | .remove = usb_hcd_pci_remove, | |
02597d2d | 878 | .shutdown = uhci_shutdown, |
1da177e4 LT |
879 | |
880 | #ifdef CONFIG_PM | |
881 | .suspend = usb_hcd_pci_suspend, | |
882 | .resume = usb_hcd_pci_resume, | |
883 | #endif /* PM */ | |
884 | }; | |
885 | ||
886 | static int __init uhci_hcd_init(void) | |
887 | { | |
888 | int retval = -ENOMEM; | |
889 | ||
890 | printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n"); | |
891 | ||
892 | if (usb_disabled()) | |
893 | return -ENODEV; | |
894 | ||
8d402e1a | 895 | if (DEBUG_CONFIGURED) { |
1da177e4 LT |
896 | errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); |
897 | if (!errbuf) | |
898 | goto errbuf_failed; | |
8d402e1a AS |
899 | uhci_debugfs_root = debugfs_create_dir("uhci", NULL); |
900 | if (!uhci_debugfs_root) | |
901 | goto debug_failed; | |
1da177e4 LT |
902 | } |
903 | ||
1da177e4 LT |
904 | uhci_up_cachep = kmem_cache_create("uhci_urb_priv", |
905 | sizeof(struct urb_priv), 0, 0, NULL, NULL); | |
906 | if (!uhci_up_cachep) | |
907 | goto up_failed; | |
908 | ||
909 | retval = pci_register_driver(&uhci_pci_driver); | |
910 | if (retval) | |
911 | goto init_failed; | |
912 | ||
913 | return 0; | |
914 | ||
915 | init_failed: | |
1a1d92c1 | 916 | kmem_cache_destroy(uhci_up_cachep); |
1da177e4 LT |
917 | |
918 | up_failed: | |
919 | debugfs_remove(uhci_debugfs_root); | |
920 | ||
921 | debug_failed: | |
1bc3c9e1 | 922 | kfree(errbuf); |
1da177e4 LT |
923 | |
924 | errbuf_failed: | |
925 | ||
926 | return retval; | |
927 | } | |
928 | ||
929 | static void __exit uhci_hcd_cleanup(void) | |
930 | { | |
931 | pci_unregister_driver(&uhci_pci_driver); | |
1a1d92c1 | 932 | kmem_cache_destroy(uhci_up_cachep); |
1da177e4 | 933 | debugfs_remove(uhci_debugfs_root); |
1bc3c9e1 | 934 | kfree(errbuf); |
1da177e4 LT |
935 | } |
936 | ||
937 | module_init(uhci_hcd_init); | |
938 | module_exit(uhci_hcd_cleanup); | |
939 | ||
940 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
941 | MODULE_DESCRIPTION(DRIVER_DESC); | |
942 | MODULE_LICENSE("GPL"); |