[linux-2.6-block.git] / drivers / usb / host / r8a66597.h

// SPDX-License-Identifier: GPL-2.0
/*
 * R8A66597 HCD (Host Controller Driver)
 *
 * Copyright (C) 2006-2007 Renesas Solutions Corp.
 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
 * Portions Copyright (C) 2004-2005 David Brownell
 * Portions Copyright (C) 1999 Roman Weissgaerber
 *
 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 */

#ifndef __R8A66597_H__
#define __R8A66597_H__

#include <linux/clk.h>
#include <linux/usb/r8a66597.h>

#define R8A66597_MAX_NUM_PIPE		10
#define R8A66597_BUF_BSIZE		8
#define R8A66597_MAX_DEVICE		10
#define R8A66597_MAX_ROOT_HUB		2
#define R8A66597_MAX_SAMPLING		5
#define R8A66597_RH_POLL_TIME		10
#define R8A66597_MAX_DMA_CHANNEL	2
#define R8A66597_PIPE_NO_DMA		R8A66597_MAX_DMA_CHANNEL
#define check_bulk_or_isoc(pipenum)	((pipenum >= 1 && pipenum <= 5))
#define check_interrupt(pipenum)	((pipenum >= 6 && pipenum <= 9))
#define make_devsel(addr)		(addr << 12)

struct r8a66597_pipe_info {
	unsigned long timer_interval;
	u16 pipenum;
	u16 address;	/* R8A66597 HCD usb address */
	u16 epnum;
	u16 maxpacket;
	u16 type;
	u16 bufnum;
	u16 buf_bsize;
	u16 interval;
	u16 dir_in;
};

struct r8a66597_pipe {
	struct r8a66597_pipe_info info;

	unsigned long fifoaddr;
	unsigned long fifosel;
	unsigned long fifoctr;
	unsigned long pipectr;
	unsigned long pipetre;
	unsigned long pipetrn;
};

struct r8a66597_td {
	struct r8a66597_pipe *pipe;
	struct urb *urb;
	struct list_head queue;

	u16 type;
	u16 pipenum;
	int iso_cnt;

	u16 address;		/* R8A66597's USB address */
	u16 maxpacket;

	unsigned zero_packet:1;
	unsigned short_packet:1;
	unsigned set_address:1;
};

struct r8a66597_device {
	u16	address;	/* R8A66597's USB address */
	u16	hub_port;
	u16	root_port;

	unsigned short ep_in_toggle;
	unsigned short ep_out_toggle;
	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
	unsigned char dma_map;

	enum usb_device_state state;

	struct usb_device *udev;
	int usb_address;
	struct list_head device_list;
};

struct r8a66597_root_hub {
	u32 port;
	u16 old_syssts;
	int scount;

	struct r8a66597_device	*dev;
};

struct r8a66597;

struct r8a66597_timers {
	struct timer_list td;
	struct timer_list interval;
	struct r8a66597 *r8a66597;
};

struct r8a66597 {
	spinlock_t lock;
	void __iomem *reg;
	struct clk *clk;
	struct r8a66597_platdata	*pdata;
	struct r8a66597_device		device0;
	struct r8a66597_root_hub	root_hub[R8A66597_MAX_ROOT_HUB];
	struct list_head		pipe_queue[R8A66597_MAX_NUM_PIPE];

	struct timer_list rh_timer;
	struct r8a66597_timers timers[R8A66597_MAX_NUM_PIPE];

	unsigned short address_map;
	unsigned short timeout_map;
	unsigned short interval_map;
	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
	unsigned char dma_map;
	unsigned int max_root_hub;

	struct list_head child_device;
	unsigned long child_connect_map[4];

	unsigned bus_suspended:1;
	unsigned irq_sense_low:1;
};

static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
{
	return (struct r8a66597 *)(hcd->hcd_priv);
}

static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
{
	return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
}

static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
						  u16 pipenum)
{
	if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
		return NULL;

	return list_entry(r8a66597->pipe_queue[pipenum].next,
			  struct r8a66597_td, queue);
}

static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
					   u16 pipenum)
{
	struct r8a66597_td *td;

	td = r8a66597_get_td(r8a66597, pipenum);
	return (td ? td->urb : NULL);
}

static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
{
	return ioread16(r8a66597->reg + offset);
}

static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
				      unsigned long offset, u16 *buf,
				      int len)
{
	void __iomem *fifoaddr = r8a66597->reg + offset;
	unsigned long count;

	if (r8a66597->pdata->on_chip) {
		count = len / 4;
		ioread32_rep(fifoaddr, buf, count);

		if (len & 0x00000003) {
			unsigned long tmp = ioread32(fifoaddr);
			memcpy((unsigned char *)buf + count * 4, &tmp,
			       len & 0x03);
		}
	} else {
		len = (len + 1) / 2;
		ioread16_rep(fifoaddr, buf, len);
	}
}

static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
				  unsigned long offset)
{
	iowrite16(val, r8a66597->reg + offset);
}

static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
				 u16 val, u16 pat, unsigned long offset)
{
	u16 tmp;
	tmp = r8a66597_read(r8a66597, offset);
	tmp = tmp & (~pat);
	tmp = tmp | val;
	r8a66597_write(r8a66597, tmp, offset);
}

#define r8a66597_bclr(r8a66597, val, offset)	\
			r8a66597_mdfy(r8a66597, 0, val, offset)
#define r8a66597_bset(r8a66597, val, offset)	\
			r8a66597_mdfy(r8a66597, val, 0, offset)

static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
				       struct r8a66597_pipe *pipe, u16 *buf,
				       int len)
{
	void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr;
	unsigned long count;
	unsigned char *pb;
	int i;

	if (r8a66597->pdata->on_chip) {
		count = len / 4;
		iowrite32_rep(fifoaddr, buf, count);

		if (len & 0x00000003) {
			pb = (unsigned char *)buf + count * 4;
			for (i = 0; i < (len & 0x00000003); i++) {
				if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
					iowrite8(pb[i], fifoaddr + i);
				else
					iowrite8(pb[i], fifoaddr + 3 - i);
			}
		}
	} else {
		int odd = len & 0x0001;

		len = len / 2;
		iowrite16_rep(fifoaddr, buf, len);
		if (unlikely(odd)) {
			buf = &buf[len];
			if (r8a66597->pdata->wr0_shorted_to_wr1)
				r8a66597_bclr(r8a66597, MBW_16, pipe->fifosel);
			iowrite8((unsigned char)*buf, fifoaddr);
			if (r8a66597->pdata->wr0_shorted_to_wr1)
				r8a66597_bset(r8a66597, MBW_16, pipe->fifosel);
		}
	}
}

static inline unsigned long get_syscfg_reg(int port)
{
	return port == 0 ? SYSCFG0 : SYSCFG1;
}

static inline unsigned long get_syssts_reg(int port)
{
	return port == 0 ? SYSSTS0 : SYSSTS1;
}

static inline unsigned long get_dvstctr_reg(int port)
{
	return port == 0 ? DVSTCTR0 : DVSTCTR1;
}

static inline unsigned long get_dmacfg_reg(int port)
{
	return port == 0 ? DMA0CFG : DMA1CFG;
}

static inline unsigned long get_intenb_reg(int port)
{
	return port == 0 ? INTENB1 : INTENB2;
}

static inline unsigned long get_intsts_reg(int port)
{
	return port == 0 ? INTSTS1 : INTSTS2;
}

static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
{
	unsigned long dvstctr_reg = get_dvstctr_reg(port);

	return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
}

static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
				       int power)
{
	unsigned long dvstctr_reg = get_dvstctr_reg(port);

	if (r8a66597->pdata->port_power) {
		r8a66597->pdata->port_power(port, power);
	} else {
		if (power)
			r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
		else
			r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
	}
}

static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
{
	u16 clock = 0;

	switch (pdata->xtal) {
	case R8A66597_PLATDATA_XTAL_12MHZ:
		clock = XTAL12;
		break;
	case R8A66597_PLATDATA_XTAL_24MHZ:
		clock = XTAL24;
		break;
	case R8A66597_PLATDATA_XTAL_48MHZ:
		clock = XTAL48;
		break;
	default:
		printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
		break;
	}

	return clock;
}

#define get_pipectr_addr(pipenum)	(PIPE1CTR + (pipenum - 1) * 2)
#define get_pipetre_addr(pipenum)	(PIPE1TRE + (pipenum - 1) * 4)
#define get_pipetrn_addr(pipenum)	(PIPE1TRN + (pipenum - 1) * 4)
#define get_devadd_addr(address)	(DEVADD0 + address * 2)

#define enable_irq_ready(r8a66597, pipenum)	\
	enable_pipe_irq(r8a66597, pipenum, BRDYENB)
#define disable_irq_ready(r8a66597, pipenum)	\
	disable_pipe_irq(r8a66597, pipenum, BRDYENB)
#define enable_irq_empty(r8a66597, pipenum)	\
	enable_pipe_irq(r8a66597, pipenum, BEMPENB)
#define disable_irq_empty(r8a66597, pipenum)	\
	disable_pipe_irq(r8a66597, pipenum, BEMPENB)
#define enable_irq_nrdy(r8a66597, pipenum)	\
	enable_pipe_irq(r8a66597, pipenum, NRDYENB)
#define disable_irq_nrdy(r8a66597, pipenum)	\
	disable_pipe_irq(r8a66597, pipenum, NRDYENB)

#endif	/* __R8A66597_H__ */
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
5d304358 YS	2	/*
	3	* R8A66597 HCD (Host Controller Driver)
	4	*
	5	* Copyright (C) 2006-2007 Renesas Solutions Corp.
	6	* Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
	7	* Portions Copyright (C) 2004-2005 David Brownell
	8	* Portions Copyright (C) 1999 Roman Weissgaerber
	9	*
	10	* Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; version 2 of the License.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	24	*
	25	*/
	26
	27	#ifndef __R8A66597_H__
	28	#define __R8A66597_H__
	29
765786e0	30	#include <linux/clk.h>
5effabbe YS	31	#include <linux/usb/r8a66597.h>
5effabbe YS	32
5d304358 YS	33	#define R8A66597_MAX_NUM_PIPE 10
	34	#define R8A66597_BUF_BSIZE 8
	35	#define R8A66597_MAX_DEVICE 10
	36	#define R8A66597_MAX_ROOT_HUB 2
29fab0cd YS	37	#define R8A66597_MAX_SAMPLING 5
29fab0cd YS	38	#define R8A66597_RH_POLL_TIME 10
5d304358 YS	39	#define R8A66597_MAX_DMA_CHANNEL 2
	40	#define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
	41	#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
	42	#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
	43	#define make_devsel(addr) (addr << 12)
	44
	45	struct r8a66597_pipe_info {
6d879107	46	unsigned long timer_interval;
e294531d	47	u16 pipenum;
dc0d5c1e	48	u16 address; /* R8A66597 HCD usb address */
e294531d YS	49	u16 epnum;
	50	u16 maxpacket;
	51	u16 type;
	52	u16 bufnum;
	53	u16 buf_bsize;
	54	u16 interval;
	55	u16 dir_in;
5d304358 YS	56	};
	57
	58	struct r8a66597_pipe {
	59	struct r8a66597_pipe_info info;
	60
	61	unsigned long fifoaddr;
	62	unsigned long fifosel;
	63	unsigned long fifoctr;
	64	unsigned long pipectr;
	65	unsigned long pipetre;
	66	unsigned long pipetrn;
	67	};
	68
	69	struct r8a66597_td {
	70	struct r8a66597_pipe *pipe;
	71	struct urb *urb;
	72	struct list_head queue;
	73
	74	u16 type;
	75	u16 pipenum;
	76	int iso_cnt;
	77
	78	u16 address; /* R8A66597's USB address */
	79	u16 maxpacket;
	80
	81	unsigned zero_packet:1;
	82	unsigned short_packet:1;
	83	unsigned set_address:1;
	84	};
	85
	86	struct r8a66597_device {
	87	u16 address; /* R8A66597's USB address */
	88	u16 hub_port;
	89	u16 root_port;
	90
	91	unsigned short ep_in_toggle;
	92	unsigned short ep_out_toggle;
	93	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
	94	unsigned char dma_map;
	95
	96	enum usb_device_state state;
	97
	98	struct usb_device *udev;
	99	int usb_address;
	100	struct list_head device_list;
	101	};
	102
	103	struct r8a66597_root_hub {
	104	u32 port;
	105	u16 old_syssts;
	106	int scount;
	107
	108	struct r8a66597_device *dev;
	109	};
	110
8e4e276a KC	111	struct r8a66597;
	112
	113	struct r8a66597_timers {
	114	struct timer_list td;
	115	struct timer_list interval;
	116	struct r8a66597 *r8a66597;
	117	};
	118
5d304358 YS	119	struct r8a66597 {
5d304358 YS	120	spinlock_t lock;
1c98347e	121	void __iomem *reg;
765786e0	122	struct clk *clk;
5effabbe	123	struct r8a66597_platdata *pdata;
5d304358 YS	124	struct r8a66597_device device0;
	125	struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
	126	struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
	127
	128	struct timer_list rh_timer;
8e4e276a	129	struct r8a66597_timers timers[R8A66597_MAX_NUM_PIPE];
5d304358 YS	130
	131	unsigned short address_map;
	132	unsigned short timeout_map;
6d879107	133	unsigned short interval_map;
5d304358 YS	134	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
5d304358 YS	135	unsigned char dma_map;
719a72b7	136	unsigned int max_root_hub;
5d304358 YS	137
	138	struct list_head child_device;
	139	unsigned long child_connect_map[4];
e1e609be YS	140
e1e609be YS	141	unsigned bus_suspended:1;
5effabbe	142	unsigned irq_sense_low:1;
5d304358 YS	143	};
	144
	145	static inline struct r8a66597 hcd_to_r8a66597(struct usb_hcd hcd)
	146	{
	147	return (struct r8a66597 *)(hcd->hcd_priv);
	148	}
	149
	150	static inline struct usb_hcd r8a66597_to_hcd(struct r8a66597 r8a66597)
	151	{
	152	return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
	153	}
	154
	155	static inline struct r8a66597_td r8a66597_get_td(struct r8a66597 r8a66597,
	156	u16 pipenum)
	157	{
	158	if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
	159	return NULL;
	160
	161	return list_entry(r8a66597->pipe_queue[pipenum].next,
	162	struct r8a66597_td, queue);
	163	}
	164
	165	static inline struct urb r8a66597_get_urb(struct r8a66597 r8a66597,
	166	u16 pipenum)
	167	{
	168	struct r8a66597_td *td;
	169
	170	td = r8a66597_get_td(r8a66597, pipenum);
	171	return (td ? td->urb : NULL);
	172	}
	173
	174	static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
	175	{
1c98347e	176	return ioread16(r8a66597->reg + offset);
5d304358 YS	177	}
	178
	179	static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
	180	unsigned long offset, u16 *buf,
	181	int len)
	182	{
1c98347e	183	void __iomem *fifoaddr = r8a66597->reg + offset;
9424ea29 YS	184	unsigned long count;
9424ea29 YS	185
719a72b7 MD	186	if (r8a66597->pdata->on_chip) {
719a72b7 MD	187	count = len / 4;
1c98347e	188	ioread32_rep(fifoaddr, buf, count);
9424ea29	189
719a72b7	190	if (len & 0x00000003) {
1c98347e	191	unsigned long tmp = ioread32(fifoaddr);
719a72b7 MD	192	memcpy((unsigned char )buf + count 4, &tmp,
	193	len & 0x03);
	194	}
	195	} else {
	196	len = (len + 1) / 2;
1c98347e	197	ioread16_rep(fifoaddr, buf, len);
9424ea29	198	}
5d304358 YS	199	}
	200
	201	static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
	202	unsigned long offset)
	203	{
1c98347e	204	iowrite16(val, r8a66597->reg + offset);
5d304358 YS	205	}
5d304358 YS	206
f2e9039a YS	207	static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
	208	u16 val, u16 pat, unsigned long offset)
	209	{
	210	u16 tmp;
	211	tmp = r8a66597_read(r8a66597, offset);
	212	tmp = tmp & (~pat);
	213	tmp = tmp \| val;
	214	r8a66597_write(r8a66597, tmp, offset);
	215	}
	216
	217	#define r8a66597_bclr(r8a66597, val, offset) \
	218	r8a66597_mdfy(r8a66597, 0, val, offset)
	219	#define r8a66597_bset(r8a66597, val, offset) \
	220	r8a66597_mdfy(r8a66597, val, 0, offset)
	221
5d304358	222	static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
f2e9039a	223	struct r8a66597_pipe pipe, u16 buf,
5d304358 YS	224	int len)
5d304358 YS	225	{
f2e9039a	226	void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr;
9424ea29 YS	227	unsigned long count;
	228	unsigned char *pb;
	229	int i;
	230
719a72b7 MD	231	if (r8a66597->pdata->on_chip) {
719a72b7 MD	232	count = len / 4;
1c98347e	233	iowrite32_rep(fifoaddr, buf, count);
719a72b7 MD	234
	235	if (len & 0x00000003) {
	236	pb = (unsigned char )buf + count 4;
	237	for (i = 0; i < (len & 0x00000003); i++) {
	238	if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
1c98347e	239	iowrite8(pb[i], fifoaddr + i);
719a72b7	240	else
1c98347e	241	iowrite8(pb[i], fifoaddr + 3 - i);
719a72b7 MD	242	}
	243	}
	244	} else {
	245	int odd = len & 0x0001;
	246
	247	len = len / 2;
ac9dfe9c	248	iowrite16_rep(fifoaddr, buf, len);
719a72b7 MD	249	if (unlikely(odd)) {
719a72b7 MD	250	buf = &buf[len];
f2e9039a YS	251	if (r8a66597->pdata->wr0_shorted_to_wr1)
f2e9039a YS	252	r8a66597_bclr(r8a66597, MBW_16, pipe->fifosel);
1c98347e	253	iowrite8((unsigned char)*buf, fifoaddr);
f2e9039a YS	254	if (r8a66597->pdata->wr0_shorted_to_wr1)
f2e9039a YS	255	r8a66597_bset(r8a66597, MBW_16, pipe->fifosel);
9424ea29 YS	256	}
9424ea29 YS	257	}
5d304358 YS	258	}
5d304358 YS	259
5d304358 YS	260	static inline unsigned long get_syscfg_reg(int port)
	261	{
	262	return port == 0 ? SYSCFG0 : SYSCFG1;
	263	}
	264
	265	static inline unsigned long get_syssts_reg(int port)
	266	{
	267	return port == 0 ? SYSSTS0 : SYSSTS1;
	268	}
	269
	270	static inline unsigned long get_dvstctr_reg(int port)
	271	{
	272	return port == 0 ? DVSTCTR0 : DVSTCTR1;
	273	}
	274
9424ea29 YS	275	static inline unsigned long get_dmacfg_reg(int port)
	276	{
	277	return port == 0 ? DMA0CFG : DMA1CFG;
	278	}
	279
5d304358 YS	280	static inline unsigned long get_intenb_reg(int port)
	281	{
	282	return port == 0 ? INTENB1 : INTENB2;
	283	}
	284
	285	static inline unsigned long get_intsts_reg(int port)
	286	{
	287	return port == 0 ? INTSTS1 : INTSTS2;
	288	}
	289
	290	static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
	291	{
	292	unsigned long dvstctr_reg = get_dvstctr_reg(port);
	293
	294	return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
	295	}
	296
	297	static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
	298	int power)
	299	{
	300	unsigned long dvstctr_reg = get_dvstctr_reg(port);
	301
5effabbe YS	302	if (r8a66597->pdata->port_power) {
	303	r8a66597->pdata->port_power(port, power);
	304	} else {
	305	if (power)
	306	r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
	307	else
	308	r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
	309	}
	310	}
	311
	312	static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
	313	{
	314	u16 clock = 0;
	315
	316	switch (pdata->xtal) {
	317	case R8A66597_PLATDATA_XTAL_12MHZ:
	318	clock = XTAL12;
	319	break;
	320	case R8A66597_PLATDATA_XTAL_24MHZ:
	321	clock = XTAL24;
	322	break;
	323	case R8A66597_PLATDATA_XTAL_48MHZ:
	324	clock = XTAL48;
	325	break;
	326	default:
	327	printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
	328	break;
	329	}
	330
	331	return clock;
5d304358 YS	332	}
	333
	334	#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
	335	#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
	336	#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
	337	#define get_devadd_addr(address) (DEVADD0 + address * 2)
	338
	339	#define enable_irq_ready(r8a66597, pipenum) \
	340	enable_pipe_irq(r8a66597, pipenum, BRDYENB)
	341	#define disable_irq_ready(r8a66597, pipenum) \
	342	disable_pipe_irq(r8a66597, pipenum, BRDYENB)
	343	#define enable_irq_empty(r8a66597, pipenum) \
	344	enable_pipe_irq(r8a66597, pipenum, BEMPENB)
	345	#define disable_irq_empty(r8a66597, pipenum) \
	346	disable_pipe_irq(r8a66597, pipenum, BEMPENB)
	347	#define enable_irq_nrdy(r8a66597, pipenum) \
	348	enable_pipe_irq(r8a66597, pipenum, NRDYENB)
	349	#define disable_irq_nrdy(r8a66597, pipenum) \
	350	disable_pipe_irq(r8a66597, pipenum, NRDYENB)
	351
	352	#endif /* __R8A66597_H__ */
	353