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Intel xhci: refactor EHCI/xHCI port switching
[linux-2.6-block.git] / drivers / usb / host / pci-quirks.c
CommitLineData
7586269c
DB		 1/*
2 * This file contains code to reset and initialize USB host controllers.
3 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4 * It may need to run early during booting -- before USB would normally
5 * initialize -- to ensure that Linux doesn't use any legacy modes.
6 *
7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
8 * (and others)
9 */
10
7586269c 11#include <linux/types.h>
51c9e6c7 12#include <linux/kconfig.h>
7586269c
DB		 13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/init.h>
16#include <linux/delay.h>
f940fcd8 17#include <linux/export.h>
7586269c 18#include <linux/acpi.h>
3610ea53 19#include <linux/dmi.h>
75e2df60 20#include "pci-quirks.h"
66d4eadd 21#include "xhci-ext-caps.h"
7586269c
DB		 22
23
7586269c
DB		 24#define UHCI_USBLEGSUP 0xc0 /* legacy support */
25#define UHCI_USBCMD 0 /* command register */
7586269c 26#define UHCI_USBINTR 4 /* interrupt register */
bb200f6e
AS		 27#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
28#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
29#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
30#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
31#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
32#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
33#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
7586269c
DB		 34
35#define OHCI_CONTROL 0x04
36#define OHCI_CMDSTATUS 0x08
37#define OHCI_INTRSTATUS 0x0c
38#define OHCI_INTRENABLE 0x10
39#define OHCI_INTRDISABLE 0x14
6ea12a04 40#define OHCI_FMINTERVAL 0x34
c6187597 41#define OHCI_HCFS (3 << 6) /* hc functional state */
6ea12a04 42#define OHCI_HCR (1 << 0) /* host controller reset */
7586269c 43#define OHCI_OCR (1 << 3) /* ownership change request */
f2cb36c1 44#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
7586269c
DB		 45#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
46#define OHCI_INTR_OC (1 << 30) /* ownership change */
47
48#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
49#define EHCI_USBCMD 0 /* command register */
50#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
51#define EHCI_USBSTS 4 /* status register */
52#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
53#define EHCI_USBINTR 8 /* interrupt register */
4fe5354f 54#define EHCI_CONFIGFLAG 0x40 /* configured flag register */
7586269c
DB		 55#define EHCI_USBLEGSUP 0 /* legacy support register */
56#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
57#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
58#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
59#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
60
ad93562b
AX		 61/* AMD quirk use */
62#define AB_REG_BAR_LOW 0xe0
63#define AB_REG_BAR_HIGH 0xe1
64#define AB_REG_BAR_SB700 0xf0
65#define AB_INDX(addr) ((addr) + 0x00)
66#define AB_DATA(addr) ((addr) + 0x04)
67#define AX_INDXC 0x30
68#define AX_DATAC 0x34
69
70#define NB_PCIE_INDX_ADDR 0xe0
71#define NB_PCIE_INDX_DATA 0xe4
72#define PCIE_P_CNTL 0x10040
73#define BIF_NB 0x10002
74#define NB_PIF0_PWRDOWN_0 0x01100012
75#define NB_PIF0_PWRDOWN_1 0x01100013
76
69e848c2 77#define USB_INTEL_XUSB2PR 0xD0
a96874a2 78#define USB_INTEL_USB2PRM 0xD4
69e848c2 79#define USB_INTEL_USB3_PSSEN 0xD8
a96874a2 80#define USB_INTEL_USB3PRM 0xDC
69e848c2 81
ad93562b
AX		 82static struct amd_chipset_info {
83 struct pci_dev *nb_dev;
84 struct pci_dev *smbus_dev;
85 int nb_type;
86 int sb_type;
87 int isoc_reqs;
88 int probe_count;
89 int probe_result;
90} amd_chipset;
91
92static DEFINE_SPINLOCK(amd_lock);
93
2621d011
MG		 94void sb800_prefetch(struct device *dev, int on)
95{
96 u16 misc;
97 struct pci_dev *pdev = to_pci_dev(dev);
98
99 pci_read_config_word(pdev, 0x50, &misc);
100 if (on == 0)
101 pci_write_config_word(pdev, 0x50, misc & 0xfcff);
102 else
103 pci_write_config_word(pdev, 0x50, misc | 0x0300);
104}
105EXPORT_SYMBOL_GPL(sb800_prefetch);
106
ad93562b
AX		 107int usb_amd_find_chipset_info(void)
108{
109 u8 rev = 0;
110 unsigned long flags;
9ab7927b
JR		 111 struct amd_chipset_info info;
112 int ret;
ad93562b
AX		 113
114 spin_lock_irqsave(&amd_lock, flags);
115
ad93562b 116 /* probe only once */
9ab7927b
JR		 117 if (amd_chipset.probe_count > 0) {
118 amd_chipset.probe_count++;
ad93562b
AX		 119 spin_unlock_irqrestore(&amd_lock, flags);
120 return amd_chipset.probe_result;
121 }
9ab7927b
JR		 122 memset(&info, 0, sizeof(info));
123 spin_unlock_irqrestore(&amd_lock, flags);
ad93562b 124
9ab7927b
JR		 125 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
126 if (info.smbus_dev) {
127 rev = info.smbus_dev->revision;
ad93562b 128 if (rev >= 0x40)
9ab7927b 129 info.sb_type = 1;
ad93562b 130 else if (rev >= 0x30 && rev <= 0x3b)
9ab7927b 131 info.sb_type = 3;
ad93562b 132 } else {
9ab7927b
JR		 133 info.smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
134 0x780b, NULL);
135 if (!info.smbus_dev) {
136 ret = 0;
137 goto commit;
ad93562b 138 }
9ab7927b
JR		 139
140 rev = info.smbus_dev->revision;
ad93562b 141 if (rev >= 0x11 && rev <= 0x18)
9ab7927b 142 info.sb_type = 2;
ad93562b
AX		 143 }
144
9ab7927b
JR		 145 if (info.sb_type == 0) {
146 if (info.smbus_dev) {
147 pci_dev_put(info.smbus_dev);
148 info.smbus_dev = NULL;
ad93562b 149 }
9ab7927b
JR		 150 ret = 0;
151 goto commit;
ad93562b
AX		 152 }
153
9ab7927b
JR		 154 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
155 if (info.nb_dev) {
156 info.nb_type = 1;
ad93562b 157 } else {
9ab7927b
JR		 158 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
159 if (info.nb_dev) {
160 info.nb_type = 2;
161 } else {
162 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
163 0x9600, NULL);
164 if (info.nb_dev)
165 info.nb_type = 3;
ad93562b
AX		 166 }
167 }
168
9ab7927b 169 ret = info.probe_result = 1;
ad93562b
AX		 170 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
171
9ab7927b
JR		 172commit:
173
174 spin_lock_irqsave(&amd_lock, flags);
175 if (amd_chipset.probe_count > 0) {
176 /* race - someone else was faster - drop devices */
177
178 /* Mark that we where here */
179 amd_chipset.probe_count++;
180 ret = amd_chipset.probe_result;
181
182 spin_unlock_irqrestore(&amd_lock, flags);
183
184 if (info.nb_dev)
185 pci_dev_put(info.nb_dev);
186 if (info.smbus_dev)
187 pci_dev_put(info.smbus_dev);
188
189 } else {
190 /* no race - commit the result */
191 info.probe_count++;
192 amd_chipset = info;
193 spin_unlock_irqrestore(&amd_lock, flags);
194 }
195
196 return ret;
ad93562b
AX		 197}
198EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
199
200/*
201 * The hardware normally enables the A-link power management feature, which
202 * lets the system lower the power consumption in idle states.
203 *
204 * This USB quirk prevents the link going into that lower power state
205 * during isochronous transfers.
206 *
207 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
208 * some AMD platforms may stutter or have breaks occasionally.
209 */
210static void usb_amd_quirk_pll(int disable)
211{
212 u32 addr, addr_low, addr_high, val;
213 u32 bit = disable ? 0 : 1;
214 unsigned long flags;
215
216 spin_lock_irqsave(&amd_lock, flags);
217
218 if (disable) {
219 amd_chipset.isoc_reqs++;
220 if (amd_chipset.isoc_reqs > 1) {
221 spin_unlock_irqrestore(&amd_lock, flags);
222 return;
223 }
224 } else {
225 amd_chipset.isoc_reqs--;
226 if (amd_chipset.isoc_reqs > 0) {
227 spin_unlock_irqrestore(&amd_lock, flags);
228 return;
229 }
230 }
231
232 if (amd_chipset.sb_type == 1 || amd_chipset.sb_type == 2) {
233 outb_p(AB_REG_BAR_LOW, 0xcd6);
234 addr_low = inb_p(0xcd7);
235 outb_p(AB_REG_BAR_HIGH, 0xcd6);
236 addr_high = inb_p(0xcd7);
237 addr = addr_high << 8 | addr_low;
238
239 outl_p(0x30, AB_INDX(addr));
240 outl_p(0x40, AB_DATA(addr));
241 outl_p(0x34, AB_INDX(addr));
242 val = inl_p(AB_DATA(addr));
243 } else if (amd_chipset.sb_type == 3) {
244 pci_read_config_dword(amd_chipset.smbus_dev,
245 AB_REG_BAR_SB700, &addr);
246 outl(AX_INDXC, AB_INDX(addr));
247 outl(0x40, AB_DATA(addr));
248 outl(AX_DATAC, AB_INDX(addr));
249 val = inl(AB_DATA(addr));
250 } else {
251 spin_unlock_irqrestore(&amd_lock, flags);
252 return;
253 }
254
255 if (disable) {
256 val &= ~0x08;
257 val |= (1 << 4) | (1 << 9);
258 } else {
259 val |= 0x08;
260 val &= ~((1 << 4) | (1 << 9));
261 }
262 outl_p(val, AB_DATA(addr));
263
264 if (!amd_chipset.nb_dev) {
265 spin_unlock_irqrestore(&amd_lock, flags);
266 return;
267 }
268
269 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
270 addr = PCIE_P_CNTL;
271 pci_write_config_dword(amd_chipset.nb_dev,
272 NB_PCIE_INDX_ADDR, addr);
273 pci_read_config_dword(amd_chipset.nb_dev,
274 NB_PCIE_INDX_DATA, &val);
275
276 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
277 val |= bit | (bit << 3) | (bit << 12);
278 val |= ((!bit) << 4) | ((!bit) << 9);
279 pci_write_config_dword(amd_chipset.nb_dev,
280 NB_PCIE_INDX_DATA, val);
281
282 addr = BIF_NB;
283 pci_write_config_dword(amd_chipset.nb_dev,
284 NB_PCIE_INDX_ADDR, addr);
285 pci_read_config_dword(amd_chipset.nb_dev,
286 NB_PCIE_INDX_DATA, &val);
287 val &= ~(1 << 8);
288 val |= bit << 8;
289
290 pci_write_config_dword(amd_chipset.nb_dev,
291 NB_PCIE_INDX_DATA, val);
292 } else if (amd_chipset.nb_type == 2) {
293 addr = NB_PIF0_PWRDOWN_0;
294 pci_write_config_dword(amd_chipset.nb_dev,
295 NB_PCIE_INDX_ADDR, addr);
296 pci_read_config_dword(amd_chipset.nb_dev,
297 NB_PCIE_INDX_DATA, &val);
298 if (disable)
299 val &= ~(0x3f << 7);
300 else
301 val |= 0x3f << 7;
302
303 pci_write_config_dword(amd_chipset.nb_dev,
304 NB_PCIE_INDX_DATA, val);
305
306 addr = NB_PIF0_PWRDOWN_1;
307 pci_write_config_dword(amd_chipset.nb_dev,
308 NB_PCIE_INDX_ADDR, addr);
309 pci_read_config_dword(amd_chipset.nb_dev,
310 NB_PCIE_INDX_DATA, &val);
311 if (disable)
312 val &= ~(0x3f << 7);
313 else
314 val |= 0x3f << 7;
315
316 pci_write_config_dword(amd_chipset.nb_dev,
317 NB_PCIE_INDX_DATA, val);
318 }
319
320 spin_unlock_irqrestore(&amd_lock, flags);
321 return;
322}
323
324void usb_amd_quirk_pll_disable(void)
325{
326 usb_amd_quirk_pll(1);
327}
328EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
329
330void usb_amd_quirk_pll_enable(void)
331{
332 usb_amd_quirk_pll(0);
333}
334EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
335
336void usb_amd_dev_put(void)
337{
9ab7927b 338 struct pci_dev *nb, *smbus;
ad93562b
AX		 339 unsigned long flags;
340
341 spin_lock_irqsave(&amd_lock, flags);
342
343 amd_chipset.probe_count--;
344 if (amd_chipset.probe_count > 0) {
345 spin_unlock_irqrestore(&amd_lock, flags);
346 return;
347 }
348
9ab7927b
JR		 349 /* save them to pci_dev_put outside of spinlock */
350 nb = amd_chipset.nb_dev;
351 smbus = amd_chipset.smbus_dev;
352
353 amd_chipset.nb_dev = NULL;
354 amd_chipset.smbus_dev = NULL;
ad93562b
AX		 355 amd_chipset.nb_type = 0;
356 amd_chipset.sb_type = 0;
357 amd_chipset.isoc_reqs = 0;
358 amd_chipset.probe_result = 0;
359
360 spin_unlock_irqrestore(&amd_lock, flags);
9ab7927b
JR		 361
362 if (nb)
363 pci_dev_put(nb);
364 if (smbus)
365 pci_dev_put(smbus);
ad93562b
AX		 366}
367EXPORT_SYMBOL_GPL(usb_amd_dev_put);
7586269c 368
bb200f6e
AS		 369/*
370 * Make sure the controller is completely inactive, unable to
371 * generate interrupts or do DMA.
372 */
373void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
374{
375 /* Turn off PIRQ enable and SMI enable. (This also turns off the
376 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
377 */
378 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
379
380 /* Reset the HC - this will force us to get a
381 * new notification of any already connected
382 * ports due to the virtual disconnect that it
383 * implies.
384 */
385 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
386 mb();
387 udelay(5);
388 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
389 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
390
391 /* Just to be safe, disable interrupt requests and
392 * make sure the controller is stopped.
393 */
394 outw(0, base + UHCI_USBINTR);
395 outw(0, base + UHCI_USBCMD);
396}
397EXPORT_SYMBOL_GPL(uhci_reset_hc);
398
399/*
400 * Initialize a controller that was newly discovered or has just been
401 * resumed. In either case we can't be sure of its previous state.
402 *
403 * Returns: 1 if the controller was reset, 0 otherwise.
404 */
405int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
406{
407 u16 legsup;
408 unsigned int cmd, intr;
409
410 /*
411 * When restarting a suspended controller, we expect all the
412 * settings to be the same as we left them:
413 *
414 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
415 * Controller is stopped and configured with EGSM set;
416 * No interrupts enabled except possibly Resume Detect.
417 *
418 * If any of these conditions are violated we do a complete reset.
419 */
420 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
421 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
422 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
441b62c1 423 __func__, legsup);
bb200f6e
AS		 424 goto reset_needed;
425 }
426
427 cmd = inw(base + UHCI_USBCMD);
428 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
429 !(cmd & UHCI_USBCMD_EGSM)) {
430 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
441b62c1 431 __func__, cmd);
bb200f6e
AS		 432 goto reset_needed;
433 }
434
435 intr = inw(base + UHCI_USBINTR);
436 if (intr & (~UHCI_USBINTR_RESUME)) {
437 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
441b62c1 438 __func__, intr);
bb200f6e
AS		 439 goto reset_needed;
440 }
441 return 0;
442
443reset_needed:
444 dev_dbg(&pdev->dev, "Performing full reset\n");
445 uhci_reset_hc(pdev, base);
446 return 1;
447}
448EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
449
541ab4af
LT		 450static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
451{
452 u16 cmd;
453 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
454}
455
456#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
457#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
458
41ac7b3a 459static void quirk_usb_handoff_uhci(struct pci_dev *pdev)
7586269c
DB		 460{
461 unsigned long base = 0;
7586269c
DB		 462 int i;
463
541ab4af
LT		 464 if (!pio_enabled(pdev))
465 return;
466
7586269c
DB		 467 for (i = 0; i < PCI_ROM_RESOURCE; i++)
468 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
469 base = pci_resource_start(pdev, i);
470 break;
471 }
472
bb200f6e
AS		 473 if (base)
474 uhci_check_and_reset_hc(pdev, base);
7586269c
DB		 475}
476
41ac7b3a 477static int mmio_resource_enabled(struct pci_dev *pdev, int idx)
541ab4af
LT		 478{
479 return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
480}
481
41ac7b3a 482static void quirk_usb_handoff_ohci(struct pci_dev *pdev)
7586269c
DB		 483{
484 void __iomem *base;
3df7169e 485 u32 control;
c6187597
AS		 486 u32 fminterval;
487 int cnt;
7586269c 488
541ab4af
LT		 489 if (!mmio_resource_enabled(pdev, 0))
490 return;
491
8e8ce4b6
AV		 492 base = pci_ioremap_bar(pdev, 0);
493 if (base == NULL)
494 return;
7586269c 495
3df7169e
AS		 496 control = readl(base + OHCI_CONTROL);
497
f2cb36c1 498/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
3df7169e
AS		 499#ifdef __hppa__
500#define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
501#else
502#define OHCI_CTRL_MASK OHCI_CTRL_RWC
503
f2cb36c1 504 if (control & OHCI_CTRL_IR) {
c1b45f24 505 int wait_time = 500; /* arbitrary; 5 seconds */
7586269c
DB		 506 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
507 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
508 while (wait_time > 0 &&
509 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
510 wait_time -= 10;
511 msleep(10);
512 }
f2cb36c1 513 if (wait_time <= 0)
f0fda801 514 dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
515 " (BIOS bug?) %08x\n",
a38408cd 516 readl(base + OHCI_CONTROL));
7586269c 517 }
f2cb36c1 518#endif
7586269c 519
c6187597
AS		 520 /* disable interrupts */
521 writel((u32) ~0, base + OHCI_INTRDISABLE);
6ea12a04 522
c6187597
AS		 523 /* Reset the USB bus, if the controller isn't already in RESET */
524 if (control & OHCI_HCFS) {
525 /* Go into RESET, preserving RWC (and possibly IR) */
526 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
527 readl(base + OHCI_CONTROL);
6ea12a04 528
c6187597 529 /* drive bus reset for at least 50 ms (7.1.7.5) */
6ea12a04 530 msleep(50);
c6187597 531 }
6ea12a04 532
c6187597
AS		 533 /* software reset of the controller, preserving HcFmInterval */
534 fminterval = readl(base + OHCI_FMINTERVAL);
535 writel(OHCI_HCR, base + OHCI_CMDSTATUS);
6ea12a04 536
c6187597
AS		 537 /* reset requires max 10 us delay */
538 for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */
539 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
540 break;
541 udelay(1);
6ea12a04 542 }
c6187597 543 writel(fminterval, base + OHCI_FMINTERVAL);
3df7169e 544
c6187597 545 /* Now the controller is safely in SUSPEND and nothing can wake it up */
7586269c
DB		 546 iounmap(base);
547}
548
2f82686e 549static const struct dmi_system_id ehci_dmi_nohandoff_table[] = {
03c75362
AA		 550 {
551 /* Pegatron Lucid (ExoPC) */
552 .matches = {
553 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
554 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
555 },
556 },
0c42a4e8
AA		 557 {
558 /* Pegatron Lucid (Ordissimo AIRIS) */
559 .matches = {
560 DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
c323dc02 561 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
0c42a4e8
AA		 562 },
563 },
8daf8b60
AA		 564 {
565 /* Pegatron Lucid (Ordissimo) */
566 .matches = {
567 DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"),
568 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
569 },
570 },
03c75362
AA		 571 { }
572};
573
41ac7b3a 574static void ehci_bios_handoff(struct pci_dev *pdev,
5c853013
AR		 575 void __iomem *op_reg_base,
576 u32 cap, u8 offset)
577{
3610ea53
AR		 578 int try_handoff = 1, tried_handoff = 0;
579
03c75362
AA		 580 /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying
581 * the handoff on its unused controller. Skip it. */
3610ea53 582 if (pdev->vendor == 0x8086 && pdev->device == 0x283a) {
03c75362 583 if (dmi_check_system(ehci_dmi_nohandoff_table))
3610ea53
AR		 584 try_handoff = 0;
585 }
5c853013 586
3610ea53 587 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
5c853013
AR		 588 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
589
590#if 0
591/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
592 * but that seems dubious in general (the BIOS left it off intentionally)
593 * and is known to prevent some systems from booting. so we won't do this
594 * unless maybe we can determine when we're on a system that needs SMI forced.
595 */
596 /* BIOS workaround (?): be sure the pre-Linux code
597 * receives the SMI
598 */
599 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
600 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
601 val | EHCI_USBLEGCTLSTS_SOOE);
602#endif
603
604 /* some systems get upset if this semaphore is
605 * set for any other reason than forcing a BIOS
606 * handoff..
607 */
608 pci_write_config_byte(pdev, offset + 3, 1);
609 }
610
611 /* if boot firmware now owns EHCI, spin till it hands it over. */
3610ea53
AR		 612 if (try_handoff) {
613 int msec = 1000;
614 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
615 tried_handoff = 1;
616 msleep(10);
617 msec -= 10;
618 pci_read_config_dword(pdev, offset, &cap);
619 }
5c853013
AR		 620 }
621
622 if (cap & EHCI_USBLEGSUP_BIOS) {
623 /* well, possibly buggy BIOS... try to shut it down,
624 * and hope nothing goes too wrong
625 */
3610ea53
AR		 626 if (try_handoff)
627 dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
628 " (BIOS bug?) %08x\n", cap);
5c853013
AR		 629 pci_write_config_byte(pdev, offset + 2, 0);
630 }
631
632 /* just in case, always disable EHCI SMIs */
633 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
634
635 /* If the BIOS ever owned the controller then we can't expect
636 * any power sessions to remain intact.
637 */
638 if (tried_handoff)
639 writel(0, op_reg_base + EHCI_CONFIGFLAG);
640}
641
41ac7b3a 642static void quirk_usb_disable_ehci(struct pci_dev *pdev)
7586269c 643{
7586269c 644 void __iomem *base, *op_reg_base;
5c853013 645 u32 hcc_params, cap, val;
401feafa 646 u8 offset, cap_length;
97ff22ee 647 int wait_time, count = 256/4;
7586269c 648
541ab4af
LT		 649 if (!mmio_resource_enabled(pdev, 0))
650 return;
651
8e8ce4b6
AV		 652 base = pci_ioremap_bar(pdev, 0);
653 if (base == NULL)
654 return;
7586269c
DB		 655
656 cap_length = readb(base);
657 op_reg_base = base + cap_length;
401feafa
DB		 658
659 /* EHCI 0.96 and later may have "extended capabilities"
660 * spec section 5.1 explains the bios handoff, e.g. for
661 * booting from USB disk or using a usb keyboard
662 */
7586269c 663 hcc_params = readl(base + EHCI_HCC_PARAMS);
401feafa 664 offset = (hcc_params >> 8) & 0xff;
6e14bda1 665 while (offset && --count) {
401feafa 666 pci_read_config_dword(pdev, offset, &cap);
401feafa 667
5c853013
AR		 668 switch (cap & 0xff) {
669 case 1:
670 ehci_bios_handoff(pdev, op_reg_base, cap, offset);
401feafa 671 break;
5c853013
AR		 672 case 0: /* Illegal reserved cap, set cap=0 so we exit */
673 cap = 0; /* then fallthrough... */
401feafa 674 default:
f0fda801 675 dev_warn(&pdev->dev, "EHCI: unrecognized capability "
5c853013 676 "%02x\n", cap & 0xff);
7586269c 677 }
401feafa 678 offset = (cap >> 8) & 0xff;
7586269c 679 }
401feafa 680 if (!count)
f0fda801 681 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
7586269c
DB		 682
683 /*
684 * halt EHCI & disable its interrupts in any case
685 */
686 val = readl(op_reg_base + EHCI_USBSTS);
687 if ((val & EHCI_USBSTS_HALTED) == 0) {
688 val = readl(op_reg_base + EHCI_USBCMD);
689 val &= ~EHCI_USBCMD_RUN;
690 writel(val, op_reg_base + EHCI_USBCMD);
691
692 wait_time = 2000;
7586269c
DB		 693 do {
694 writel(0x3f, op_reg_base + EHCI_USBSTS);
97ff22ee
AS		 695 udelay(100);
696 wait_time -= 100;
7586269c
DB		 697 val = readl(op_reg_base + EHCI_USBSTS);
698 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
699 break;
700 }
701 } while (wait_time > 0);
702 }
703 writel(0, op_reg_base + EHCI_USBINTR);
704 writel(0x3f, op_reg_base + EHCI_USBSTS);
705
706 iounmap(base);
7586269c
DB		 707}
708
66d4eadd
SS		 709/*
710 * handshake - spin reading a register until handshake completes
711 * @ptr: address of hc register to be read
712 * @mask: bits to look at in result of read
713 * @done: value of those bits when handshake succeeds
714 * @wait_usec: timeout in microseconds
715 * @delay_usec: delay in microseconds to wait between polling
716 *
717 * Polls a register every delay_usec microseconds.
718 * Returns 0 when the mask bits have the value done.
719 * Returns -ETIMEDOUT if this condition is not true after
720 * wait_usec microseconds have passed.
721 */
722static int handshake(void __iomem *ptr, u32 mask, u32 done,
723 int wait_usec, int delay_usec)
724{
725 u32 result;
726
727 do {
728 result = readl(ptr);
729 result &= mask;
730 if (result == done)
731 return 0;
732 udelay(delay_usec);
733 wait_usec -= delay_usec;
734 } while (wait_usec > 0);
735 return -ETIMEDOUT;
736}
737
69e848c2
SS		 738/*
739 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
740 * share some number of ports. These ports can be switched between either
741 * controller. Not all of the ports under the EHCI host controller may be
742 * switchable.
743 *
744 * The ports should be switched over to xHCI before PCI probes for any device
745 * start. This avoids active devices under EHCI being disconnected during the
746 * port switchover, which could cause loss of data on USB storage devices, or
747 * failed boot when the root file system is on a USB mass storage device and is
748 * enumerated under EHCI first.
749 *
750 * We write into the xHC's PCI configuration space in some Intel-specific
751 * registers to switch the ports over. The USB 3.0 terminations and the USB
752 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
753 * terminations before switching the USB 2.0 wires over, so that USB 3.0
754 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
755 */
26b76798 756void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev)
69e848c2
SS		 757{
758 u32 ports_available;
26b76798
MN		 759 bool ehci_found = false;
760 struct pci_dev *companion = NULL;
761
762 /* make sure an intel EHCI controller exists */
763 for_each_pci_dev(companion) {
764 if (companion->class == PCI_CLASS_SERIAL_USB_EHCI &&
765 companion->vendor == PCI_VENDOR_ID_INTEL) {
766 ehci_found = true;
767 break;
768 }
769 }
770
771 if (!ehci_found)
772 return;
69e848c2 773
51c9e6c7
SS		 774 /* Don't switchover the ports if the user hasn't compiled the xHCI
775 * driver. Otherwise they will see "dead" USB ports that don't power
776 * the devices.
777 */
778 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) {
779 dev_warn(&xhci_pdev->dev,
780 "CONFIG_USB_XHCI_HCD is turned off, "
781 "defaulting to EHCI.\n");
782 dev_warn(&xhci_pdev->dev,
783 "USB 3.0 devices will work at USB 2.0 speeds.\n");
58b2939b 784 usb_disable_xhci_ports(xhci_pdev);
51c9e6c7
SS		 785 return;
786 }
787
a96874a2
KYL		 788 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
789 * Indicate the ports that can be changed from OS.
790 */
791 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM,
792 &ports_available);
793
794 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",
795 ports_available);
796
69e848c2 797 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
a96874a2
KYL		 798 * Register, to turn on SuperSpeed terminations for the
799 * switchable ports.
69e848c2
SS		 800 */
801 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
802 cpu_to_le32(ports_available));
803
804 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
805 &ports_available);
806 dev_dbg(&xhci_pdev->dev, "USB 3.0 ports that are now enabled "
807 "under xHCI: 0x%x\n", ports_available);
808
a96874a2
KYL		 809 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
810 * Indicate the USB 2.0 ports to be controlled by the xHCI host.
811 */
812
813 pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM,
814 &ports_available);
815
816 dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
817 ports_available);
818
69e848c2
SS		 819 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
820 * switch the USB 2.0 power and data lines over to the xHCI
821 * host.
822 */
823 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
824 cpu_to_le32(ports_available));
825
826 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
827 &ports_available);
828 dev_dbg(&xhci_pdev->dev, "USB 2.0 ports that are now switched over "
829 "to xHCI: 0x%x\n", ports_available);
830}
26b76798 831EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports);
69e848c2 832
e95829f4
SS		 833void usb_disable_xhci_ports(struct pci_dev *xhci_pdev)
834{
835 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0);
836 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0);
837}
838EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
839
66d4eadd
SS		 840/**
841 * PCI Quirks for xHCI.
842 *
843 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
844 * It signals to the BIOS that the OS wants control of the host controller,
845 * and then waits 5 seconds for the BIOS to hand over control.
846 * If we timeout, assume the BIOS is broken and take control anyway.
847 */
41ac7b3a 848static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
66d4eadd
SS		 849{
850 void __iomem *base;
851 int ext_cap_offset;
852 void __iomem *op_reg_base;
853 u32 val;
854 int timeout;
e955a1cd 855 int len = pci_resource_len(pdev, 0);
66d4eadd
SS		 856
857 if (!mmio_resource_enabled(pdev, 0))
858 return;
859
e955a1cd 860 base = ioremap_nocache(pci_resource_start(pdev, 0), len);
66d4eadd
SS		 861 if (base == NULL)
862 return;
7586269c 863
66d4eadd
SS		 864 /*
865 * Find the Legacy Support Capability register -
866 * this is optional for xHCI host controllers.
867 */
868 ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
869 do {
e955a1cd
MG		 870 if ((ext_cap_offset + sizeof(val)) > len) {
871 /* We're reading garbage from the controller */
872 dev_warn(&pdev->dev,
873 "xHCI controller failing to respond");
874 return;
875 }
876
66d4eadd
SS		 877 if (!ext_cap_offset)
878 /* We've reached the end of the extended capabilities */
879 goto hc_init;
e955a1cd 880
66d4eadd
SS		 881 val = readl(base + ext_cap_offset);
882 if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
883 break;
884 ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
885 } while (1);
886
887 /* If the BIOS owns the HC, signal that the OS wants it, and wait */
888 if (val & XHCI_HC_BIOS_OWNED) {
6768458b 889 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
66d4eadd
SS		 890
891 /* Wait for 5 seconds with 10 microsecond polling interval */
892 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
893 0, 5000, 10);
894
895 /* Assume a buggy BIOS and take HC ownership anyway */
896 if (timeout) {
897 dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
898 " (BIOS bug ?) %08x\n", val);
899 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
900 }
901 }
902
95018a53
AH		 903 val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
904 /* Mask off (turn off) any enabled SMIs */
905 val &= XHCI_LEGACY_DISABLE_SMI;
906 /* Mask all SMI events bits, RW1C */
907 val |= XHCI_LEGACY_SMI_EVENTS;
908 /* Disable any BIOS SMIs and clear all SMI events*/
909 writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
66d4eadd 910
29d21457 911hc_init:
26b76798
MN		 912 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
913 usb_enable_intel_xhci_ports(pdev);
29d21457 914
66d4eadd
SS		 915 op_reg_base = base + XHCI_HC_LENGTH(readl(base));
916
917 /* Wait for the host controller to be ready before writing any
918 * operational or runtime registers. Wait 5 seconds and no more.
919 */
920 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
921 5000, 10);
922 /* Assume a buggy HC and start HC initialization anyway */
923 if (timeout) {
924 val = readl(op_reg_base + XHCI_STS_OFFSET);
925 dev_warn(&pdev->dev,
926 "xHCI HW not ready after 5 sec (HC bug?) "
927 "status = 0x%x\n", val);
928 }
929
930 /* Send the halt and disable interrupts command */
931 val = readl(op_reg_base + XHCI_CMD_OFFSET);
932 val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
933 writel(val, op_reg_base + XHCI_CMD_OFFSET);
934
935 /* Wait for the HC to halt - poll every 125 usec (one microframe). */
936 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
937 XHCI_MAX_HALT_USEC, 125);
938 if (timeout) {
939 val = readl(op_reg_base + XHCI_STS_OFFSET);
940 dev_warn(&pdev->dev,
941 "xHCI HW did not halt within %d usec "
942 "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
943 }
944
945 iounmap(base);
946}
7586269c 947
41ac7b3a 948static void quirk_usb_early_handoff(struct pci_dev *pdev)
7586269c 949{
e4436a7c
J		 950 /* Skip Netlogic mips SoC's internal PCI USB controller.
951 * This device does not need/support EHCI/OHCI handoff
952 */
953 if (pdev->vendor == 0x184e) /* vendor Netlogic */
954 return;
cab928ee
SS		 955 if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
956 pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
957 pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
958 pdev->class != PCI_CLASS_SERIAL_USB_XHCI)
959 return;
e4436a7c 960
cab928ee
SS		 961 if (pci_enable_device(pdev) < 0) {
962 dev_warn(&pdev->dev, "Can't enable PCI device, "
963 "BIOS handoff failed.\n");
964 return;
965 }
478a3bab 966 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
7586269c 967 quirk_usb_handoff_uhci(pdev);
478a3bab 968 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
7586269c 969 quirk_usb_handoff_ohci(pdev);
478a3bab 970 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
7586269c 971 quirk_usb_disable_ehci(pdev);
66d4eadd
SS		 972 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
973 quirk_usb_handoff_xhci(pdev);
cab928ee 974 pci_disable_device(pdev);
7586269c 975}
8474ecd9
YL		 976DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
977 PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
Linux 6.x block layer and io_uring tree(s)