[linux-2.6-block.git] / drivers / usb / host / ohci-pxa27x.c

/*
 * OHCI HCD (Host Controller Driver) for USB.
 *
 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
 * (C) Copyright 2002 Hewlett-Packard Company
 *
 * Bus Glue for pxa27x
 *
 * Written by Christopher Hoover <ch@hpl.hp.com>
 * Based on fragments of previous driver by Russell King et al.
 *
 * Modified for LH7A404 from ohci-sa1111.c
 *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
 *
 * Modified for pxa27x from ohci-lh7a404.c
 *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
 *
 * This file is licenced under the GPL.
 */

#include <linux/clk.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include <linux/platform_data/usb-pxa3xx-ulpi.h>
#include <linux/platform_device.h>
#include <linux/signal.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>
#include <linux/usb/otg.h>

#include <mach/hardware.h>

#include "ohci.h"

#define DRIVER_DESC "OHCI PXA27x/PXA3x driver"

/*
 * UHC: USB Host Controller (OHCI-like) register definitions
 */
#define UHCREV		(0x0000) /* UHC HCI Spec Revision */
#define UHCHCON		(0x0004) /* UHC Host Control Register */
#define UHCCOMS		(0x0008) /* UHC Command Status Register */
#define UHCINTS		(0x000C) /* UHC Interrupt Status Register */
#define UHCINTE		(0x0010) /* UHC Interrupt Enable */
#define UHCINTD		(0x0014) /* UHC Interrupt Disable */
#define UHCHCCA		(0x0018) /* UHC Host Controller Comm. Area */
#define UHCPCED		(0x001C) /* UHC Period Current Endpt Descr */
#define UHCCHED		(0x0020) /* UHC Control Head Endpt Descr */
#define UHCCCED		(0x0024) /* UHC Control Current Endpt Descr */
#define UHCBHED		(0x0028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED		(0x002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD	(0x0030) /* UHC Done Head */
#define UHCFMI		(0x0034) /* UHC Frame Interval */
#define UHCFMR		(0x0038) /* UHC Frame Remaining */
#define UHCFMN		(0x003C) /* UHC Frame Number */
#define UHCPERS		(0x0040) /* UHC Periodic Start */
#define UHCLS		(0x0044) /* UHC Low Speed Threshold */

#define UHCRHDA		(0x0048) /* UHC Root Hub Descriptor A */
#define UHCRHDA_NOCP	(1 << 12)	/* No over current protection */
#define UHCRHDA_OCPM	(1 << 11)	/* Over Current Protection Mode */
#define UHCRHDA_POTPGT(x) \
			(((x) & 0xff) << 24) /* Power On To Power Good Time */

#define UHCRHDB		(0x004C) /* UHC Root Hub Descriptor B */
#define UHCRHS		(0x0050) /* UHC Root Hub Status */
#define UHCRHPS1	(0x0054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2	(0x0058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3	(0x005C) /* UHC Root Hub Port 3 Status */

#define UHCSTAT		(0x0060) /* UHC Status Register */
#define UHCSTAT_UPS3	(1 << 16)	/* USB Power Sense Port3 */
#define UHCSTAT_SBMAI	(1 << 15)	/* System Bus Master Abort Interrupt*/
#define UHCSTAT_SBTAI	(1 << 14)	/* System Bus Target Abort Interrupt*/
#define UHCSTAT_UPRI	(1 << 13)	/* USB Port Resume Interrupt */
#define UHCSTAT_UPS2	(1 << 12)	/* USB Power Sense Port 2 */
#define UHCSTAT_UPS1	(1 << 11)	/* USB Power Sense Port 1 */
#define UHCSTAT_HTA	(1 << 10)	/* HCI Target Abort */
#define UHCSTAT_HBA	(1 << 8)	/* HCI Buffer Active */
#define UHCSTAT_RWUE	(1 << 7)	/* HCI Remote Wake Up Event */

#define UHCHR           (0x0064) /* UHC Reset Register */
#define UHCHR_SSEP3	(1 << 11)	/* Sleep Standby Enable for Port3 */
#define UHCHR_SSEP2	(1 << 10)	/* Sleep Standby Enable for Port2 */
#define UHCHR_SSEP1	(1 << 9)	/* Sleep Standby Enable for Port1 */
#define UHCHR_PCPL	(1 << 7)	/* Power control polarity low */
#define UHCHR_PSPL	(1 << 6)	/* Power sense polarity low */
#define UHCHR_SSE	(1 << 5)	/* Sleep Standby Enable */
#define UHCHR_UIT	(1 << 4)	/* USB Interrupt Test */
#define UHCHR_SSDC	(1 << 3)	/* Simulation Scale Down Clock */
#define UHCHR_CGR	(1 << 2)	/* Clock Generation Reset */
#define UHCHR_FHR	(1 << 1)	/* Force Host Controller Reset */
#define UHCHR_FSBIR	(1 << 0)	/* Force System Bus Iface Reset */

#define UHCHIE          (0x0068) /* UHC Interrupt Enable Register*/
#define UHCHIE_UPS3IE	(1 << 14)	/* Power Sense Port3 IntEn */
#define UHCHIE_UPRIE	(1 << 13)	/* Port Resume IntEn */
#define UHCHIE_UPS2IE	(1 << 12)	/* Power Sense Port2 IntEn */
#define UHCHIE_UPS1IE	(1 << 11)	/* Power Sense Port1 IntEn */
#define UHCHIE_TAIE	(1 << 10)	/* HCI Interface Transfer Abort
					   Interrupt Enable*/
#define UHCHIE_HBAIE	(1 << 8)	/* HCI Buffer Active IntEn */
#define UHCHIE_RWIE	(1 << 7)	/* Remote Wake-up IntEn */

#define UHCHIT          (0x006C) /* UHC Interrupt Test register */

#define PXA_UHC_MAX_PORTNUM    3

static const char hcd_name[] = "ohci-pxa27x";

static struct hc_driver __read_mostly ohci_pxa27x_hc_driver;

struct pxa27x_ohci {
	struct clk	*clk;
	void __iomem	*mmio_base;
};

#define to_pxa27x_ohci(hcd)	(struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv)

/*
  PMM_NPS_MODE -- PMM Non-power switching mode
      Ports are powered continuously.

  PMM_GLOBAL_MODE -- PMM global switching mode
      All ports are powered at the same time.

  PMM_PERPORT_MODE -- PMM per port switching mode
      Ports are powered individually.
 */
static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode)
{
	uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
	uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);

	switch (mode) {
	case PMM_NPS_MODE:
		uhcrhda |= RH_A_NPS;
		break;
	case PMM_GLOBAL_MODE:
		uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
		break;
	case PMM_PERPORT_MODE:
		uhcrhda &= ~(RH_A_NPS);
		uhcrhda |= RH_A_PSM;

		/* Set port power control mask bits, only 3 ports. */
		uhcrhdb |= (0x7<<17);
		break;
	default:
		printk( KERN_ERR
			"Invalid mode %d, set to non-power switch mode.\n",
			mode );

		uhcrhda |= RH_A_NPS;
	}

	__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
	__raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
	return 0;
}

/*-------------------------------------------------------------------------*/

static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci,
				   struct pxaohci_platform_data *inf)
{
	uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
	uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);

	if (inf->flags & ENABLE_PORT1)
		uhchr &= ~UHCHR_SSEP1;

	if (inf->flags & ENABLE_PORT2)
		uhchr &= ~UHCHR_SSEP2;

	if (inf->flags & ENABLE_PORT3)
		uhchr &= ~UHCHR_SSEP3;

	if (inf->flags & POWER_CONTROL_LOW)
		uhchr |= UHCHR_PCPL;

	if (inf->flags & POWER_SENSE_LOW)
		uhchr |= UHCHR_PSPL;

	if (inf->flags & NO_OC_PROTECTION)
		uhcrhda |= UHCRHDA_NOCP;
	else
		uhcrhda &= ~UHCRHDA_NOCP;

	if (inf->flags & OC_MODE_PERPORT)
		uhcrhda |= UHCRHDA_OCPM;
	else
		uhcrhda &= ~UHCRHDA_OCPM;

	if (inf->power_on_delay) {
		uhcrhda &= ~UHCRHDA_POTPGT(0xff);
		uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
	}

	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
	__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
}

static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci)
{
	uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);

	__raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
	udelay(11);
	__raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
}

#ifdef CONFIG_PXA27x
extern void pxa27x_clear_otgph(void);
#else
#define pxa27x_clear_otgph()	do {} while (0)
#endif

static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
{
	int retval = 0;
	struct pxaohci_platform_data *inf;
	uint32_t uhchr;
	struct usb_hcd *hcd = dev_get_drvdata(dev);

	inf = dev_get_platdata(dev);

	clk_prepare_enable(pxa_ohci->clk);

	pxa27x_reset_hc(pxa_ohci);

	uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);

	while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
		cpu_relax();

	pxa27x_setup_hc(pxa_ohci, inf);

	if (inf->init)
		retval = inf->init(dev);

	if (retval < 0)
		return retval;

	if (cpu_is_pxa3xx())
		pxa3xx_u2d_start_hc(&hcd->self);

	uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
	__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);

	/* Clear any OTG Pin Hold */
	pxa27x_clear_otgph();
	return 0;
}

static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
{
	struct pxaohci_platform_data *inf;
	struct usb_hcd *hcd = dev_get_drvdata(dev);
	uint32_t uhccoms;

	inf = dev_get_platdata(dev);

	if (cpu_is_pxa3xx())
		pxa3xx_u2d_stop_hc(&hcd->self);

	if (inf->exit)
		inf->exit(dev);

	pxa27x_reset_hc(pxa_ohci);

	/* Host Controller Reset */
	uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
	__raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
	udelay(10);

	clk_disable_unprepare(pxa_ohci->clk);
}

#ifdef CONFIG_OF
static const struct of_device_id pxa_ohci_dt_ids[] = {
	{ .compatible = "marvell,pxa-ohci" },
	{ }
};

MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);

static int ohci_pxa_of_init(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct pxaohci_platform_data *pdata;
	u32 tmp;
	int ret;

	if (!np)
		return 0;

	/* Right now device-tree probed devices don't get dma_mask set.
	 * Since shared usb code relies on it, set it here for now.
	 * Once we have dma capability bindings this can go away.
	 */
	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	if (of_get_property(np, "marvell,enable-port1", NULL))
		pdata->flags |= ENABLE_PORT1;
	if (of_get_property(np, "marvell,enable-port2", NULL))
		pdata->flags |= ENABLE_PORT2;
	if (of_get_property(np, "marvell,enable-port3", NULL))
		pdata->flags |= ENABLE_PORT3;
	if (of_get_property(np, "marvell,port-sense-low", NULL))
		pdata->flags |= POWER_SENSE_LOW;
	if (of_get_property(np, "marvell,power-control-low", NULL))
		pdata->flags |= POWER_CONTROL_LOW;
	if (of_get_property(np, "marvell,no-oc-protection", NULL))
		pdata->flags |= NO_OC_PROTECTION;
	if (of_get_property(np, "marvell,oc-mode-perport", NULL))
		pdata->flags |= OC_MODE_PERPORT;
	if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
		pdata->power_on_delay = tmp;
	if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
		pdata->port_mode = tmp;
	if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
		pdata->power_budget = tmp;

	pdev->dev.platform_data = pdata;

	return 0;
}
#else
static int ohci_pxa_of_init(struct platform_device *pdev)
{
	return 0;
}
#endif

/*-------------------------------------------------------------------------*/

/* configure so an HC device and id are always provided */
/* always called with process context; sleeping is OK */


/**
 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
 * Context: !in_interrupt()
 *
 * Allocates basic resources for this USB host controller, and
 * then invokes the start() method for the HCD associated with it
 * through the hotplug entry's driver_data.
 *
 */
int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
{
	int retval, irq;
	struct usb_hcd *hcd;
	struct pxaohci_platform_data *inf;
	struct pxa27x_ohci *pxa_ohci;
	struct ohci_hcd *ohci;
	struct resource *r;
	struct clk *usb_clk;

	retval = ohci_pxa_of_init(pdev);
	if (retval)
		return retval;

	inf = dev_get_platdata(&pdev->dev);

	if (!inf)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		pr_err("no resource of IORESOURCE_IRQ");
		return -ENXIO;
	}

	usb_clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(usb_clk))
		return PTR_ERR(usb_clk);

	hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
	if (!hcd) {
		retval = -ENOMEM;
		goto err0;
	}

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		pr_err("no resource of IORESOURCE_MEM");
		retval = -ENXIO;
		goto err1;
	}

	hcd->rsrc_start = r->start;
	hcd->rsrc_len = resource_size(r);

	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
		pr_debug("request_mem_region failed");
		retval = -EBUSY;
		goto err1;
	}

	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
	if (!hcd->regs) {
		pr_debug("ioremap failed");
		retval = -ENOMEM;
		goto err2;
	}

	/* initialize "struct pxa27x_ohci" */
	pxa_ohci = to_pxa27x_ohci(hcd);
	pxa_ohci->clk = usb_clk;
	pxa_ohci->mmio_base = (void __iomem *)hcd->regs;

	retval = pxa27x_start_hc(pxa_ohci, &pdev->dev);
	if (retval < 0) {
		pr_debug("pxa27x_start_hc failed");
		goto err3;
	}

	/* Select Power Management Mode */
	pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);

	if (inf->power_budget)
		hcd->power_budget = inf->power_budget;

	/* The value of NDP in roothub_a is incorrect on this hardware */
	ohci = hcd_to_ohci(hcd);
	ohci->num_ports = 3;

	retval = usb_add_hcd(hcd, irq, 0);
	if (retval == 0)
		return retval;

	pxa27x_stop_hc(pxa_ohci, &pdev->dev);
 err3:
	iounmap(hcd->regs);
 err2:
	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 err1:
	usb_put_hcd(hcd);
 err0:
	clk_put(usb_clk);
	return retval;
}


/* may be called without controller electrically present */
/* may be called with controller, bus, and devices active */

/**
 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
 * @dev: USB Host Controller being removed
 * Context: !in_interrupt()
 *
 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
 * the HCD's stop() method.  It is always called from a thread
 * context, normally "rmmod", "apmd", or something similar.
 *
 */
void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
{
	struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);

	usb_remove_hcd(hcd);
	pxa27x_stop_hc(pxa_ohci, &pdev->dev);
	iounmap(hcd->regs);
	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	clk_put(pxa_ohci->clk);
	usb_put_hcd(hcd);
}

/*-------------------------------------------------------------------------*/

static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
{
	pr_debug ("In ohci_hcd_pxa27x_drv_probe");

	if (usb_disabled())
		return -ENODEV;

	return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
}

static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
{
	struct usb_hcd *hcd = platform_get_drvdata(pdev);

	usb_hcd_pxa27x_remove(hcd, pdev);
	return 0;
}

#ifdef CONFIG_PM
static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
{
	struct usb_hcd *hcd = dev_get_drvdata(dev);
	struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
	bool do_wakeup = device_may_wakeup(dev);
	int ret;


	if (time_before(jiffies, ohci->next_statechange))
		msleep(5);
	ohci->next_statechange = jiffies;

	ret = ohci_suspend(hcd, do_wakeup);
	if (ret)
		return ret;

	pxa27x_stop_hc(pxa_ohci, dev);
	return ret;
}

static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
{
	struct usb_hcd *hcd = dev_get_drvdata(dev);
	struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
	struct pxaohci_platform_data *inf = dev_get_platdata(dev);
	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
	int status;

	if (time_before(jiffies, ohci->next_statechange))
		msleep(5);
	ohci->next_statechange = jiffies;

	status = pxa27x_start_hc(pxa_ohci, dev);
	if (status < 0)
		return status;

	/* Select Power Management Mode */
	pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);

	ohci_resume(hcd, false);
	return 0;
}

static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
	.suspend	= ohci_hcd_pxa27x_drv_suspend,
	.resume		= ohci_hcd_pxa27x_drv_resume,
};
#endif

static struct platform_driver ohci_hcd_pxa27x_driver = {
	.probe		= ohci_hcd_pxa27x_drv_probe,
	.remove		= ohci_hcd_pxa27x_drv_remove,
	.shutdown	= usb_hcd_platform_shutdown,
	.driver		= {
		.name	= "pxa27x-ohci",
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(pxa_ohci_dt_ids),
#ifdef CONFIG_PM
		.pm	= &ohci_hcd_pxa27x_pm_ops,
#endif
	},
};

static const struct ohci_driver_overrides pxa27x_overrides __initconst = {
	.extra_priv_size =      sizeof(struct pxa27x_ohci),
};

static int __init ohci_pxa27x_init(void)
{
	if (usb_disabled())
		return -ENODEV;

	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
	ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides);
	return platform_driver_register(&ohci_hcd_pxa27x_driver);
}
module_init(ohci_pxa27x_init);

static void __exit ohci_pxa27x_cleanup(void)
{
	platform_driver_unregister(&ohci_hcd_pxa27x_driver);
}
module_exit(ohci_pxa27x_cleanup);

MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pxa27x-ohci");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* OHCI HCD (Host Controller Driver) for USB.
	3	*
	4	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
	5	* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
	6	* (C) Copyright 2002 Hewlett-Packard Company
	7	*
	8	* Bus Glue for pxa27x
	9	*
	10	* Written by Christopher Hoover <ch@hpl.hp.com>
	11	* Based on fragments of previous driver by Russell King et al.
	12	*
	13	* Modified for LH7A404 from ohci-sa1111.c
	14	* by Durgesh Pattamatta <pattamattad@sharpsec.com>
	15	*
	16	* Modified for pxa27x from ohci-lh7a404.c
	17	* by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
	18	*
	19	* This file is licenced under the GPL.
	20	*/
	21
a8bcf410	22	#include <linux/clk.h>
b8ad5c37	23	#include <linux/device.h>
9876388e	24	#include <linux/dma-mapping.h>
b8ad5c37 MG	25	#include <linux/io.h>
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
1139b451 DM	28	#include <linux/of_platform.h>
1139b451 DM	29	#include <linux/of_gpio.h>
293b2da1 AB	30	#include <linux/platform_data/usb-ohci-pxa27x.h>
293b2da1 AB	31	#include <linux/platform_data/usb-pxa3xx-ulpi.h>
b8ad5c37 MG	32	#include <linux/platform_device.h>
	33	#include <linux/signal.h>
	34	#include <linux/usb.h>
	35	#include <linux/usb/hcd.h>
	36	#include <linux/usb/otg.h>
	37
	38	#include <mach/hardware.h>
	39
	40	#include "ohci.h"
	41
	42	#define DRIVER_DESC "OHCI PXA27x/PXA3x driver"
1da177e4	43
596050bc EM	44	/*
	45	* UHC: USB Host Controller (OHCI-like) register definitions
	46	*/
0c392ed9 EM	47	#define UHCREV (0x0000) /* UHC HCI Spec Revision */
	48	#define UHCHCON (0x0004) /* UHC Host Control Register */
	49	#define UHCCOMS (0x0008) /* UHC Command Status Register */
	50	#define UHCINTS (0x000C) /* UHC Interrupt Status Register */
	51	#define UHCINTE (0x0010) /* UHC Interrupt Enable */
	52	#define UHCINTD (0x0014) /* UHC Interrupt Disable */
	53	#define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
	54	#define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
	55	#define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
	56	#define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
	57	#define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
	58	#define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
	59	#define UHCDHEAD (0x0030) /* UHC Done Head */
	60	#define UHCFMI (0x0034) /* UHC Frame Interval */
	61	#define UHCFMR (0x0038) /* UHC Frame Remaining */
	62	#define UHCFMN (0x003C) /* UHC Frame Number */
	63	#define UHCPERS (0x0040) /* UHC Periodic Start */
	64	#define UHCLS (0x0044) /* UHC Low Speed Threshold */
	65
	66	#define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
596050bc EM	67	#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
	68	#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
	69	#define UHCRHDA_POTPGT(x) \
	70	(((x) & 0xff) << 24) /* Power On To Power Good Time */
	71
0c392ed9 EM	72	#define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
	73	#define UHCRHS (0x0050) /* UHC Root Hub Status */
	74	#define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
	75	#define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
	76	#define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
596050bc	77
0c392ed9	78	#define UHCSTAT (0x0060) /* UHC Status Register */
596050bc EM	79	#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
	80	#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
	81	#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
	82	#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
	83	#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
	84	#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
	85	#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
	86	#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
	87	#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
	88
0c392ed9	89	#define UHCHR (0x0064) /* UHC Reset Register */
596050bc EM	90	#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
	91	#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
	92	#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
	93	#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
	94	#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
	95	#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
	96	#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
	97	#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
	98	#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
	99	#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
	100	#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
	101
0c392ed9	102	#define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
596050bc EM	103	#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
	104	#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
	105	#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
	106	#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
	107	#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
	108	Interrupt Enable*/
	109	#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
	110	#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
	111
0c392ed9	112	#define UHCHIT (0x006C) /* UHC Interrupt Test register */
596050bc	113
1da177e4 LT	114	#define PXA_UHC_MAX_PORTNUM 3
1da177e4 LT	115
b8ad5c37	116	static const char hcd_name[] = "ohci-pxa27x";
1da177e4	117
b8ad5c37 MG	118	static struct hc_driver __read_mostly ohci_pxa27x_hc_driver;
	119
	120	struct pxa27x_ohci {
0c392ed9 EM	121	struct clk *clk;
	122	void __iomem *mmio_base;
	123	};
	124
b8ad5c37	125	#define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv)
a8bcf410	126
1da177e4 LT	127	/*
	128	PMM_NPS_MODE -- PMM Non-power switching mode
	129	Ports are powered continuously.
	130
	131	PMM_GLOBAL_MODE -- PMM global switching mode
	132	All ports are powered at the same time.
	133
	134	PMM_PERPORT_MODE -- PMM per port switching mode
	135	Ports are powered individually.
	136	*/
b8ad5c37	137	static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode)
1da177e4	138	{
b8ad5c37 MG	139	uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
b8ad5c37 MG	140	uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
0c392ed9 EM	141
0c392ed9 EM	142	switch (mode) {
1da177e4	143	case PMM_NPS_MODE:
0c392ed9	144	uhcrhda \|= RH_A_NPS;
dd9048af	145	break;
1da177e4	146	case PMM_GLOBAL_MODE:
0c392ed9	147	uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
1da177e4 LT	148	break;
1da177e4 LT	149	case PMM_PERPORT_MODE:
0c392ed9 EM	150	uhcrhda &= ~(RH_A_NPS);
0c392ed9 EM	151	uhcrhda \|= RH_A_PSM;
1da177e4 LT	152
1da177e4 LT	153	/* Set port power control mask bits, only 3 ports. */
0c392ed9	154	uhcrhdb \|= (0x7<<17);
1da177e4 LT	155	break;
	156	default:
	157	printk( KERN_ERR
dd9048af	158	"Invalid mode %d, set to non-power switch mode.\n",
1da177e4 LT	159	mode );
1da177e4 LT	160
0c392ed9	161	uhcrhda \|= RH_A_NPS;
1da177e4 LT	162	}
1da177e4 LT	163
b8ad5c37 MG	164	__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
b8ad5c37 MG	165	__raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
1da177e4 LT	166	return 0;
	167	}
	168
1da177e4 LT	169	/-------------------------------------------------------------------------/
1da177e4 LT	170
b8ad5c37	171	static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci,
0c392ed9	172	struct pxaohci_platform_data *inf)
097b5334	173	{
b8ad5c37 MG	174	uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
b8ad5c37 MG	175	uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
097b5334 EM	176
	177	if (inf->flags & ENABLE_PORT1)
	178	uhchr &= ~UHCHR_SSEP1;
	179
	180	if (inf->flags & ENABLE_PORT2)
	181	uhchr &= ~UHCHR_SSEP2;
	182
	183	if (inf->flags & ENABLE_PORT3)
	184	uhchr &= ~UHCHR_SSEP3;
	185
	186	if (inf->flags & POWER_CONTROL_LOW)
	187	uhchr \|= UHCHR_PCPL;
	188
	189	if (inf->flags & POWER_SENSE_LOW)
	190	uhchr \|= UHCHR_PSPL;
	191
	192	if (inf->flags & NO_OC_PROTECTION)
	193	uhcrhda \|= UHCRHDA_NOCP;
7b4361f0 AB	194	else
7b4361f0 AB	195	uhcrhda &= ~UHCRHDA_NOCP;
097b5334 EM	196
	197	if (inf->flags & OC_MODE_PERPORT)
	198	uhcrhda \|= UHCRHDA_OCPM;
7b4361f0 AB	199	else
7b4361f0 AB	200	uhcrhda &= ~UHCRHDA_OCPM;
097b5334 EM	201
	202	if (inf->power_on_delay) {
	203	uhcrhda &= ~UHCRHDA_POTPGT(0xff);
	204	uhcrhda \|= UHCRHDA_POTPGT(inf->power_on_delay / 2);
	205	}
	206
b8ad5c37 MG	207	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
b8ad5c37 MG	208	__raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
0c392ed9 EM	209	}
0c392ed9 EM	210
b8ad5c37	211	static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci)
0c392ed9	212	{
b8ad5c37	213	uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
0c392ed9	214
b8ad5c37	215	__raw_writel(uhchr \| UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
0c392ed9	216	udelay(11);
b8ad5c37	217	__raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
097b5334 EM	218	}
097b5334 EM	219
59376cc3	220	#ifdef CONFIG_PXA27x
0cb0b0d3 EM	221	extern void pxa27x_clear_otgph(void);
	222	#else
	223	#define pxa27x_clear_otgph() do {} while (0)
	224	#endif
	225
b8ad5c37	226	static int pxa27x_start_hc(struct pxa27x_ohci pxa_ohci, struct device dev)
1da177e4	227	{
81f280e2 RP	228	int retval = 0;
81f280e2 RP	229	struct pxaohci_platform_data *inf;
0c392ed9	230	uint32_t uhchr;
b8ad5c37	231	struct usb_hcd *hcd = dev_get_drvdata(dev);
81f280e2	232
d4f09e28	233	inf = dev_get_platdata(dev);
81f280e2	234
b8ad5c37	235	clk_prepare_enable(pxa_ohci->clk);
1da177e4	236
b8ad5c37	237	pxa27x_reset_hc(pxa_ohci);
1da177e4	238
b8ad5c37 MG	239	uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) \| UHCHR_FSBIR;
b8ad5c37 MG	240	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
0c392ed9	241
b8ad5c37	242	while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
1da177e4 LT	243	cpu_relax();
1da177e4 LT	244
b8ad5c37	245	pxa27x_setup_hc(pxa_ohci, inf);
097b5334	246
81f280e2 RP	247	if (inf->init)
81f280e2 RP	248	retval = inf->init(dev);
155faf5e	249
81f280e2 RP	250	if (retval < 0)
81f280e2 RP	251	return retval;
1da177e4	252
6dc3ae84	253	if (cpu_is_pxa3xx())
b8ad5c37	254	pxa3xx_u2d_start_hc(&hcd->self);
6dc3ae84	255
b8ad5c37 MG	256	uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
	257	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
	258	__raw_writel(UHCHIE_UPRIE \| UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
155faf5e DB	259
155faf5e DB	260	/* Clear any OTG Pin Hold */
0cb0b0d3	261	pxa27x_clear_otgph();
81f280e2	262	return 0;
1da177e4 LT	263	}
1da177e4 LT	264
b8ad5c37	265	static void pxa27x_stop_hc(struct pxa27x_ohci pxa_ohci, struct device dev)
1da177e4	266	{
81f280e2	267	struct pxaohci_platform_data *inf;
b8ad5c37	268	struct usb_hcd *hcd = dev_get_drvdata(dev);
0c392ed9	269	uint32_t uhccoms;
81f280e2	270
d4f09e28	271	inf = dev_get_platdata(dev);
81f280e2	272
6dc3ae84	273	if (cpu_is_pxa3xx())
b8ad5c37	274	pxa3xx_u2d_stop_hc(&hcd->self);
6dc3ae84	275
81f280e2 RP	276	if (inf->exit)
	277	inf->exit(dev);
	278
b8ad5c37	279	pxa27x_reset_hc(pxa_ohci);
1da177e4	280
0c392ed9	281	/* Host Controller Reset */
b8ad5c37 MG	282	uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) \| 0x01;
b8ad5c37 MG	283	__raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
1da177e4 LT	284	udelay(10);
1da177e4 LT	285
b8ad5c37	286	clk_disable_unprepare(pxa_ohci->clk);
1da177e4 LT	287	}
1da177e4 LT	288
1139b451 DM	289	#ifdef CONFIG_OF
	290	static const struct of_device_id pxa_ohci_dt_ids[] = {
	291	{ .compatible = "marvell,pxa-ohci" },
	292	{ }
	293	};
	294
	295	MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
	296
41ac7b3a	297	static int ohci_pxa_of_init(struct platform_device *pdev)
1139b451 DM	298	{
	299	struct device_node *np = pdev->dev.of_node;
	300	struct pxaohci_platform_data *pdata;
	301	u32 tmp;
22d9d8e8	302	int ret;
1139b451 DM	303
	304	if (!np)
	305	return 0;
	306
	307	/* Right now device-tree probed devices don't get dma_mask set.
	308	* Since shared usb code relies on it, set it here for now.
	309	* Once we have dma capability bindings this can go away.
	310	*/
e1fd7341	311	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
22d9d8e8 RK	312	if (ret)
22d9d8e8 RK	313	return ret;
1139b451 DM	314
	315	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	316	if (!pdata)
	317	return -ENOMEM;
	318
	319	if (of_get_property(np, "marvell,enable-port1", NULL))
	320	pdata->flags \|= ENABLE_PORT1;
	321	if (of_get_property(np, "marvell,enable-port2", NULL))
	322	pdata->flags \|= ENABLE_PORT2;
	323	if (of_get_property(np, "marvell,enable-port3", NULL))
	324	pdata->flags \|= ENABLE_PORT3;
	325	if (of_get_property(np, "marvell,port-sense-low", NULL))
	326	pdata->flags \|= POWER_SENSE_LOW;
	327	if (of_get_property(np, "marvell,power-control-low", NULL))
	328	pdata->flags \|= POWER_CONTROL_LOW;
	329	if (of_get_property(np, "marvell,no-oc-protection", NULL))
	330	pdata->flags \|= NO_OC_PROTECTION;
	331	if (of_get_property(np, "marvell,oc-mode-perport", NULL))
	332	pdata->flags \|= OC_MODE_PERPORT;
	333	if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
	334	pdata->power_on_delay = tmp;
	335	if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
	336	pdata->port_mode = tmp;
	337	if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
	338	pdata->power_budget = tmp;
	339
	340	pdev->dev.platform_data = pdata;
	341
	342	return 0;
	343	}
	344	#else
41ac7b3a	345	static int ohci_pxa_of_init(struct platform_device *pdev)
1139b451 DM	346	{
	347	return 0;
	348	}
	349	#endif
1da177e4 LT	350
	351	/-------------------------------------------------------------------------/
	352
	353	/* configure so an HC device and id are always provided */
	354	/* always called with process context; sleeping is OK */
	355
	356
	357	/**
	358	* usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
	359	* Context: !in_interrupt()
	360	*
	361	* Allocates basic resources for this USB host controller, and
	362	* then invokes the start() method for the HCD associated with it
	363	* through the hotplug entry's driver_data.
	364	*
	365	*/
81f280e2	366	int usb_hcd_pxa27x_probe (const struct hc_driver driver, struct platform_device pdev)
1da177e4	367	{
84bab739	368	int retval, irq;
1da177e4	369	struct usb_hcd *hcd;
81f280e2	370	struct pxaohci_platform_data *inf;
b8ad5c37 MG	371	struct pxa27x_ohci *pxa_ohci;
b8ad5c37 MG	372	struct ohci_hcd *ohci;
84bab739	373	struct resource *r;
0c392ed9	374	struct clk *usb_clk;
81f280e2	375
1139b451 DM	376	retval = ohci_pxa_of_init(pdev);
	377	if (retval)
	378	return retval;
	379
d4f09e28	380	inf = dev_get_platdata(&pdev->dev);
1da177e4	381
81f280e2 RP	382	if (!inf)
	383	return -ENODEV;
	384
84bab739 EM	385	irq = platform_get_irq(pdev, 0);
	386	if (irq < 0) {
	387	pr_err("no resource of IORESOURCE_IRQ");
	388	return -ENXIO;
1da177e4 LT	389	}
1da177e4 LT	390
e0d8b13a	391	usb_clk = clk_get(&pdev->dev, NULL);
a8bcf410	392	if (IS_ERR(usb_clk))
	393	return PTR_ERR(usb_clk);
	394
81f280e2	395	hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
7febe2be JL	396	if (!hcd) {
	397	retval = -ENOMEM;
	398	goto err0;
	399	}
84bab739 EM	400
	401	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	402	if (!r) {
	403	pr_err("no resource of IORESOURCE_MEM");
	404	retval = -ENXIO;
	405	goto err1;
	406	}
	407
	408	hcd->rsrc_start = r->start;
	409	hcd->rsrc_len = resource_size(r);
1da177e4 LT	410
	411	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
	412	pr_debug("request_mem_region failed");
	413	retval = -EBUSY;
	414	goto err1;
	415	}
	416
	417	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
	418	if (!hcd->regs) {
	419	pr_debug("ioremap failed");
	420	retval = -ENOMEM;
	421	goto err2;
	422	}
	423
0c392ed9	424	/* initialize "struct pxa27x_ohci" */
b8ad5c37 MG	425	pxa_ohci = to_pxa27x_ohci(hcd);
	426	pxa_ohci->clk = usb_clk;
	427	pxa_ohci->mmio_base = (void __iomem *)hcd->regs;
0c392ed9	428
b8ad5c37 MG	429	retval = pxa27x_start_hc(pxa_ohci, &pdev->dev);
b8ad5c37 MG	430	if (retval < 0) {
81f280e2 RP	431	pr_debug("pxa27x_start_hc failed");
	432	goto err3;
	433	}
1da177e4 LT	434
1da177e4 LT	435	/* Select Power Management Mode */
b8ad5c37	436	pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
1da177e4	437
0c27c5d5 RP	438	if (inf->power_budget)
	439	hcd->power_budget = inf->power_budget;
	440
b8ad5c37 MG	441	/* The value of NDP in roothub_a is incorrect on this hardware */
	442	ohci = hcd_to_ohci(hcd);
	443	ohci->num_ports = 3;
1da177e4	444
b5dd18d8	445	retval = usb_add_hcd(hcd, irq, 0);
1da177e4 LT	446	if (retval == 0)
	447	return retval;
	448
b8ad5c37	449	pxa27x_stop_hc(pxa_ohci, &pdev->dev);
81f280e2	450	err3:
1da177e4 LT	451	iounmap(hcd->regs);
	452	err2:
	453	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	454	err1:
	455	usb_put_hcd(hcd);
7febe2be	456	err0:
a8bcf410	457	clk_put(usb_clk);
1da177e4 LT	458	return retval;
	459	}
	460
	461
	462	/* may be called without controller electrically present */
	463	/* may be called with controller, bus, and devices active */
	464
	465	/**
	466	* usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
	467	* @dev: USB Host Controller being removed
	468	* Context: !in_interrupt()
	469	*
	470	* Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
	471	* the HCD's stop() method. It is always called from a thread
	472	* context, normally "rmmod", "apmd", or something similar.
	473	*
	474	*/
81f280e2	475	void usb_hcd_pxa27x_remove (struct usb_hcd hcd, struct platform_device pdev)
1da177e4	476	{
b8ad5c37	477	struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
0c392ed9	478
1da177e4	479	usb_remove_hcd(hcd);
b8ad5c37	480	pxa27x_stop_hc(pxa_ohci, &pdev->dev);
1da177e4 LT	481	iounmap(hcd->regs);
1da177e4 LT	482	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
b8ad5c37	483	clk_put(pxa_ohci->clk);
1da177e4	484	usb_put_hcd(hcd);
1da177e4 LT	485	}
	486
	487	/-------------------------------------------------------------------------/
	488
3ae5eaec	489	static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
1da177e4	490	{
1da177e4 LT	491	pr_debug ("In ohci_hcd_pxa27x_drv_probe");
	492
	493	if (usb_disabled())
	494	return -ENODEV;
	495
81f280e2	496	return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
1da177e4 LT	497	}
1da177e4 LT	498
3ae5eaec	499	static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
1da177e4	500	{
3ae5eaec	501	struct usb_hcd *hcd = platform_get_drvdata(pdev);
1da177e4 LT	502
	503	usb_hcd_pxa27x_remove(hcd, pdev);
	504	return 0;
	505	}
	506
b7f3f59b MR	507	#ifdef CONFIG_PM
b7f3f59b MR	508	static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
1da177e4	509	{
b7f3f59b	510	struct usb_hcd *hcd = dev_get_drvdata(dev);
b8ad5c37 MG	511	struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
b8ad5c37 MG	512	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
4ceaa893 MG	513	bool do_wakeup = device_may_wakeup(dev);
	514	int ret;
	515
2e1dcc16	516
b8ad5c37	517	if (time_before(jiffies, ohci->next_statechange))
2e1dcc16	518	msleep(5);
b8ad5c37	519	ohci->next_statechange = jiffies;
2e1dcc16	520
4ceaa893 MG	521	ret = ohci_suspend(hcd, do_wakeup);
	522	if (ret)
	523	return ret;
	524
b8ad5c37	525	pxa27x_stop_hc(pxa_ohci, dev);
4ceaa893	526	return ret;
1da177e4 LT	527	}
1da177e4 LT	528
b7f3f59b	529	static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
1da177e4	530	{
b7f3f59b	531	struct usb_hcd *hcd = dev_get_drvdata(dev);
b8ad5c37	532	struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
d4f09e28	533	struct pxaohci_platform_data *inf = dev_get_platdata(dev);
b8ad5c37	534	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
2e1dcc16 RP	535	int status;
2e1dcc16 RP	536
b8ad5c37	537	if (time_before(jiffies, ohci->next_statechange))
2e1dcc16	538	msleep(5);
b8ad5c37	539	ohci->next_statechange = jiffies;
2e1dcc16	540
b8ad5c37 MG	541	status = pxa27x_start_hc(pxa_ohci, dev);
b8ad5c37 MG	542	if (status < 0)
2e1dcc16 RP	543	return status;
2e1dcc16 RP	544
a75d048e	545	/* Select Power Management Mode */
b8ad5c37	546	pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
a75d048e	547
cfa49b4b	548	ohci_resume(hcd, false);
1da177e4 LT	549	return 0;
1da177e4 LT	550	}
b7f3f59b	551
47145210	552	static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
b7f3f59b MR	553	.suspend = ohci_hcd_pxa27x_drv_suspend,
	554	.resume = ohci_hcd_pxa27x_drv_resume,
	555	};
2e1dcc16	556	#endif
1da177e4	557
3ae5eaec	558	static struct platform_driver ohci_hcd_pxa27x_driver = {
1da177e4 LT	559	.probe = ohci_hcd_pxa27x_drv_probe,
1da177e4 LT	560	.remove = ohci_hcd_pxa27x_drv_remove,
dd9048af	561	.shutdown = usb_hcd_platform_shutdown,
3ae5eaec RK	562	.driver = {
3ae5eaec RK	563	.name = "pxa27x-ohci",
f4fce61d	564	.owner = THIS_MODULE,
1139b451	565	.of_match_table = of_match_ptr(pxa_ohci_dt_ids),
b7f3f59b MR	566	#ifdef CONFIG_PM
	567	.pm = &ohci_hcd_pxa27x_pm_ops,
	568	#endif
3ae5eaec	569	},
1da177e4 LT	570	};
1da177e4 LT	571
b8ad5c37 MG	572	static const struct ohci_driver_overrides pxa27x_overrides __initconst = {
	573	.extra_priv_size = sizeof(struct pxa27x_ohci),
	574	};
	575
	576	static int __init ohci_pxa27x_init(void)
	577	{
	578	if (usb_disabled())
	579	return -ENODEV;
	580
	581	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
	582	ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides);
	583	return platform_driver_register(&ohci_hcd_pxa27x_driver);
	584	}
	585	module_init(ohci_pxa27x_init);
	586
	587	static void __exit ohci_pxa27x_cleanup(void)
	588	{
	589	platform_driver_unregister(&ohci_hcd_pxa27x_driver);
	590	}
	591	module_exit(ohci_pxa27x_cleanup);
	592
	593	MODULE_DESCRIPTION(DRIVER_DESC);
	594	MODULE_LICENSE("GPL");
	595	MODULE_ALIAS("platform:pxa27x-ohci");