[linux-block.git] / drivers / usb / host / ohci-pci.c

/*
 * OHCI HCD (Host Controller Driver) for USB.
 *
 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
 *
 * [ Initialisation is based on Linus'  ]
 * [ uhci code and gregs ohci fragments ]
 * [ (C) Copyright 1999 Linus Torvalds  ]
 * [ (C) Copyright 1999 Gregory P. Smith]
 *
 * PCI Bus Glue
 *
 * This file is licenced under the GPL.
 */

#ifndef CONFIG_PCI
#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
#endif

/*-------------------------------------------------------------------------*/

static int broken_suspend(struct usb_hcd *hcd)
{
	device_init_wakeup(&hcd->self.root_hub->dev, 0);
	return 0;
}

/* AMD 756, for most chips (early revs), corrupts register
 * values on read ... so enable the vendor workaround.
 */
static int ohci_quirk_amd756(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

	ohci->flags = OHCI_QUIRK_AMD756;
	ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");

	/* also erratum 10 (suspend/resume issues) */
	return broken_suspend(hcd);
}

/* Apple's OHCI driver has a lot of bizarre workarounds
 * for this chip.  Evidently control and bulk lists
 * can get confused.  (B&W G3 models, and ...)
 */
static int ohci_quirk_opti(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

	ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");

	return 0;
}

/* Check for NSC87560. We have to look at the bridge (fn1) to
 * identify the USB (fn2). This quirk might apply to more or
 * even all NSC stuff.
 */
static int ohci_quirk_ns(struct usb_hcd *hcd)
{
	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	struct pci_dev	*b;

	b  = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
	if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
	    && b->vendor == PCI_VENDOR_ID_NS) {
		struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

		ohci->flags |= OHCI_QUIRK_SUPERIO;
		ohci_dbg (ohci, "Using NSC SuperIO setup\n");
	}
	pci_dev_put(b);

	return 0;
}

/* Check for Compaq's ZFMicro chipset, which needs short
 * delays before control or bulk queues get re-activated
 * in finish_unlinks()
 */
static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

	ohci->flags |= OHCI_QUIRK_ZFMICRO;
	ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");

	return 0;
}

/* Check for Toshiba SCC OHCI which has big endian registers
 * and little endian in memory data structures
 */
static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

	/* That chip is only present in the southbridge of some
	 * cell based platforms which are supposed to select
	 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
	 * that was the case though.
	 */
#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
	ohci->flags |= OHCI_QUIRK_BE_MMIO;
	ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
	return 0;
#else
	ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
	return -ENXIO;
#endif
}

/* Check for NEC chip and apply quirk for allegedly lost interrupts.
 */

static void ohci_quirk_nec_worker(struct work_struct *work)
{
	struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
	int status;

	status = ohci_init(ohci);
	if (status != 0) {
		ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
			 "ohci_init", status);
		return;
	}

	status = ohci_restart(ohci);
	if (status != 0)
		ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
			 "ohci_restart", status);
}

static int ohci_quirk_nec(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

	ohci->flags |= OHCI_QUIRK_NEC;
	INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
	ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");

	return 0;
}

/* List of quirks for OHCI */
static const struct pci_device_id ohci_pci_quirks[] = {
	{
		PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
		.driver_data = (unsigned long)ohci_quirk_amd756,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
		.driver_data = (unsigned long)ohci_quirk_opti,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
		.driver_data = (unsigned long)ohci_quirk_ns,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
		.driver_data = (unsigned long)ohci_quirk_zfmicro,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
		.driver_data = (unsigned long)ohci_quirk_toshiba_scc,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
		.driver_data = (unsigned long)ohci_quirk_nec,
	},
	{
		/* Toshiba portege 4000 */
		.vendor		= PCI_VENDOR_ID_AL,
		.device		= 0x5237,
		.subvendor	= PCI_VENDOR_ID_TOSHIBA,
		.subdevice	= 0x0004,
		.driver_data	= (unsigned long) broken_suspend,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
		.driver_data = (unsigned long) broken_suspend,
	},
	/* FIXME for some of the early AMD 760 southbridges, OHCI
	 * won't work at all.  blacklist them.
	 */

	{},
};

static int ohci_pci_reset (struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
	int ret = 0;

	if (hcd->self.controller) {
		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
		const struct pci_device_id *quirk_id;

		quirk_id = pci_match_id(ohci_pci_quirks, pdev);
		if (quirk_id != NULL) {
			int (*quirk)(struct usb_hcd *ohci);
			quirk = (void *)quirk_id->driver_data;
			ret = quirk(hcd);
		}
	}
	if (ret == 0) {
		ohci_hcd_init (ohci);
		return ohci_init (ohci);
	}
	return ret;
}


static int __devinit ohci_pci_start (struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
	int		ret;

#ifdef CONFIG_PM /* avoid warnings about unused pdev */
	if (hcd->self.controller) {
		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);

		/* RWC may not be set for add-in PCI cards, since boot
		 * firmware probably ignored them.  This transfers PCI
		 * PM wakeup capabilities (once the PCI layer is fixed).
		 */
		if (device_may_wakeup(&pdev->dev))
			ohci->hc_control |= OHCI_CTRL_RWC;
	}
#endif /* CONFIG_PM */

	ret = ohci_run (ohci);
	if (ret < 0) {
		ohci_err (ohci, "can't start\n");
		ohci_stop (hcd);
	}
	return ret;
}

#ifdef	CONFIG_PM

static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
	unsigned long	flags;
	int		rc = 0;

	/* Root hub was already suspended. Disable irq emission and
	 * mark HW unaccessible, bail out if RH has been resumed. Use
	 * the spinlock to properly synchronize with possible pending
	 * RH suspend or resume activity.
	 *
	 * This is still racy as hcd->state is manipulated outside of
	 * any locks =P But that will be a different fix.
	 */
	spin_lock_irqsave (&ohci->lock, flags);
	if (hcd->state != HC_STATE_SUSPENDED) {
		rc = -EINVAL;
		goto bail;
	}
	ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
	(void)ohci_readl(ohci, &ohci->regs->intrdisable);

	/* make sure snapshot being resumed re-enumerates everything */
	if (message.event == PM_EVENT_PRETHAW)
		ohci_usb_reset(ohci);

	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 bail:
	spin_unlock_irqrestore (&ohci->lock, flags);

	return rc;
}


static int ohci_pci_resume (struct usb_hcd *hcd)
{
	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	ohci_finish_controller_resume(hcd);
	return 0;
}

#endif	/* CONFIG_PM */


/*-------------------------------------------------------------------------*/

static const struct hc_driver ohci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"OHCI Host Controller",
	.hcd_priv_size =	sizeof(struct ohci_hcd),

	/*
	 * generic hardware linkage
	 */
	.irq =			ohci_irq,
	.flags =		HCD_MEMORY | HCD_USB11,

	/*
	 * basic lifecycle operations
	 */
	.reset =		ohci_pci_reset,
	.start =		ohci_pci_start,
	.stop =			ohci_stop,
	.shutdown =		ohci_shutdown,

#ifdef	CONFIG_PM
	.pci_suspend =		ohci_pci_suspend,
	.pci_resume =		ohci_pci_resume,
#endif

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ohci_urb_enqueue,
	.urb_dequeue =		ohci_urb_dequeue,
	.endpoint_disable =	ohci_endpoint_disable,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ohci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ohci_hub_status_data,
	.hub_control =		ohci_hub_control,
	.hub_irq_enable =	ohci_rhsc_enable,
#ifdef	CONFIG_PM
	.bus_suspend =		ohci_bus_suspend,
	.bus_resume =		ohci_bus_resume,
#endif
	.start_port_reset =	ohci_start_port_reset,
};

/*-------------------------------------------------------------------------*/


static const struct pci_device_id pci_ids [] = { {
	/* handle any USB OHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
	.driver_data =	(unsigned long) &ohci_pci_hc_driver,
	}, { /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE (pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ohci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,

#ifdef	CONFIG_PM
	.suspend =	usb_hcd_pci_suspend,
	.resume =	usb_hcd_pci_resume,
#endif

	.shutdown =	usb_hcd_pci_shutdown,
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* OHCI HCD (Host Controller Driver) for USB.
	3	*
	4	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
	5	* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
dd9048af	6	*
1da177e4 LT	7	* [ Initialisation is based on Linus' ]
	8	* [ uhci code and gregs ohci fragments ]
	9	* [ (C) Copyright 1999 Linus Torvalds ]
	10	* [ (C) Copyright 1999 Gregory P. Smith]
dd9048af	11	*
1da177e4 LT	12	* PCI Bus Glue
	13	*
	14	* This file is licenced under the GPL.
	15	*/
dd9048af	16
1da177e4 LT	17	#ifndef CONFIG_PCI
	18	#error "This file is PCI bus glue. CONFIG_PCI must be defined."
	19	#endif
	20
	21	/-------------------------------------------------------------------------/
	22
931384fb DB	23	static int broken_suspend(struct usb_hcd *hcd)
	24	{
	25	device_init_wakeup(&hcd->self.root_hub->dev, 0);
	26	return 0;
	27	}
	28
4302a595 BH	29	/* AMD 756, for most chips (early revs), corrupts register
	30	* values on read ... so enable the vendor workaround.
	31	*/
931384fb	32	static int ohci_quirk_amd756(struct usb_hcd *hcd)
1da177e4 LT	33	{
	34	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	35
4302a595 BH	36	ohci->flags = OHCI_QUIRK_AMD756;
	37	ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
	38
	39	/* also erratum 10 (suspend/resume issues) */
931384fb	40	return broken_suspend(hcd);
1da177e4 LT	41	}
1da177e4 LT	42
4302a595 BH	43	/* Apple's OHCI driver has a lot of bizarre workarounds
	44	* for this chip. Evidently control and bulk lists
	45	* can get confused. (B&W G3 models, and ...)
	46	*/
931384fb	47	static int ohci_quirk_opti(struct usb_hcd *hcd)
1da177e4 LT	48	{
1da177e4 LT	49	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1da177e4	50
4302a595 BH	51	ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
	52
	53	return 0;
	54	}
	55
	56	/* Check for NSC87560. We have to look at the bridge (fn1) to
	57	* identify the USB (fn2). This quirk might apply to more or
	58	* even all NSC stuff.
	59	*/
931384fb	60	static int ohci_quirk_ns(struct usb_hcd *hcd)
4302a595 BH	61	{
	62	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	63	struct pci_dev *b;
	64
	65	b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
	66	if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
	67	&& b->vendor == PCI_VENDOR_ID_NS) {
	68	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	69
	70	ohci->flags \|= OHCI_QUIRK_SUPERIO;
	71	ohci_dbg (ohci, "Using NSC SuperIO setup\n");
	72	}
	73	pci_dev_put(b);
	74
	75	return 0;
	76	}
	77
	78	/* Check for Compaq's ZFMicro chipset, which needs short
	79	* delays before control or bulk queues get re-activated
	80	* in finish_unlinks()
	81	*/
931384fb	82	static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
4302a595 BH	83	{
	84	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	85
	86	ohci->flags \|= OHCI_QUIRK_ZFMICRO;
89a0fd18	87	ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");
4302a595 BH	88
	89	return 0;
	90	}
	91
11d1a4aa BH	92	/* Check for Toshiba SCC OHCI which has big endian registers
	93	* and little endian in memory data structures
	94	*/
931384fb	95	static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
11d1a4aa BH	96	{
	97	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	98
	99	/* That chip is only present in the southbridge of some
	100	* cell based platforms which are supposed to select
	101	* CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
	102	* that was the case though.
	103	*/
	104	#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
	105	ohci->flags \|= OHCI_QUIRK_BE_MMIO;
	106	ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
	107	return 0;
	108	#else
	109	ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
	110	return -ENXIO;
	111	#endif
	112	}
4302a595	113
d576bb9f MH	114	/* Check for NEC chip and apply quirk for allegedly lost interrupts.
d576bb9f MH	115	*/
89a0fd18 MN	116
	117	static void ohci_quirk_nec_worker(struct work_struct *work)
	118	{
	119	struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
	120	int status;
	121
	122	status = ohci_init(ohci);
	123	if (status != 0) {
	124	ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
	125	"ohci_init", status);
	126	return;
	127	}
	128
	129	status = ohci_restart(ohci);
	130	if (status != 0)
	131	ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
	132	"ohci_restart", status);
	133	}
	134
d576bb9f MH	135	static int ohci_quirk_nec(struct usb_hcd *hcd)
	136	{
	137	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	138
	139	ohci->flags \|= OHCI_QUIRK_NEC;
89a0fd18	140	INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
d576bb9f MH	141	ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");
	142
	143	return 0;
	144	}
	145
4302a595 BH	146	/* List of quirks for OHCI */
	147	static const struct pci_device_id ohci_pci_quirks[] = {
	148	{
	149	PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
	150	.driver_data = (unsigned long)ohci_quirk_amd756,
	151	},
	152	{
	153	PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
	154	.driver_data = (unsigned long)ohci_quirk_opti,
	155	},
	156	{
	157	PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
	158	.driver_data = (unsigned long)ohci_quirk_ns,
	159	},
	160	{
	161	PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
	162	.driver_data = (unsigned long)ohci_quirk_zfmicro,
	163	},
11d1a4aa BH	164	{
	165	PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
	166	.driver_data = (unsigned long)ohci_quirk_toshiba_scc,
	167	},
d576bb9f MH	168	{
	169	PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
	170	.driver_data = (unsigned long)ohci_quirk_nec,
	171	},
931384fb DB	172	{
	173	/* Toshiba portege 4000 */
	174	.vendor = PCI_VENDOR_ID_AL,
	175	.device = 0x5237,
8ab5e8c0	176	.subvendor = PCI_VENDOR_ID_TOSHIBA,
931384fb DB	177	.subdevice = 0x0004,
	178	.driver_data = (unsigned long) broken_suspend,
	179	},
33f73e56 RA	180	{
	181	PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
	182	.driver_data = (unsigned long) broken_suspend,
	183	},
4302a595 BH	184	/* FIXME for some of the early AMD 760 southbridges, OHCI
4302a595 BH	185	* won't work at all. blacklist them.
6a9062f3	186	*/
11d1a4aa	187
4302a595 BH	188	{},
	189	};
	190
	191	static int ohci_pci_reset (struct usb_hcd *hcd)
	192	{
	193	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	194	int ret = 0;
	195
6a9062f3	196	if (hcd->self.controller) {
1da177e4	197	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
4302a595	198	const struct pci_device_id *quirk_id;
1da177e4	199
4302a595 BH	200	quirk_id = pci_match_id(ohci_pci_quirks, pdev);
	201	if (quirk_id != NULL) {
	202	int (quirk)(struct usb_hcd ohci);
	203	quirk = (void *)quirk_id->driver_data;
	204	ret = quirk(hcd);
1da177e4	205	}
4302a595 BH	206	}
	207	if (ret == 0) {
	208	ohci_hcd_init (ohci);
	209	return ohci_init (ohci);
	210	}
	211	return ret;
	212	}
1da177e4	213
1da177e4	214
4302a595 BH	215	static int __devinit ohci_pci_start (struct usb_hcd *hcd)
	216	{
	217	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	218	int ret;
0e498763	219
4302a595 BH	220	#ifdef CONFIG_PM /* avoid warnings about unused pdev */
	221	if (hcd->self.controller) {
	222	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
6a9062f3 DB	223
	224	/* RWC may not be set for add-in PCI cards, since boot
	225	* firmware probably ignored them. This transfers PCI
	226	* PM wakeup capabilities (once the PCI layer is fixed).
	227	*/
	228	if (device_may_wakeup(&pdev->dev))
	229	ohci->hc_control \|= OHCI_CTRL_RWC;
1da177e4	230	}
4302a595	231	#endif /* CONFIG_PM */
1da177e4	232
4302a595 BH	233	ret = ohci_run (ohci);
4302a595 BH	234	if (ret < 0) {
1da177e4 LT	235	ohci_err (ohci, "can't start\n");
1da177e4 LT	236	ohci_stop (hcd);
1da177e4	237	}
4302a595	238	return ret;
1da177e4 LT	239	}
	240
	241	#ifdef CONFIG_PM
	242
9a5d3e98	243	static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
1da177e4	244	{
8de98402 BH	245	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	246	unsigned long flags;
	247	int rc = 0;
	248
	249	/* Root hub was already suspended. Disable irq emission and
	250	* mark HW unaccessible, bail out if RH has been resumed. Use
	251	* the spinlock to properly synchronize with possible pending
	252	* RH suspend or resume activity.
	253	*
	254	* This is still racy as hcd->state is manipulated outside of
	255	* any locks =P But that will be a different fix.
	256	*/
	257	spin_lock_irqsave (&ohci->lock, flags);
	258	if (hcd->state != HC_STATE_SUSPENDED) {
	259	rc = -EINVAL;
	260	goto bail;
	261	}
	262	ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
	263	(void)ohci_readl(ohci, &ohci->regs->intrdisable);
18584999 DB	264
	265	/* make sure snapshot being resumed re-enumerates everything */
	266	if (message.event == PM_EVENT_PRETHAW)
	267	ohci_usb_reset(ohci);
	268
8de98402 BH	269	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	270	bail:
	271	spin_unlock_irqrestore (&ohci->lock, flags);
	272
	273	return rc;
1da177e4 LT	274	}
	275
	276
	277	static int ohci_pci_resume (struct usb_hcd *hcd)
	278	{
8de98402	279	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
43bbb7e0	280	ohci_finish_controller_resume(hcd);
f197b2c5	281	return 0;
1da177e4 LT	282	}
	283
	284	#endif /* CONFIG_PM */
	285
	286
	287	/-------------------------------------------------------------------------/
	288
	289	static const struct hc_driver ohci_pci_hc_driver = {
	290	.description = hcd_name,
	291	.product_desc = "OHCI Host Controller",
	292	.hcd_priv_size = sizeof(struct ohci_hcd),
	293
	294	/*
	295	* generic hardware linkage
	296	*/
	297	.irq = ohci_irq,
	298	.flags = HCD_MEMORY \| HCD_USB11,
	299
	300	/*
	301	* basic lifecycle operations
	302	*/
	303	.reset = ohci_pci_reset,
	304	.start = ohci_pci_start,
d413984a	305	.stop = ohci_stop,
64a21d02	306	.shutdown = ohci_shutdown,
d413984a	307
1da177e4	308	#ifdef CONFIG_PM
7be7d741 AS	309	.pci_suspend = ohci_pci_suspend,
7be7d741 AS	310	.pci_resume = ohci_pci_resume,
1da177e4	311	#endif
1da177e4 LT	312
	313	/*
	314	* managing i/o requests and associated device resources
	315	*/
	316	.urb_enqueue = ohci_urb_enqueue,
	317	.urb_dequeue = ohci_urb_dequeue,
	318	.endpoint_disable = ohci_endpoint_disable,
	319
	320	/*
	321	* scheduling support
	322	*/
	323	.get_frame_number = ohci_get_frame,
	324
	325	/*
	326	* root hub support
	327	*/
	328	.hub_status_data = ohci_hub_status_data,
	329	.hub_control = ohci_hub_control,
09ca8adb	330	.hub_irq_enable = ohci_rhsc_enable,
8ad7fe16	331	#ifdef CONFIG_PM
0c0382e3 AS	332	.bus_suspend = ohci_bus_suspend,
0c0382e3 AS	333	.bus_resume = ohci_bus_resume,
1da177e4 LT	334	#endif
	335	.start_port_reset = ohci_start_port_reset,
	336	};
	337
	338	/-------------------------------------------------------------------------/
	339
	340
	341	static const struct pci_device_id pci_ids [] = { {
	342	/* handle any USB OHCI controller */
c67808ee	343	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
1da177e4 LT	344	.driver_data = (unsigned long) &ohci_pci_hc_driver,
	345	}, { /* end: all zeroes */ }
	346	};
	347	MODULE_DEVICE_TABLE (pci, pci_ids);
	348
	349	/* pci driver glue; this is a "new style" PCI driver module */
	350	static struct pci_driver ohci_pci_driver = {
	351	.name = (char *) hcd_name,
	352	.id_table = pci_ids,
	353
	354	.probe = usb_hcd_pci_probe,
	355	.remove = usb_hcd_pci_remove,
	356
	357	#ifdef CONFIG_PM
	358	.suspend = usb_hcd_pci_suspend,
	359	.resume = usb_hcd_pci_resume,
	360	#endif
64a21d02 AG	361
64a21d02 AG	362	.shutdown = usb_hcd_pci_shutdown,
1da177e4 LT	363	};
1da177e4 LT	364