[linux-block.git] / drivers / usb / host / ohci-pci.c

/*
 * OHCI HCD (Host Controller Driver) for USB.
 *
 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
 *
 * [ Initialisation is based on Linus'  ]
 * [ uhci code and gregs ohci fragments ]
 * [ (C) Copyright 1999 Linus Torvalds  ]
 * [ (C) Copyright 1999 Gregory P. Smith]
 *
 * PCI Bus Glue
 *
 * This file is licenced under the GPL.
 */

#ifndef CONFIG_PCI
#error "This file is PCI bus glue.  CONFIG_PCI must be defined."
#endif

#include <linux/pci.h>
#include <linux/io.h>


/* constants used to work around PM-related transfer
 * glitches in some AMD 700 series southbridges
 */
#define AB_REG_BAR	0xf0
#define AB_INDX(addr)	((addr) + 0x00)
#define AB_DATA(addr)	((addr) + 0x04)
#define AX_INDXC	0X30
#define AX_DATAC	0x34

#define NB_PCIE_INDX_ADDR	0xe0
#define NB_PCIE_INDX_DATA	0xe4
#define PCIE_P_CNTL		0x10040
#define BIF_NB			0x10002

static struct pci_dev *amd_smbus_dev;
static struct pci_dev *amd_hb_dev;
static int amd_ohci_iso_count;

/*-------------------------------------------------------------------------*/

static int broken_suspend(struct usb_hcd *hcd)
{
	device_init_wakeup(&hcd->self.root_hub->dev, 0);
	return 0;
}

/* AMD 756, for most chips (early revs), corrupts register
 * values on read ... so enable the vendor workaround.
 */
static int ohci_quirk_amd756(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

	ohci->flags = OHCI_QUIRK_AMD756;
	ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");

	/* also erratum 10 (suspend/resume issues) */
	return broken_suspend(hcd);
}

/* Apple's OHCI driver has a lot of bizarre workarounds
 * for this chip.  Evidently control and bulk lists
 * can get confused.  (B&W G3 models, and ...)
 */
static int ohci_quirk_opti(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

	ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");

	return 0;
}

/* Check for NSC87560. We have to look at the bridge (fn1) to
 * identify the USB (fn2). This quirk might apply to more or
 * even all NSC stuff.
 */
static int ohci_quirk_ns(struct usb_hcd *hcd)
{
	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	struct pci_dev	*b;

	b  = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
	if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
	    && b->vendor == PCI_VENDOR_ID_NS) {
		struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

		ohci->flags |= OHCI_QUIRK_SUPERIO;
		ohci_dbg (ohci, "Using NSC SuperIO setup\n");
	}
	pci_dev_put(b);

	return 0;
}

/* Check for Compaq's ZFMicro chipset, which needs short
 * delays before control or bulk queues get re-activated
 * in finish_unlinks()
 */
static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

	ohci->flags |= OHCI_QUIRK_ZFMICRO;
	ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");

	return 0;
}

/* Check for Toshiba SCC OHCI which has big endian registers
 * and little endian in memory data structures
 */
static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

	/* That chip is only present in the southbridge of some
	 * cell based platforms which are supposed to select
	 * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
	 * that was the case though.
	 */
#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
	ohci->flags |= OHCI_QUIRK_BE_MMIO;
	ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
	return 0;
#else
	ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
	return -ENXIO;
#endif
}

/* Check for NEC chip and apply quirk for allegedly lost interrupts.
 */

static void ohci_quirk_nec_worker(struct work_struct *work)
{
	struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
	int status;

	status = ohci_init(ohci);
	if (status != 0) {
		ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
			 "ohci_init", status);
		return;
	}

	status = ohci_restart(ohci);
	if (status != 0)
		ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
			 "ohci_restart", status);
}

static int ohci_quirk_nec(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);

	ohci->flags |= OHCI_QUIRK_NEC;
	INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
	ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");

	return 0;
}

static int ohci_quirk_amd700(struct usb_hcd *hcd)
{
	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
	u8 rev = 0;

	if (!amd_smbus_dev)
		amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
				PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
	if (!amd_smbus_dev)
		return 0;

	pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
	if ((rev > 0x3b) || (rev < 0x30)) {
		pci_dev_put(amd_smbus_dev);
		amd_smbus_dev = NULL;
		return 0;
	}

	amd_ohci_iso_count++;

	if (!amd_hb_dev)
		amd_hb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9600, NULL);

	ohci->flags |= OHCI_QUIRK_AMD_ISO;
	ohci_dbg(ohci, "enabled AMD ISO transfers quirk\n");

	return 0;
}

/*
 * The hardware normally enables the A-link power management feature, which
 * lets the system lower the power consumption in idle states.
 *
 * Assume the system is configured to have USB 1.1 ISO transfers going
 * to or from a USB device.  Without this quirk, that stream may stutter
 * or have breaks occasionally.  For transfers going to speakers, this
 * makes a very audible mess...
 *
 * That audio playback corruption is due to the audio stream getting
 * interrupted occasionally when the link goes in lower power state
 * This USB quirk prevents the link going into that lower power state
 * during audio playback or other ISO operations.
 */
static void quirk_amd_pll(int on)
{
	u32 addr;
	u32 val;
	u32 bit = (on > 0) ? 1 : 0;

	pci_read_config_dword(amd_smbus_dev, AB_REG_BAR, &addr);

	/* BIT names/meanings are NDA-protected, sorry ... */

	outl(AX_INDXC, AB_INDX(addr));
	outl(0x40, AB_DATA(addr));
	outl(AX_DATAC, AB_INDX(addr));
	val = inl(AB_DATA(addr));
	val &= ~((1 << 3) | (1 << 4) | (1 << 9));
	val |= (bit << 3) | ((!bit) << 4) | ((!bit) << 9);
	outl(val, AB_DATA(addr));

	if (amd_hb_dev) {
		addr = PCIE_P_CNTL;
		pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_ADDR, addr);

		pci_read_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, &val);
		val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
		val |= bit | (bit << 3) | (bit << 12);
		val |= ((!bit) << 4) | ((!bit) << 9);
		pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, val);

		addr = BIF_NB;
		pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_ADDR, addr);

		pci_read_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, &val);
		val &= ~(1 << 8);
		val |= bit << 8;
		pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, val);
	}
}

static void amd_iso_dev_put(void)
{
	amd_ohci_iso_count--;
	if (amd_ohci_iso_count == 0) {
		if (amd_smbus_dev) {
			pci_dev_put(amd_smbus_dev);
			amd_smbus_dev = NULL;
		}
		if (amd_hb_dev) {
			pci_dev_put(amd_hb_dev);
			amd_hb_dev = NULL;
		}
	}

}

/* List of quirks for OHCI */
static const struct pci_device_id ohci_pci_quirks[] = {
	{
		PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
		.driver_data = (unsigned long)ohci_quirk_amd756,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
		.driver_data = (unsigned long)ohci_quirk_opti,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
		.driver_data = (unsigned long)ohci_quirk_ns,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
		.driver_data = (unsigned long)ohci_quirk_zfmicro,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
		.driver_data = (unsigned long)ohci_quirk_toshiba_scc,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
		.driver_data = (unsigned long)ohci_quirk_nec,
	},
	{
		/* Toshiba portege 4000 */
		.vendor		= PCI_VENDOR_ID_AL,
		.device		= 0x5237,
		.subvendor	= PCI_VENDOR_ID_TOSHIBA,
		.subdevice	= 0x0004,
		.driver_data	= (unsigned long) broken_suspend,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
		.driver_data = (unsigned long) broken_suspend,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4397),
		.driver_data = (unsigned long)ohci_quirk_amd700,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4398),
		.driver_data = (unsigned long)ohci_quirk_amd700,
	},
	{
		PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399),
		.driver_data = (unsigned long)ohci_quirk_amd700,
	},

	/* FIXME for some of the early AMD 760 southbridges, OHCI
	 * won't work at all.  blacklist them.
	 */

	{},
};

static int ohci_pci_reset (struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
	int ret = 0;

	if (hcd->self.controller) {
		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
		const struct pci_device_id *quirk_id;

		quirk_id = pci_match_id(ohci_pci_quirks, pdev);
		if (quirk_id != NULL) {
			int (*quirk)(struct usb_hcd *ohci);
			quirk = (void *)quirk_id->driver_data;
			ret = quirk(hcd);
		}
	}
	if (ret == 0) {
		ohci_hcd_init (ohci);
		return ohci_init (ohci);
	}
	return ret;
}


static int __devinit ohci_pci_start (struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
	int		ret;

#ifdef CONFIG_PM /* avoid warnings about unused pdev */
	if (hcd->self.controller) {
		struct pci_dev *pdev = to_pci_dev(hcd->self.controller);

		/* RWC may not be set for add-in PCI cards, since boot
		 * firmware probably ignored them.  This transfers PCI
		 * PM wakeup capabilities.
		 */
		if (device_can_wakeup(&pdev->dev))
			ohci->hc_control |= OHCI_CTRL_RWC;
	}
#endif /* CONFIG_PM */

	ret = ohci_run (ohci);
	if (ret < 0) {
		ohci_err (ohci, "can't start\n");
		ohci_stop (hcd);
	}
	return ret;
}

#ifdef	CONFIG_PM

static int ohci_pci_suspend(struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
	unsigned long	flags;
	int		rc = 0;

	/* Root hub was already suspended. Disable irq emission and
	 * mark HW unaccessible, bail out if RH has been resumed. Use
	 * the spinlock to properly synchronize with possible pending
	 * RH suspend or resume activity.
	 *
	 * This is still racy as hcd->state is manipulated outside of
	 * any locks =P But that will be a different fix.
	 */
	spin_lock_irqsave (&ohci->lock, flags);
	if (hcd->state != HC_STATE_SUSPENDED) {
		rc = -EINVAL;
		goto bail;
	}
	ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
	(void)ohci_readl(ohci, &ohci->regs->intrdisable);

	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 bail:
	spin_unlock_irqrestore (&ohci->lock, flags);

	return rc;
}


static int ohci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);

	/* Make sure resume from hibernation re-enumerates everything */
	if (hibernated)
		ohci_usb_reset(hcd_to_ohci(hcd));

	ohci_finish_controller_resume(hcd);
	return 0;
}

#endif	/* CONFIG_PM */


/*-------------------------------------------------------------------------*/

static const struct hc_driver ohci_pci_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"OHCI Host Controller",
	.hcd_priv_size =	sizeof(struct ohci_hcd),

	/*
	 * generic hardware linkage
	 */
	.irq =			ohci_irq,
	.flags =		HCD_MEMORY | HCD_USB11,

	/*
	 * basic lifecycle operations
	 */
	.reset =		ohci_pci_reset,
	.start =		ohci_pci_start,
	.stop =			ohci_stop,
	.shutdown =		ohci_shutdown,

#ifdef	CONFIG_PM
	.pci_suspend =		ohci_pci_suspend,
	.pci_resume =		ohci_pci_resume,
#endif

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ohci_urb_enqueue,
	.urb_dequeue =		ohci_urb_dequeue,
	.endpoint_disable =	ohci_endpoint_disable,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ohci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ohci_hub_status_data,
	.hub_control =		ohci_hub_control,
#ifdef	CONFIG_PM
	.bus_suspend =		ohci_bus_suspend,
	.bus_resume =		ohci_bus_resume,
#endif
	.start_port_reset =	ohci_start_port_reset,
};

/*-------------------------------------------------------------------------*/


static const struct pci_device_id pci_ids [] = { {
	/* handle any USB OHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
	.driver_data =	(unsigned long) &ohci_pci_hc_driver,
	}, { /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE (pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ohci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,
	.shutdown =	usb_hcd_pci_shutdown,

#ifdef CONFIG_PM_SLEEP
	.driver =	{
		.pm =	&usb_hcd_pci_pm_ops
	},
#endif
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* OHCI HCD (Host Controller Driver) for USB.
	3	*
	4	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
	5	* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
dd9048af	6	*
1da177e4 LT	7	* [ Initialisation is based on Linus' ]
	8	* [ uhci code and gregs ohci fragments ]
	9	* [ (C) Copyright 1999 Linus Torvalds ]
	10	* [ (C) Copyright 1999 Gregory P. Smith]
dd9048af	11	*
1da177e4 LT	12	* PCI Bus Glue
	13	*
	14	* This file is licenced under the GPL.
	15	*/
dd9048af	16
1da177e4 LT	17	#ifndef CONFIG_PCI
	18	#error "This file is PCI bus glue. CONFIG_PCI must be defined."
	19	#endif
	20
ab1666c1 LY	21	#include <linux/pci.h>
	22	#include <linux/io.h>
	23
	24
	25	/* constants used to work around PM-related transfer
	26	* glitches in some AMD 700 series southbridges
	27	*/
	28	#define AB_REG_BAR 0xf0
	29	#define AB_INDX(addr) ((addr) + 0x00)
	30	#define AB_DATA(addr) ((addr) + 0x04)
	31	#define AX_INDXC 0X30
	32	#define AX_DATAC 0x34
	33
	34	#define NB_PCIE_INDX_ADDR 0xe0
	35	#define NB_PCIE_INDX_DATA 0xe4
	36	#define PCIE_P_CNTL 0x10040
	37	#define BIF_NB 0x10002
	38
	39	static struct pci_dev *amd_smbus_dev;
	40	static struct pci_dev *amd_hb_dev;
	41	static int amd_ohci_iso_count;
	42
1da177e4 LT	43	/-------------------------------------------------------------------------/
1da177e4 LT	44
931384fb DB	45	static int broken_suspend(struct usb_hcd *hcd)
	46	{
	47	device_init_wakeup(&hcd->self.root_hub->dev, 0);
	48	return 0;
	49	}
	50
4302a595 BH	51	/* AMD 756, for most chips (early revs), corrupts register
	52	* values on read ... so enable the vendor workaround.
	53	*/
931384fb	54	static int ohci_quirk_amd756(struct usb_hcd *hcd)
1da177e4 LT	55	{
	56	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	57
4302a595 BH	58	ohci->flags = OHCI_QUIRK_AMD756;
	59	ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
	60
	61	/* also erratum 10 (suspend/resume issues) */
931384fb	62	return broken_suspend(hcd);
1da177e4 LT	63	}
1da177e4 LT	64
4302a595 BH	65	/* Apple's OHCI driver has a lot of bizarre workarounds
	66	* for this chip. Evidently control and bulk lists
	67	* can get confused. (B&W G3 models, and ...)
	68	*/
931384fb	69	static int ohci_quirk_opti(struct usb_hcd *hcd)
1da177e4 LT	70	{
1da177e4 LT	71	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1da177e4	72
4302a595 BH	73	ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
	74
	75	return 0;
	76	}
	77
	78	/* Check for NSC87560. We have to look at the bridge (fn1) to
	79	* identify the USB (fn2). This quirk might apply to more or
	80	* even all NSC stuff.
	81	*/
931384fb	82	static int ohci_quirk_ns(struct usb_hcd *hcd)
4302a595 BH	83	{
	84	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
	85	struct pci_dev *b;
	86
	87	b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
	88	if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
	89	&& b->vendor == PCI_VENDOR_ID_NS) {
	90	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	91
	92	ohci->flags \|= OHCI_QUIRK_SUPERIO;
	93	ohci_dbg (ohci, "Using NSC SuperIO setup\n");
	94	}
	95	pci_dev_put(b);
	96
	97	return 0;
	98	}
	99
	100	/* Check for Compaq's ZFMicro chipset, which needs short
	101	* delays before control or bulk queues get re-activated
	102	* in finish_unlinks()
	103	*/
931384fb	104	static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
4302a595 BH	105	{
	106	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	107
	108	ohci->flags \|= OHCI_QUIRK_ZFMICRO;
89a0fd18	109	ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");
4302a595 BH	110
	111	return 0;
	112	}
	113
11d1a4aa BH	114	/* Check for Toshiba SCC OHCI which has big endian registers
	115	* and little endian in memory data structures
	116	*/
931384fb	117	static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
11d1a4aa BH	118	{
	119	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	120
	121	/* That chip is only present in the southbridge of some
	122	* cell based platforms which are supposed to select
	123	* CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
	124	* that was the case though.
	125	*/
	126	#ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
	127	ohci->flags \|= OHCI_QUIRK_BE_MMIO;
	128	ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
	129	return 0;
	130	#else
	131	ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
	132	return -ENXIO;
	133	#endif
	134	}
4302a595	135
d576bb9f MH	136	/* Check for NEC chip and apply quirk for allegedly lost interrupts.
d576bb9f MH	137	*/
89a0fd18 MN	138
	139	static void ohci_quirk_nec_worker(struct work_struct *work)
	140	{
	141	struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
	142	int status;
	143
	144	status = ohci_init(ohci);
	145	if (status != 0) {
	146	ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
	147	"ohci_init", status);
	148	return;
	149	}
	150
	151	status = ohci_restart(ohci);
	152	if (status != 0)
	153	ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
	154	"ohci_restart", status);
	155	}
	156
d576bb9f MH	157	static int ohci_quirk_nec(struct usb_hcd *hcd)
	158	{
	159	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	160
	161	ohci->flags \|= OHCI_QUIRK_NEC;
89a0fd18	162	INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
d576bb9f MH	163	ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");
	164
	165	return 0;
	166	}
	167
ab1666c1 LY	168	static int ohci_quirk_amd700(struct usb_hcd *hcd)
	169	{
	170	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
	171	u8 rev = 0;
	172
	173	if (!amd_smbus_dev)
	174	amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
	175	PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
	176	if (!amd_smbus_dev)
	177	return 0;
	178
	179	pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
	180	if ((rev > 0x3b) \|\| (rev < 0x30)) {
	181	pci_dev_put(amd_smbus_dev);
	182	amd_smbus_dev = NULL;
	183	return 0;
	184	}
	185
	186	amd_ohci_iso_count++;
	187
	188	if (!amd_hb_dev)
	189	amd_hb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9600, NULL);
	190
	191	ohci->flags \|= OHCI_QUIRK_AMD_ISO;
	192	ohci_dbg(ohci, "enabled AMD ISO transfers quirk\n");
	193
	194	return 0;
	195	}
	196
	197	/*
	198	* The hardware normally enables the A-link power management feature, which
	199	* lets the system lower the power consumption in idle states.
	200	*
	201	* Assume the system is configured to have USB 1.1 ISO transfers going
	202	* to or from a USB device. Without this quirk, that stream may stutter
	203	* or have breaks occasionally. For transfers going to speakers, this
	204	* makes a very audible mess...
	205	*
	206	* That audio playback corruption is due to the audio stream getting
	207	* interrupted occasionally when the link goes in lower power state
	208	* This USB quirk prevents the link going into that lower power state
	209	* during audio playback or other ISO operations.
	210	*/
	211	static void quirk_amd_pll(int on)
	212	{
	213	u32 addr;
	214	u32 val;
	215	u32 bit = (on > 0) ? 1 : 0;
	216
	217	pci_read_config_dword(amd_smbus_dev, AB_REG_BAR, &addr);
	218
	219	/* BIT names/meanings are NDA-protected, sorry ... */
	220
	221	outl(AX_INDXC, AB_INDX(addr));
	222	outl(0x40, AB_DATA(addr));
	223	outl(AX_DATAC, AB_INDX(addr));
	224	val = inl(AB_DATA(addr));
	225	val &= ~((1 << 3) \| (1 << 4) \| (1 << 9));
	226	val \|= (bit << 3) \| ((!bit) << 4) \| ((!bit) << 9);
	227	outl(val, AB_DATA(addr));
	228
	229	if (amd_hb_dev) {
	230	addr = PCIE_P_CNTL;
	231	pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_ADDR, addr);
232
233	pci_read_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, &val);
234	val &= ~(1 \| (1 << 3) \| (1 << 4) \| (1 << 9) \| (1 << 12));
235	val \|= bit \| (bit << 3) \| (bit << 12);
236	val \|= ((!bit) << 4) \| ((!bit) << 9);
237	pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, val);
238
239	addr = BIF_NB;
240	pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_ADDR, addr);
241
242	pci_read_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, &val);
243	val &= ~(1 << 8);
244	val \|= bit << 8;
245	pci_write_config_dword(amd_hb_dev, NB_PCIE_INDX_DATA, val);
246	}
247	}
248
249	static void amd_iso_dev_put(void)
250	{
251	amd_ohci_iso_count--;
252	if (amd_ohci_iso_count == 0) {
253	if (amd_smbus_dev) {
254	pci_dev_put(amd_smbus_dev);
255	amd_smbus_dev = NULL;
256	}
257	if (amd_hb_dev) {
258	pci_dev_put(amd_hb_dev);
259	amd_hb_dev = NULL;
260	}
261	}
262
263	}
264
4302a595 BH	265	/* List of quirks for OHCI */
	266	static const struct pci_device_id ohci_pci_quirks[] = {
	267	{
	268	PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
	269	.driver_data = (unsigned long)ohci_quirk_amd756,
	270	},
	271	{
	272	PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
	273	.driver_data = (unsigned long)ohci_quirk_opti,
	274	},
	275	{
	276	PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
	277	.driver_data = (unsigned long)ohci_quirk_ns,
	278	},
	279	{
	280	PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
	281	.driver_data = (unsigned long)ohci_quirk_zfmicro,
	282	},
11d1a4aa BH	283	{
	284	PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
	285	.driver_data = (unsigned long)ohci_quirk_toshiba_scc,
	286	},
d576bb9f MH	287	{
	288	PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
	289	.driver_data = (unsigned long)ohci_quirk_nec,
	290	},
931384fb DB	291	{
	292	/* Toshiba portege 4000 */
	293	.vendor = PCI_VENDOR_ID_AL,
	294	.device = 0x5237,
8ab5e8c0	295	.subvendor = PCI_VENDOR_ID_TOSHIBA,
931384fb DB	296	.subdevice = 0x0004,
	297	.driver_data = (unsigned long) broken_suspend,
	298	},
33f73e56 RA	299	{
	300	PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
	301	.driver_data = (unsigned long) broken_suspend,
	302	},
ab1666c1 LY	303	{
	304	PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4397),
	305	.driver_data = (unsigned long)ohci_quirk_amd700,
	306	},
	307	{
	308	PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4398),
	309	.driver_data = (unsigned long)ohci_quirk_amd700,
	310	},
	311	{
	312	PCI_DEVICE(PCI_VENDOR_ID_ATI, 0x4399),
	313	.driver_data = (unsigned long)ohci_quirk_amd700,
	314	},
	315
4302a595 BH	316	/* FIXME for some of the early AMD 760 southbridges, OHCI
4302a595 BH	317	* won't work at all. blacklist them.
6a9062f3	318	*/
11d1a4aa	319
4302a595 BH	320	{},
	321	};
	322
	323	static int ohci_pci_reset (struct usb_hcd *hcd)
	324	{
	325	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	326	int ret = 0;
	327
6a9062f3	328	if (hcd->self.controller) {
1da177e4	329	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
4302a595	330	const struct pci_device_id *quirk_id;
1da177e4	331
4302a595 BH	332	quirk_id = pci_match_id(ohci_pci_quirks, pdev);
	333	if (quirk_id != NULL) {
	334	int (quirk)(struct usb_hcd ohci);
	335	quirk = (void *)quirk_id->driver_data;
	336	ret = quirk(hcd);
1da177e4	337	}
4302a595 BH	338	}
	339	if (ret == 0) {
	340	ohci_hcd_init (ohci);
	341	return ohci_init (ohci);
	342	}
	343	return ret;
	344	}
1da177e4	345
1da177e4	346
4302a595 BH	347	static int __devinit ohci_pci_start (struct usb_hcd *hcd)
	348	{
	349	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	350	int ret;
0e498763	351
4302a595 BH	352	#ifdef CONFIG_PM /* avoid warnings about unused pdev */
	353	if (hcd->self.controller) {
	354	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
6a9062f3 DB	355
	356	/* RWC may not be set for add-in PCI cards, since boot
	357	* firmware probably ignored them. This transfers PCI
6fd9086a	358	* PM wakeup capabilities.
6a9062f3	359	*/
6fd9086a	360	if (device_can_wakeup(&pdev->dev))
6a9062f3	361	ohci->hc_control \|= OHCI_CTRL_RWC;
1da177e4	362	}
4302a595	363	#endif /* CONFIG_PM */
1da177e4	364
4302a595 BH	365	ret = ohci_run (ohci);
4302a595 BH	366	if (ret < 0) {
1da177e4 LT	367	ohci_err (ohci, "can't start\n");
1da177e4 LT	368	ohci_stop (hcd);
1da177e4	369	}
4302a595	370	return ret;
1da177e4 LT	371	}
	372
	373	#ifdef CONFIG_PM
	374
6ec4beb5	375	static int ohci_pci_suspend(struct usb_hcd *hcd)
1da177e4	376	{
8de98402 BH	377	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	378	unsigned long flags;
	379	int rc = 0;
	380
	381	/* Root hub was already suspended. Disable irq emission and
	382	* mark HW unaccessible, bail out if RH has been resumed. Use
	383	* the spinlock to properly synchronize with possible pending
	384	* RH suspend or resume activity.
	385	*
	386	* This is still racy as hcd->state is manipulated outside of
	387	* any locks =P But that will be a different fix.
	388	*/
	389	spin_lock_irqsave (&ohci->lock, flags);
	390	if (hcd->state != HC_STATE_SUSPENDED) {
	391	rc = -EINVAL;
	392	goto bail;
	393	}
	394	ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
	395	(void)ohci_readl(ohci, &ohci->regs->intrdisable);
18584999	396
8de98402 BH	397	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
	398	bail:
	399	spin_unlock_irqrestore (&ohci->lock, flags);
	400
	401	return rc;
1da177e4 LT	402	}
	403
	404
6ec4beb5	405	static int ohci_pci_resume(struct usb_hcd *hcd, bool hibernated)
1da177e4	406	{
8de98402	407	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
6ec4beb5 AS	408
	409	/* Make sure resume from hibernation re-enumerates everything */
	410	if (hibernated)
	411	ohci_usb_reset(hcd_to_ohci(hcd));
	412
43bbb7e0	413	ohci_finish_controller_resume(hcd);
f197b2c5	414	return 0;
1da177e4 LT	415	}
	416
	417	#endif /* CONFIG_PM */
	418
	419
	420	/-------------------------------------------------------------------------/
	421
	422	static const struct hc_driver ohci_pci_hc_driver = {
	423	.description = hcd_name,
	424	.product_desc = "OHCI Host Controller",
	425	.hcd_priv_size = sizeof(struct ohci_hcd),
	426
	427	/*
	428	* generic hardware linkage
	429	*/
	430	.irq = ohci_irq,
	431	.flags = HCD_MEMORY \| HCD_USB11,
	432
	433	/*
	434	* basic lifecycle operations
	435	*/
	436	.reset = ohci_pci_reset,
	437	.start = ohci_pci_start,
d413984a	438	.stop = ohci_stop,
64a21d02	439	.shutdown = ohci_shutdown,
d413984a	440
1da177e4	441	#ifdef CONFIG_PM
7be7d741 AS	442	.pci_suspend = ohci_pci_suspend,
7be7d741 AS	443	.pci_resume = ohci_pci_resume,
1da177e4	444	#endif
1da177e4 LT	445
	446	/*
	447	* managing i/o requests and associated device resources
	448	*/
	449	.urb_enqueue = ohci_urb_enqueue,
	450	.urb_dequeue = ohci_urb_dequeue,
	451	.endpoint_disable = ohci_endpoint_disable,
	452
	453	/*
	454	* scheduling support
	455	*/
	456	.get_frame_number = ohci_get_frame,
	457
	458	/*
	459	* root hub support
	460	*/
	461	.hub_status_data = ohci_hub_status_data,
	462	.hub_control = ohci_hub_control,
8ad7fe16	463	#ifdef CONFIG_PM
0c0382e3 AS	464	.bus_suspend = ohci_bus_suspend,
0c0382e3 AS	465	.bus_resume = ohci_bus_resume,
1da177e4 LT	466	#endif
	467	.start_port_reset = ohci_start_port_reset,
	468	};
	469
	470	/-------------------------------------------------------------------------/
	471
	472
	473	static const struct pci_device_id pci_ids [] = { {
	474	/* handle any USB OHCI controller */
c67808ee	475	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
1da177e4 LT	476	.driver_data = (unsigned long) &ohci_pci_hc_driver,
	477	}, { /* end: all zeroes */ }
	478	};
	479	MODULE_DEVICE_TABLE (pci, pci_ids);
	480
	481	/* pci driver glue; this is a "new style" PCI driver module */
	482	static struct pci_driver ohci_pci_driver = {
	483	.name = (char *) hcd_name,
	484	.id_table = pci_ids,
	485
	486	.probe = usb_hcd_pci_probe,
	487	.remove = usb_hcd_pci_remove,
abb30641	488	.shutdown = usb_hcd_pci_shutdown,
1da177e4	489
abb30641 AS	490	#ifdef CONFIG_PM_SLEEP
	491	.driver = {
	492	.pm = &usb_hcd_pci_pm_ops
	493	},
1da177e4 LT	494	#endif
1da177e4 LT	495	};