Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * OHCI HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
5 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> | |
6 | * | |
7 | * [ Initialisation is based on Linus' ] | |
8 | * [ uhci code and gregs ohci fragments ] | |
9 | * [ (C) Copyright 1999 Linus Torvalds ] | |
10 | * [ (C) Copyright 1999 Gregory P. Smith] | |
11 | * | |
12 | * | |
13 | * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller | |
14 | * interfaces (though some non-x86 Intel chips use it). It supports | |
15 | * smarter hardware than UHCI. A download link for the spec available | |
16 | * through the http://www.usb.org website. | |
17 | * | |
18 | * History: | |
19 | * | |
20 | * 2004/03/24 LH7A404 support (Durgesh Pattamatta & Marc Singer) | |
21 | * 2004/02/04 use generic dma_* functions instead of pci_* (dsaxena@plexity.net) | |
22 | * 2003/02/24 show registers in sysfs (Kevin Brosius) | |
23 | * | |
24 | * 2002/09/03 get rid of ed hashtables, rework periodic scheduling and | |
25 | * bandwidth accounting; if debugging, show schedules in driverfs | |
26 | * 2002/07/19 fixes to management of ED and schedule state. | |
27 | * 2002/06/09 SA-1111 support (Christopher Hoover) | |
28 | * 2002/06/01 remember frame when HC won't see EDs any more; use that info | |
29 | * to fix urb unlink races caused by interrupt latency assumptions; | |
30 | * minor ED field and function naming updates | |
31 | * 2002/01/18 package as a patch for 2.5.3; this should match the | |
32 | * 2.4.17 kernel modulo some bugs being fixed. | |
33 | * | |
34 | * 2001/10/18 merge pmac cleanup (Benjamin Herrenschmidt) and bugfixes | |
35 | * from post-2.4.5 patches. | |
36 | * 2001/09/20 URB_ZERO_PACKET support; hcca_dma portability, OPTi warning | |
37 | * 2001/09/07 match PCI PM changes, errnos from Linus' tree | |
38 | * 2001/05/05 fork 2.4.5 version into "hcd" framework, cleanup, simplify; | |
39 | * pbook pci quirks gone (please fix pbook pci sw!) (db) | |
40 | * | |
41 | * 2001/04/08 Identify version on module load (gb) | |
42 | * 2001/03/24 td/ed hashing to remove bus_to_virt (Steve Longerbeam); | |
43 | pci_map_single (db) | |
44 | * 2001/03/21 td and dev/ed allocation uses new pci_pool API (db) | |
45 | * 2001/03/07 hcca allocation uses pci_alloc_consistent (Steve Longerbeam) | |
46 | * | |
47 | * 2000/09/26 fixed races in removing the private portion of the urb | |
48 | * 2000/09/07 disable bulk and control lists when unlinking the last | |
49 | * endpoint descriptor in order to avoid unrecoverable errors on | |
50 | * the Lucent chips. (rwc@sgi) | |
51 | * 2000/08/29 use bandwidth claiming hooks (thanks Randy!), fix some | |
52 | * urb unlink probs, indentation fixes | |
53 | * 2000/08/11 various oops fixes mostly affecting iso and cleanup from | |
54 | * device unplugs. | |
55 | * 2000/06/28 use PCI hotplug framework, for better power management | |
56 | * and for Cardbus support (David Brownell) | |
57 | * 2000/earlier: fixes for NEC/Lucent chips; suspend/resume handling | |
58 | * when the controller loses power; handle UE; cleanup; ... | |
59 | * | |
60 | * v5.2 1999/12/07 URB 3rd preview, | |
61 | * v5.1 1999/11/30 URB 2nd preview, cpia, (usb-scsi) | |
62 | * v5.0 1999/11/22 URB Technical preview, Paul Mackerras powerbook susp/resume | |
63 | * i386: HUB, Keyboard, Mouse, Printer | |
64 | * | |
65 | * v4.3 1999/10/27 multiple HCs, bulk_request | |
66 | * v4.2 1999/09/05 ISO API alpha, new dev alloc, neg Error-codes | |
67 | * v4.1 1999/08/27 Randy Dunlap's - ISO API first impl. | |
68 | * v4.0 1999/08/18 | |
69 | * v3.0 1999/06/25 | |
70 | * v2.1 1999/05/09 code clean up | |
71 | * v2.0 1999/05/04 | |
72 | * v1.0 1999/04/27 initial release | |
73 | * | |
74 | * This file is licenced under the GPL. | |
75 | */ | |
76 | ||
1da177e4 LT |
77 | #include <linux/module.h> |
78 | #include <linux/moduleparam.h> | |
79 | #include <linux/pci.h> | |
80 | #include <linux/kernel.h> | |
81 | #include <linux/delay.h> | |
82 | #include <linux/ioport.h> | |
83 | #include <linux/sched.h> | |
84 | #include <linux/slab.h> | |
85 | #include <linux/smp_lock.h> | |
86 | #include <linux/errno.h> | |
87 | #include <linux/init.h> | |
88 | #include <linux/timer.h> | |
89 | #include <linux/list.h> | |
1da177e4 | 90 | #include <linux/usb.h> |
3a16f7b4 | 91 | #include <linux/usb/otg.h> |
1da177e4 | 92 | #include <linux/dma-mapping.h> |
f4df0e33 DB |
93 | #include <linux/dmapool.h> |
94 | #include <linux/reboot.h> | |
1da177e4 LT |
95 | |
96 | #include <asm/io.h> | |
97 | #include <asm/irq.h> | |
98 | #include <asm/system.h> | |
99 | #include <asm/unaligned.h> | |
100 | #include <asm/byteorder.h> | |
101 | ||
f4df0e33 | 102 | #include "../core/hcd.h" |
1da177e4 | 103 | |
d413984a | 104 | #define DRIVER_VERSION "2006 August 04" |
1da177e4 LT |
105 | #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" |
106 | #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" | |
107 | ||
108 | /*-------------------------------------------------------------------------*/ | |
109 | ||
8de98402 | 110 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
1da177e4 LT |
111 | |
112 | /* For initializing controller (mask in an HCFS mode too) */ | |
d413984a | 113 | #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR |
1da177e4 | 114 | #define OHCI_INTR_INIT \ |
d413984a DB |
115 | (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ |
116 | | OHCI_INTR_RD | OHCI_INTR_WDH) | |
1da177e4 LT |
117 | |
118 | #ifdef __hppa__ | |
119 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ | |
120 | #define IR_DISABLE | |
121 | #endif | |
122 | ||
123 | #ifdef CONFIG_ARCH_OMAP | |
124 | /* OMAP doesn't support IR (no SMM; not needed) */ | |
125 | #define IR_DISABLE | |
126 | #endif | |
127 | ||
128 | /*-------------------------------------------------------------------------*/ | |
129 | ||
130 | static const char hcd_name [] = "ohci_hcd"; | |
131 | ||
d413984a DB |
132 | #define STATECHANGE_DELAY msecs_to_jiffies(300) |
133 | ||
1da177e4 LT |
134 | #include "ohci.h" |
135 | ||
136 | static void ohci_dump (struct ohci_hcd *ohci, int verbose); | |
137 | static int ohci_init (struct ohci_hcd *ohci); | |
138 | static void ohci_stop (struct usb_hcd *hcd); | |
139 | ||
140 | #include "ohci-hub.c" | |
141 | #include "ohci-dbg.c" | |
142 | #include "ohci-mem.c" | |
143 | #include "ohci-q.c" | |
144 | ||
145 | ||
146 | /* | |
147 | * On architectures with edge-triggered interrupts we must never return | |
148 | * IRQ_NONE. | |
149 | */ | |
150 | #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ | |
151 | #define IRQ_NOTMINE IRQ_HANDLED | |
152 | #else | |
153 | #define IRQ_NOTMINE IRQ_NONE | |
154 | #endif | |
155 | ||
156 | ||
157 | /* Some boards misreport power switching/overcurrent */ | |
158 | static int distrust_firmware = 1; | |
159 | module_param (distrust_firmware, bool, 0); | |
160 | MODULE_PARM_DESC (distrust_firmware, | |
161 | "true to distrust firmware power/overcurrent setup"); | |
162 | ||
163 | /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ | |
164 | static int no_handshake = 0; | |
165 | module_param (no_handshake, bool, 0); | |
166 | MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); | |
167 | ||
168 | /*-------------------------------------------------------------------------*/ | |
169 | ||
170 | /* | |
171 | * queue up an urb for anything except the root hub | |
172 | */ | |
173 | static int ohci_urb_enqueue ( | |
174 | struct usb_hcd *hcd, | |
175 | struct usb_host_endpoint *ep, | |
176 | struct urb *urb, | |
55016f10 | 177 | gfp_t mem_flags |
1da177e4 LT |
178 | ) { |
179 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
180 | struct ed *ed; | |
181 | urb_priv_t *urb_priv; | |
182 | unsigned int pipe = urb->pipe; | |
183 | int i, size = 0; | |
184 | unsigned long flags; | |
185 | int retval = 0; | |
186 | ||
187 | #ifdef OHCI_VERBOSE_DEBUG | |
188 | urb_print (urb, "SUB", usb_pipein (pipe)); | |
189 | #endif | |
190 | ||
191 | /* every endpoint has a ed, locate and maybe (re)initialize it */ | |
192 | if (! (ed = ed_get (ohci, ep, urb->dev, pipe, urb->interval))) | |
193 | return -ENOMEM; | |
194 | ||
195 | /* for the private part of the URB we need the number of TDs (size) */ | |
196 | switch (ed->type) { | |
197 | case PIPE_CONTROL: | |
198 | /* td_submit_urb() doesn't yet handle these */ | |
199 | if (urb->transfer_buffer_length > 4096) | |
200 | return -EMSGSIZE; | |
201 | ||
202 | /* 1 TD for setup, 1 for ACK, plus ... */ | |
203 | size = 2; | |
204 | /* FALLTHROUGH */ | |
205 | // case PIPE_INTERRUPT: | |
206 | // case PIPE_BULK: | |
207 | default: | |
208 | /* one TD for every 4096 Bytes (can be upto 8K) */ | |
209 | size += urb->transfer_buffer_length / 4096; | |
210 | /* ... and for any remaining bytes ... */ | |
211 | if ((urb->transfer_buffer_length % 4096) != 0) | |
212 | size++; | |
213 | /* ... and maybe a zero length packet to wrap it up */ | |
214 | if (size == 0) | |
215 | size++; | |
216 | else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 | |
217 | && (urb->transfer_buffer_length | |
218 | % usb_maxpacket (urb->dev, pipe, | |
219 | usb_pipeout (pipe))) == 0) | |
220 | size++; | |
221 | break; | |
222 | case PIPE_ISOCHRONOUS: /* number of packets from URB */ | |
223 | size = urb->number_of_packets; | |
224 | break; | |
225 | } | |
226 | ||
227 | /* allocate the private part of the URB */ | |
228 | urb_priv = kmalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), | |
229 | mem_flags); | |
230 | if (!urb_priv) | |
231 | return -ENOMEM; | |
232 | memset (urb_priv, 0, sizeof (urb_priv_t) + size * sizeof (struct td *)); | |
233 | INIT_LIST_HEAD (&urb_priv->pending); | |
234 | urb_priv->length = size; | |
235 | urb_priv->ed = ed; | |
236 | ||
237 | /* allocate the TDs (deferring hash chain updates) */ | |
238 | for (i = 0; i < size; i++) { | |
239 | urb_priv->td [i] = td_alloc (ohci, mem_flags); | |
240 | if (!urb_priv->td [i]) { | |
241 | urb_priv->length = i; | |
242 | urb_free_priv (ohci, urb_priv); | |
243 | return -ENOMEM; | |
244 | } | |
245 | } | |
246 | ||
247 | spin_lock_irqsave (&ohci->lock, flags); | |
248 | ||
249 | /* don't submit to a dead HC */ | |
8de98402 BH |
250 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { |
251 | retval = -ENODEV; | |
252 | goto fail; | |
253 | } | |
1da177e4 LT |
254 | if (!HC_IS_RUNNING(hcd->state)) { |
255 | retval = -ENODEV; | |
256 | goto fail; | |
257 | } | |
258 | ||
259 | /* in case of unlink-during-submit */ | |
260 | spin_lock (&urb->lock); | |
261 | if (urb->status != -EINPROGRESS) { | |
262 | spin_unlock (&urb->lock); | |
263 | urb->hcpriv = urb_priv; | |
7d12e780 | 264 | finish_urb (ohci, urb); |
1da177e4 LT |
265 | retval = 0; |
266 | goto fail; | |
267 | } | |
268 | ||
269 | /* schedule the ed if needed */ | |
270 | if (ed->state == ED_IDLE) { | |
271 | retval = ed_schedule (ohci, ed); | |
272 | if (retval < 0) | |
273 | goto fail0; | |
274 | if (ed->type == PIPE_ISOCHRONOUS) { | |
275 | u16 frame = ohci_frame_no(ohci); | |
276 | ||
277 | /* delay a few frames before the first TD */ | |
278 | frame += max_t (u16, 8, ed->interval); | |
279 | frame &= ~(ed->interval - 1); | |
280 | frame |= ed->branch; | |
281 | urb->start_frame = frame; | |
282 | ||
283 | /* yes, only URB_ISO_ASAP is supported, and | |
284 | * urb->start_frame is never used as input. | |
285 | */ | |
286 | } | |
287 | } else if (ed->type == PIPE_ISOCHRONOUS) | |
288 | urb->start_frame = ed->last_iso + ed->interval; | |
289 | ||
290 | /* fill the TDs and link them to the ed; and | |
291 | * enable that part of the schedule, if needed | |
292 | * and update count of queued periodic urbs | |
293 | */ | |
294 | urb->hcpriv = urb_priv; | |
295 | td_submit_urb (ohci, urb); | |
296 | ||
297 | fail0: | |
298 | spin_unlock (&urb->lock); | |
299 | fail: | |
300 | if (retval) | |
301 | urb_free_priv (ohci, urb_priv); | |
302 | spin_unlock_irqrestore (&ohci->lock, flags); | |
303 | return retval; | |
304 | } | |
305 | ||
306 | /* | |
307 | * decouple the URB from the HC queues (TDs, urb_priv); it's | |
308 | * already marked using urb->status. reporting is always done | |
309 | * asynchronously, and we might be dealing with an urb that's | |
310 | * partially transferred, or an ED with other urbs being unlinked. | |
311 | */ | |
312 | static int ohci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb) | |
313 | { | |
314 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
315 | unsigned long flags; | |
316 | ||
317 | #ifdef OHCI_VERBOSE_DEBUG | |
318 | urb_print (urb, "UNLINK", 1); | |
319 | #endif | |
320 | ||
321 | spin_lock_irqsave (&ohci->lock, flags); | |
322 | if (HC_IS_RUNNING(hcd->state)) { | |
323 | urb_priv_t *urb_priv; | |
324 | ||
325 | /* Unless an IRQ completed the unlink while it was being | |
326 | * handed to us, flag it for unlink and giveback, and force | |
327 | * some upcoming INTR_SF to call finish_unlinks() | |
328 | */ | |
329 | urb_priv = urb->hcpriv; | |
330 | if (urb_priv) { | |
331 | if (urb_priv->ed->state == ED_OPER) | |
332 | start_ed_unlink (ohci, urb_priv->ed); | |
333 | } | |
334 | } else { | |
335 | /* | |
336 | * with HC dead, we won't respect hc queue pointers | |
337 | * any more ... just clean up every urb's memory. | |
338 | */ | |
339 | if (urb->hcpriv) | |
7d12e780 | 340 | finish_urb (ohci, urb); |
1da177e4 LT |
341 | } |
342 | spin_unlock_irqrestore (&ohci->lock, flags); | |
343 | return 0; | |
344 | } | |
345 | ||
346 | /*-------------------------------------------------------------------------*/ | |
347 | ||
348 | /* frees config/altsetting state for endpoints, | |
349 | * including ED memory, dummy TD, and bulk/intr data toggle | |
350 | */ | |
351 | ||
352 | static void | |
353 | ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
354 | { | |
355 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
356 | unsigned long flags; | |
357 | struct ed *ed = ep->hcpriv; | |
358 | unsigned limit = 1000; | |
359 | ||
360 | /* ASSERT: any requests/urbs are being unlinked */ | |
361 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
362 | ||
363 | if (!ed) | |
364 | return; | |
365 | ||
366 | rescan: | |
367 | spin_lock_irqsave (&ohci->lock, flags); | |
368 | ||
369 | if (!HC_IS_RUNNING (hcd->state)) { | |
370 | sanitize: | |
371 | ed->state = ED_IDLE; | |
7d12e780 | 372 | finish_unlinks (ohci, 0); |
1da177e4 LT |
373 | } |
374 | ||
375 | switch (ed->state) { | |
376 | case ED_UNLINK: /* wait for hw to finish? */ | |
377 | /* major IRQ delivery trouble loses INTR_SF too... */ | |
378 | if (limit-- == 0) { | |
379 | ohci_warn (ohci, "IRQ INTR_SF lossage\n"); | |
380 | goto sanitize; | |
381 | } | |
382 | spin_unlock_irqrestore (&ohci->lock, flags); | |
22c43863 | 383 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
384 | goto rescan; |
385 | case ED_IDLE: /* fully unlinked */ | |
386 | if (list_empty (&ed->td_list)) { | |
387 | td_free (ohci, ed->dummy); | |
388 | ed_free (ohci, ed); | |
389 | break; | |
390 | } | |
391 | /* else FALL THROUGH */ | |
392 | default: | |
393 | /* caller was supposed to have unlinked any requests; | |
394 | * that's not our job. can't recover; must leak ed. | |
395 | */ | |
396 | ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", | |
397 | ed, ep->desc.bEndpointAddress, ed->state, | |
398 | list_empty (&ed->td_list) ? "" : " (has tds)"); | |
399 | td_free (ohci, ed->dummy); | |
400 | break; | |
401 | } | |
402 | ep->hcpriv = NULL; | |
403 | spin_unlock_irqrestore (&ohci->lock, flags); | |
404 | return; | |
405 | } | |
406 | ||
407 | static int ohci_get_frame (struct usb_hcd *hcd) | |
408 | { | |
409 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
410 | ||
411 | return ohci_frame_no(ohci); | |
412 | } | |
413 | ||
414 | static void ohci_usb_reset (struct ohci_hcd *ohci) | |
415 | { | |
416 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); | |
417 | ohci->hc_control &= OHCI_CTRL_RWC; | |
418 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
419 | } | |
420 | ||
64a21d02 | 421 | /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and |
f4df0e33 DB |
422 | * other cases where the next software may expect clean state from the |
423 | * "firmware". this is bus-neutral, unlike shutdown() methods. | |
424 | */ | |
64a21d02 AG |
425 | static void |
426 | ohci_shutdown (struct usb_hcd *hcd) | |
f4df0e33 DB |
427 | { |
428 | struct ohci_hcd *ohci; | |
429 | ||
64a21d02 | 430 | ohci = hcd_to_ohci (hcd); |
f4df0e33 DB |
431 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
432 | ohci_usb_reset (ohci); | |
433 | /* flush the writes */ | |
434 | (void) ohci_readl (ohci, &ohci->regs->control); | |
f4df0e33 DB |
435 | } |
436 | ||
1da177e4 LT |
437 | /*-------------------------------------------------------------------------* |
438 | * HC functions | |
439 | *-------------------------------------------------------------------------*/ | |
440 | ||
441 | /* init memory, and kick BIOS/SMM off */ | |
442 | ||
443 | static int ohci_init (struct ohci_hcd *ohci) | |
444 | { | |
445 | int ret; | |
6a9062f3 | 446 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 LT |
447 | |
448 | disable (ohci); | |
6a9062f3 | 449 | ohci->regs = hcd->regs; |
1da177e4 | 450 | |
6a9062f3 DB |
451 | /* REVISIT this BIOS handshake is now moved into PCI "quirks", and |
452 | * was never needed for most non-PCI systems ... remove the code? | |
453 | */ | |
454 | ||
1da177e4 LT |
455 | #ifndef IR_DISABLE |
456 | /* SMM owns the HC? not for long! */ | |
457 | if (!no_handshake && ohci_readl (ohci, | |
458 | &ohci->regs->control) & OHCI_CTRL_IR) { | |
459 | u32 temp; | |
460 | ||
461 | ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); | |
462 | ||
463 | /* this timeout is arbitrary. we make it long, so systems | |
464 | * depending on usb keyboards may be usable even if the | |
465 | * BIOS/SMM code seems pretty broken. | |
466 | */ | |
467 | temp = 500; /* arbitrary: five seconds */ | |
468 | ||
469 | ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); | |
470 | ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); | |
471 | while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { | |
472 | msleep (10); | |
473 | if (--temp == 0) { | |
474 | ohci_err (ohci, "USB HC takeover failed!" | |
475 | " (BIOS/SMM bug)\n"); | |
476 | return -EBUSY; | |
477 | } | |
478 | } | |
479 | ohci_usb_reset (ohci); | |
480 | } | |
481 | #endif | |
482 | ||
483 | /* Disable HC interrupts */ | |
484 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
6a9062f3 DB |
485 | |
486 | /* flush the writes, and save key bits like RWC */ | |
487 | if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) | |
488 | ohci->hc_control |= OHCI_CTRL_RWC; | |
1da177e4 | 489 | |
fdd13b36 DB |
490 | /* Read the number of ports unless overridden */ |
491 | if (ohci->num_ports == 0) | |
492 | ohci->num_ports = roothub_a(ohci) & RH_A_NDP; | |
493 | ||
1da177e4 LT |
494 | if (ohci->hcca) |
495 | return 0; | |
496 | ||
6a9062f3 | 497 | ohci->hcca = dma_alloc_coherent (hcd->self.controller, |
1da177e4 LT |
498 | sizeof *ohci->hcca, &ohci->hcca_dma, 0); |
499 | if (!ohci->hcca) | |
500 | return -ENOMEM; | |
501 | ||
502 | if ((ret = ohci_mem_init (ohci)) < 0) | |
6a9062f3 DB |
503 | ohci_stop (hcd); |
504 | else { | |
6a9062f3 DB |
505 | create_debug_files (ohci); |
506 | } | |
1da177e4 LT |
507 | |
508 | return ret; | |
1da177e4 LT |
509 | } |
510 | ||
511 | /*-------------------------------------------------------------------------*/ | |
512 | ||
513 | /* Start an OHCI controller, set the BUS operational | |
514 | * resets USB and controller | |
515 | * enable interrupts | |
1da177e4 LT |
516 | */ |
517 | static int ohci_run (struct ohci_hcd *ohci) | |
518 | { | |
519 | u32 mask, temp; | |
1da177e4 | 520 | int first = ohci->fminterval == 0; |
6a9062f3 | 521 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 LT |
522 | |
523 | disable (ohci); | |
524 | ||
525 | /* boot firmware should have set this up (5.1.1.3.1) */ | |
526 | if (first) { | |
527 | ||
528 | temp = ohci_readl (ohci, &ohci->regs->fminterval); | |
529 | ohci->fminterval = temp & 0x3fff; | |
530 | if (ohci->fminterval != FI) | |
531 | ohci_dbg (ohci, "fminterval delta %d\n", | |
532 | ohci->fminterval - FI); | |
533 | ohci->fminterval |= FSMP (ohci->fminterval) << 16; | |
534 | /* also: power/overcurrent flags in roothub.a */ | |
535 | } | |
536 | ||
6a9062f3 DB |
537 | /* Reset USB nearly "by the book". RemoteWakeupConnected was |
538 | * saved if boot firmware (BIOS/SMM/...) told us it's connected, | |
539 | * or if bus glue did the same (e.g. for PCI add-in cards with | |
540 | * PCI PM support). | |
1da177e4 | 541 | */ |
1da177e4 LT |
542 | ohci_dbg (ohci, "resetting from state '%s', control = 0x%x\n", |
543 | hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS), | |
6a9062f3 DB |
544 | ohci_readl (ohci, &ohci->regs->control)); |
545 | if ((ohci->hc_control & OHCI_CTRL_RWC) != 0 | |
546 | && !device_may_wakeup(hcd->self.controller)) | |
547 | device_init_wakeup(hcd->self.controller, 1); | |
1da177e4 LT |
548 | |
549 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
550 | case OHCI_USB_OPER: | |
551 | temp = 0; | |
552 | break; | |
553 | case OHCI_USB_SUSPEND: | |
554 | case OHCI_USB_RESUME: | |
555 | ohci->hc_control &= OHCI_CTRL_RWC; | |
556 | ohci->hc_control |= OHCI_USB_RESUME; | |
557 | temp = 10 /* msec wait */; | |
558 | break; | |
559 | // case OHCI_USB_RESET: | |
560 | default: | |
561 | ohci->hc_control &= OHCI_CTRL_RWC; | |
562 | ohci->hc_control |= OHCI_USB_RESET; | |
563 | temp = 50 /* msec wait */; | |
564 | break; | |
565 | } | |
566 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
567 | // flush the writes | |
568 | (void) ohci_readl (ohci, &ohci->regs->control); | |
569 | msleep(temp); | |
570 | temp = roothub_a (ohci); | |
571 | if (!(temp & RH_A_NPS)) { | |
1da177e4 | 572 | /* power down each port */ |
fdd13b36 | 573 | for (temp = 0; temp < ohci->num_ports; temp++) |
1da177e4 LT |
574 | ohci_writel (ohci, RH_PS_LSDA, |
575 | &ohci->regs->roothub.portstatus [temp]); | |
576 | } | |
577 | // flush those writes | |
578 | (void) ohci_readl (ohci, &ohci->regs->control); | |
579 | memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); | |
580 | ||
581 | /* 2msec timelimit here means no irqs/preempt */ | |
582 | spin_lock_irq (&ohci->lock); | |
583 | ||
584 | retry: | |
585 | /* HC Reset requires max 10 us delay */ | |
586 | ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
587 | temp = 30; /* ... allow extra time */ | |
588 | while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { | |
589 | if (--temp == 0) { | |
590 | spin_unlock_irq (&ohci->lock); | |
591 | ohci_err (ohci, "USB HC reset timed out!\n"); | |
592 | return -1; | |
593 | } | |
594 | udelay (1); | |
595 | } | |
596 | ||
597 | /* now we're in the SUSPEND state ... must go OPERATIONAL | |
598 | * within 2msec else HC enters RESUME | |
599 | * | |
600 | * ... but some hardware won't init fmInterval "by the book" | |
601 | * (SiS, OPTi ...), so reset again instead. SiS doesn't need | |
602 | * this if we write fmInterval after we're OPERATIONAL. | |
603 | * Unclear about ALi, ServerWorks, and others ... this could | |
604 | * easily be a longstanding bug in chip init on Linux. | |
605 | */ | |
606 | if (ohci->flags & OHCI_QUIRK_INITRESET) { | |
607 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
608 | // flush those writes | |
609 | (void) ohci_readl (ohci, &ohci->regs->control); | |
610 | } | |
611 | ||
612 | /* Tell the controller where the control and bulk lists are | |
613 | * The lists are empty now. */ | |
614 | ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); | |
615 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); | |
616 | ||
617 | /* a reset clears this */ | |
618 | ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); | |
619 | ||
620 | periodic_reinit (ohci); | |
621 | ||
622 | /* some OHCI implementations are finicky about how they init. | |
623 | * bogus values here mean not even enumeration could work. | |
624 | */ | |
625 | if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 | |
626 | || !ohci_readl (ohci, &ohci->regs->periodicstart)) { | |
627 | if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { | |
628 | ohci->flags |= OHCI_QUIRK_INITRESET; | |
629 | ohci_dbg (ohci, "enabling initreset quirk\n"); | |
630 | goto retry; | |
631 | } | |
632 | spin_unlock_irq (&ohci->lock); | |
633 | ohci_err (ohci, "init err (%08x %04x)\n", | |
634 | ohci_readl (ohci, &ohci->regs->fminterval), | |
635 | ohci_readl (ohci, &ohci->regs->periodicstart)); | |
636 | return -EOVERFLOW; | |
637 | } | |
638 | ||
d413984a DB |
639 | /* use rhsc irqs after khubd is fully initialized */ |
640 | hcd->poll_rh = 1; | |
641 | hcd->uses_new_polling = 1; | |
642 | ||
643 | /* start controller operations */ | |
1da177e4 | 644 | ohci->hc_control &= OHCI_CTRL_RWC; |
d413984a DB |
645 | ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; |
646 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
6a9062f3 | 647 | hcd->state = HC_STATE_RUNNING; |
1da177e4 LT |
648 | |
649 | /* wake on ConnectStatusChange, matching external hubs */ | |
650 | ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); | |
651 | ||
652 | /* Choose the interrupts we care about now, others later on demand */ | |
653 | mask = OHCI_INTR_INIT; | |
d413984a | 654 | ohci_writel (ohci, ~0, &ohci->regs->intrstatus); |
1da177e4 LT |
655 | ohci_writel (ohci, mask, &ohci->regs->intrenable); |
656 | ||
657 | /* handle root hub init quirks ... */ | |
658 | temp = roothub_a (ohci); | |
659 | temp &= ~(RH_A_PSM | RH_A_OCPM); | |
660 | if (ohci->flags & OHCI_QUIRK_SUPERIO) { | |
661 | /* NSC 87560 and maybe others */ | |
662 | temp |= RH_A_NOCP; | |
663 | temp &= ~(RH_A_POTPGT | RH_A_NPS); | |
664 | ohci_writel (ohci, temp, &ohci->regs->roothub.a); | |
665 | } else if ((ohci->flags & OHCI_QUIRK_AMD756) || distrust_firmware) { | |
666 | /* hub power always on; required for AMD-756 and some | |
667 | * Mac platforms. ganged overcurrent reporting, if any. | |
668 | */ | |
669 | temp |= RH_A_NPS; | |
670 | ohci_writel (ohci, temp, &ohci->regs->roothub.a); | |
671 | } | |
672 | ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); | |
673 | ohci_writel (ohci, (temp & RH_A_NPS) ? 0 : RH_B_PPCM, | |
674 | &ohci->regs->roothub.b); | |
675 | // flush those writes | |
676 | (void) ohci_readl (ohci, &ohci->regs->control); | |
677 | ||
d413984a | 678 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
1da177e4 LT |
679 | spin_unlock_irq (&ohci->lock); |
680 | ||
681 | // POTPGT delay is bits 24-31, in 2 ms units. | |
682 | mdelay ((temp >> 23) & 0x1fe); | |
6a9062f3 | 683 | hcd->state = HC_STATE_RUNNING; |
1da177e4 LT |
684 | |
685 | ohci_dump (ohci, 1); | |
686 | ||
1da177e4 LT |
687 | return 0; |
688 | } | |
689 | ||
690 | /*-------------------------------------------------------------------------*/ | |
691 | ||
692 | /* an interrupt happens */ | |
693 | ||
7d12e780 | 694 | static irqreturn_t ohci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
695 | { |
696 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
697 | struct ohci_regs __iomem *regs = ohci->regs; | |
698 | int ints; | |
699 | ||
700 | /* we can eliminate a (slow) ohci_readl() | |
701 | if _only_ WDH caused this irq */ | |
702 | if ((ohci->hcca->done_head != 0) | |
703 | && ! (hc32_to_cpup (ohci, &ohci->hcca->done_head) | |
704 | & 0x01)) { | |
705 | ints = OHCI_INTR_WDH; | |
706 | ||
707 | /* cardbus/... hardware gone before remove() */ | |
708 | } else if ((ints = ohci_readl (ohci, ®s->intrstatus)) == ~(u32)0) { | |
709 | disable (ohci); | |
710 | ohci_dbg (ohci, "device removed!\n"); | |
711 | return IRQ_HANDLED; | |
712 | ||
713 | /* interrupt for some other device? */ | |
714 | } else if ((ints &= ohci_readl (ohci, ®s->intrenable)) == 0) { | |
715 | return IRQ_NOTMINE; | |
d413984a DB |
716 | } |
717 | ||
d413984a DB |
718 | if (ints & OHCI_INTR_RHSC) { |
719 | ohci_vdbg (ohci, "rhsc\n"); | |
d413984a DB |
720 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
721 | ohci_writel (ohci, OHCI_INTR_RHSC, ®s->intrstatus); | |
722 | usb_hcd_poll_rh_status(hcd); | |
723 | } | |
1da177e4 LT |
724 | |
725 | if (ints & OHCI_INTR_UE) { | |
726 | disable (ohci); | |
727 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); | |
728 | // e.g. due to PCI Master/Target Abort | |
729 | ||
730 | ohci_dump (ohci, 1); | |
731 | ohci_usb_reset (ohci); | |
732 | } | |
733 | ||
734 | if (ints & OHCI_INTR_RD) { | |
735 | ohci_vdbg (ohci, "resume detect\n"); | |
e0fd3cbc | 736 | ohci_writel (ohci, OHCI_INTR_RD, ®s->intrstatus); |
8d1a243b AS |
737 | hcd->poll_rh = 1; |
738 | if (ohci->autostop) { | |
739 | spin_lock (&ohci->lock); | |
740 | ohci_rh_resume (ohci); | |
741 | spin_unlock (&ohci->lock); | |
742 | } else | |
f197b2c5 | 743 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
744 | } |
745 | ||
746 | if (ints & OHCI_INTR_WDH) { | |
747 | if (HC_IS_RUNNING(hcd->state)) | |
8d1a243b | 748 | ohci_writel (ohci, OHCI_INTR_WDH, ®s->intrdisable); |
1da177e4 | 749 | spin_lock (&ohci->lock); |
7d12e780 | 750 | dl_done_list (ohci); |
1da177e4 LT |
751 | spin_unlock (&ohci->lock); |
752 | if (HC_IS_RUNNING(hcd->state)) | |
753 | ohci_writel (ohci, OHCI_INTR_WDH, ®s->intrenable); | |
754 | } | |
755 | ||
756 | /* could track INTR_SO to reduce available PCI/... bandwidth */ | |
757 | ||
758 | /* handle any pending URB/ED unlinks, leaving INTR_SF enabled | |
759 | * when there's still unlinking to be done (next frame). | |
760 | */ | |
761 | spin_lock (&ohci->lock); | |
762 | if (ohci->ed_rm_list) | |
7d12e780 | 763 | finish_unlinks (ohci, ohci_frame_no(ohci)); |
1da177e4 LT |
764 | if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list |
765 | && HC_IS_RUNNING(hcd->state)) | |
766 | ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); | |
767 | spin_unlock (&ohci->lock); | |
768 | ||
769 | if (HC_IS_RUNNING(hcd->state)) { | |
770 | ohci_writel (ohci, ints, ®s->intrstatus); | |
771 | ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); | |
772 | // flush those writes | |
773 | (void) ohci_readl (ohci, &ohci->regs->control); | |
774 | } | |
775 | ||
776 | return IRQ_HANDLED; | |
777 | } | |
778 | ||
779 | /*-------------------------------------------------------------------------*/ | |
780 | ||
781 | static void ohci_stop (struct usb_hcd *hcd) | |
782 | { | |
783 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
784 | ||
785 | ohci_dbg (ohci, "stop %s controller (state 0x%02x)\n", | |
786 | hcfs2string (ohci->hc_control & OHCI_CTRL_HCFS), | |
787 | hcd->state); | |
788 | ohci_dump (ohci, 1); | |
789 | ||
790 | flush_scheduled_work(); | |
791 | ||
792 | ohci_usb_reset (ohci); | |
793 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
71795c1d PZ |
794 | free_irq(hcd->irq, hcd); |
795 | hcd->irq = -1; | |
796 | ||
1da177e4 LT |
797 | remove_debug_files (ohci); |
798 | ohci_mem_cleanup (ohci); | |
799 | if (ohci->hcca) { | |
800 | dma_free_coherent (hcd->self.controller, | |
801 | sizeof *ohci->hcca, | |
802 | ohci->hcca, ohci->hcca_dma); | |
803 | ohci->hcca = NULL; | |
804 | ohci->hcca_dma = 0; | |
805 | } | |
806 | } | |
807 | ||
808 | /*-------------------------------------------------------------------------*/ | |
809 | ||
810 | /* must not be called from interrupt context */ | |
811 | ||
8ad7fe16 | 812 | #ifdef CONFIG_PM |
1da177e4 LT |
813 | |
814 | static int ohci_restart (struct ohci_hcd *ohci) | |
815 | { | |
816 | int temp; | |
817 | int i; | |
818 | struct urb_priv *priv; | |
1da177e4 LT |
819 | |
820 | /* mark any devices gone, so they do nothing till khubd disconnects. | |
821 | * recycle any "live" eds/tds (and urbs) right away. | |
822 | * later, khubd disconnect processing will recycle the other state, | |
823 | * (either as disconnect/reconnect, or maybe someday as a reset). | |
824 | */ | |
825 | spin_lock_irq(&ohci->lock); | |
826 | disable (ohci); | |
1c50c317 | 827 | usb_root_hub_lost_power(ohci_to_hcd(ohci)->self.root_hub); |
1da177e4 LT |
828 | if (!list_empty (&ohci->pending)) |
829 | ohci_dbg(ohci, "abort schedule...\n"); | |
830 | list_for_each_entry (priv, &ohci->pending, pending) { | |
831 | struct urb *urb = priv->td[0]->urb; | |
832 | struct ed *ed = priv->ed; | |
833 | ||
834 | switch (ed->state) { | |
835 | case ED_OPER: | |
836 | ed->state = ED_UNLINK; | |
837 | ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); | |
838 | ed_deschedule (ohci, ed); | |
839 | ||
840 | ed->ed_next = ohci->ed_rm_list; | |
841 | ed->ed_prev = NULL; | |
842 | ohci->ed_rm_list = ed; | |
843 | /* FALLTHROUGH */ | |
844 | case ED_UNLINK: | |
845 | break; | |
846 | default: | |
847 | ohci_dbg(ohci, "bogus ed %p state %d\n", | |
848 | ed, ed->state); | |
849 | } | |
850 | ||
851 | spin_lock (&urb->lock); | |
852 | urb->status = -ESHUTDOWN; | |
853 | spin_unlock (&urb->lock); | |
854 | } | |
7d12e780 | 855 | finish_unlinks (ohci, 0); |
1da177e4 LT |
856 | spin_unlock_irq(&ohci->lock); |
857 | ||
858 | /* paranoia, in case that didn't work: */ | |
859 | ||
860 | /* empty the interrupt branches */ | |
861 | for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; | |
862 | for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; | |
863 | ||
864 | /* no EDs to remove */ | |
865 | ohci->ed_rm_list = NULL; | |
866 | ||
867 | /* empty control and bulk lists */ | |
868 | ohci->ed_controltail = NULL; | |
869 | ohci->ed_bulktail = NULL; | |
870 | ||
871 | if ((temp = ohci_run (ohci)) < 0) { | |
872 | ohci_err (ohci, "can't restart, %d\n", temp); | |
873 | return temp; | |
874 | } else { | |
875 | /* here we "know" root ports should always stay powered, | |
876 | * and that if we try to turn them back on the root hub | |
877 | * will respond to CSC processing. | |
878 | */ | |
fdd13b36 | 879 | i = ohci->num_ports; |
1da177e4 LT |
880 | while (i--) |
881 | ohci_writel (ohci, RH_PS_PSS, | |
839ab1d4 | 882 | &ohci->regs->roothub.portstatus [i]); |
1da177e4 LT |
883 | ohci_dbg (ohci, "restart complete\n"); |
884 | } | |
885 | return 0; | |
886 | } | |
887 | #endif | |
888 | ||
889 | /*-------------------------------------------------------------------------*/ | |
890 | ||
891 | #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC | |
892 | ||
893 | MODULE_AUTHOR (DRIVER_AUTHOR); | |
894 | MODULE_DESCRIPTION (DRIVER_INFO); | |
895 | MODULE_LICENSE ("GPL"); | |
896 | ||
897 | #ifdef CONFIG_PCI | |
898 | #include "ohci-pci.c" | |
899 | #endif | |
900 | ||
901 | #ifdef CONFIG_SA1111 | |
902 | #include "ohci-sa1111.c" | |
903 | #endif | |
904 | ||
3eb0c5f4 BD |
905 | #ifdef CONFIG_ARCH_S3C2410 |
906 | #include "ohci-s3c2410.c" | |
907 | #endif | |
908 | ||
1da177e4 LT |
909 | #ifdef CONFIG_ARCH_OMAP |
910 | #include "ohci-omap.c" | |
911 | #endif | |
912 | ||
913 | #ifdef CONFIG_ARCH_LH7A404 | |
914 | #include "ohci-lh7a404.c" | |
915 | #endif | |
916 | ||
917 | #ifdef CONFIG_PXA27x | |
918 | #include "ohci-pxa27x.c" | |
919 | #endif | |
920 | ||
a5b7474a LB |
921 | #ifdef CONFIG_ARCH_EP93XX |
922 | #include "ohci-ep93xx.c" | |
923 | #endif | |
924 | ||
1da177e4 LT |
925 | #ifdef CONFIG_SOC_AU1X00 |
926 | #include "ohci-au1xxx.c" | |
927 | #endif | |
928 | ||
929 | #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC | |
930 | #include "ohci-ppc-soc.c" | |
931 | #endif | |
932 | ||
0365ee0a | 933 | #if defined(CONFIG_ARCH_AT91RM9200) || defined(CONFIG_ARCH_AT91SAM9261) |
39a269c0 AV |
934 | #include "ohci-at91.c" |
935 | #endif | |
936 | ||
60bbfc84 VW |
937 | #ifdef CONFIG_ARCH_PNX4008 |
938 | #include "ohci-pnx4008.c" | |
939 | #endif | |
940 | ||
1da177e4 LT |
941 | #if !(defined(CONFIG_PCI) \ |
942 | || defined(CONFIG_SA1111) \ | |
3eb0c5f4 | 943 | || defined(CONFIG_ARCH_S3C2410) \ |
1da177e4 LT |
944 | || defined(CONFIG_ARCH_OMAP) \ |
945 | || defined (CONFIG_ARCH_LH7A404) \ | |
946 | || defined (CONFIG_PXA27x) \ | |
a5b7474a | 947 | || defined (CONFIG_ARCH_EP93XX) \ |
1da177e4 LT |
948 | || defined (CONFIG_SOC_AU1X00) \ |
949 | || defined (CONFIG_USB_OHCI_HCD_PPC_SOC) \ | |
39a269c0 | 950 | || defined (CONFIG_ARCH_AT91RM9200) \ |
0365ee0a | 951 | || defined (CONFIG_ARCH_AT91SAM9261) \ |
60bbfc84 | 952 | || defined (CONFIG_ARCH_PNX4008) \ |
1da177e4 LT |
953 | ) |
954 | #error "missing bus glue for ohci-hcd" | |
955 | #endif |