Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0+ |
62194244 JH |
2 | /* |
3 | * SAMSUNG EXYNOS USB HOST OHCI Controller | |
4 | * | |
5 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
6 | * Author: Jingoo Han <jg1.han@samsung.com> | |
62194244 JH |
7 | */ |
8 | ||
9 | #include <linux/clk.h> | |
50a97e05 MG |
10 | #include <linux/dma-mapping.h> |
11 | #include <linux/io.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
d5138930 | 14 | #include <linux/of.h> |
62194244 | 15 | #include <linux/platform_device.h> |
7d28e54b | 16 | #include <linux/phy/phy.h> |
50a97e05 MG |
17 | #include <linux/usb.h> |
18 | #include <linux/usb/hcd.h> | |
50a97e05 MG |
19 | |
20 | #include "ohci.h" | |
21 | ||
dea7b202 | 22 | #define DRIVER_DESC "OHCI Exynos driver" |
50a97e05 | 23 | |
50a97e05 MG |
24 | static struct hc_driver __read_mostly exynos_ohci_hc_driver; |
25 | ||
26 | #define to_exynos_ohci(hcd) (struct exynos_ohci_hcd *)(hcd_to_ohci(hcd)->priv) | |
62194244 | 27 | |
7d28e54b VG |
28 | #define PHY_NUMBER 3 |
29 | ||
62194244 | 30 | struct exynos_ohci_hcd { |
62194244 | 31 | struct clk *clk; |
01d40714 | 32 | struct device_node *of_node; |
2db94162 | 33 | struct phy *phy[PHY_NUMBER]; |
214b606e | 34 | bool legacy_phy; |
62194244 JH |
35 | }; |
36 | ||
7d28e54b VG |
37 | static int exynos_ohci_get_phy(struct device *dev, |
38 | struct exynos_ohci_hcd *exynos_ohci) | |
39 | { | |
40 | struct device_node *child; | |
41 | struct phy *phy; | |
214b606e | 42 | int phy_number, num_phys; |
2db94162 | 43 | int ret; |
7d28e54b | 44 | |
2db94162 | 45 | /* Get PHYs for the controller */ |
214b606e MS |
46 | num_phys = of_count_phandle_with_args(dev->of_node, "phys", |
47 | "#phy-cells"); | |
48 | for (phy_number = 0; phy_number < num_phys; phy_number++) { | |
49 | phy = devm_of_phy_get_by_index(dev, dev->of_node, phy_number); | |
50 | if (IS_ERR(phy)) | |
51 | return PTR_ERR(phy); | |
52 | exynos_ohci->phy[phy_number] = phy; | |
53 | } | |
54 | if (num_phys > 0) | |
55 | return 0; | |
56 | ||
57 | /* Get PHYs using legacy bindings */ | |
7d28e54b VG |
58 | for_each_available_child_of_node(dev->of_node, child) { |
59 | ret = of_property_read_u32(child, "reg", &phy_number); | |
60 | if (ret) { | |
61 | dev_err(dev, "Failed to parse device tree\n"); | |
62 | of_node_put(child); | |
63 | return ret; | |
64 | } | |
65 | ||
66 | if (phy_number >= PHY_NUMBER) { | |
67 | dev_err(dev, "Invalid number of PHYs\n"); | |
68 | of_node_put(child); | |
69 | return -EINVAL; | |
70 | } | |
71 | ||
41a435e3 | 72 | phy = devm_of_phy_optional_get(dev, child, NULL); |
2db94162 | 73 | exynos_ohci->phy[phy_number] = phy; |
2db94162 | 74 | if (IS_ERR(phy)) { |
41a435e3 GU |
75 | of_node_put(child); |
76 | return PTR_ERR(phy); | |
2f7f41c7 | 77 | } |
7d28e54b VG |
78 | } |
79 | ||
214b606e | 80 | exynos_ohci->legacy_phy = true; |
2db94162 | 81 | return 0; |
7d28e54b VG |
82 | } |
83 | ||
84 | static int exynos_ohci_phy_enable(struct device *dev) | |
ed993bf1 | 85 | { |
54969ed6 | 86 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
50a97e05 | 87 | struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd); |
7d28e54b VG |
88 | int i; |
89 | int ret = 0; | |
90 | ||
7d28e54b | 91 | for (i = 0; ret == 0 && i < PHY_NUMBER; i++) |
41a435e3 | 92 | ret = phy_power_on(exynos_ohci->phy[i]); |
7d28e54b VG |
93 | if (ret) |
94 | for (i--; i >= 0; i--) | |
41a435e3 | 95 | phy_power_off(exynos_ohci->phy[i]); |
7d28e54b VG |
96 | |
97 | return ret; | |
ed993bf1 VG |
98 | } |
99 | ||
54969ed6 | 100 | static void exynos_ohci_phy_disable(struct device *dev) |
ed993bf1 | 101 | { |
54969ed6 | 102 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
50a97e05 | 103 | struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd); |
7d28e54b | 104 | int i; |
ed993bf1 | 105 | |
7d28e54b | 106 | for (i = 0; i < PHY_NUMBER; i++) |
41a435e3 | 107 | phy_power_off(exynos_ohci->phy[i]); |
ed993bf1 VG |
108 | } |
109 | ||
41ac7b3a | 110 | static int exynos_ohci_probe(struct platform_device *pdev) |
62194244 | 111 | { |
62194244 JH |
112 | struct exynos_ohci_hcd *exynos_ohci; |
113 | struct usb_hcd *hcd; | |
62194244 JH |
114 | struct resource *res; |
115 | int irq; | |
116 | int err; | |
117 | ||
d5138930 VG |
118 | /* |
119 | * Right now device-tree probed devices don't get dma_mask set. | |
120 | * Since shared usb code relies on it, set it here for now. | |
121 | * Once we move to full device tree support this will vanish off. | |
122 | */ | |
e1fd7341 | 123 | err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
22d9d8e8 RK |
124 | if (err) |
125 | return err; | |
d5138930 | 126 | |
50a97e05 MG |
127 | hcd = usb_create_hcd(&exynos_ohci_hc_driver, |
128 | &pdev->dev, dev_name(&pdev->dev)); | |
129 | if (!hcd) { | |
130 | dev_err(&pdev->dev, "Unable to create HCD\n"); | |
62194244 | 131 | return -ENOMEM; |
50a97e05 MG |
132 | } |
133 | ||
134 | exynos_ohci = to_exynos_ohci(hcd); | |
62194244 | 135 | |
7d28e54b VG |
136 | err = exynos_ohci_get_phy(&pdev->dev, exynos_ohci); |
137 | if (err) | |
3d284c95 | 138 | goto fail_io; |
ed993bf1 | 139 | |
3d284c95 | 140 | exynos_ohci->clk = devm_clk_get_enabled(&pdev->dev, "usbhost"); |
62194244 JH |
141 | |
142 | if (IS_ERR(exynos_ohci->clk)) { | |
143 | dev_err(&pdev->dev, "Failed to get usbhost clock\n"); | |
144 | err = PTR_ERR(exynos_ohci->clk); | |
3d284c95 | 145 | goto fail_io; |
62194244 JH |
146 | } |
147 | ||
31a7b792 | 148 | hcd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
bae00c1a VG |
149 | if (IS_ERR(hcd->regs)) { |
150 | err = PTR_ERR(hcd->regs); | |
62194244 JH |
151 | goto fail_io; |
152 | } | |
b87a9c52 VB |
153 | hcd->rsrc_start = res->start; |
154 | hcd->rsrc_len = resource_size(res); | |
62194244 JH |
155 | |
156 | irq = platform_get_irq(pdev, 0); | |
1d416983 TB |
157 | if (irq < 0) { |
158 | err = irq; | |
390a0a78 | 159 | goto fail_io; |
62194244 JH |
160 | } |
161 | ||
50a97e05 | 162 | platform_set_drvdata(pdev, hcd); |
62194244 | 163 | |
7d28e54b VG |
164 | err = exynos_ohci_phy_enable(&pdev->dev); |
165 | if (err) { | |
166 | dev_err(&pdev->dev, "Failed to enable USB phy\n"); | |
167 | goto fail_io; | |
168 | } | |
62194244 | 169 | |
01d40714 | 170 | /* |
214b606e MS |
171 | * Workaround: reset of_node pointer to avoid conflict between legacy |
172 | * Exynos OHCI port subnodes and generic USB device bindings | |
01d40714 MS |
173 | */ |
174 | exynos_ohci->of_node = pdev->dev.of_node; | |
214b606e MS |
175 | if (exynos_ohci->legacy_phy) |
176 | pdev->dev.of_node = NULL; | |
01d40714 | 177 | |
62194244 JH |
178 | err = usb_add_hcd(hcd, irq, IRQF_SHARED); |
179 | if (err) { | |
180 | dev_err(&pdev->dev, "Failed to add USB HCD\n"); | |
ed993bf1 | 181 | goto fail_add_hcd; |
62194244 | 182 | } |
3c9740a1 | 183 | device_wakeup_enable(hcd->self.controller); |
62194244 JH |
184 | return 0; |
185 | ||
ed993bf1 | 186 | fail_add_hcd: |
54969ed6 | 187 | exynos_ohci_phy_disable(&pdev->dev); |
01d40714 | 188 | pdev->dev.of_node = exynos_ohci->of_node; |
62194244 | 189 | fail_io: |
62194244 | 190 | usb_put_hcd(hcd); |
62194244 JH |
191 | return err; |
192 | } | |
193 | ||
16fe06cd | 194 | static void exynos_ohci_remove(struct platform_device *pdev) |
62194244 | 195 | { |
50a97e05 MG |
196 | struct usb_hcd *hcd = platform_get_drvdata(pdev); |
197 | struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd); | |
62194244 | 198 | |
01d40714 MS |
199 | pdev->dev.of_node = exynos_ohci->of_node; |
200 | ||
62194244 JH |
201 | usb_remove_hcd(hcd); |
202 | ||
54969ed6 | 203 | exynos_ohci_phy_disable(&pdev->dev); |
62194244 | 204 | |
62194244 | 205 | usb_put_hcd(hcd); |
62194244 JH |
206 | } |
207 | ||
208 | static void exynos_ohci_shutdown(struct platform_device *pdev) | |
209 | { | |
50a97e05 | 210 | struct usb_hcd *hcd = platform_get_drvdata(pdev); |
62194244 JH |
211 | |
212 | if (hcd->driver->shutdown) | |
213 | hcd->driver->shutdown(hcd); | |
214 | } | |
215 | ||
62194244 JH |
216 | static int exynos_ohci_suspend(struct device *dev) |
217 | { | |
50a97e05 MG |
218 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
219 | struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd); | |
14982e31 | 220 | bool do_wakeup = device_may_wakeup(dev); |
14982e31 | 221 | int rc = ohci_suspend(hcd, do_wakeup); |
62194244 | 222 | |
14982e31 MG |
223 | if (rc) |
224 | return rc; | |
066ba8e0 | 225 | |
54969ed6 | 226 | exynos_ohci_phy_disable(dev); |
e864abed | 227 | |
c05c946c | 228 | clk_disable_unprepare(exynos_ohci->clk); |
e864abed | 229 | |
14982e31 | 230 | return 0; |
62194244 JH |
231 | } |
232 | ||
233 | static int exynos_ohci_resume(struct device *dev) | |
234 | { | |
50a97e05 MG |
235 | struct usb_hcd *hcd = dev_get_drvdata(dev); |
236 | struct exynos_ohci_hcd *exynos_ohci = to_exynos_ohci(hcd); | |
7d28e54b | 237 | int ret; |
62194244 | 238 | |
c05c946c | 239 | clk_prepare_enable(exynos_ohci->clk); |
e864abed | 240 | |
7d28e54b VG |
241 | ret = exynos_ohci_phy_enable(dev); |
242 | if (ret) { | |
243 | dev_err(dev, "Failed to enable USB phy\n"); | |
244 | clk_disable_unprepare(exynos_ohci->clk); | |
245 | return ret; | |
246 | } | |
62194244 | 247 | |
cfa49b4b | 248 | ohci_resume(hcd, false); |
62194244 JH |
249 | |
250 | return 0; | |
251 | } | |
62194244 | 252 | |
50a97e05 MG |
253 | static const struct ohci_driver_overrides exynos_overrides __initconst = { |
254 | .extra_priv_size = sizeof(struct exynos_ohci_hcd), | |
255 | }; | |
256 | ||
a6a243b6 AM |
257 | static DEFINE_SIMPLE_DEV_PM_OPS(exynos_ohci_pm_ops, |
258 | exynos_ohci_suspend, exynos_ohci_resume); | |
62194244 | 259 | |
d5138930 VG |
260 | #ifdef CONFIG_OF |
261 | static const struct of_device_id exynos_ohci_match[] = { | |
6e247777 | 262 | { .compatible = "samsung,exynos4210-ohci" }, |
d5138930 VG |
263 | {}, |
264 | }; | |
265 | MODULE_DEVICE_TABLE(of, exynos_ohci_match); | |
266 | #endif | |
267 | ||
62194244 JH |
268 | static struct platform_driver exynos_ohci_driver = { |
269 | .probe = exynos_ohci_probe, | |
16fe06cd | 270 | .remove_new = exynos_ohci_remove, |
62194244 JH |
271 | .shutdown = exynos_ohci_shutdown, |
272 | .driver = { | |
273 | .name = "exynos-ohci", | |
a6a243b6 | 274 | .pm = pm_ptr(&exynos_ohci_pm_ops), |
d5138930 | 275 | .of_match_table = of_match_ptr(exynos_ohci_match), |
62194244 JH |
276 | } |
277 | }; | |
50a97e05 MG |
278 | static int __init ohci_exynos_init(void) |
279 | { | |
280 | if (usb_disabled()) | |
281 | return -ENODEV; | |
282 | ||
50a97e05 MG |
283 | ohci_init_driver(&exynos_ohci_hc_driver, &exynos_overrides); |
284 | return platform_driver_register(&exynos_ohci_driver); | |
285 | } | |
286 | module_init(ohci_exynos_init); | |
287 | ||
288 | static void __exit ohci_exynos_cleanup(void) | |
289 | { | |
290 | platform_driver_unregister(&exynos_ohci_driver); | |
291 | } | |
292 | module_exit(ohci_exynos_cleanup); | |
62194244 JH |
293 | |
294 | MODULE_ALIAS("platform:exynos-ohci"); | |
295 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); | |
9fdce69f | 296 | MODULE_DESCRIPTION("OHCI support for Samsung S5P/Exynos SoC Series"); |
50a97e05 | 297 | MODULE_LICENSE("GPL v2"); |