Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 LT |
2 | /* |
3 | * Copyright (c) 2001-2002 by David Brownell | |
1da177e4 LT |
4 | */ |
5 | ||
6 | #ifndef __LINUX_EHCI_HCD_H | |
7 | #define __LINUX_EHCI_HCD_H | |
8 | ||
9 | /* definitions used for the EHCI driver */ | |
10 | ||
6dbd682b SR |
11 | /* |
12 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to | |
13 | * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on | |
14 | * the host controller implementation. | |
15 | * | |
16 | * To facilitate the strongest possible byte-order checking from "sparse" | |
17 | * and so on, we use __leXX unless that's not practical. | |
18 | */ | |
19 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
20 | typedef __u32 __bitwise __hc32; | |
21 | typedef __u16 __bitwise __hc16; | |
22 | #else | |
23 | #define __hc32 __le32 | |
24 | #define __hc16 __le16 | |
25 | #endif | |
26 | ||
411c9403 | 27 | /* statistics can be kept for tuning/monitoring */ |
1c20163d | 28 | #ifdef CONFIG_DYNAMIC_DEBUG |
9ec6e9d3 RQ |
29 | #define EHCI_STATS |
30 | #endif | |
31 | ||
1da177e4 LT |
32 | struct ehci_stats { |
33 | /* irq usage */ | |
34 | unsigned long normal; | |
35 | unsigned long error; | |
99ac5b1e | 36 | unsigned long iaa; |
1da177e4 LT |
37 | unsigned long lost_iaa; |
38 | ||
39 | /* termination of urbs from core */ | |
40 | unsigned long complete; | |
41 | unsigned long unlink; | |
42 | }; | |
43 | ||
ffa0248e AS |
44 | /* |
45 | * Scheduling and budgeting information for periodic transfers, for both | |
46 | * high-speed devices and full/low-speed devices lying behind a TT. | |
47 | */ | |
48 | struct ehci_per_sched { | |
49 | struct usb_device *udev; /* access to the TT */ | |
50 | struct usb_host_endpoint *ep; | |
b35c5009 | 51 | struct list_head ps_list; /* node on ehci_tt's ps_list */ |
ffa0248e | 52 | u16 tt_usecs; /* time on the FS/LS bus */ |
d0ce5c6b | 53 | u16 cs_mask; /* C-mask and S-mask bytes */ |
ffa0248e AS |
54 | u16 period; /* actual period in frames */ |
55 | u16 phase; /* actual phase, frame part */ | |
d0ce5c6b AS |
56 | u8 bw_phase; /* same, for bandwidth |
57 | reservation */ | |
ffa0248e AS |
58 | u8 phase_uf; /* uframe part of the phase */ |
59 | u8 usecs, c_usecs; /* times on the HS bus */ | |
d0ce5c6b AS |
60 | u8 bw_uperiod; /* period in microframes, for |
61 | bandwidth reservation */ | |
62 | u8 bw_period; /* same, in frames */ | |
ffa0248e | 63 | }; |
91a99b5e AS |
64 | #define NO_FRAME 29999 /* frame not assigned yet */ |
65 | ||
1da177e4 | 66 | /* ehci_hcd->lock guards shared data against other CPUs: |
99ac5b1e | 67 | * ehci_hcd: async, unlink, periodic (and shadow), ... |
1da177e4 LT |
68 | * usb_host_endpoint: hcpriv |
69 | * ehci_qh: qh_next, qtd_list | |
70 | * ehci_qtd: qtd_list | |
71 | * | |
72 | * Also, hold this lock when talking to HC registers or | |
73 | * when updating hw_* fields in shared qh/qtd/... structures. | |
74 | */ | |
75 | ||
76 | #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ | |
77 | ||
c0c53dbc AS |
78 | /* |
79 | * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the | |
80 | * controller may be doing DMA. Lower values mean there's no DMA. | |
81 | */ | |
e8799906 AS |
82 | enum ehci_rh_state { |
83 | EHCI_RH_HALTED, | |
84 | EHCI_RH_SUSPENDED, | |
c0c53dbc AS |
85 | EHCI_RH_RUNNING, |
86 | EHCI_RH_STOPPING | |
e8799906 AS |
87 | }; |
88 | ||
d58b4bcc AS |
89 | /* |
90 | * Timer events, ordered by increasing delay length. | |
91 | * Always update event_delays_ns[] and event_handlers[] (defined in | |
92 | * ehci-timer.c) in parallel with this list. | |
93 | */ | |
94 | enum ehci_hrtimer_event { | |
31446610 | 95 | EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ |
3ca9aeba | 96 | EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ |
bf6387bc | 97 | EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ |
df202255 | 98 | EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ |
55934eb3 | 99 | EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ |
87d61912 | 100 | EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */ |
9118f9eb | 101 | EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ |
32830f20 | 102 | EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ |
9d938747 | 103 | EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ |
3ca9aeba | 104 | EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ |
31446610 | 105 | EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ |
18aafe64 | 106 | EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ |
d58b4bcc AS |
107 | EHCI_HRTIMER_NUM_EVENTS /* Must come last */ |
108 | }; | |
109 | #define EHCI_HRTIMER_NO_EVENT 99 | |
110 | ||
1da177e4 | 111 | struct ehci_hcd { /* one per controller */ |
d58b4bcc AS |
112 | /* timing support */ |
113 | enum ehci_hrtimer_event next_hrtimer_event; | |
114 | unsigned enabled_hrtimer_events; | |
115 | ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; | |
116 | struct hrtimer hrtimer; | |
117 | ||
3ca9aeba | 118 | int PSS_poll_count; |
31446610 | 119 | int ASS_poll_count; |
bf6387bc | 120 | int died_poll_count; |
3ca9aeba | 121 | |
56c1e26d DB |
122 | /* glue to PCI and HCD framework */ |
123 | struct ehci_caps __iomem *caps; | |
124 | struct ehci_regs __iomem *regs; | |
125 | struct ehci_dbg_port __iomem *debug; | |
126 | ||
127 | __u32 hcs_params; /* cached register copy */ | |
1da177e4 | 128 | spinlock_t lock; |
e8799906 | 129 | enum ehci_rh_state rh_state; |
1da177e4 | 130 | |
df202255 | 131 | /* general schedule support */ |
361aabf3 AS |
132 | bool scanning:1; |
133 | bool need_rescan:1; | |
df202255 | 134 | bool intr_unlinking:1; |
214ac7a0 | 135 | bool iaa_in_progress:1; |
3c273a05 | 136 | bool async_unlinking:1; |
43fe3a99 | 137 | bool shutdown:1; |
569b394f | 138 | struct ehci_qh *qh_scan_next; |
df202255 | 139 | |
1da177e4 LT |
140 | /* async schedule support */ |
141 | struct ehci_qh *async; | |
3d091a6f | 142 | struct ehci_qh *dummy; /* For AMD quirk use */ |
6e018751 | 143 | struct list_head async_unlink; |
214ac7a0 | 144 | struct list_head async_idle; |
32830f20 | 145 | unsigned async_unlink_cycle; |
31446610 | 146 | unsigned async_count; /* async activity count */ |
87d61912 AS |
147 | __hc32 old_current; /* Test for QH becoming */ |
148 | __hc32 old_token; /* inactive during unlink */ | |
1da177e4 LT |
149 | |
150 | /* periodic schedule support */ | |
151 | #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ | |
152 | unsigned periodic_size; | |
6dbd682b | 153 | __hc32 *periodic; /* hw periodic table */ |
1da177e4 | 154 | dma_addr_t periodic_dma; |
569b394f | 155 | struct list_head intr_qh_list; |
1da177e4 LT |
156 | unsigned i_thresh; /* uframes HC might cache */ |
157 | ||
158 | union ehci_shadow *pshadow; /* mirror hw periodic table */ | |
9118f9eb | 159 | struct list_head intr_unlink_wait; |
6e018751 | 160 | struct list_head intr_unlink; |
9118f9eb | 161 | unsigned intr_unlink_wait_cycle; |
df202255 | 162 | unsigned intr_unlink_cycle; |
f4289078 | 163 | unsigned now_frame; /* frame from HC hardware */ |
c3ee9b76 | 164 | unsigned last_iso_frame; /* last frame scanned for iso */ |
569b394f AS |
165 | unsigned intr_count; /* intr activity count */ |
166 | unsigned isoc_count; /* isoc activity count */ | |
3ca9aeba | 167 | unsigned periodic_count; /* periodic activity count */ |
cc62a7eb KS |
168 | unsigned uframe_periodic_max; /* max periodic time per uframe */ |
169 | ||
1da177e4 | 170 | |
f4289078 | 171 | /* list of itds & sitds completed while now_frame was still active */ |
9aa09d2f | 172 | struct list_head cached_itd_list; |
55934eb3 | 173 | struct ehci_itd *last_itd_to_free; |
0e5f231b | 174 | struct list_head cached_sitd_list; |
55934eb3 | 175 | struct ehci_sitd *last_sitd_to_free; |
9aa09d2f | 176 | |
1da177e4 | 177 | /* per root hub port */ |
9dc3af5e | 178 | unsigned long reset_done[EHCI_MAX_ROOT_PORTS]; |
383975d7 | 179 | |
57e06c11 AS |
180 | /* bit vectors (one bit per port) */ |
181 | unsigned long bus_suspended; /* which ports were | |
182 | already suspended at the start of a bus suspend */ | |
183 | unsigned long companion_ports; /* which ports are | |
184 | dedicated to the companion controller */ | |
383975d7 AS |
185 | unsigned long owned_ports; /* which ports are |
186 | owned by the companion during a bus suspend */ | |
d1f114d1 AS |
187 | unsigned long port_c_suspend; /* which ports have |
188 | the change-suspend feature turned on */ | |
eafe5b99 AS |
189 | unsigned long suspended_ports; /* which ports are |
190 | suspended */ | |
a448e4dc AS |
191 | unsigned long resuming_ports; /* which ports have |
192 | started to resume */ | |
1da177e4 LT |
193 | |
194 | /* per-HC memory pools (could be per-bus, but ...) */ | |
195 | struct dma_pool *qh_pool; /* qh per active urb */ | |
196 | struct dma_pool *qtd_pool; /* one or more per qh */ | |
197 | struct dma_pool *itd_pool; /* itd per iso urb */ | |
198 | struct dma_pool *sitd_pool; /* sitd per split iso urb */ | |
199 | ||
68335e81 | 200 | unsigned random_frame; |
1da177e4 | 201 | unsigned long next_statechange; |
ee4ecb8a | 202 | ktime_t last_periodic_enable; |
1da177e4 LT |
203 | u32 command; |
204 | ||
8cd42e97 | 205 | /* SILICON QUIRKS */ |
f8aeb3bb | 206 | unsigned no_selective_suspend:1; |
8cd42e97 | 207 | unsigned has_fsl_port_bug:1; /* FreeScale */ |
f8786a91 | 208 | unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */ |
9d4b8270 | 209 | unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */ |
083522d7 | 210 | unsigned big_endian_mmio:1; |
6dbd682b | 211 | unsigned big_endian_desc:1; |
c430131a | 212 | unsigned big_endian_capbase:1; |
796bcae7 | 213 | unsigned has_amcc_usb23:1; |
403dbd36 | 214 | unsigned need_io_watchdog:1; |
ad93562b | 215 | unsigned amd_pll_fix:1; |
3d091a6f | 216 | unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ |
2f7ac6c1 | 217 | unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ |
68aa95d5 | 218 | unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ |
e6604a7f | 219 | unsigned need_oc_pp_cycle:1; /* MPC834X port power */ |
feffe09f | 220 | unsigned imx28_write_fix:1; /* For Freescale i.MX28 */ |
796bcae7 VB |
221 | |
222 | /* required for usb32 quirk */ | |
223 | #define OHCI_CTRL_HCFS (3 << 6) | |
224 | #define OHCI_USB_OPER (2 << 6) | |
225 | #define OHCI_USB_SUSPEND (3 << 6) | |
226 | ||
227 | #define OHCI_HCCTRL_OFFSET 0x4 | |
228 | #define OHCI_HCCTRL_LEN 0x4 | |
229 | __hc32 *ohci_hcctrl_reg; | |
331ac6b2 | 230 | unsigned has_hostpc:1; |
2cdcec4f | 231 | unsigned has_tdi_phy_lpm:1; |
5a9cdf33 | 232 | unsigned has_ppcd:1; /* support per-port change bits */ |
f8aeb3bb | 233 | u8 sbrn; /* packed release number */ |
1da177e4 | 234 | |
1da177e4 LT |
235 | /* irq statistics */ |
236 | #ifdef EHCI_STATS | |
237 | struct ehci_stats stats; | |
a0ef2bdf | 238 | # define INCR(x) ((x)++) |
1da177e4 | 239 | #else |
a0ef2bdf | 240 | # define INCR(x) do {} while (0) |
694cc208 TJ |
241 | #endif |
242 | ||
243 | /* debug files */ | |
1c20163d | 244 | #ifdef CONFIG_DYNAMIC_DEBUG |
694cc208 | 245 | struct dentry *debug_dir; |
1da177e4 | 246 | #endif |
9debc179 | 247 | |
d0ce5c6b AS |
248 | /* bandwidth usage */ |
249 | #define EHCI_BANDWIDTH_SIZE 64 | |
250 | #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3) | |
251 | u8 bandwidth[EHCI_BANDWIDTH_SIZE]; | |
252 | /* us allocated per uframe */ | |
b35c5009 AS |
253 | u8 tt_budget[EHCI_BANDWIDTH_SIZE]; |
254 | /* us budgeted per uframe */ | |
255 | struct list_head tt_list; | |
d0ce5c6b | 256 | |
9debc179 | 257 | /* platform-specific data -- must come last */ |
6bc3f397 | 258 | unsigned long priv[] __aligned(sizeof(s64)); |
1da177e4 LT |
259 | }; |
260 | ||
53bd6a60 | 261 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
e06e2264 | 262 | static inline struct ehci_hcd *hcd_to_ehci(struct usb_hcd *hcd) |
1da177e4 LT |
263 | { |
264 | return (struct ehci_hcd *) (hcd->hcd_priv); | |
265 | } | |
e06e2264 | 266 | static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci) |
1da177e4 | 267 | { |
e06e2264 | 268 | return container_of((void *) ehci, struct usb_hcd, hcd_priv); |
1da177e4 LT |
269 | } |
270 | ||
1da177e4 LT |
271 | /*-------------------------------------------------------------------------*/ |
272 | ||
0af36739 | 273 | #include <linux/usb/ehci_def.h> |
1da177e4 LT |
274 | |
275 | /*-------------------------------------------------------------------------*/ | |
276 | ||
6dbd682b | 277 | #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) |
1da177e4 LT |
278 | |
279 | /* | |
280 | * EHCI Specification 0.95 Section 3.5 | |
53bd6a60 | 281 | * QTD: describe data transfer components (buffer, direction, ...) |
1da177e4 LT |
282 | * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". |
283 | * | |
284 | * These are associated only with "QH" (Queue Head) structures, | |
285 | * used with control, bulk, and interrupt transfers. | |
286 | */ | |
287 | struct ehci_qtd { | |
288 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
289 | __hc32 hw_next; /* see EHCI 3.5.1 */ |
290 | __hc32 hw_alt_next; /* see EHCI 3.5.2 */ | |
291 | __hc32 hw_token; /* see EHCI 3.5.3 */ | |
1da177e4 LT |
292 | #define QTD_TOGGLE (1 << 31) /* data toggle */ |
293 | #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) | |
294 | #define QTD_IOC (1 << 15) /* interrupt on complete */ | |
295 | #define QTD_CERR(tok) (((tok)>>10) & 0x3) | |
296 | #define QTD_PID(tok) (((tok)>>8) & 0x3) | |
297 | #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
298 | #define QTD_STS_HALT (1 << 6) /* halted on error */ | |
299 | #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
300 | #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ | |
301 | #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ | |
302 | #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
303 | #define QTD_STS_STS (1 << 1) /* split transaction state */ | |
304 | #define QTD_STS_PING (1 << 0) /* issue PING? */ | |
6dbd682b SR |
305 | |
306 | #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) | |
307 | #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) | |
308 | #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) | |
309 | ||
9dc3af5e GB |
310 | __hc32 hw_buf[5]; /* see EHCI 3.5.4 */ |
311 | __hc32 hw_buf_hi[5]; /* Appendix B */ | |
1da177e4 LT |
312 | |
313 | /* the rest is HCD-private */ | |
314 | dma_addr_t qtd_dma; /* qtd address */ | |
315 | struct list_head qtd_list; /* sw qtd list */ | |
316 | struct urb *urb; /* qtd's urb */ | |
317 | size_t length; /* length of buffer */ | |
3a9e742f | 318 | } __aligned(32); |
1da177e4 LT |
319 | |
320 | /* mask NakCnt+T in qh->hw_alt_next */ | |
e06e2264 | 321 | #define QTD_MASK(ehci) cpu_to_hc32(ehci, ~0x1f) |
1da177e4 | 322 | |
e06e2264 | 323 | #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1) |
1da177e4 LT |
324 | |
325 | /*-------------------------------------------------------------------------*/ | |
326 | ||
327 | /* type tag from {qh,itd,sitd,fstn}->hw_next */ | |
10f2b962 | 328 | #define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) |
1da177e4 | 329 | |
6dbd682b SR |
330 | /* |
331 | * Now the following defines are not converted using the | |
551509d2 | 332 | * cpu_to_le32() macro anymore, since we have to support |
6dbd682b SR |
333 | * "dynamic" switching between be and le support, so that the driver |
334 | * can be used on one system with SoC EHCI controller using big-endian | |
335 | * descriptors as well as a normal little-endian PCI EHCI controller. | |
336 | */ | |
1da177e4 | 337 | /* values for that type tag */ |
6dbd682b SR |
338 | #define Q_TYPE_ITD (0 << 1) |
339 | #define Q_TYPE_QH (1 << 1) | |
340 | #define Q_TYPE_SITD (2 << 1) | |
341 | #define Q_TYPE_FSTN (3 << 1) | |
1da177e4 LT |
342 | |
343 | /* next async queue entry, or pointer to interrupt/periodic QH */ | |
10f2b962 GB |
344 | #define QH_NEXT(ehci, dma) \ |
345 | (cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH)) | |
1da177e4 LT |
346 | |
347 | /* for periodic/async schedules and qtd lists, mark end of list */ | |
6dbd682b | 348 | #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ |
1da177e4 LT |
349 | |
350 | /* | |
351 | * Entries in periodic shadow table are pointers to one of four kinds | |
352 | * of data structure. That's dictated by the hardware; a type tag is | |
353 | * encoded in the low bits of the hardware's periodic schedule. Use | |
354 | * Q_NEXT_TYPE to get the tag. | |
355 | * | |
356 | * For entries in the async schedule, the type tag always says "qh". | |
357 | */ | |
358 | union ehci_shadow { | |
53bd6a60 | 359 | struct ehci_qh *qh; /* Q_TYPE_QH */ |
1da177e4 LT |
360 | struct ehci_itd *itd; /* Q_TYPE_ITD */ |
361 | struct ehci_sitd *sitd; /* Q_TYPE_SITD */ | |
362 | struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ | |
6dbd682b | 363 | __hc32 *hw_next; /* (all types) */ |
1da177e4 LT |
364 | void *ptr; |
365 | }; | |
366 | ||
367 | /*-------------------------------------------------------------------------*/ | |
368 | ||
369 | /* | |
370 | * EHCI Specification 0.95 Section 3.6 | |
371 | * QH: describes control/bulk/interrupt endpoints | |
372 | * See Fig 3-7 "Queue Head Structure Layout". | |
373 | * | |
374 | * These appear in both the async and (for interrupt) periodic schedules. | |
375 | */ | |
376 | ||
3807e26d AD |
377 | /* first part defined by EHCI spec */ |
378 | struct ehci_qh_hw { | |
6dbd682b SR |
379 | __hc32 hw_next; /* see EHCI 3.6.1 */ |
380 | __hc32 hw_info1; /* see EHCI 3.6.2 */ | |
4c53de72 AS |
381 | #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ |
382 | #define QH_HEAD (1 << 15) /* Head of async reclamation list */ | |
383 | #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ | |
384 | #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ | |
385 | #define QH_LOW_SPEED (1 << 12) | |
386 | #define QH_FULL_SPEED (0 << 12) | |
387 | #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ | |
6dbd682b | 388 | __hc32 hw_info2; /* see EHCI 3.6.2 */ |
7dedacf4 DB |
389 | #define QH_SMASK 0x000000ff |
390 | #define QH_CMASK 0x0000ff00 | |
391 | #define QH_HUBADDR 0x007f0000 | |
392 | #define QH_HUBPORT 0x3f800000 | |
393 | #define QH_MULT 0xc0000000 | |
6dbd682b | 394 | __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ |
53bd6a60 | 395 | |
1da177e4 | 396 | /* qtd overlay (hardware parts of a struct ehci_qtd) */ |
6dbd682b SR |
397 | __hc32 hw_qtd_next; |
398 | __hc32 hw_alt_next; | |
399 | __hc32 hw_token; | |
9dc3af5e GB |
400 | __hc32 hw_buf[5]; |
401 | __hc32 hw_buf_hi[5]; | |
3a9e742f | 402 | } __aligned(32); |
1da177e4 | 403 | |
3807e26d | 404 | struct ehci_qh { |
8c5bf7be | 405 | struct ehci_qh_hw *hw; /* Must come first */ |
1da177e4 LT |
406 | /* the rest is HCD-private */ |
407 | dma_addr_t qh_dma; /* address of qh */ | |
408 | union ehci_shadow qh_next; /* ptr to qh; or periodic */ | |
409 | struct list_head qtd_list; /* sw qtd list */ | |
569b394f | 410 | struct list_head intr_node; /* list of intr QHs */ |
1da177e4 | 411 | struct ehci_qtd *dummy; |
6e018751 | 412 | struct list_head unlink_node; |
ffa0248e | 413 | struct ehci_per_sched ps; /* scheduling info */ |
1da177e4 | 414 | |
df202255 | 415 | unsigned unlink_cycle; |
1da177e4 LT |
416 | |
417 | u8 qh_state; | |
418 | #define QH_STATE_LINKED 1 /* HC sees this */ | |
419 | #define QH_STATE_UNLINK 2 /* HC may still see this */ | |
420 | #define QH_STATE_IDLE 3 /* HC doesn't see this */ | |
99ac5b1e | 421 | #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ |
1da177e4 LT |
422 | #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ |
423 | ||
a2c2706e AS |
424 | u8 xacterrs; /* XactErr retry counter */ |
425 | #define QH_XACTERR_MAX 32 /* XactErr retry limit */ | |
426 | ||
fcc5184e AS |
427 | u8 unlink_reason; |
428 | #define QH_UNLINK_HALTED 0x01 /* Halt flag is set */ | |
429 | #define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */ | |
430 | #define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */ | |
431 | #define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */ | |
432 | #define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */ | |
433 | #define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */ | |
434 | ||
1da177e4 | 435 | u8 gap_uf; /* uframes split/csplit gap */ |
914b7012 | 436 | |
e04f5f7e | 437 | unsigned is_out:1; /* bulk or intr OUT */ |
914b7012 | 438 | unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ |
7bc782d7 | 439 | unsigned dequeue_during_giveback:1; |
fc0855f2 | 440 | unsigned should_be_inactive:1; |
3807e26d | 441 | }; |
1da177e4 LT |
442 | |
443 | /*-------------------------------------------------------------------------*/ | |
444 | ||
445 | /* description of one iso transaction (up to 3 KB data if highspeed) */ | |
446 | struct ehci_iso_packet { | |
447 | /* These will be copied to iTD when scheduling */ | |
448 | u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ | |
6dbd682b | 449 | __hc32 transaction; /* itd->hw_transaction[i] |= */ |
1da177e4 LT |
450 | u8 cross; /* buf crosses pages */ |
451 | /* for full speed OUT splits */ | |
452 | u32 buf1; | |
453 | }; | |
454 | ||
455 | /* temporary schedule data for packets from iso urbs (both speeds) | |
456 | * each packet is one logical usb transaction to the device (not TT), | |
457 | * beginning at stream->next_uframe | |
458 | */ | |
459 | struct ehci_iso_sched { | |
460 | struct list_head td_list; | |
461 | unsigned span; | |
46c73d1d | 462 | unsigned first_packet; |
6bc3f397 | 463 | struct ehci_iso_packet packet[]; |
1da177e4 LT |
464 | }; |
465 | ||
466 | /* | |
467 | * ehci_iso_stream - groups all (s)itds for this endpoint. | |
468 | * acts like a qh would, if EHCI had them for ISO. | |
469 | */ | |
470 | struct ehci_iso_stream { | |
1082f57a CL |
471 | /* first field matches ehci_hq, but is NULL */ |
472 | struct ehci_qh_hw *hw; | |
1da177e4 | 473 | |
1da177e4 LT |
474 | u8 bEndpointAddress; |
475 | u8 highspeed; | |
1da177e4 LT |
476 | struct list_head td_list; /* queued itds/sitds */ |
477 | struct list_head free_list; /* list of unused itds/sitds */ | |
1da177e4 LT |
478 | |
479 | /* output of (re)scheduling */ | |
ffa0248e | 480 | struct ehci_per_sched ps; /* scheduling info */ |
91a99b5e | 481 | unsigned next_uframe; |
6dbd682b | 482 | __hc32 splits; |
1da177e4 LT |
483 | |
484 | /* the rest is derived from the endpoint descriptor, | |
1da177e4 LT |
485 | * including the extra info for hw_bufp[0..2] |
486 | */ | |
ffa0248e | 487 | u16 uperiod; /* period in uframes */ |
1da177e4 | 488 | u16 maxp; |
1da177e4 LT |
489 | unsigned bandwidth; |
490 | ||
491 | /* This is used to initialize iTD's hw_bufp fields */ | |
6dbd682b SR |
492 | __hc32 buf0; |
493 | __hc32 buf1; | |
494 | __hc32 buf2; | |
1da177e4 LT |
495 | |
496 | /* this is used to initialize sITD's tt info */ | |
6dbd682b | 497 | __hc32 address; |
1da177e4 LT |
498 | }; |
499 | ||
500 | /*-------------------------------------------------------------------------*/ | |
501 | ||
502 | /* | |
503 | * EHCI Specification 0.95 Section 3.3 | |
504 | * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" | |
505 | * | |
506 | * Schedule records for high speed iso xfers | |
507 | */ | |
508 | struct ehci_itd { | |
509 | /* first part defined by EHCI spec */ | |
6dbd682b | 510 | __hc32 hw_next; /* see EHCI 3.3.1 */ |
9dc3af5e | 511 | __hc32 hw_transaction[8]; /* see EHCI 3.3.2 */ |
1da177e4 LT |
512 | #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ |
513 | #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ | |
514 | #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ | |
515 | #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ | |
516 | #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) | |
517 | #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ | |
518 | ||
6dbd682b | 519 | #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) |
1da177e4 | 520 | |
9dc3af5e GB |
521 | __hc32 hw_bufp[7]; /* see EHCI 3.3.3 */ |
522 | __hc32 hw_bufp_hi[7]; /* Appendix B */ | |
1da177e4 LT |
523 | |
524 | /* the rest is HCD-private */ | |
525 | dma_addr_t itd_dma; /* for this itd */ | |
526 | union ehci_shadow itd_next; /* ptr to periodic q entry */ | |
527 | ||
528 | struct urb *urb; | |
529 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
530 | struct list_head itd_list; /* list of stream's itds */ | |
531 | ||
532 | /* any/all hw_transactions here may be used by that urb */ | |
533 | unsigned frame; /* where scheduled */ | |
534 | unsigned pg; | |
535 | unsigned index[8]; /* in urb->iso_frame_desc */ | |
3a9e742f | 536 | } __aligned(32); |
1da177e4 LT |
537 | |
538 | /*-------------------------------------------------------------------------*/ | |
539 | ||
540 | /* | |
53bd6a60 | 541 | * EHCI Specification 0.95 Section 3.4 |
1da177e4 LT |
542 | * siTD, aka split-transaction isochronous Transfer Descriptor |
543 | * ... describe full speed iso xfers through TT in hubs | |
544 | * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) | |
545 | */ | |
546 | struct ehci_sitd { | |
547 | /* first part defined by EHCI spec */ | |
6dbd682b | 548 | __hc32 hw_next; |
1da177e4 | 549 | /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ |
6dbd682b SR |
550 | __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ |
551 | __hc32 hw_uframe; /* EHCI table 3-10 */ | |
552 | __hc32 hw_results; /* EHCI table 3-11 */ | |
1da177e4 LT |
553 | #define SITD_IOC (1 << 31) /* interrupt on completion */ |
554 | #define SITD_PAGE (1 << 30) /* buffer 0/1 */ | |
4510a072 | 555 | #define SITD_LENGTH(x) (((x) >> 16) & 0x3ff) |
1da177e4 LT |
556 | #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ |
557 | #define SITD_STS_ERR (1 << 6) /* error from TT */ | |
558 | #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
559 | #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ | |
560 | #define SITD_STS_XACT (1 << 3) /* illegal IN response */ | |
561 | #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
562 | #define SITD_STS_STS (1 << 1) /* split transaction state */ | |
563 | ||
6dbd682b | 564 | #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) |
1da177e4 | 565 | |
9dc3af5e | 566 | __hc32 hw_buf[2]; /* EHCI table 3-12 */ |
6dbd682b | 567 | __hc32 hw_backpointer; /* EHCI table 3-13 */ |
9dc3af5e | 568 | __hc32 hw_buf_hi[2]; /* Appendix B */ |
1da177e4 LT |
569 | |
570 | /* the rest is HCD-private */ | |
571 | dma_addr_t sitd_dma; | |
572 | union ehci_shadow sitd_next; /* ptr to periodic q entry */ | |
573 | ||
574 | struct urb *urb; | |
575 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
576 | struct list_head sitd_list; /* list of stream's sitds */ | |
577 | unsigned frame; | |
578 | unsigned index; | |
3a9e742f | 579 | } __aligned(32); |
1da177e4 LT |
580 | |
581 | /*-------------------------------------------------------------------------*/ | |
582 | ||
583 | /* | |
584 | * EHCI Specification 0.96 Section 3.7 | |
585 | * Periodic Frame Span Traversal Node (FSTN) | |
586 | * | |
587 | * Manages split interrupt transactions (using TT) that span frame boundaries | |
588 | * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN | |
589 | * makes the HC jump (back) to a QH to scan for fs/ls QH completions until | |
590 | * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. | |
591 | */ | |
592 | struct ehci_fstn { | |
6dbd682b SR |
593 | __hc32 hw_next; /* any periodic q entry */ |
594 | __hc32 hw_prev; /* qh or EHCI_LIST_END */ | |
1da177e4 LT |
595 | |
596 | /* the rest is HCD-private */ | |
597 | dma_addr_t fstn_dma; | |
598 | union ehci_shadow fstn_next; /* ptr to periodic q entry */ | |
3a9e742f | 599 | } __aligned(32); |
1da177e4 LT |
600 | |
601 | /*-------------------------------------------------------------------------*/ | |
602 | ||
b35c5009 AS |
603 | /* |
604 | * USB-2.0 Specification Sections 11.14 and 11.18 | |
605 | * Scheduling and budgeting split transactions using TTs | |
606 | * | |
607 | * A hub can have a single TT for all its ports, or multiple TTs (one for each | |
608 | * port). The bandwidth and budgeting information for the full/low-speed bus | |
609 | * below each TT is self-contained and independent of the other TTs or the | |
610 | * high-speed bus. | |
611 | * | |
612 | * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated | |
613 | * to an interrupt or isochronous endpoint for each frame. "Budget" refers to | |
614 | * the best-case estimate of the number of full-speed bytes allocated to an | |
615 | * endpoint for each microframe within an allocated frame. | |
616 | * | |
617 | * Removal of an endpoint invalidates a TT's budget. Instead of trying to | |
618 | * keep an up-to-date record, we recompute the budget when it is needed. | |
619 | */ | |
620 | ||
621 | struct ehci_tt { | |
622 | u16 bandwidth[EHCI_BANDWIDTH_FRAMES]; | |
623 | ||
624 | struct list_head tt_list; /* List of all ehci_tt's */ | |
625 | struct list_head ps_list; /* Items using this TT */ | |
626 | struct usb_tt *usb_tt; | |
627 | int tt_port; /* TT port number */ | |
628 | }; | |
629 | ||
630 | /*-------------------------------------------------------------------------*/ | |
631 | ||
16032c4f AS |
632 | /* Prepare the PORTSC wakeup flags during controller suspend/resume */ |
633 | ||
4147200d | 634 | #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ |
8af0219e | 635 | ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup) |
16032c4f | 636 | |
4147200d | 637 | #define ehci_prepare_ports_for_controller_resume(ehci) \ |
8af0219e | 638 | ehci_adjust_port_wakeup_flags(ehci, false, false) |
16032c4f AS |
639 | |
640 | /*-------------------------------------------------------------------------*/ | |
641 | ||
1da177e4 LT |
642 | #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT |
643 | ||
644 | /* | |
645 | * Some EHCI controllers have a Transaction Translator built into the | |
646 | * root hub. This is a non-standard feature. Each controller will need | |
647 | * to add code to the following inline functions, and call them as | |
648 | * needed (mostly in root hub code). | |
649 | */ | |
650 | ||
a8e51775 | 651 | #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) |
1da177e4 LT |
652 | |
653 | /* Returns the speed of a device attached to a port on the root hub. */ | |
654 | static inline unsigned int | |
655 | ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) | |
656 | { | |
657 | if (ehci_is_TDI(ehci)) { | |
331ac6b2 | 658 | switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { |
1da177e4 LT |
659 | case 0: |
660 | return 0; | |
661 | case 1: | |
288ead45 | 662 | return USB_PORT_STAT_LOW_SPEED; |
1da177e4 LT |
663 | case 2: |
664 | default: | |
288ead45 | 665 | return USB_PORT_STAT_HIGH_SPEED; |
1da177e4 LT |
666 | } |
667 | } | |
288ead45 | 668 | return USB_PORT_STAT_HIGH_SPEED; |
1da177e4 LT |
669 | } |
670 | ||
671 | #else | |
672 | ||
673 | #define ehci_is_TDI(e) (0) | |
674 | ||
288ead45 | 675 | #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED |
1da177e4 LT |
676 | #endif |
677 | ||
8cd42e97 KG |
678 | /*-------------------------------------------------------------------------*/ |
679 | ||
680 | #ifdef CONFIG_PPC_83xx | |
681 | /* Some Freescale processors have an erratum in which the TT | |
682 | * port number in the queue head was 0..N-1 instead of 1..N. | |
683 | */ | |
684 | #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) | |
685 | #else | |
686 | #define ehci_has_fsl_portno_bug(e) (0) | |
687 | #endif | |
688 | ||
f8786a91 NB |
689 | #define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */ |
690 | ||
691 | #if defined(CONFIG_PPC_85xx) | |
692 | /* Some Freescale processors have an erratum (USB A-005275) in which | |
693 | * incoming packets get corrupted in HS mode | |
694 | */ | |
695 | #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata) | |
696 | #else | |
697 | #define ehci_has_fsl_hs_errata(e) (0) | |
698 | #endif | |
699 | ||
9d4b8270 CH |
700 | /* |
701 | * Some Freescale/NXP processors have an erratum (USB A-005697) | |
702 | * in which we need to wait for 10ms for bus to enter suspend mode | |
703 | * after setting SUSP bit. | |
704 | */ | |
705 | #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata) | |
706 | ||
083522d7 BH |
707 | /* |
708 | * While most USB host controllers implement their registers in | |
709 | * little-endian format, a minority (celleb companion chip) implement | |
710 | * them in big endian format. | |
711 | * | |
712 | * This attempts to support either format at compile time without a | |
713 | * runtime penalty, or both formats with the additional overhead | |
714 | * of checking a flag bit. | |
c430131a JA |
715 | * |
716 | * ehci_big_endian_capbase is a special quirk for controllers that | |
717 | * implement the HC capability registers as separate registers and not | |
718 | * as fields of a 32-bit register. | |
083522d7 BH |
719 | */ |
720 | ||
721 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
722 | #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) | |
c430131a | 723 | #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) |
083522d7 BH |
724 | #else |
725 | #define ehci_big_endian_mmio(e) 0 | |
c430131a | 726 | #define ehci_big_endian_capbase(e) 0 |
083522d7 BH |
727 | #endif |
728 | ||
6dbd682b SR |
729 | /* |
730 | * Big-endian read/write functions are arch-specific. | |
731 | * Other arches can be added if/when they're needed. | |
6dbd682b | 732 | */ |
91bc4d31 VB |
733 | #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) |
734 | #define readl_be(addr) __raw_readl((__force unsigned *)addr) | |
735 | #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) | |
736 | #endif | |
737 | ||
6dbd682b | 738 | static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, |
c021170f | 739 | __u32 __iomem *regs) |
083522d7 | 740 | { |
d728e327 | 741 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 742 | return ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
743 | readl_be(regs) : |
744 | readl(regs); | |
d728e327 | 745 | #else |
68f50e52 | 746 | return readl(regs); |
d728e327 | 747 | #endif |
083522d7 BH |
748 | } |
749 | ||
feffe09f PC |
750 | #ifdef CONFIG_SOC_IMX28 |
751 | static inline void imx28_ehci_writel(const unsigned int val, | |
752 | volatile __u32 __iomem *addr) | |
753 | { | |
754 | __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); | |
755 | } | |
756 | #else | |
757 | static inline void imx28_ehci_writel(const unsigned int val, | |
758 | volatile __u32 __iomem *addr) | |
759 | { | |
760 | } | |
761 | #endif | |
6dbd682b SR |
762 | static inline void ehci_writel(const struct ehci_hcd *ehci, |
763 | const unsigned int val, __u32 __iomem *regs) | |
083522d7 | 764 | { |
d728e327 | 765 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 766 | ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
767 | writel_be(val, regs) : |
768 | writel(val, regs); | |
d728e327 | 769 | #else |
feffe09f PC |
770 | if (ehci->imx28_write_fix) |
771 | imx28_ehci_writel(val, regs); | |
772 | else | |
773 | writel(val, regs); | |
d728e327 | 774 | #endif |
083522d7 | 775 | } |
8cd42e97 | 776 | |
796bcae7 VB |
777 | /* |
778 | * On certain ppc-44x SoC there is a HW issue, that could only worked around with | |
779 | * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. | |
25985edc | 780 | * Other common bits are dependent on has_amcc_usb23 quirk flag. |
796bcae7 VB |
781 | */ |
782 | #ifdef CONFIG_44x | |
783 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | |
784 | { | |
785 | u32 hc_control; | |
786 | ||
787 | hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); | |
788 | if (operational) | |
789 | hc_control |= OHCI_USB_OPER; | |
790 | else | |
791 | hc_control |= OHCI_USB_SUSPEND; | |
792 | ||
793 | writel_be(hc_control, ehci->ohci_hcctrl_reg); | |
794 | (void) readl_be(ehci->ohci_hcctrl_reg); | |
795 | } | |
796 | #else | |
797 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | |
798 | { } | |
799 | #endif | |
800 | ||
1da177e4 LT |
801 | /*-------------------------------------------------------------------------*/ |
802 | ||
6dbd682b SR |
803 | /* |
804 | * The AMCC 440EPx not only implements its EHCI registers in big-endian | |
805 | * format, but also its DMA data structures (descriptors). | |
806 | * | |
807 | * EHCI controllers accessed through PCI work normally (little-endian | |
808 | * everywhere), so we won't bother supporting a BE-only mode for now. | |
809 | */ | |
810 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
811 | #define ehci_big_endian_desc(e) ((e)->big_endian_desc) | |
812 | ||
813 | /* cpu to ehci */ | |
e06e2264 | 814 | static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x) |
6dbd682b SR |
815 | { |
816 | return ehci_big_endian_desc(ehci) | |
817 | ? (__force __hc32)cpu_to_be32(x) | |
818 | : (__force __hc32)cpu_to_le32(x); | |
819 | } | |
820 | ||
821 | /* ehci to cpu */ | |
e06e2264 | 822 | static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x) |
6dbd682b SR |
823 | { |
824 | return ehci_big_endian_desc(ehci) | |
825 | ? be32_to_cpu((__force __be32)x) | |
826 | : le32_to_cpu((__force __le32)x); | |
827 | } | |
828 | ||
e06e2264 | 829 | static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) |
6dbd682b SR |
830 | { |
831 | return ehci_big_endian_desc(ehci) | |
832 | ? be32_to_cpup((__force __be32 *)x) | |
833 | : le32_to_cpup((__force __le32 *)x); | |
834 | } | |
835 | ||
836 | #else | |
837 | ||
838 | /* cpu to ehci */ | |
e06e2264 | 839 | static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x) |
6dbd682b SR |
840 | { |
841 | return cpu_to_le32(x); | |
842 | } | |
843 | ||
844 | /* ehci to cpu */ | |
e06e2264 | 845 | static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x) |
6dbd682b SR |
846 | { |
847 | return le32_to_cpu(x); | |
848 | } | |
849 | ||
e06e2264 | 850 | static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x) |
6dbd682b SR |
851 | { |
852 | return le32_to_cpup(x); | |
853 | } | |
854 | ||
855 | #endif | |
856 | ||
857 | /*-------------------------------------------------------------------------*/ | |
858 | ||
d6064aca | 859 | #define ehci_dbg(ehci, fmt, args...) \ |
b5566d07 | 860 | dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args) |
d6064aca | 861 | #define ehci_err(ehci, fmt, args...) \ |
b5566d07 | 862 | dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args) |
d6064aca | 863 | #define ehci_info(ehci, fmt, args...) \ |
b5566d07 | 864 | dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args) |
d6064aca | 865 | #define ehci_warn(ehci, fmt, args...) \ |
b5566d07 | 866 | dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args) |
d6064aca | 867 | |
1da177e4 LT |
868 | /*-------------------------------------------------------------------------*/ |
869 | ||
3e023203 AS |
870 | /* Declarations of things exported for use by ehci platform drivers */ |
871 | ||
872 | struct ehci_driver_overrides { | |
3e023203 AS |
873 | size_t extra_priv_size; |
874 | int (*reset)(struct usb_hcd *hcd); | |
11a7e594 MG |
875 | int (*port_power)(struct usb_hcd *hcd, |
876 | int portnum, bool enable); | |
3e023203 AS |
877 | }; |
878 | ||
879 | extern void ehci_init_driver(struct hc_driver *drv, | |
880 | const struct ehci_driver_overrides *over); | |
881 | extern int ehci_setup(struct usb_hcd *hcd); | |
2f3a6b86 MG |
882 | extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, |
883 | u32 mask, u32 done, int usec); | |
74db22cb | 884 | extern int ehci_reset(struct ehci_hcd *ehci); |
3e023203 | 885 | |
3e023203 | 886 | extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); |
314b41b1 | 887 | extern int ehci_resume(struct usb_hcd *hcd, bool force_reset); |
74db22cb RM |
888 | extern void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci, |
889 | bool suspending, bool do_wakeup); | |
3e023203 | 890 | |
37769939 LP |
891 | extern int ehci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, |
892 | u16 wIndex, char *buf, u16 wLength); | |
893 | ||
1da177e4 | 894 | #endif /* __LINUX_EHCI_HCD_H */ |