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USB: serial: ipaq: remove product and vendor module parameters
[linux-block.git] / drivers / usb / host / ehci-tegra.c
CommitLineData
79ad3b5a
BG		 1/*
2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2009 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 */
18
19#include <linux/clk.h>
20#include <linux/platform_device.h>
21#include <linux/platform_data/tegra_usb.h>
22#include <linux/irq.h>
23#include <linux/usb/otg.h>
4a53f4e6
OJ		 24#include <linux/gpio.h>
25#include <linux/of.h>
26#include <linux/of_gpio.h>
27
79ad3b5a 28#include <mach/usb_phy.h>
4a53f4e6 29#include <mach/iomap.h>
79ad3b5a 30
fbf9865c
RM		 31#define TEGRA_USB_DMA_ALIGN 32
32
79ad3b5a
BG		 33struct tegra_ehci_hcd {
34 struct ehci_hcd *ehci;
35 struct tegra_usb_phy *phy;
36 struct clk *clk;
37 struct clk *emc_clk;
86753811 38 struct usb_phy *transceiver;
79ad3b5a
BG		 39 int host_resumed;
40 int bus_suspended;
41 int port_resuming;
42 int power_down_on_bus_suspend;
43 enum tegra_usb_phy_port_speed port_speed;
44};
45
46static void tegra_ehci_power_up(struct usb_hcd *hcd)
47{
48 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
49
50 clk_enable(tegra->emc_clk);
51 clk_enable(tegra->clk);
52 tegra_usb_phy_power_on(tegra->phy);
53 tegra->host_resumed = 1;
54}
55
56static void tegra_ehci_power_down(struct usb_hcd *hcd)
57{
58 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
59
60 tegra->host_resumed = 0;
61 tegra_usb_phy_power_off(tegra->phy);
62 clk_disable(tegra->clk);
63 clk_disable(tegra->emc_clk);
64}
65
1f594b64
JL		 66static int tegra_ehci_internal_port_reset(
67 struct ehci_hcd *ehci,
68 u32 __iomem *portsc_reg
69)
70{
71 u32 temp;
72 unsigned long flags;
73 int retval = 0;
74 int i, tries;
75 u32 saved_usbintr;
76
77 spin_lock_irqsave(&ehci->lock, flags);
78 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
79 /* disable USB interrupt */
80 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
81 spin_unlock_irqrestore(&ehci->lock, flags);
82
83 /*
84 * Here we have to do Port Reset at most twice for
85 * Port Enable bit to be set.
86 */
87 for (i = 0; i < 2; i++) {
88 temp = ehci_readl(ehci, portsc_reg);
89 temp |= PORT_RESET;
90 ehci_writel(ehci, temp, portsc_reg);
91 mdelay(10);
92 temp &= ~PORT_RESET;
93 ehci_writel(ehci, temp, portsc_reg);
94 mdelay(1);
95 tries = 100;
96 do {
97 mdelay(1);
98 /*
99 * Up to this point, Port Enable bit is
100 * expected to be set after 2 ms waiting.
101 * USB1 usually takes extra 45 ms, for safety,
102 * we take 100 ms as timeout.
103 */
104 temp = ehci_readl(ehci, portsc_reg);
105 } while (!(temp & PORT_PE) && tries--);
106 if (temp & PORT_PE)
107 break;
108 }
109 if (i == 2)
110 retval = -ETIMEDOUT;
111
112 /*
113 * Clear Connect Status Change bit if it's set.
114 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
115 */
116 if (temp & PORT_CSC)
117 ehci_writel(ehci, PORT_CSC, portsc_reg);
118
119 /*
120 * Write to clear any interrupt status bits that might be set
121 * during port reset.
122 */
123 temp = ehci_readl(ehci, &ehci->regs->status);
124 ehci_writel(ehci, temp, &ehci->regs->status);
125
126 /* restore original interrupt enable bits */
127 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
128 return retval;
129}
130
79ad3b5a
BG		 131static int tegra_ehci_hub_control(
132 struct usb_hcd *hcd,
133 u16 typeReq,
134 u16 wValue,
135 u16 wIndex,
136 char *buf,
137 u16 wLength
138)
139{
140 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
141 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
142 u32 __iomem *status_reg;
143 u32 temp;
144 unsigned long flags;
145 int retval = 0;
146
147 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
148
149 spin_lock_irqsave(&ehci->lock, flags);
150
151 /*
152 * In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
153 * that are write on clear, by writing back the register read value, so
154 * USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
155 */
156 if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
157 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
158 ehci_writel(ehci, temp & ~PORT_PE, status_reg);
159 goto done;
160 }
161
162 else if (typeReq == GetPortStatus) {
163 temp = ehci_readl(ehci, status_reg);
164 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
165 /* Resume completed, re-enable disconnect detection */
166 tegra->port_resuming = 0;
167 tegra_usb_phy_postresume(tegra->phy);
168 }
169 }
170
171 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
172 temp = ehci_readl(ehci, status_reg);
173 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
174 retval = -EPIPE;
175 goto done;
176 }
177
178 temp &= ~PORT_WKCONN_E;
179 temp |= PORT_WKDISC_E | PORT_WKOC_E;
180 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
181
182 /*
183 * If a transaction is in progress, there may be a delay in
184 * suspending the port. Poll until the port is suspended.
185 */
186 if (handshake(ehci, status_reg, PORT_SUSPEND,
187 PORT_SUSPEND, 5000))
188 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
189
190 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
191 goto done;
192 }
193
1f594b64
JL		 194 /* For USB1 port we need to issue Port Reset twice internally */
195 if (tegra->phy->instance == 0 &&
196 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
197 spin_unlock_irqrestore(&ehci->lock, flags);
198 return tegra_ehci_internal_port_reset(ehci, status_reg);
199 }
200
79ad3b5a
BG		 201 /*
202 * Tegra host controller will time the resume operation to clear the bit
203 * when the port control state switches to HS or FS Idle. This behavior
204 * is different from EHCI where the host controller driver is required
205 * to set this bit to a zero after the resume duration is timed in the
206 * driver.
207 */
208 else if (typeReq == ClearPortFeature &&
209 wValue == USB_PORT_FEAT_SUSPEND) {
210 temp = ehci_readl(ehci, status_reg);
211 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
212 retval = -EPIPE;
213 goto done;
214 }
215
216 if (!(temp & PORT_SUSPEND))
217 goto done;
218
219 /* Disable disconnect detection during port resume */
220 tegra_usb_phy_preresume(tegra->phy);
221
222 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
223
224 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
225 /* start resume signalling */
226 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
227
228 spin_unlock_irqrestore(&ehci->lock, flags);
229 msleep(20);
230 spin_lock_irqsave(&ehci->lock, flags);
231
232 /* Poll until the controller clears RESUME and SUSPEND */
233 if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
234 pr_err("%s: timeout waiting for RESUME\n", __func__);
235 if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
236 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
237
238 ehci->reset_done[wIndex-1] = 0;
239
240 tegra->port_resuming = 1;
241 goto done;
242 }
243
244 spin_unlock_irqrestore(&ehci->lock, flags);
245
246 /* Handle the hub control events here */
247 return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
248done:
249 spin_unlock_irqrestore(&ehci->lock, flags);
250 return retval;
251}
252
253static void tegra_ehci_restart(struct usb_hcd *hcd)
254{
255 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
256
257 ehci_reset(ehci);
258
259 /* setup the frame list and Async q heads */
260 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
261 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
262 /* setup the command register and set the controller in RUN mode */
263 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
264 ehci->command |= CMD_RUN;
265 ehci_writel(ehci, ehci->command, &ehci->regs->command);
266
267 down_write(&ehci_cf_port_reset_rwsem);
268 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
269 /* flush posted writes */
270 ehci_readl(ehci, &ehci->regs->command);
271 up_write(&ehci_cf_port_reset_rwsem);
272}
273
274static int tegra_usb_suspend(struct usb_hcd *hcd)
275{
276 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
277 struct ehci_regs __iomem *hw = tegra->ehci->regs;
278 unsigned long flags;
279
280 spin_lock_irqsave(&tegra->ehci->lock, flags);
281
282 tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3;
283 ehci_halt(tegra->ehci);
284 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
285
286 spin_unlock_irqrestore(&tegra->ehci->lock, flags);
287
288 tegra_ehci_power_down(hcd);
289 return 0;
290}
291
292static int tegra_usb_resume(struct usb_hcd *hcd)
293{
294 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
295 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
296 struct ehci_regs __iomem *hw = ehci->regs;
297 unsigned long val;
298
299 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
300 tegra_ehci_power_up(hcd);
301
302 if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) {
303 /* Wait for the phy to detect new devices
304 * before we restart the controller */
305 msleep(10);
306 goto restart;
307 }
308
309 /* Force the phy to keep data lines in suspend state */
310 tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed);
311
312 /* Enable host mode */
313 tdi_reset(ehci);
314
315 /* Enable Port Power */
316 val = readl(&hw->port_status[0]);
317 val |= PORT_POWER;
318 writel(val, &hw->port_status[0]);
319 udelay(10);
320
321 /* Check if the phy resume from LP0. When the phy resume from LP0
322 * USB register will be reset. */
323 if (!readl(&hw->async_next)) {
324 /* Program the field PTC based on the saved speed mode */
325 val = readl(&hw->port_status[0]);
326 val &= ~PORT_TEST(~0);
327 if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH)
328 val |= PORT_TEST_FORCE;
329 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL)
330 val |= PORT_TEST(6);
331 else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
332 val |= PORT_TEST(7);
333 writel(val, &hw->port_status[0]);
334 udelay(10);
335
336 /* Disable test mode by setting PTC field to NORMAL_OP */
337 val = readl(&hw->port_status[0]);
338 val &= ~PORT_TEST(~0);
339 writel(val, &hw->port_status[0]);
340 udelay(10);
341 }
342
343 /* Poll until CCS is enabled */
344 if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
345 PORT_CONNECT, 2000)) {
346 pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
347 goto restart;
348 }
349
350 /* Poll until PE is enabled */
351 if (handshake(ehci, &hw->port_status[0], PORT_PE,
352 PORT_PE, 2000)) {
353 pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
354 goto restart;
355 }
356
357 /* Clear the PCI status, to avoid an interrupt taken upon resume */
358 val = readl(&hw->status);
359 val |= STS_PCD;
360 writel(val, &hw->status);
361
362 /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */
363 val = readl(&hw->port_status[0]);
364 if ((val & PORT_POWER) && (val & PORT_PE)) {
365 val |= PORT_SUSPEND;
366 writel(val, &hw->port_status[0]);
367
368 /* Wait until port suspend completes */
369 if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
370 PORT_SUSPEND, 1000)) {
371 pr_err("%s: timeout waiting for PORT_SUSPEND\n",
372 __func__);
373 goto restart;
374 }
375 }
376
377 tegra_ehci_phy_restore_end(tegra->phy);
378 return 0;
379
380restart:
381 if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH)
382 tegra_ehci_phy_restore_end(tegra->phy);
383
384 tegra_ehci_restart(hcd);
385 return 0;
386}
387
388static void tegra_ehci_shutdown(struct usb_hcd *hcd)
389{
390 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
391
392 /* ehci_shutdown touches the USB controller registers, make sure
393 * controller has clocks to it */
394 if (!tegra->host_resumed)
395 tegra_ehci_power_up(hcd);
396
397 ehci_shutdown(hcd);
398}
399
400static int tegra_ehci_setup(struct usb_hcd *hcd)
401{
402 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
403 int retval;
404
405 /* EHCI registers start at offset 0x100 */
406 ehci->caps = hcd->regs + 0x100;
407 ehci->regs = hcd->regs + 0x100 +
c430131a 408 HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
79ad3b5a
BG		 409
410 dbg_hcs_params(ehci, "reset");
411 dbg_hcc_params(ehci, "reset");
412
413 /* cache this readonly data; minimize chip reads */
414 ehci->hcs_params = readl(&ehci->caps->hcs_params);
415
416 /* switch to host mode */
417 hcd->has_tt = 1;
418 ehci_reset(ehci);
419
420 retval = ehci_halt(ehci);
421 if (retval)
422 return retval;
423
424 /* data structure init */
425 retval = ehci_init(hcd);
426 if (retval)
427 return retval;
428
429 ehci->sbrn = 0x20;
430
431 ehci_port_power(ehci, 1);
432 return retval;
433}
434
435#ifdef CONFIG_PM
436static int tegra_ehci_bus_suspend(struct usb_hcd *hcd)
437{
438 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
439 int error_status = 0;
440
441 error_status = ehci_bus_suspend(hcd);
442 if (!error_status && tegra->power_down_on_bus_suspend) {
443 tegra_usb_suspend(hcd);
444 tegra->bus_suspended = 1;
445 }
446
447 return error_status;
448}
449
450static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
451{
452 struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller);
453
454 if (tegra->bus_suspended && tegra->power_down_on_bus_suspend) {
455 tegra_usb_resume(hcd);
456 tegra->bus_suspended = 0;
457 }
458
459 tegra_usb_phy_preresume(tegra->phy);
460 tegra->port_resuming = 1;
461 return ehci_bus_resume(hcd);
462}
463#endif
464
fe375774 465struct dma_aligned_buffer {
fbf9865c
RM		 466 void *kmalloc_ptr;
467 void *old_xfer_buffer;
468 u8 data[0];
469};
470
fe375774 471static void free_dma_aligned_buffer(struct urb *urb)
fbf9865c 472{
fe375774 473 struct dma_aligned_buffer *temp;
fbf9865c
RM		 474
475 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
476 return;
477
fe375774
VB		 478 temp = container_of(urb->transfer_buffer,
479 struct dma_aligned_buffer, data);
fbf9865c 480
fe375774 481 if (usb_urb_dir_in(urb))
fbf9865c
RM		 482 memcpy(temp->old_xfer_buffer, temp->data,
483 urb->transfer_buffer_length);
484 urb->transfer_buffer = temp->old_xfer_buffer;
485 kfree(temp->kmalloc_ptr);
486
487 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
488}
489
fe375774 490static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
fbf9865c 491{
fe375774 492 struct dma_aligned_buffer *temp, *kmalloc_ptr;
fbf9865c
RM		 493 size_t kmalloc_size;
494
495 if (urb->num_sgs || urb->sg ||
496 urb->transfer_buffer_length == 0 ||
497 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
498 return 0;
499
fbf9865c
RM		 500 /* Allocate a buffer with enough padding for alignment */
501 kmalloc_size = urb->transfer_buffer_length +
fe375774 502 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
fbf9865c
RM		 503
504 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
505 if (!kmalloc_ptr)
506 return -ENOMEM;
507
fe375774 508 /* Position our struct dma_aligned_buffer such that data is aligned */
fbf9865c 509 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
fbf9865c
RM		 510 temp->kmalloc_ptr = kmalloc_ptr;
511 temp->old_xfer_buffer = urb->transfer_buffer;
fe375774 512 if (usb_urb_dir_out(urb))
fbf9865c
RM		 513 memcpy(temp->data, urb->transfer_buffer,
514 urb->transfer_buffer_length);
515 urb->transfer_buffer = temp->data;
516
517 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
518
519 return 0;
520}
521
522static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
523 gfp_t mem_flags)
524{
525 int ret;
526
fe375774 527 ret = alloc_dma_aligned_buffer(urb, mem_flags);
fbf9865c
RM		 528 if (ret)
529 return ret;
530
531 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
532 if (ret)
fe375774 533 free_dma_aligned_buffer(urb);
fbf9865c
RM		 534
535 return ret;
536}
537
538static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
539{
540 usb_hcd_unmap_urb_for_dma(hcd, urb);
fe375774 541 free_dma_aligned_buffer(urb);
fbf9865c
RM		 542}
543
79ad3b5a
BG		 544static const struct hc_driver tegra_ehci_hc_driver = {
545 .description = hcd_name,
546 .product_desc = "Tegra EHCI Host Controller",
547 .hcd_priv_size = sizeof(struct ehci_hcd),
79ad3b5a
BG		 548 .flags = HCD_USB2 | HCD_MEMORY,
549
c6fa0b4c 550 /* standard ehci functions */
79ad3b5a 551 .irq = ehci_irq,
79ad3b5a
BG		 552 .start = ehci_run,
553 .stop = ehci_stop,
79ad3b5a
BG		 554 .urb_enqueue = ehci_urb_enqueue,
555 .urb_dequeue = ehci_urb_dequeue,
556 .endpoint_disable = ehci_endpoint_disable,
557 .endpoint_reset = ehci_endpoint_reset,
558 .get_frame_number = ehci_get_frame,
559 .hub_status_data = ehci_hub_status_data,
79ad3b5a 560 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
c6fa0b4c
VB		 561 .relinquish_port = ehci_relinquish_port,
562 .port_handed_over = ehci_port_handed_over,
563
564 /* modified ehci functions for tegra */
565 .reset = tegra_ehci_setup,
566 .shutdown = tegra_ehci_shutdown,
567 .map_urb_for_dma = tegra_ehci_map_urb_for_dma,
568 .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma,
569 .hub_control = tegra_ehci_hub_control,
79ad3b5a
BG		 570#ifdef CONFIG_PM
571 .bus_suspend = tegra_ehci_bus_suspend,
572 .bus_resume = tegra_ehci_bus_resume,
573#endif
79ad3b5a
BG		 574};
575
4a53f4e6
OJ		 576static int setup_vbus_gpio(struct platform_device *pdev)
577{
578 int err = 0;
579 int gpio;
580
581 if (!pdev->dev.of_node)
582 return 0;
583
584 gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0);
585 if (!gpio_is_valid(gpio))
586 return 0;
587
588 err = gpio_request(gpio, "vbus_gpio");
589 if (err) {
590 dev_err(&pdev->dev, "can't request vbus gpio %d", gpio);
591 return err;
592 }
593 err = gpio_direction_output(gpio, 1);
594 if (err) {
595 dev_err(&pdev->dev, "can't enable vbus\n");
596 return err;
597 }
598 gpio_set_value(gpio, 1);
599
600 return err;
601}
602
603static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32);
604
79ad3b5a
BG		 605static int tegra_ehci_probe(struct platform_device *pdev)
606{
607 struct resource *res;
608 struct usb_hcd *hcd;
609 struct tegra_ehci_hcd *tegra;
610 struct tegra_ehci_platform_data *pdata;
611 int err = 0;
612 int irq;
613 int instance = pdev->id;
614
615 pdata = pdev->dev.platform_data;
616 if (!pdata) {
617 dev_err(&pdev->dev, "Platform data missing\n");
618 return -EINVAL;
619 }
620
4a53f4e6
OJ		 621 /* Right now device-tree probed devices don't get dma_mask set.
622 * Since shared usb code relies on it, set it here for now.
623 * Once we have dma capability bindings this can go away.
624 */
625 if (!pdev->dev.dma_mask)
626 pdev->dev.dma_mask = &tegra_ehci_dma_mask;
627
628 setup_vbus_gpio(pdev);
629
79ad3b5a
BG		 630 tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL);
631 if (!tegra)
632 return -ENOMEM;
633
634 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
635 dev_name(&pdev->dev));
636 if (!hcd) {
637 dev_err(&pdev->dev, "Unable to create HCD\n");
638 err = -ENOMEM;
639 goto fail_hcd;
640 }
641
642 platform_set_drvdata(pdev, tegra);
643
644 tegra->clk = clk_get(&pdev->dev, NULL);
645 if (IS_ERR(tegra->clk)) {
646 dev_err(&pdev->dev, "Can't get ehci clock\n");
647 err = PTR_ERR(tegra->clk);
648 goto fail_clk;
649 }
650
651 err = clk_enable(tegra->clk);
652 if (err)
653 goto fail_clken;
654
655 tegra->emc_clk = clk_get(&pdev->dev, "emc");
656 if (IS_ERR(tegra->emc_clk)) {
657 dev_err(&pdev->dev, "Can't get emc clock\n");
658 err = PTR_ERR(tegra->emc_clk);
659 goto fail_emc_clk;
660 }
661
662 clk_enable(tegra->emc_clk);
663 clk_set_rate(tegra->emc_clk, 400000000);
664
665 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
666 if (!res) {
667 dev_err(&pdev->dev, "Failed to get I/O memory\n");
668 err = -ENXIO;
669 goto fail_io;
670 }
671 hcd->rsrc_start = res->start;
672 hcd->rsrc_len = resource_size(res);
673 hcd->regs = ioremap(res->start, resource_size(res));
674 if (!hcd->regs) {
675 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
676 err = -ENOMEM;
677 goto fail_io;
678 }
679
4a53f4e6
OJ		 680 /* This is pretty ugly and needs to be fixed when we do only
681 * device-tree probing. Old code relies on the platform_device
682 * numbering that we lack for device-tree-instantiated devices.
683 */
684 if (instance < 0) {
685 switch (res->start) {
686 case TEGRA_USB_BASE:
687 instance = 0;
688 break;
689 case TEGRA_USB2_BASE:
690 instance = 1;
691 break;
692 case TEGRA_USB3_BASE:
693 instance = 2;
694 break;
695 default:
696 err = -ENODEV;
697 dev_err(&pdev->dev, "unknown usb instance\n");
698 goto fail_phy;
699 }
700 }
701
79ad3b5a
BG		 702 tegra->phy = tegra_usb_phy_open(instance, hcd->regs, pdata->phy_config,
703 TEGRA_USB_PHY_MODE_HOST);
704 if (IS_ERR(tegra->phy)) {
705 dev_err(&pdev->dev, "Failed to open USB phy\n");
706 err = -ENXIO;
707 goto fail_phy;
708 }
709
710 err = tegra_usb_phy_power_on(tegra->phy);
711 if (err) {
712 dev_err(&pdev->dev, "Failed to power on the phy\n");
713 goto fail;
714 }
715
716 tegra->host_resumed = 1;
717 tegra->power_down_on_bus_suspend = pdata->power_down_on_bus_suspend;
718 tegra->ehci = hcd_to_ehci(hcd);
719
720 irq = platform_get_irq(pdev, 0);
721 if (!irq) {
722 dev_err(&pdev->dev, "Failed to get IRQ\n");
723 err = -ENODEV;
724 goto fail;
725 }
726 set_irq_flags(irq, IRQF_VALID);
727
728#ifdef CONFIG_USB_OTG_UTILS
729 if (pdata->operating_mode == TEGRA_USB_OTG) {
b96d3b08 730 tegra->transceiver = usb_get_transceiver();
79ad3b5a 731 if (tegra->transceiver)
6e13c650 732 otg_set_host(tegra->transceiver->otg, &hcd->self);
79ad3b5a
BG		 733 }
734#endif
735
b5dd18d8 736 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
79ad3b5a
BG		 737 if (err) {
738 dev_err(&pdev->dev, "Failed to add USB HCD\n");
739 goto fail;
740 }
741
742 return err;
743
744fail:
745#ifdef CONFIG_USB_OTG_UTILS
746 if (tegra->transceiver) {
6e13c650 747 otg_set_host(tegra->transceiver->otg, NULL);
b96d3b08 748 usb_put_transceiver(tegra->transceiver);
79ad3b5a
BG		 749 }
750#endif
751 tegra_usb_phy_close(tegra->phy);
752fail_phy:
753 iounmap(hcd->regs);
754fail_io:
755 clk_disable(tegra->emc_clk);
756 clk_put(tegra->emc_clk);
757fail_emc_clk:
758 clk_disable(tegra->clk);
759fail_clken:
760 clk_put(tegra->clk);
761fail_clk:
762 usb_put_hcd(hcd);
763fail_hcd:
764 kfree(tegra);
765 return err;
766}
767
768#ifdef CONFIG_PM
769static int tegra_ehci_resume(struct platform_device *pdev)
770{
771 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
772 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
773
774 if (tegra->bus_suspended)
775 return 0;
776
777 return tegra_usb_resume(hcd);
778}
779
780static int tegra_ehci_suspend(struct platform_device *pdev, pm_message_t state)
781{
782 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
783 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
784
785 if (tegra->bus_suspended)
786 return 0;
787
788 if (time_before(jiffies, tegra->ehci->next_statechange))
789 msleep(10);
790
791 return tegra_usb_suspend(hcd);
792}
793#endif
794
795static int tegra_ehci_remove(struct platform_device *pdev)
796{
797 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
798 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
799
800 if (tegra == NULL || hcd == NULL)
801 return -EINVAL;
802
803#ifdef CONFIG_USB_OTG_UTILS
804 if (tegra->transceiver) {
6e13c650 805 otg_set_host(tegra->transceiver->otg, NULL);
b96d3b08 806 usb_put_transceiver(tegra->transceiver);
79ad3b5a
BG		 807 }
808#endif
809
810 usb_remove_hcd(hcd);
811 usb_put_hcd(hcd);
812
813 tegra_usb_phy_close(tegra->phy);
814 iounmap(hcd->regs);
815
816 clk_disable(tegra->clk);
817 clk_put(tegra->clk);
818
819 clk_disable(tegra->emc_clk);
820 clk_put(tegra->emc_clk);
821
822 kfree(tegra);
823 return 0;
824}
825
826static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
827{
828 struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev);
829 struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci);
830
831 if (hcd->driver->shutdown)
832 hcd->driver->shutdown(hcd);
833}
834
4a53f4e6
OJ		 835static struct of_device_id tegra_ehci_of_match[] __devinitdata = {
836 { .compatible = "nvidia,tegra20-ehci", },
837 { },
838};
839
79ad3b5a
BG		 840static struct platform_driver tegra_ehci_driver = {
841 .probe = tegra_ehci_probe,
842 .remove = tegra_ehci_remove,
843#ifdef CONFIG_PM
844 .suspend = tegra_ehci_suspend,
845 .resume = tegra_ehci_resume,
846#endif
847 .shutdown = tegra_ehci_hcd_shutdown,
848 .driver = {
849 .name = "tegra-ehci",
4a53f4e6 850 .of_match_table = tegra_ehci_of_match,
79ad3b5a
BG		 851 }
852};
Linux 6.x block layer and io_uring tree(s)