Commit | Line | Data |
---|---|---|
79ad3b5a BG |
1 | /* |
2 | * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
bbdabdb6 | 5 | * Copyright (C) 2009 - 2013 NVIDIA Corporation |
79ad3b5a BG |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
9fc5f24e MG |
20 | #include <linux/clk/tegra.h> |
21 | #include <linux/dma-mapping.h> | |
ded017ee | 22 | #include <linux/err.h> |
4a53f4e6 | 23 | #include <linux/gpio.h> |
9fc5f24e MG |
24 | #include <linux/io.h> |
25 | #include <linux/irq.h> | |
26 | #include <linux/module.h> | |
4a53f4e6 | 27 | #include <linux/of.h> |
327d8b42 | 28 | #include <linux/of_device.h> |
4a53f4e6 | 29 | #include <linux/of_gpio.h> |
9fc5f24e | 30 | #include <linux/platform_device.h> |
ebf20de4 | 31 | #include <linux/pm_runtime.h> |
9fc5f24e | 32 | #include <linux/slab.h> |
bbdabdb6 | 33 | #include <linux/usb/ehci_def.h> |
1ba8216f | 34 | #include <linux/usb/tegra_usb_phy.h> |
9fc5f24e MG |
35 | #include <linux/usb.h> |
36 | #include <linux/usb/hcd.h> | |
37 | #include <linux/usb/otg.h> | |
38 | ||
39 | #include "ehci.h" | |
54388b28 SW |
40 | |
41 | #define TEGRA_USB_BASE 0xC5000000 | |
42 | #define TEGRA_USB2_BASE 0xC5004000 | |
43 | #define TEGRA_USB3_BASE 0xC5008000 | |
79ad3b5a | 44 | |
9fc5f24e MG |
45 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) |
46 | ||
fbf9865c RM |
47 | #define TEGRA_USB_DMA_ALIGN 32 |
48 | ||
9fc5f24e MG |
49 | #define DRIVER_DESC "Tegra EHCI driver" |
50 | #define DRV_NAME "tegra-ehci" | |
51 | ||
52 | static struct hc_driver __read_mostly tegra_ehci_hc_driver; | |
53 | ||
327d8b42 TT |
54 | struct tegra_ehci_soc_config { |
55 | bool has_hostpc; | |
56 | }; | |
57 | ||
9fc5f24e MG |
58 | static int (*orig_hub_control)(struct usb_hcd *hcd, |
59 | u16 typeReq, u16 wValue, u16 wIndex, | |
60 | char *buf, u16 wLength); | |
61 | ||
79ad3b5a | 62 | struct tegra_ehci_hcd { |
79ad3b5a BG |
63 | struct tegra_usb_phy *phy; |
64 | struct clk *clk; | |
79ad3b5a | 65 | int port_resuming; |
585355c5 | 66 | bool needs_double_reset; |
79ad3b5a BG |
67 | enum tegra_usb_phy_port_speed port_speed; |
68 | }; | |
69 | ||
1f594b64 JL |
70 | static int tegra_ehci_internal_port_reset( |
71 | struct ehci_hcd *ehci, | |
72 | u32 __iomem *portsc_reg | |
73 | ) | |
74 | { | |
75 | u32 temp; | |
76 | unsigned long flags; | |
77 | int retval = 0; | |
78 | int i, tries; | |
79 | u32 saved_usbintr; | |
80 | ||
81 | spin_lock_irqsave(&ehci->lock, flags); | |
82 | saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); | |
83 | /* disable USB interrupt */ | |
84 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | |
85 | spin_unlock_irqrestore(&ehci->lock, flags); | |
86 | ||
87 | /* | |
88 | * Here we have to do Port Reset at most twice for | |
89 | * Port Enable bit to be set. | |
90 | */ | |
91 | for (i = 0; i < 2; i++) { | |
92 | temp = ehci_readl(ehci, portsc_reg); | |
93 | temp |= PORT_RESET; | |
94 | ehci_writel(ehci, temp, portsc_reg); | |
95 | mdelay(10); | |
96 | temp &= ~PORT_RESET; | |
97 | ehci_writel(ehci, temp, portsc_reg); | |
98 | mdelay(1); | |
99 | tries = 100; | |
100 | do { | |
101 | mdelay(1); | |
102 | /* | |
103 | * Up to this point, Port Enable bit is | |
104 | * expected to be set after 2 ms waiting. | |
105 | * USB1 usually takes extra 45 ms, for safety, | |
106 | * we take 100 ms as timeout. | |
107 | */ | |
108 | temp = ehci_readl(ehci, portsc_reg); | |
109 | } while (!(temp & PORT_PE) && tries--); | |
110 | if (temp & PORT_PE) | |
111 | break; | |
112 | } | |
113 | if (i == 2) | |
114 | retval = -ETIMEDOUT; | |
115 | ||
116 | /* | |
117 | * Clear Connect Status Change bit if it's set. | |
118 | * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. | |
119 | */ | |
120 | if (temp & PORT_CSC) | |
121 | ehci_writel(ehci, PORT_CSC, portsc_reg); | |
122 | ||
123 | /* | |
124 | * Write to clear any interrupt status bits that might be set | |
125 | * during port reset. | |
126 | */ | |
127 | temp = ehci_readl(ehci, &ehci->regs->status); | |
128 | ehci_writel(ehci, temp, &ehci->regs->status); | |
129 | ||
130 | /* restore original interrupt enable bits */ | |
131 | ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); | |
132 | return retval; | |
133 | } | |
134 | ||
79ad3b5a BG |
135 | static int tegra_ehci_hub_control( |
136 | struct usb_hcd *hcd, | |
137 | u16 typeReq, | |
138 | u16 wValue, | |
139 | u16 wIndex, | |
140 | char *buf, | |
141 | u16 wLength | |
142 | ) | |
143 | { | |
c19d14d6 SW |
144 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
145 | struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv; | |
79ad3b5a BG |
146 | u32 __iomem *status_reg; |
147 | u32 temp; | |
148 | unsigned long flags; | |
149 | int retval = 0; | |
150 | ||
151 | status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; | |
152 | ||
153 | spin_lock_irqsave(&ehci->lock, flags); | |
154 | ||
6d5f89c7 | 155 | if (typeReq == GetPortStatus) { |
79ad3b5a BG |
156 | temp = ehci_readl(ehci, status_reg); |
157 | if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { | |
158 | /* Resume completed, re-enable disconnect detection */ | |
159 | tegra->port_resuming = 0; | |
ab137d04 | 160 | tegra_usb_phy_postresume(hcd->phy); |
79ad3b5a BG |
161 | } |
162 | } | |
163 | ||
164 | else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { | |
165 | temp = ehci_readl(ehci, status_reg); | |
166 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { | |
167 | retval = -EPIPE; | |
168 | goto done; | |
169 | } | |
170 | ||
b0876574 | 171 | temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E); |
79ad3b5a BG |
172 | temp |= PORT_WKDISC_E | PORT_WKOC_E; |
173 | ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); | |
174 | ||
175 | /* | |
176 | * If a transaction is in progress, there may be a delay in | |
177 | * suspending the port. Poll until the port is suspended. | |
178 | */ | |
2f3a6b86 | 179 | if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, |
79ad3b5a BG |
180 | PORT_SUSPEND, 5000)) |
181 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); | |
182 | ||
183 | set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); | |
184 | goto done; | |
185 | } | |
186 | ||
1f594b64 | 187 | /* For USB1 port we need to issue Port Reset twice internally */ |
585355c5 | 188 | if (tegra->needs_double_reset && |
1f594b64 JL |
189 | (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { |
190 | spin_unlock_irqrestore(&ehci->lock, flags); | |
191 | return tegra_ehci_internal_port_reset(ehci, status_reg); | |
192 | } | |
193 | ||
79ad3b5a BG |
194 | /* |
195 | * Tegra host controller will time the resume operation to clear the bit | |
196 | * when the port control state switches to HS or FS Idle. This behavior | |
197 | * is different from EHCI where the host controller driver is required | |
198 | * to set this bit to a zero after the resume duration is timed in the | |
199 | * driver. | |
200 | */ | |
201 | else if (typeReq == ClearPortFeature && | |
202 | wValue == USB_PORT_FEAT_SUSPEND) { | |
203 | temp = ehci_readl(ehci, status_reg); | |
204 | if ((temp & PORT_RESET) || !(temp & PORT_PE)) { | |
205 | retval = -EPIPE; | |
206 | goto done; | |
207 | } | |
208 | ||
209 | if (!(temp & PORT_SUSPEND)) | |
210 | goto done; | |
211 | ||
212 | /* Disable disconnect detection during port resume */ | |
ab137d04 | 213 | tegra_usb_phy_preresume(hcd->phy); |
79ad3b5a BG |
214 | |
215 | ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); | |
216 | ||
217 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | |
218 | /* start resume signalling */ | |
219 | ehci_writel(ehci, temp | PORT_RESUME, status_reg); | |
a448e4dc | 220 | set_bit(wIndex-1, &ehci->resuming_ports); |
79ad3b5a BG |
221 | |
222 | spin_unlock_irqrestore(&ehci->lock, flags); | |
223 | msleep(20); | |
224 | spin_lock_irqsave(&ehci->lock, flags); | |
225 | ||
226 | /* Poll until the controller clears RESUME and SUSPEND */ | |
2f3a6b86 | 227 | if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) |
79ad3b5a | 228 | pr_err("%s: timeout waiting for RESUME\n", __func__); |
2f3a6b86 | 229 | if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) |
79ad3b5a BG |
230 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); |
231 | ||
232 | ehci->reset_done[wIndex-1] = 0; | |
a448e4dc | 233 | clear_bit(wIndex-1, &ehci->resuming_ports); |
79ad3b5a BG |
234 | |
235 | tegra->port_resuming = 1; | |
236 | goto done; | |
237 | } | |
238 | ||
239 | spin_unlock_irqrestore(&ehci->lock, flags); | |
240 | ||
241 | /* Handle the hub control events here */ | |
9fc5f24e MG |
242 | return orig_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); |
243 | ||
79ad3b5a BG |
244 | done: |
245 | spin_unlock_irqrestore(&ehci->lock, flags); | |
246 | return retval; | |
247 | } | |
248 | ||
fe375774 | 249 | struct dma_aligned_buffer { |
fbf9865c RM |
250 | void *kmalloc_ptr; |
251 | void *old_xfer_buffer; | |
252 | u8 data[0]; | |
253 | }; | |
254 | ||
fe375774 | 255 | static void free_dma_aligned_buffer(struct urb *urb) |
fbf9865c | 256 | { |
fe375774 | 257 | struct dma_aligned_buffer *temp; |
fbf9865c RM |
258 | |
259 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) | |
260 | return; | |
261 | ||
fe375774 VB |
262 | temp = container_of(urb->transfer_buffer, |
263 | struct dma_aligned_buffer, data); | |
fbf9865c | 264 | |
fe375774 | 265 | if (usb_urb_dir_in(urb)) |
fbf9865c RM |
266 | memcpy(temp->old_xfer_buffer, temp->data, |
267 | urb->transfer_buffer_length); | |
268 | urb->transfer_buffer = temp->old_xfer_buffer; | |
269 | kfree(temp->kmalloc_ptr); | |
270 | ||
271 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; | |
272 | } | |
273 | ||
fe375774 | 274 | static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) |
fbf9865c | 275 | { |
fe375774 | 276 | struct dma_aligned_buffer *temp, *kmalloc_ptr; |
fbf9865c RM |
277 | size_t kmalloc_size; |
278 | ||
279 | if (urb->num_sgs || urb->sg || | |
280 | urb->transfer_buffer_length == 0 || | |
281 | !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1))) | |
282 | return 0; | |
283 | ||
fbf9865c RM |
284 | /* Allocate a buffer with enough padding for alignment */ |
285 | kmalloc_size = urb->transfer_buffer_length + | |
fe375774 | 286 | sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1; |
fbf9865c RM |
287 | |
288 | kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); | |
289 | if (!kmalloc_ptr) | |
290 | return -ENOMEM; | |
291 | ||
fe375774 | 292 | /* Position our struct dma_aligned_buffer such that data is aligned */ |
fbf9865c | 293 | temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1; |
fbf9865c RM |
294 | temp->kmalloc_ptr = kmalloc_ptr; |
295 | temp->old_xfer_buffer = urb->transfer_buffer; | |
fe375774 | 296 | if (usb_urb_dir_out(urb)) |
fbf9865c RM |
297 | memcpy(temp->data, urb->transfer_buffer, |
298 | urb->transfer_buffer_length); | |
299 | urb->transfer_buffer = temp->data; | |
300 | ||
301 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; | |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, | |
307 | gfp_t mem_flags) | |
308 | { | |
309 | int ret; | |
310 | ||
fe375774 | 311 | ret = alloc_dma_aligned_buffer(urb, mem_flags); |
fbf9865c RM |
312 | if (ret) |
313 | return ret; | |
314 | ||
315 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
316 | if (ret) | |
fe375774 | 317 | free_dma_aligned_buffer(urb); |
fbf9865c RM |
318 | |
319 | return ret; | |
320 | } | |
321 | ||
322 | static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) | |
323 | { | |
324 | usb_hcd_unmap_urb_for_dma(hcd, urb); | |
fe375774 | 325 | free_dma_aligned_buffer(urb); |
fbf9865c RM |
326 | } |
327 | ||
327d8b42 TT |
328 | static const struct tegra_ehci_soc_config tegra30_soc_config = { |
329 | .has_hostpc = true, | |
330 | }; | |
331 | ||
332 | static const struct tegra_ehci_soc_config tegra20_soc_config = { | |
333 | .has_hostpc = false, | |
334 | }; | |
335 | ||
336 | static struct of_device_id tegra_ehci_of_match[] = { | |
337 | { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config }, | |
338 | { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config }, | |
339 | { }, | |
340 | }; | |
341 | ||
79ad3b5a BG |
342 | static int tegra_ehci_probe(struct platform_device *pdev) |
343 | { | |
327d8b42 TT |
344 | const struct of_device_id *match; |
345 | const struct tegra_ehci_soc_config *soc_config; | |
79ad3b5a BG |
346 | struct resource *res; |
347 | struct usb_hcd *hcd; | |
c19d14d6 | 348 | struct ehci_hcd *ehci; |
79ad3b5a | 349 | struct tegra_ehci_hcd *tegra; |
79ad3b5a BG |
350 | int err = 0; |
351 | int irq; | |
bbdabdb6 | 352 | struct usb_phy *u_phy; |
79ad3b5a | 353 | |
327d8b42 TT |
354 | match = of_match_device(tegra_ehci_of_match, &pdev->dev); |
355 | if (!match) { | |
356 | dev_err(&pdev->dev, "Error: No device match found\n"); | |
357 | return -ENODEV; | |
358 | } | |
359 | soc_config = match->data; | |
360 | ||
4a53f4e6 OJ |
361 | /* Right now device-tree probed devices don't get dma_mask set. |
362 | * Since shared usb code relies on it, set it here for now. | |
363 | * Once we have dma capability bindings this can go away. | |
364 | */ | |
e1fd7341 | 365 | err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
22d9d8e8 RK |
366 | if (err) |
367 | return err; | |
4a53f4e6 | 368 | |
c19d14d6 SW |
369 | hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev, |
370 | dev_name(&pdev->dev)); | |
371 | if (!hcd) { | |
372 | dev_err(&pdev->dev, "Unable to create HCD\n"); | |
f5b8c8b6 | 373 | return -ENOMEM; |
c19d14d6 SW |
374 | } |
375 | platform_set_drvdata(pdev, hcd); | |
376 | ehci = hcd_to_ehci(hcd); | |
377 | tegra = (struct tegra_ehci_hcd *)ehci->priv; | |
378 | ||
379 | hcd->has_tt = 1; | |
79ad3b5a | 380 | |
bc2ff98f | 381 | tegra->clk = devm_clk_get(&pdev->dev, NULL); |
79ad3b5a BG |
382 | if (IS_ERR(tegra->clk)) { |
383 | dev_err(&pdev->dev, "Can't get ehci clock\n"); | |
c19d14d6 SW |
384 | err = PTR_ERR(tegra->clk); |
385 | goto cleanup_hcd_create; | |
79ad3b5a BG |
386 | } |
387 | ||
20de12cc | 388 | err = clk_prepare_enable(tegra->clk); |
79ad3b5a | 389 | if (err) |
dafbe92e | 390 | goto cleanup_hcd_create; |
79ad3b5a | 391 | |
eb5369ed VB |
392 | tegra_periph_reset_assert(tegra->clk); |
393 | udelay(1); | |
394 | tegra_periph_reset_deassert(tegra->clk); | |
395 | ||
7db71a9a | 396 | u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0); |
2d22b42d VB |
397 | if (IS_ERR(u_phy)) { |
398 | err = PTR_ERR(u_phy); | |
c19d14d6 | 399 | goto cleanup_clk_en; |
2d22b42d | 400 | } |
c19d14d6 | 401 | hcd->phy = u_phy; |
2d22b42d | 402 | |
585355c5 VB |
403 | tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node, |
404 | "nvidia,needs-double-reset"); | |
405 | ||
79ad3b5a BG |
406 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
407 | if (!res) { | |
408 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | |
409 | err = -ENXIO; | |
c19d14d6 | 410 | goto cleanup_clk_en; |
79ad3b5a BG |
411 | } |
412 | hcd->rsrc_start = res->start; | |
413 | hcd->rsrc_len = resource_size(res); | |
bc2ff98f | 414 | hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
79ad3b5a BG |
415 | if (!hcd->regs) { |
416 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | |
417 | err = -ENOMEM; | |
c19d14d6 | 418 | goto cleanup_clk_en; |
4a53f4e6 | 419 | } |
c19d14d6 | 420 | ehci->caps = hcd->regs + 0x100; |
327d8b42 | 421 | ehci->has_hostpc = soc_config->has_hostpc; |
4a53f4e6 | 422 | |
2d22b42d VB |
423 | err = usb_phy_init(hcd->phy); |
424 | if (err) { | |
425 | dev_err(&pdev->dev, "Failed to initialize phy\n"); | |
c19d14d6 | 426 | goto cleanup_clk_en; |
79ad3b5a BG |
427 | } |
428 | ||
bbdabdb6 VB |
429 | u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), |
430 | GFP_KERNEL); | |
431 | if (!u_phy->otg) { | |
432 | dev_err(&pdev->dev, "Failed to alloc memory for otg\n"); | |
433 | err = -ENOMEM; | |
2d22b42d | 434 | goto cleanup_phy; |
bbdabdb6 VB |
435 | } |
436 | u_phy->otg->host = hcd_to_bus(hcd); | |
437 | ||
ab137d04 | 438 | err = usb_phy_set_suspend(hcd->phy, 0); |
79ad3b5a BG |
439 | if (err) { |
440 | dev_err(&pdev->dev, "Failed to power on the phy\n"); | |
2d22b42d | 441 | goto cleanup_phy; |
79ad3b5a BG |
442 | } |
443 | ||
79ad3b5a BG |
444 | irq = platform_get_irq(pdev, 0); |
445 | if (!irq) { | |
446 | dev_err(&pdev->dev, "Failed to get IRQ\n"); | |
447 | err = -ENODEV; | |
2d22b42d | 448 | goto cleanup_phy; |
79ad3b5a | 449 | } |
79ad3b5a | 450 | |
de3f2337 | 451 | otg_set_host(u_phy->otg, &hcd->self); |
79ad3b5a | 452 | |
b5dd18d8 | 453 | err = usb_add_hcd(hcd, irq, IRQF_SHARED); |
79ad3b5a BG |
454 | if (err) { |
455 | dev_err(&pdev->dev, "Failed to add USB HCD\n"); | |
de3f2337 | 456 | goto cleanup_otg_set_host; |
79ad3b5a BG |
457 | } |
458 | ||
459 | return err; | |
460 | ||
de3f2337 TT |
461 | cleanup_otg_set_host: |
462 | otg_set_host(u_phy->otg, NULL); | |
8fefcfdd | 463 | cleanup_phy: |
ab137d04 | 464 | usb_phy_shutdown(hcd->phy); |
c19d14d6 SW |
465 | cleanup_clk_en: |
466 | clk_disable_unprepare(tegra->clk); | |
2d22b42d | 467 | cleanup_hcd_create: |
79ad3b5a | 468 | usb_put_hcd(hcd); |
79ad3b5a BG |
469 | return err; |
470 | } | |
471 | ||
79ad3b5a BG |
472 | static int tegra_ehci_remove(struct platform_device *pdev) |
473 | { | |
c19d14d6 SW |
474 | struct usb_hcd *hcd = platform_get_drvdata(pdev); |
475 | struct tegra_ehci_hcd *tegra = | |
476 | (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv; | |
79ad3b5a | 477 | |
de3f2337 | 478 | otg_set_host(hcd->phy->otg, NULL); |
79ad3b5a | 479 | |
ab137d04 | 480 | usb_phy_shutdown(hcd->phy); |
79ad3b5a | 481 | usb_remove_hcd(hcd); |
ecc8a0cd VB |
482 | usb_put_hcd(hcd); |
483 | ||
20de12cc | 484 | clk_disable_unprepare(tegra->clk); |
79ad3b5a | 485 | |
79ad3b5a BG |
486 | return 0; |
487 | } | |
488 | ||
489 | static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) | |
490 | { | |
c19d14d6 | 491 | struct usb_hcd *hcd = platform_get_drvdata(pdev); |
79ad3b5a BG |
492 | |
493 | if (hcd->driver->shutdown) | |
494 | hcd->driver->shutdown(hcd); | |
495 | } | |
496 | ||
497 | static struct platform_driver tegra_ehci_driver = { | |
498 | .probe = tegra_ehci_probe, | |
499 | .remove = tegra_ehci_remove, | |
79ad3b5a BG |
500 | .shutdown = tegra_ehci_hcd_shutdown, |
501 | .driver = { | |
9fc5f24e | 502 | .name = DRV_NAME, |
4a53f4e6 | 503 | .of_match_table = tegra_ehci_of_match, |
79ad3b5a BG |
504 | } |
505 | }; | |
9fc5f24e MG |
506 | |
507 | static const struct ehci_driver_overrides tegra_overrides __initconst = { | |
508 | .extra_priv_size = sizeof(struct tegra_ehci_hcd), | |
509 | }; | |
510 | ||
511 | static int __init ehci_tegra_init(void) | |
512 | { | |
513 | if (usb_disabled()) | |
514 | return -ENODEV; | |
515 | ||
516 | pr_info(DRV_NAME ": " DRIVER_DESC "\n"); | |
517 | ||
518 | ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides); | |
519 | ||
520 | /* | |
521 | * The Tegra HW has some unusual quirks, which require Tegra-specific | |
522 | * workarounds. We override certain hc_driver functions here to | |
523 | * achieve that. We explicitly do not enhance ehci_driver_overrides to | |
524 | * allow this more easily, since this is an unusual case, and we don't | |
525 | * want to encourage others to override these functions by making it | |
526 | * too easy. | |
527 | */ | |
528 | ||
529 | orig_hub_control = tegra_ehci_hc_driver.hub_control; | |
530 | ||
531 | tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma; | |
532 | tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma; | |
533 | tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control; | |
534 | ||
535 | return platform_driver_register(&tegra_ehci_driver); | |
536 | } | |
537 | module_init(ehci_tegra_init); | |
538 | ||
539 | static void __exit ehci_tegra_cleanup(void) | |
540 | { | |
541 | platform_driver_unregister(&tegra_ehci_driver); | |
542 | } | |
543 | module_exit(ehci_tegra_cleanup); | |
544 | ||
545 | MODULE_DESCRIPTION(DRIVER_DESC); | |
546 | MODULE_LICENSE("GPL"); | |
547 | MODULE_ALIAS("platform:" DRV_NAME); | |
548 | MODULE_DEVICE_TABLE(of, tegra_ehci_of_match); |