Commit | Line | Data |
---|---|---|
79ad3b5a BG |
1 | /* |
2 | * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
bbdabdb6 | 5 | * Copyright (C) 2009 - 2013 NVIDIA Corporation |
79ad3b5a BG |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
ded017ee | 20 | #include <linux/err.h> |
79ad3b5a BG |
21 | #include <linux/platform_device.h> |
22 | #include <linux/platform_data/tegra_usb.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/usb/otg.h> | |
4a53f4e6 OJ |
25 | #include <linux/gpio.h> |
26 | #include <linux/of.h> | |
27 | #include <linux/of_gpio.h> | |
ebf20de4 | 28 | #include <linux/pm_runtime.h> |
bbdabdb6 | 29 | #include <linux/usb/ehci_def.h> |
1ba8216f | 30 | #include <linux/usb/tegra_usb_phy.h> |
eb5369ed | 31 | #include <linux/clk/tegra.h> |
54388b28 SW |
32 | |
33 | #define TEGRA_USB_BASE 0xC5000000 | |
34 | #define TEGRA_USB2_BASE 0xC5004000 | |
35 | #define TEGRA_USB3_BASE 0xC5008000 | |
79ad3b5a | 36 | |
fbf9865c RM |
37 | #define TEGRA_USB_DMA_ALIGN 32 |
38 | ||
79ad3b5a BG |
39 | struct tegra_ehci_hcd { |
40 | struct ehci_hcd *ehci; | |
41 | struct tegra_usb_phy *phy; | |
42 | struct clk *clk; | |
86753811 | 43 | struct usb_phy *transceiver; |
79ad3b5a | 44 | int port_resuming; |
585355c5 | 45 | bool needs_double_reset; |
79ad3b5a BG |
46 | enum tegra_usb_phy_port_speed port_speed; |
47 | }; | |
48 | ||
1f594b64 JL |
49 | static int tegra_ehci_internal_port_reset( |
50 | struct ehci_hcd *ehci, | |
51 | u32 __iomem *portsc_reg | |
52 | ) | |
53 | { | |
54 | u32 temp; | |
55 | unsigned long flags; | |
56 | int retval = 0; | |
57 | int i, tries; | |
58 | u32 saved_usbintr; | |
59 | ||
60 | spin_lock_irqsave(&ehci->lock, flags); | |
61 | saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); | |
62 | /* disable USB interrupt */ | |
63 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | |
64 | spin_unlock_irqrestore(&ehci->lock, flags); | |
65 | ||
66 | /* | |
67 | * Here we have to do Port Reset at most twice for | |
68 | * Port Enable bit to be set. | |
69 | */ | |
70 | for (i = 0; i < 2; i++) { | |
71 | temp = ehci_readl(ehci, portsc_reg); | |
72 | temp |= PORT_RESET; | |
73 | ehci_writel(ehci, temp, portsc_reg); | |
74 | mdelay(10); | |
75 | temp &= ~PORT_RESET; | |
76 | ehci_writel(ehci, temp, portsc_reg); | |
77 | mdelay(1); | |
78 | tries = 100; | |
79 | do { | |
80 | mdelay(1); | |
81 | /* | |
82 | * Up to this point, Port Enable bit is | |
83 | * expected to be set after 2 ms waiting. | |
84 | * USB1 usually takes extra 45 ms, for safety, | |
85 | * we take 100 ms as timeout. | |
86 | */ | |
87 | temp = ehci_readl(ehci, portsc_reg); | |
88 | } while (!(temp & PORT_PE) && tries--); | |
89 | if (temp & PORT_PE) | |
90 | break; | |
91 | } | |
92 | if (i == 2) | |
93 | retval = -ETIMEDOUT; | |
94 | ||
95 | /* | |
96 | * Clear Connect Status Change bit if it's set. | |
97 | * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. | |
98 | */ | |
99 | if (temp & PORT_CSC) | |
100 | ehci_writel(ehci, PORT_CSC, portsc_reg); | |
101 | ||
102 | /* | |
103 | * Write to clear any interrupt status bits that might be set | |
104 | * during port reset. | |
105 | */ | |
106 | temp = ehci_readl(ehci, &ehci->regs->status); | |
107 | ehci_writel(ehci, temp, &ehci->regs->status); | |
108 | ||
109 | /* restore original interrupt enable bits */ | |
110 | ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); | |
111 | return retval; | |
112 | } | |
113 | ||
79ad3b5a BG |
114 | static int tegra_ehci_hub_control( |
115 | struct usb_hcd *hcd, | |
116 | u16 typeReq, | |
117 | u16 wValue, | |
118 | u16 wIndex, | |
119 | char *buf, | |
120 | u16 wLength | |
121 | ) | |
122 | { | |
123 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
124 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
125 | u32 __iomem *status_reg; | |
126 | u32 temp; | |
127 | unsigned long flags; | |
128 | int retval = 0; | |
129 | ||
130 | status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; | |
131 | ||
132 | spin_lock_irqsave(&ehci->lock, flags); | |
133 | ||
6d5f89c7 | 134 | if (typeReq == GetPortStatus) { |
79ad3b5a BG |
135 | temp = ehci_readl(ehci, status_reg); |
136 | if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { | |
137 | /* Resume completed, re-enable disconnect detection */ | |
138 | tegra->port_resuming = 0; | |
ab137d04 | 139 | tegra_usb_phy_postresume(hcd->phy); |
79ad3b5a BG |
140 | } |
141 | } | |
142 | ||
143 | else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { | |
144 | temp = ehci_readl(ehci, status_reg); | |
145 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { | |
146 | retval = -EPIPE; | |
147 | goto done; | |
148 | } | |
149 | ||
b0876574 | 150 | temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E); |
79ad3b5a BG |
151 | temp |= PORT_WKDISC_E | PORT_WKOC_E; |
152 | ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); | |
153 | ||
154 | /* | |
155 | * If a transaction is in progress, there may be a delay in | |
156 | * suspending the port. Poll until the port is suspended. | |
157 | */ | |
2f3a6b86 | 158 | if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, |
79ad3b5a BG |
159 | PORT_SUSPEND, 5000)) |
160 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); | |
161 | ||
162 | set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); | |
163 | goto done; | |
164 | } | |
165 | ||
1f594b64 | 166 | /* For USB1 port we need to issue Port Reset twice internally */ |
585355c5 | 167 | if (tegra->needs_double_reset && |
1f594b64 JL |
168 | (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { |
169 | spin_unlock_irqrestore(&ehci->lock, flags); | |
170 | return tegra_ehci_internal_port_reset(ehci, status_reg); | |
171 | } | |
172 | ||
79ad3b5a BG |
173 | /* |
174 | * Tegra host controller will time the resume operation to clear the bit | |
175 | * when the port control state switches to HS or FS Idle. This behavior | |
176 | * is different from EHCI where the host controller driver is required | |
177 | * to set this bit to a zero after the resume duration is timed in the | |
178 | * driver. | |
179 | */ | |
180 | else if (typeReq == ClearPortFeature && | |
181 | wValue == USB_PORT_FEAT_SUSPEND) { | |
182 | temp = ehci_readl(ehci, status_reg); | |
183 | if ((temp & PORT_RESET) || !(temp & PORT_PE)) { | |
184 | retval = -EPIPE; | |
185 | goto done; | |
186 | } | |
187 | ||
188 | if (!(temp & PORT_SUSPEND)) | |
189 | goto done; | |
190 | ||
191 | /* Disable disconnect detection during port resume */ | |
ab137d04 | 192 | tegra_usb_phy_preresume(hcd->phy); |
79ad3b5a BG |
193 | |
194 | ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); | |
195 | ||
196 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | |
197 | /* start resume signalling */ | |
198 | ehci_writel(ehci, temp | PORT_RESUME, status_reg); | |
a448e4dc | 199 | set_bit(wIndex-1, &ehci->resuming_ports); |
79ad3b5a BG |
200 | |
201 | spin_unlock_irqrestore(&ehci->lock, flags); | |
202 | msleep(20); | |
203 | spin_lock_irqsave(&ehci->lock, flags); | |
204 | ||
205 | /* Poll until the controller clears RESUME and SUSPEND */ | |
2f3a6b86 | 206 | if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) |
79ad3b5a | 207 | pr_err("%s: timeout waiting for RESUME\n", __func__); |
2f3a6b86 | 208 | if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) |
79ad3b5a BG |
209 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); |
210 | ||
211 | ehci->reset_done[wIndex-1] = 0; | |
a448e4dc | 212 | clear_bit(wIndex-1, &ehci->resuming_ports); |
79ad3b5a BG |
213 | |
214 | tegra->port_resuming = 1; | |
215 | goto done; | |
216 | } | |
217 | ||
218 | spin_unlock_irqrestore(&ehci->lock, flags); | |
219 | ||
220 | /* Handle the hub control events here */ | |
221 | return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); | |
222 | done: | |
223 | spin_unlock_irqrestore(&ehci->lock, flags); | |
224 | return retval; | |
225 | } | |
226 | ||
79ad3b5a BG |
227 | static int tegra_ehci_setup(struct usb_hcd *hcd) |
228 | { | |
229 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
79ad3b5a BG |
230 | |
231 | /* EHCI registers start at offset 0x100 */ | |
232 | ehci->caps = hcd->regs + 0x100; | |
79ad3b5a BG |
233 | |
234 | /* switch to host mode */ | |
235 | hcd->has_tt = 1; | |
79ad3b5a | 236 | |
c73cee71 | 237 | return ehci_setup(hcd); |
79ad3b5a BG |
238 | } |
239 | ||
fe375774 | 240 | struct dma_aligned_buffer { |
fbf9865c RM |
241 | void *kmalloc_ptr; |
242 | void *old_xfer_buffer; | |
243 | u8 data[0]; | |
244 | }; | |
245 | ||
fe375774 | 246 | static void free_dma_aligned_buffer(struct urb *urb) |
fbf9865c | 247 | { |
fe375774 | 248 | struct dma_aligned_buffer *temp; |
fbf9865c RM |
249 | |
250 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) | |
251 | return; | |
252 | ||
fe375774 VB |
253 | temp = container_of(urb->transfer_buffer, |
254 | struct dma_aligned_buffer, data); | |
fbf9865c | 255 | |
fe375774 | 256 | if (usb_urb_dir_in(urb)) |
fbf9865c RM |
257 | memcpy(temp->old_xfer_buffer, temp->data, |
258 | urb->transfer_buffer_length); | |
259 | urb->transfer_buffer = temp->old_xfer_buffer; | |
260 | kfree(temp->kmalloc_ptr); | |
261 | ||
262 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; | |
263 | } | |
264 | ||
fe375774 | 265 | static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) |
fbf9865c | 266 | { |
fe375774 | 267 | struct dma_aligned_buffer *temp, *kmalloc_ptr; |
fbf9865c RM |
268 | size_t kmalloc_size; |
269 | ||
270 | if (urb->num_sgs || urb->sg || | |
271 | urb->transfer_buffer_length == 0 || | |
272 | !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1))) | |
273 | return 0; | |
274 | ||
fbf9865c RM |
275 | /* Allocate a buffer with enough padding for alignment */ |
276 | kmalloc_size = urb->transfer_buffer_length + | |
fe375774 | 277 | sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1; |
fbf9865c RM |
278 | |
279 | kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); | |
280 | if (!kmalloc_ptr) | |
281 | return -ENOMEM; | |
282 | ||
fe375774 | 283 | /* Position our struct dma_aligned_buffer such that data is aligned */ |
fbf9865c | 284 | temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1; |
fbf9865c RM |
285 | temp->kmalloc_ptr = kmalloc_ptr; |
286 | temp->old_xfer_buffer = urb->transfer_buffer; | |
fe375774 | 287 | if (usb_urb_dir_out(urb)) |
fbf9865c RM |
288 | memcpy(temp->data, urb->transfer_buffer, |
289 | urb->transfer_buffer_length); | |
290 | urb->transfer_buffer = temp->data; | |
291 | ||
292 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
297 | static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, | |
298 | gfp_t mem_flags) | |
299 | { | |
300 | int ret; | |
301 | ||
fe375774 | 302 | ret = alloc_dma_aligned_buffer(urb, mem_flags); |
fbf9865c RM |
303 | if (ret) |
304 | return ret; | |
305 | ||
306 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
307 | if (ret) | |
fe375774 | 308 | free_dma_aligned_buffer(urb); |
fbf9865c RM |
309 | |
310 | return ret; | |
311 | } | |
312 | ||
313 | static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) | |
314 | { | |
315 | usb_hcd_unmap_urb_for_dma(hcd, urb); | |
fe375774 | 316 | free_dma_aligned_buffer(urb); |
fbf9865c RM |
317 | } |
318 | ||
79ad3b5a BG |
319 | static const struct hc_driver tegra_ehci_hc_driver = { |
320 | .description = hcd_name, | |
321 | .product_desc = "Tegra EHCI Host Controller", | |
322 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
79ad3b5a BG |
323 | .flags = HCD_USB2 | HCD_MEMORY, |
324 | ||
c6fa0b4c | 325 | /* standard ehci functions */ |
79ad3b5a | 326 | .irq = ehci_irq, |
79ad3b5a BG |
327 | .start = ehci_run, |
328 | .stop = ehci_stop, | |
79ad3b5a BG |
329 | .urb_enqueue = ehci_urb_enqueue, |
330 | .urb_dequeue = ehci_urb_dequeue, | |
331 | .endpoint_disable = ehci_endpoint_disable, | |
332 | .endpoint_reset = ehci_endpoint_reset, | |
333 | .get_frame_number = ehci_get_frame, | |
334 | .hub_status_data = ehci_hub_status_data, | |
79ad3b5a | 335 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, |
c6fa0b4c VB |
336 | .relinquish_port = ehci_relinquish_port, |
337 | .port_handed_over = ehci_port_handed_over, | |
338 | ||
339 | /* modified ehci functions for tegra */ | |
340 | .reset = tegra_ehci_setup, | |
a4faa54e | 341 | .shutdown = ehci_shutdown, |
c6fa0b4c VB |
342 | .map_urb_for_dma = tegra_ehci_map_urb_for_dma, |
343 | .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma, | |
344 | .hub_control = tegra_ehci_hub_control, | |
79ad3b5a | 345 | #ifdef CONFIG_PM |
ebf20de4 AS |
346 | .bus_suspend = ehci_bus_suspend, |
347 | .bus_resume = ehci_bus_resume, | |
79ad3b5a | 348 | #endif |
79ad3b5a BG |
349 | }; |
350 | ||
434103ad SW |
351 | static int setup_vbus_gpio(struct platform_device *pdev, |
352 | struct tegra_ehci_platform_data *pdata) | |
4a53f4e6 OJ |
353 | { |
354 | int err = 0; | |
355 | int gpio; | |
356 | ||
434103ad SW |
357 | gpio = pdata->vbus_gpio; |
358 | if (!gpio_is_valid(gpio)) | |
359 | gpio = of_get_named_gpio(pdev->dev.of_node, | |
360 | "nvidia,vbus-gpio", 0); | |
4a53f4e6 OJ |
361 | if (!gpio_is_valid(gpio)) |
362 | return 0; | |
363 | ||
364 | err = gpio_request(gpio, "vbus_gpio"); | |
365 | if (err) { | |
366 | dev_err(&pdev->dev, "can't request vbus gpio %d", gpio); | |
367 | return err; | |
368 | } | |
369 | err = gpio_direction_output(gpio, 1); | |
370 | if (err) { | |
371 | dev_err(&pdev->dev, "can't enable vbus\n"); | |
372 | return err; | |
373 | } | |
4a53f4e6 OJ |
374 | |
375 | return err; | |
376 | } | |
377 | ||
79ad3b5a BG |
378 | static int tegra_ehci_probe(struct platform_device *pdev) |
379 | { | |
380 | struct resource *res; | |
381 | struct usb_hcd *hcd; | |
382 | struct tegra_ehci_hcd *tegra; | |
383 | struct tegra_ehci_platform_data *pdata; | |
384 | int err = 0; | |
385 | int irq; | |
2d22b42d | 386 | struct device_node *np_phy; |
bbdabdb6 | 387 | struct usb_phy *u_phy; |
79ad3b5a BG |
388 | |
389 | pdata = pdev->dev.platform_data; | |
390 | if (!pdata) { | |
391 | dev_err(&pdev->dev, "Platform data missing\n"); | |
392 | return -EINVAL; | |
393 | } | |
394 | ||
4a53f4e6 OJ |
395 | /* Right now device-tree probed devices don't get dma_mask set. |
396 | * Since shared usb code relies on it, set it here for now. | |
397 | * Once we have dma capability bindings this can go away. | |
398 | */ | |
399 | if (!pdev->dev.dma_mask) | |
3b9561e9 SW |
400 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; |
401 | if (!pdev->dev.coherent_dma_mask) | |
402 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
4a53f4e6 | 403 | |
434103ad | 404 | setup_vbus_gpio(pdev, pdata); |
4a53f4e6 | 405 | |
bc2ff98f JL |
406 | tegra = devm_kzalloc(&pdev->dev, sizeof(struct tegra_ehci_hcd), |
407 | GFP_KERNEL); | |
79ad3b5a BG |
408 | if (!tegra) |
409 | return -ENOMEM; | |
410 | ||
bc2ff98f | 411 | tegra->clk = devm_clk_get(&pdev->dev, NULL); |
79ad3b5a BG |
412 | if (IS_ERR(tegra->clk)) { |
413 | dev_err(&pdev->dev, "Can't get ehci clock\n"); | |
2d22b42d | 414 | return PTR_ERR(tegra->clk); |
79ad3b5a BG |
415 | } |
416 | ||
20de12cc | 417 | err = clk_prepare_enable(tegra->clk); |
79ad3b5a | 418 | if (err) |
2d22b42d | 419 | return err; |
79ad3b5a | 420 | |
eb5369ed VB |
421 | tegra_periph_reset_assert(tegra->clk); |
422 | udelay(1); | |
423 | tegra_periph_reset_deassert(tegra->clk); | |
424 | ||
2d22b42d VB |
425 | np_phy = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0); |
426 | if (!np_phy) { | |
427 | err = -ENODEV; | |
428 | goto cleanup_clk; | |
429 | } | |
430 | ||
431 | u_phy = tegra_usb_get_phy(np_phy); | |
432 | if (IS_ERR(u_phy)) { | |
433 | err = PTR_ERR(u_phy); | |
434 | goto cleanup_clk; | |
435 | } | |
436 | ||
585355c5 VB |
437 | tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node, |
438 | "nvidia,needs-double-reset"); | |
439 | ||
2d22b42d VB |
440 | hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev, |
441 | dev_name(&pdev->dev)); | |
442 | if (!hcd) { | |
443 | dev_err(&pdev->dev, "Unable to create HCD\n"); | |
444 | err = -ENOMEM; | |
445 | goto cleanup_clk; | |
446 | } | |
447 | hcd->phy = u_phy; | |
448 | ||
79ad3b5a BG |
449 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
450 | if (!res) { | |
451 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | |
452 | err = -ENXIO; | |
2d22b42d | 453 | goto cleanup_hcd_create; |
79ad3b5a BG |
454 | } |
455 | hcd->rsrc_start = res->start; | |
456 | hcd->rsrc_len = resource_size(res); | |
bc2ff98f | 457 | hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
79ad3b5a BG |
458 | if (!hcd->regs) { |
459 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | |
460 | err = -ENOMEM; | |
2d22b42d | 461 | goto cleanup_hcd_create; |
4a53f4e6 OJ |
462 | } |
463 | ||
2d22b42d VB |
464 | err = usb_phy_init(hcd->phy); |
465 | if (err) { | |
466 | dev_err(&pdev->dev, "Failed to initialize phy\n"); | |
467 | goto cleanup_hcd_create; | |
79ad3b5a BG |
468 | } |
469 | ||
bbdabdb6 VB |
470 | u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), |
471 | GFP_KERNEL); | |
472 | if (!u_phy->otg) { | |
473 | dev_err(&pdev->dev, "Failed to alloc memory for otg\n"); | |
474 | err = -ENOMEM; | |
2d22b42d | 475 | goto cleanup_phy; |
bbdabdb6 VB |
476 | } |
477 | u_phy->otg->host = hcd_to_bus(hcd); | |
478 | ||
ab137d04 | 479 | err = usb_phy_set_suspend(hcd->phy, 0); |
79ad3b5a BG |
480 | if (err) { |
481 | dev_err(&pdev->dev, "Failed to power on the phy\n"); | |
2d22b42d | 482 | goto cleanup_phy; |
79ad3b5a BG |
483 | } |
484 | ||
79ad3b5a BG |
485 | tegra->ehci = hcd_to_ehci(hcd); |
486 | ||
487 | irq = platform_get_irq(pdev, 0); | |
488 | if (!irq) { | |
489 | dev_err(&pdev->dev, "Failed to get IRQ\n"); | |
490 | err = -ENODEV; | |
2d22b42d | 491 | goto cleanup_phy; |
79ad3b5a | 492 | } |
79ad3b5a | 493 | |
79ad3b5a | 494 | if (pdata->operating_mode == TEGRA_USB_OTG) { |
bc2ff98f JL |
495 | tegra->transceiver = |
496 | devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); | |
4261b8f3 | 497 | if (!IS_ERR(tegra->transceiver)) |
6e13c650 | 498 | otg_set_host(tegra->transceiver->otg, &hcd->self); |
369a9a9d TR |
499 | } else { |
500 | tegra->transceiver = ERR_PTR(-ENODEV); | |
79ad3b5a | 501 | } |
79ad3b5a | 502 | |
2d22b42d VB |
503 | platform_set_drvdata(pdev, tegra); |
504 | ||
b5dd18d8 | 505 | err = usb_add_hcd(hcd, irq, IRQF_SHARED); |
79ad3b5a BG |
506 | if (err) { |
507 | dev_err(&pdev->dev, "Failed to add USB HCD\n"); | |
2d22b42d | 508 | goto cleanup_phy; |
79ad3b5a BG |
509 | } |
510 | ||
511 | return err; | |
512 | ||
2d22b42d | 513 | cleanup_phy: |
4261b8f3 | 514 | if (!IS_ERR(tegra->transceiver)) |
6e13c650 | 515 | otg_set_host(tegra->transceiver->otg, NULL); |
2d22b42d | 516 | |
ab137d04 | 517 | usb_phy_shutdown(hcd->phy); |
2d22b42d | 518 | cleanup_hcd_create: |
79ad3b5a | 519 | usb_put_hcd(hcd); |
2d22b42d VB |
520 | cleanup_clk: |
521 | clk_disable_unprepare(tegra->clk); | |
79ad3b5a BG |
522 | return err; |
523 | } | |
524 | ||
79ad3b5a BG |
525 | static int tegra_ehci_remove(struct platform_device *pdev) |
526 | { | |
527 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | |
528 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
529 | ||
4261b8f3 | 530 | if (!IS_ERR(tegra->transceiver)) |
6e13c650 | 531 | otg_set_host(tegra->transceiver->otg, NULL); |
79ad3b5a | 532 | |
ab137d04 | 533 | usb_phy_shutdown(hcd->phy); |
79ad3b5a | 534 | usb_remove_hcd(hcd); |
ecc8a0cd VB |
535 | usb_put_hcd(hcd); |
536 | ||
20de12cc | 537 | clk_disable_unprepare(tegra->clk); |
79ad3b5a | 538 | |
79ad3b5a BG |
539 | return 0; |
540 | } | |
541 | ||
542 | static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) | |
543 | { | |
544 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | |
545 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
546 | ||
547 | if (hcd->driver->shutdown) | |
548 | hcd->driver->shutdown(hcd); | |
549 | } | |
550 | ||
d3608b6d | 551 | static struct of_device_id tegra_ehci_of_match[] = { |
4a53f4e6 OJ |
552 | { .compatible = "nvidia,tegra20-ehci", }, |
553 | { }, | |
554 | }; | |
555 | ||
79ad3b5a BG |
556 | static struct platform_driver tegra_ehci_driver = { |
557 | .probe = tegra_ehci_probe, | |
558 | .remove = tegra_ehci_remove, | |
79ad3b5a BG |
559 | .shutdown = tegra_ehci_hcd_shutdown, |
560 | .driver = { | |
561 | .name = "tegra-ehci", | |
4a53f4e6 | 562 | .of_match_table = tegra_ehci_of_match, |
79ad3b5a BG |
563 | } |
564 | }; |