Commit | Line | Data |
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79ad3b5a BG |
1 | /* |
2 | * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
bbdabdb6 | 5 | * Copyright (C) 2009 - 2013 NVIDIA Corporation |
79ad3b5a BG |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
ded017ee | 20 | #include <linux/err.h> |
79ad3b5a BG |
21 | #include <linux/platform_device.h> |
22 | #include <linux/platform_data/tegra_usb.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/usb/otg.h> | |
4a53f4e6 OJ |
25 | #include <linux/gpio.h> |
26 | #include <linux/of.h> | |
27 | #include <linux/of_gpio.h> | |
ebf20de4 | 28 | #include <linux/pm_runtime.h> |
bbdabdb6 | 29 | #include <linux/usb/ehci_def.h> |
1ba8216f | 30 | #include <linux/usb/tegra_usb_phy.h> |
eb5369ed | 31 | #include <linux/clk/tegra.h> |
54388b28 SW |
32 | |
33 | #define TEGRA_USB_BASE 0xC5000000 | |
34 | #define TEGRA_USB2_BASE 0xC5004000 | |
35 | #define TEGRA_USB3_BASE 0xC5008000 | |
79ad3b5a | 36 | |
bbdabdb6 VB |
37 | /* PORTSC registers */ |
38 | #define TEGRA_USB_PORTSC1 0x184 | |
39 | #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) | |
40 | #define TEGRA_USB_PORTSC1_PHCD (1 << 23) | |
41 | ||
fbf9865c RM |
42 | #define TEGRA_USB_DMA_ALIGN 32 |
43 | ||
79ad3b5a BG |
44 | struct tegra_ehci_hcd { |
45 | struct ehci_hcd *ehci; | |
46 | struct tegra_usb_phy *phy; | |
47 | struct clk *clk; | |
86753811 | 48 | struct usb_phy *transceiver; |
79ad3b5a | 49 | int host_resumed; |
79ad3b5a | 50 | int port_resuming; |
585355c5 | 51 | bool needs_double_reset; |
79ad3b5a BG |
52 | enum tegra_usb_phy_port_speed port_speed; |
53 | }; | |
54 | ||
55 | static void tegra_ehci_power_up(struct usb_hcd *hcd) | |
56 | { | |
57 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
58 | ||
20de12cc | 59 | clk_prepare_enable(tegra->clk); |
ab137d04 | 60 | usb_phy_set_suspend(hcd->phy, 0); |
79ad3b5a BG |
61 | tegra->host_resumed = 1; |
62 | } | |
63 | ||
64 | static void tegra_ehci_power_down(struct usb_hcd *hcd) | |
65 | { | |
66 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
67 | ||
68 | tegra->host_resumed = 0; | |
ab137d04 | 69 | usb_phy_set_suspend(hcd->phy, 1); |
20de12cc | 70 | clk_disable_unprepare(tegra->clk); |
79ad3b5a BG |
71 | } |
72 | ||
1f594b64 JL |
73 | static int tegra_ehci_internal_port_reset( |
74 | struct ehci_hcd *ehci, | |
75 | u32 __iomem *portsc_reg | |
76 | ) | |
77 | { | |
78 | u32 temp; | |
79 | unsigned long flags; | |
80 | int retval = 0; | |
81 | int i, tries; | |
82 | u32 saved_usbintr; | |
83 | ||
84 | spin_lock_irqsave(&ehci->lock, flags); | |
85 | saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); | |
86 | /* disable USB interrupt */ | |
87 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | |
88 | spin_unlock_irqrestore(&ehci->lock, flags); | |
89 | ||
90 | /* | |
91 | * Here we have to do Port Reset at most twice for | |
92 | * Port Enable bit to be set. | |
93 | */ | |
94 | for (i = 0; i < 2; i++) { | |
95 | temp = ehci_readl(ehci, portsc_reg); | |
96 | temp |= PORT_RESET; | |
97 | ehci_writel(ehci, temp, portsc_reg); | |
98 | mdelay(10); | |
99 | temp &= ~PORT_RESET; | |
100 | ehci_writel(ehci, temp, portsc_reg); | |
101 | mdelay(1); | |
102 | tries = 100; | |
103 | do { | |
104 | mdelay(1); | |
105 | /* | |
106 | * Up to this point, Port Enable bit is | |
107 | * expected to be set after 2 ms waiting. | |
108 | * USB1 usually takes extra 45 ms, for safety, | |
109 | * we take 100 ms as timeout. | |
110 | */ | |
111 | temp = ehci_readl(ehci, portsc_reg); | |
112 | } while (!(temp & PORT_PE) && tries--); | |
113 | if (temp & PORT_PE) | |
114 | break; | |
115 | } | |
116 | if (i == 2) | |
117 | retval = -ETIMEDOUT; | |
118 | ||
119 | /* | |
120 | * Clear Connect Status Change bit if it's set. | |
121 | * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. | |
122 | */ | |
123 | if (temp & PORT_CSC) | |
124 | ehci_writel(ehci, PORT_CSC, portsc_reg); | |
125 | ||
126 | /* | |
127 | * Write to clear any interrupt status bits that might be set | |
128 | * during port reset. | |
129 | */ | |
130 | temp = ehci_readl(ehci, &ehci->regs->status); | |
131 | ehci_writel(ehci, temp, &ehci->regs->status); | |
132 | ||
133 | /* restore original interrupt enable bits */ | |
134 | ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); | |
135 | return retval; | |
136 | } | |
137 | ||
79ad3b5a BG |
138 | static int tegra_ehci_hub_control( |
139 | struct usb_hcd *hcd, | |
140 | u16 typeReq, | |
141 | u16 wValue, | |
142 | u16 wIndex, | |
143 | char *buf, | |
144 | u16 wLength | |
145 | ) | |
146 | { | |
147 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
148 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
149 | u32 __iomem *status_reg; | |
150 | u32 temp; | |
151 | unsigned long flags; | |
152 | int retval = 0; | |
153 | ||
154 | status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; | |
155 | ||
156 | spin_lock_irqsave(&ehci->lock, flags); | |
157 | ||
6d5f89c7 | 158 | if (typeReq == GetPortStatus) { |
79ad3b5a BG |
159 | temp = ehci_readl(ehci, status_reg); |
160 | if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { | |
161 | /* Resume completed, re-enable disconnect detection */ | |
162 | tegra->port_resuming = 0; | |
ab137d04 | 163 | tegra_usb_phy_postresume(hcd->phy); |
79ad3b5a BG |
164 | } |
165 | } | |
166 | ||
167 | else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { | |
168 | temp = ehci_readl(ehci, status_reg); | |
169 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { | |
170 | retval = -EPIPE; | |
171 | goto done; | |
172 | } | |
173 | ||
b0876574 | 174 | temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E); |
79ad3b5a BG |
175 | temp |= PORT_WKDISC_E | PORT_WKOC_E; |
176 | ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); | |
177 | ||
178 | /* | |
179 | * If a transaction is in progress, there may be a delay in | |
180 | * suspending the port. Poll until the port is suspended. | |
181 | */ | |
182 | if (handshake(ehci, status_reg, PORT_SUSPEND, | |
183 | PORT_SUSPEND, 5000)) | |
184 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); | |
185 | ||
186 | set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); | |
187 | goto done; | |
188 | } | |
189 | ||
1f594b64 | 190 | /* For USB1 port we need to issue Port Reset twice internally */ |
585355c5 | 191 | if (tegra->needs_double_reset && |
1f594b64 JL |
192 | (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { |
193 | spin_unlock_irqrestore(&ehci->lock, flags); | |
194 | return tegra_ehci_internal_port_reset(ehci, status_reg); | |
195 | } | |
196 | ||
79ad3b5a BG |
197 | /* |
198 | * Tegra host controller will time the resume operation to clear the bit | |
199 | * when the port control state switches to HS or FS Idle. This behavior | |
200 | * is different from EHCI where the host controller driver is required | |
201 | * to set this bit to a zero after the resume duration is timed in the | |
202 | * driver. | |
203 | */ | |
204 | else if (typeReq == ClearPortFeature && | |
205 | wValue == USB_PORT_FEAT_SUSPEND) { | |
206 | temp = ehci_readl(ehci, status_reg); | |
207 | if ((temp & PORT_RESET) || !(temp & PORT_PE)) { | |
208 | retval = -EPIPE; | |
209 | goto done; | |
210 | } | |
211 | ||
212 | if (!(temp & PORT_SUSPEND)) | |
213 | goto done; | |
214 | ||
215 | /* Disable disconnect detection during port resume */ | |
ab137d04 | 216 | tegra_usb_phy_preresume(hcd->phy); |
79ad3b5a BG |
217 | |
218 | ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); | |
219 | ||
220 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | |
221 | /* start resume signalling */ | |
222 | ehci_writel(ehci, temp | PORT_RESUME, status_reg); | |
a448e4dc | 223 | set_bit(wIndex-1, &ehci->resuming_ports); |
79ad3b5a BG |
224 | |
225 | spin_unlock_irqrestore(&ehci->lock, flags); | |
226 | msleep(20); | |
227 | spin_lock_irqsave(&ehci->lock, flags); | |
228 | ||
229 | /* Poll until the controller clears RESUME and SUSPEND */ | |
230 | if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) | |
231 | pr_err("%s: timeout waiting for RESUME\n", __func__); | |
232 | if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) | |
233 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); | |
234 | ||
235 | ehci->reset_done[wIndex-1] = 0; | |
a448e4dc | 236 | clear_bit(wIndex-1, &ehci->resuming_ports); |
79ad3b5a BG |
237 | |
238 | tegra->port_resuming = 1; | |
239 | goto done; | |
240 | } | |
241 | ||
242 | spin_unlock_irqrestore(&ehci->lock, flags); | |
243 | ||
244 | /* Handle the hub control events here */ | |
245 | return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); | |
246 | done: | |
247 | spin_unlock_irqrestore(&ehci->lock, flags); | |
248 | return retval; | |
249 | } | |
250 | ||
251 | static void tegra_ehci_restart(struct usb_hcd *hcd) | |
252 | { | |
253 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
254 | ||
255 | ehci_reset(ehci); | |
256 | ||
257 | /* setup the frame list and Async q heads */ | |
258 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); | |
259 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
260 | /* setup the command register and set the controller in RUN mode */ | |
261 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); | |
262 | ehci->command |= CMD_RUN; | |
263 | ehci_writel(ehci, ehci->command, &ehci->regs->command); | |
264 | ||
265 | down_write(&ehci_cf_port_reset_rwsem); | |
266 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); | |
267 | /* flush posted writes */ | |
268 | ehci_readl(ehci, &ehci->regs->command); | |
269 | up_write(&ehci_cf_port_reset_rwsem); | |
270 | } | |
271 | ||
79ad3b5a BG |
272 | static void tegra_ehci_shutdown(struct usb_hcd *hcd) |
273 | { | |
274 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
275 | ||
276 | /* ehci_shutdown touches the USB controller registers, make sure | |
277 | * controller has clocks to it */ | |
278 | if (!tegra->host_resumed) | |
279 | tegra_ehci_power_up(hcd); | |
280 | ||
281 | ehci_shutdown(hcd); | |
282 | } | |
283 | ||
284 | static int tegra_ehci_setup(struct usb_hcd *hcd) | |
285 | { | |
286 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
79ad3b5a BG |
287 | |
288 | /* EHCI registers start at offset 0x100 */ | |
289 | ehci->caps = hcd->regs + 0x100; | |
79ad3b5a BG |
290 | |
291 | /* switch to host mode */ | |
292 | hcd->has_tt = 1; | |
79ad3b5a | 293 | |
c73cee71 | 294 | return ehci_setup(hcd); |
79ad3b5a BG |
295 | } |
296 | ||
fe375774 | 297 | struct dma_aligned_buffer { |
fbf9865c RM |
298 | void *kmalloc_ptr; |
299 | void *old_xfer_buffer; | |
300 | u8 data[0]; | |
301 | }; | |
302 | ||
fe375774 | 303 | static void free_dma_aligned_buffer(struct urb *urb) |
fbf9865c | 304 | { |
fe375774 | 305 | struct dma_aligned_buffer *temp; |
fbf9865c RM |
306 | |
307 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) | |
308 | return; | |
309 | ||
fe375774 VB |
310 | temp = container_of(urb->transfer_buffer, |
311 | struct dma_aligned_buffer, data); | |
fbf9865c | 312 | |
fe375774 | 313 | if (usb_urb_dir_in(urb)) |
fbf9865c RM |
314 | memcpy(temp->old_xfer_buffer, temp->data, |
315 | urb->transfer_buffer_length); | |
316 | urb->transfer_buffer = temp->old_xfer_buffer; | |
317 | kfree(temp->kmalloc_ptr); | |
318 | ||
319 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; | |
320 | } | |
321 | ||
fe375774 | 322 | static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) |
fbf9865c | 323 | { |
fe375774 | 324 | struct dma_aligned_buffer *temp, *kmalloc_ptr; |
fbf9865c RM |
325 | size_t kmalloc_size; |
326 | ||
327 | if (urb->num_sgs || urb->sg || | |
328 | urb->transfer_buffer_length == 0 || | |
329 | !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1))) | |
330 | return 0; | |
331 | ||
fbf9865c RM |
332 | /* Allocate a buffer with enough padding for alignment */ |
333 | kmalloc_size = urb->transfer_buffer_length + | |
fe375774 | 334 | sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1; |
fbf9865c RM |
335 | |
336 | kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); | |
337 | if (!kmalloc_ptr) | |
338 | return -ENOMEM; | |
339 | ||
fe375774 | 340 | /* Position our struct dma_aligned_buffer such that data is aligned */ |
fbf9865c | 341 | temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1; |
fbf9865c RM |
342 | temp->kmalloc_ptr = kmalloc_ptr; |
343 | temp->old_xfer_buffer = urb->transfer_buffer; | |
fe375774 | 344 | if (usb_urb_dir_out(urb)) |
fbf9865c RM |
345 | memcpy(temp->data, urb->transfer_buffer, |
346 | urb->transfer_buffer_length); | |
347 | urb->transfer_buffer = temp->data; | |
348 | ||
349 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, | |
355 | gfp_t mem_flags) | |
356 | { | |
357 | int ret; | |
358 | ||
fe375774 | 359 | ret = alloc_dma_aligned_buffer(urb, mem_flags); |
fbf9865c RM |
360 | if (ret) |
361 | return ret; | |
362 | ||
363 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
364 | if (ret) | |
fe375774 | 365 | free_dma_aligned_buffer(urb); |
fbf9865c RM |
366 | |
367 | return ret; | |
368 | } | |
369 | ||
370 | static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) | |
371 | { | |
372 | usb_hcd_unmap_urb_for_dma(hcd, urb); | |
fe375774 | 373 | free_dma_aligned_buffer(urb); |
fbf9865c RM |
374 | } |
375 | ||
79ad3b5a BG |
376 | static const struct hc_driver tegra_ehci_hc_driver = { |
377 | .description = hcd_name, | |
378 | .product_desc = "Tegra EHCI Host Controller", | |
379 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
79ad3b5a BG |
380 | .flags = HCD_USB2 | HCD_MEMORY, |
381 | ||
c6fa0b4c | 382 | /* standard ehci functions */ |
79ad3b5a | 383 | .irq = ehci_irq, |
79ad3b5a BG |
384 | .start = ehci_run, |
385 | .stop = ehci_stop, | |
79ad3b5a BG |
386 | .urb_enqueue = ehci_urb_enqueue, |
387 | .urb_dequeue = ehci_urb_dequeue, | |
388 | .endpoint_disable = ehci_endpoint_disable, | |
389 | .endpoint_reset = ehci_endpoint_reset, | |
390 | .get_frame_number = ehci_get_frame, | |
391 | .hub_status_data = ehci_hub_status_data, | |
79ad3b5a | 392 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, |
c6fa0b4c VB |
393 | .relinquish_port = ehci_relinquish_port, |
394 | .port_handed_over = ehci_port_handed_over, | |
395 | ||
396 | /* modified ehci functions for tegra */ | |
397 | .reset = tegra_ehci_setup, | |
398 | .shutdown = tegra_ehci_shutdown, | |
399 | .map_urb_for_dma = tegra_ehci_map_urb_for_dma, | |
400 | .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma, | |
401 | .hub_control = tegra_ehci_hub_control, | |
79ad3b5a | 402 | #ifdef CONFIG_PM |
ebf20de4 AS |
403 | .bus_suspend = ehci_bus_suspend, |
404 | .bus_resume = ehci_bus_resume, | |
79ad3b5a | 405 | #endif |
79ad3b5a BG |
406 | }; |
407 | ||
434103ad SW |
408 | static int setup_vbus_gpio(struct platform_device *pdev, |
409 | struct tegra_ehci_platform_data *pdata) | |
4a53f4e6 OJ |
410 | { |
411 | int err = 0; | |
412 | int gpio; | |
413 | ||
434103ad SW |
414 | gpio = pdata->vbus_gpio; |
415 | if (!gpio_is_valid(gpio)) | |
416 | gpio = of_get_named_gpio(pdev->dev.of_node, | |
417 | "nvidia,vbus-gpio", 0); | |
4a53f4e6 OJ |
418 | if (!gpio_is_valid(gpio)) |
419 | return 0; | |
420 | ||
421 | err = gpio_request(gpio, "vbus_gpio"); | |
422 | if (err) { | |
423 | dev_err(&pdev->dev, "can't request vbus gpio %d", gpio); | |
424 | return err; | |
425 | } | |
426 | err = gpio_direction_output(gpio, 1); | |
427 | if (err) { | |
428 | dev_err(&pdev->dev, "can't enable vbus\n"); | |
429 | return err; | |
430 | } | |
4a53f4e6 OJ |
431 | |
432 | return err; | |
433 | } | |
434 | ||
ebf20de4 AS |
435 | #ifdef CONFIG_PM |
436 | ||
437 | static int controller_suspend(struct device *dev) | |
438 | { | |
439 | struct tegra_ehci_hcd *tegra = | |
440 | platform_get_drvdata(to_platform_device(dev)); | |
441 | struct ehci_hcd *ehci = tegra->ehci; | |
442 | struct usb_hcd *hcd = ehci_to_hcd(ehci); | |
443 | struct ehci_regs __iomem *hw = ehci->regs; | |
444 | unsigned long flags; | |
445 | ||
446 | if (time_before(jiffies, ehci->next_statechange)) | |
447 | msleep(10); | |
448 | ||
c4f34764 | 449 | ehci_halt(ehci); |
ebf20de4 | 450 | |
c4f34764 | 451 | spin_lock_irqsave(&ehci->lock, flags); |
ebf20de4 | 452 | tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3; |
ebf20de4 | 453 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
ebf20de4 AS |
454 | spin_unlock_irqrestore(&ehci->lock, flags); |
455 | ||
456 | tegra_ehci_power_down(hcd); | |
457 | return 0; | |
458 | } | |
459 | ||
460 | static int controller_resume(struct device *dev) | |
461 | { | |
462 | struct tegra_ehci_hcd *tegra = | |
463 | platform_get_drvdata(to_platform_device(dev)); | |
464 | struct ehci_hcd *ehci = tegra->ehci; | |
465 | struct usb_hcd *hcd = ehci_to_hcd(ehci); | |
466 | struct ehci_regs __iomem *hw = ehci->regs; | |
467 | unsigned long val; | |
468 | ||
469 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
470 | tegra_ehci_power_up(hcd); | |
471 | ||
472 | if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) { | |
473 | /* Wait for the phy to detect new devices | |
474 | * before we restart the controller */ | |
475 | msleep(10); | |
476 | goto restart; | |
477 | } | |
478 | ||
479 | /* Force the phy to keep data lines in suspend state */ | |
ab137d04 | 480 | tegra_ehci_phy_restore_start(hcd->phy, tegra->port_speed); |
ebf20de4 AS |
481 | |
482 | /* Enable host mode */ | |
483 | tdi_reset(ehci); | |
484 | ||
485 | /* Enable Port Power */ | |
486 | val = readl(&hw->port_status[0]); | |
487 | val |= PORT_POWER; | |
488 | writel(val, &hw->port_status[0]); | |
489 | udelay(10); | |
490 | ||
491 | /* Check if the phy resume from LP0. When the phy resume from LP0 | |
492 | * USB register will be reset. */ | |
493 | if (!readl(&hw->async_next)) { | |
494 | /* Program the field PTC based on the saved speed mode */ | |
495 | val = readl(&hw->port_status[0]); | |
496 | val &= ~PORT_TEST(~0); | |
497 | if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH) | |
498 | val |= PORT_TEST_FORCE; | |
499 | else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL) | |
500 | val |= PORT_TEST(6); | |
501 | else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) | |
502 | val |= PORT_TEST(7); | |
503 | writel(val, &hw->port_status[0]); | |
504 | udelay(10); | |
505 | ||
506 | /* Disable test mode by setting PTC field to NORMAL_OP */ | |
507 | val = readl(&hw->port_status[0]); | |
508 | val &= ~PORT_TEST(~0); | |
509 | writel(val, &hw->port_status[0]); | |
510 | udelay(10); | |
511 | } | |
512 | ||
513 | /* Poll until CCS is enabled */ | |
514 | if (handshake(ehci, &hw->port_status[0], PORT_CONNECT, | |
515 | PORT_CONNECT, 2000)) { | |
516 | pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__); | |
517 | goto restart; | |
518 | } | |
519 | ||
520 | /* Poll until PE is enabled */ | |
521 | if (handshake(ehci, &hw->port_status[0], PORT_PE, | |
522 | PORT_PE, 2000)) { | |
523 | pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__); | |
524 | goto restart; | |
525 | } | |
526 | ||
527 | /* Clear the PCI status, to avoid an interrupt taken upon resume */ | |
528 | val = readl(&hw->status); | |
529 | val |= STS_PCD; | |
530 | writel(val, &hw->status); | |
531 | ||
532 | /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */ | |
533 | val = readl(&hw->port_status[0]); | |
534 | if ((val & PORT_POWER) && (val & PORT_PE)) { | |
535 | val |= PORT_SUSPEND; | |
536 | writel(val, &hw->port_status[0]); | |
537 | ||
538 | /* Wait until port suspend completes */ | |
539 | if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND, | |
540 | PORT_SUSPEND, 1000)) { | |
541 | pr_err("%s: timeout waiting for PORT_SUSPEND\n", | |
542 | __func__); | |
543 | goto restart; | |
544 | } | |
545 | } | |
546 | ||
ab137d04 | 547 | tegra_ehci_phy_restore_end(hcd->phy); |
ebf20de4 AS |
548 | goto done; |
549 | ||
550 | restart: | |
551 | if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) | |
ab137d04 | 552 | tegra_ehci_phy_restore_end(hcd->phy); |
ebf20de4 AS |
553 | |
554 | tegra_ehci_restart(hcd); | |
555 | ||
556 | done: | |
ab137d04 | 557 | tegra_usb_phy_preresume(hcd->phy); |
ebf20de4 AS |
558 | tegra->port_resuming = 1; |
559 | return 0; | |
560 | } | |
561 | ||
562 | static int tegra_ehci_suspend(struct device *dev) | |
563 | { | |
564 | struct tegra_ehci_hcd *tegra = | |
565 | platform_get_drvdata(to_platform_device(dev)); | |
566 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
567 | int rc = 0; | |
568 | ||
569 | /* | |
570 | * When system sleep is supported and USB controller wakeup is | |
571 | * implemented: If the controller is runtime-suspended and the | |
572 | * wakeup setting needs to be changed, call pm_runtime_resume(). | |
573 | */ | |
574 | if (HCD_HW_ACCESSIBLE(hcd)) | |
575 | rc = controller_suspend(dev); | |
576 | return rc; | |
577 | } | |
578 | ||
579 | static int tegra_ehci_resume(struct device *dev) | |
580 | { | |
581 | int rc; | |
582 | ||
583 | rc = controller_resume(dev); | |
584 | if (rc == 0) { | |
585 | pm_runtime_disable(dev); | |
586 | pm_runtime_set_active(dev); | |
587 | pm_runtime_enable(dev); | |
588 | } | |
589 | return rc; | |
590 | } | |
591 | ||
592 | static int tegra_ehci_runtime_suspend(struct device *dev) | |
593 | { | |
594 | return controller_suspend(dev); | |
595 | } | |
596 | ||
597 | static int tegra_ehci_runtime_resume(struct device *dev) | |
598 | { | |
599 | return controller_resume(dev); | |
600 | } | |
601 | ||
602 | static const struct dev_pm_ops tegra_ehci_pm_ops = { | |
603 | .suspend = tegra_ehci_suspend, | |
604 | .resume = tegra_ehci_resume, | |
605 | .runtime_suspend = tegra_ehci_runtime_suspend, | |
606 | .runtime_resume = tegra_ehci_runtime_resume, | |
607 | }; | |
608 | ||
609 | #endif | |
610 | ||
bbdabdb6 VB |
611 | /* Bits of PORTSC1, which will get cleared by writing 1 into them */ |
612 | #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) | |
613 | ||
2d22b42d | 614 | void tegra_ehci_set_pts(struct usb_phy *x, u8 pts_val) |
bbdabdb6 VB |
615 | { |
616 | unsigned long val; | |
617 | struct usb_hcd *hcd = bus_to_hcd(x->otg->host); | |
618 | void __iomem *base = hcd->regs; | |
619 | ||
620 | val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; | |
621 | val &= ~TEGRA_USB_PORTSC1_PTS(3); | |
622 | val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3); | |
623 | writel(val, base + TEGRA_USB_PORTSC1); | |
624 | } | |
2d22b42d | 625 | EXPORT_SYMBOL_GPL(tegra_ehci_set_pts); |
bbdabdb6 | 626 | |
2d22b42d | 627 | void tegra_ehci_set_phcd(struct usb_phy *x, bool enable) |
bbdabdb6 VB |
628 | { |
629 | unsigned long val; | |
630 | struct usb_hcd *hcd = bus_to_hcd(x->otg->host); | |
631 | void __iomem *base = hcd->regs; | |
632 | ||
633 | val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; | |
634 | if (enable) | |
635 | val |= TEGRA_USB_PORTSC1_PHCD; | |
636 | else | |
637 | val &= ~TEGRA_USB_PORTSC1_PHCD; | |
638 | writel(val, base + TEGRA_USB_PORTSC1); | |
639 | } | |
2d22b42d | 640 | EXPORT_SYMBOL_GPL(tegra_ehci_set_phcd); |
bbdabdb6 | 641 | |
79ad3b5a BG |
642 | static int tegra_ehci_probe(struct platform_device *pdev) |
643 | { | |
644 | struct resource *res; | |
645 | struct usb_hcd *hcd; | |
646 | struct tegra_ehci_hcd *tegra; | |
647 | struct tegra_ehci_platform_data *pdata; | |
648 | int err = 0; | |
649 | int irq; | |
2d22b42d | 650 | struct device_node *np_phy; |
bbdabdb6 | 651 | struct usb_phy *u_phy; |
79ad3b5a BG |
652 | |
653 | pdata = pdev->dev.platform_data; | |
654 | if (!pdata) { | |
655 | dev_err(&pdev->dev, "Platform data missing\n"); | |
656 | return -EINVAL; | |
657 | } | |
658 | ||
4a53f4e6 OJ |
659 | /* Right now device-tree probed devices don't get dma_mask set. |
660 | * Since shared usb code relies on it, set it here for now. | |
661 | * Once we have dma capability bindings this can go away. | |
662 | */ | |
663 | if (!pdev->dev.dma_mask) | |
3b9561e9 SW |
664 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; |
665 | if (!pdev->dev.coherent_dma_mask) | |
666 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
4a53f4e6 | 667 | |
434103ad | 668 | setup_vbus_gpio(pdev, pdata); |
4a53f4e6 | 669 | |
bc2ff98f JL |
670 | tegra = devm_kzalloc(&pdev->dev, sizeof(struct tegra_ehci_hcd), |
671 | GFP_KERNEL); | |
79ad3b5a BG |
672 | if (!tegra) |
673 | return -ENOMEM; | |
674 | ||
bc2ff98f | 675 | tegra->clk = devm_clk_get(&pdev->dev, NULL); |
79ad3b5a BG |
676 | if (IS_ERR(tegra->clk)) { |
677 | dev_err(&pdev->dev, "Can't get ehci clock\n"); | |
2d22b42d | 678 | return PTR_ERR(tegra->clk); |
79ad3b5a BG |
679 | } |
680 | ||
20de12cc | 681 | err = clk_prepare_enable(tegra->clk); |
79ad3b5a | 682 | if (err) |
2d22b42d | 683 | return err; |
79ad3b5a | 684 | |
eb5369ed VB |
685 | tegra_periph_reset_assert(tegra->clk); |
686 | udelay(1); | |
687 | tegra_periph_reset_deassert(tegra->clk); | |
688 | ||
2d22b42d VB |
689 | np_phy = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0); |
690 | if (!np_phy) { | |
691 | err = -ENODEV; | |
692 | goto cleanup_clk; | |
693 | } | |
694 | ||
695 | u_phy = tegra_usb_get_phy(np_phy); | |
696 | if (IS_ERR(u_phy)) { | |
697 | err = PTR_ERR(u_phy); | |
698 | goto cleanup_clk; | |
699 | } | |
700 | ||
585355c5 VB |
701 | tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node, |
702 | "nvidia,needs-double-reset"); | |
703 | ||
2d22b42d VB |
704 | hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev, |
705 | dev_name(&pdev->dev)); | |
706 | if (!hcd) { | |
707 | dev_err(&pdev->dev, "Unable to create HCD\n"); | |
708 | err = -ENOMEM; | |
709 | goto cleanup_clk; | |
710 | } | |
711 | hcd->phy = u_phy; | |
712 | ||
79ad3b5a BG |
713 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
714 | if (!res) { | |
715 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | |
716 | err = -ENXIO; | |
2d22b42d | 717 | goto cleanup_hcd_create; |
79ad3b5a BG |
718 | } |
719 | hcd->rsrc_start = res->start; | |
720 | hcd->rsrc_len = resource_size(res); | |
bc2ff98f | 721 | hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
79ad3b5a BG |
722 | if (!hcd->regs) { |
723 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | |
724 | err = -ENOMEM; | |
2d22b42d | 725 | goto cleanup_hcd_create; |
4a53f4e6 OJ |
726 | } |
727 | ||
2d22b42d VB |
728 | err = usb_phy_init(hcd->phy); |
729 | if (err) { | |
730 | dev_err(&pdev->dev, "Failed to initialize phy\n"); | |
731 | goto cleanup_hcd_create; | |
79ad3b5a BG |
732 | } |
733 | ||
bbdabdb6 VB |
734 | u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), |
735 | GFP_KERNEL); | |
736 | if (!u_phy->otg) { | |
737 | dev_err(&pdev->dev, "Failed to alloc memory for otg\n"); | |
738 | err = -ENOMEM; | |
2d22b42d | 739 | goto cleanup_phy; |
bbdabdb6 VB |
740 | } |
741 | u_phy->otg->host = hcd_to_bus(hcd); | |
742 | ||
ab137d04 | 743 | err = usb_phy_set_suspend(hcd->phy, 0); |
79ad3b5a BG |
744 | if (err) { |
745 | dev_err(&pdev->dev, "Failed to power on the phy\n"); | |
2d22b42d | 746 | goto cleanup_phy; |
79ad3b5a BG |
747 | } |
748 | ||
749 | tegra->host_resumed = 1; | |
79ad3b5a BG |
750 | tegra->ehci = hcd_to_ehci(hcd); |
751 | ||
752 | irq = platform_get_irq(pdev, 0); | |
753 | if (!irq) { | |
754 | dev_err(&pdev->dev, "Failed to get IRQ\n"); | |
755 | err = -ENODEV; | |
2d22b42d | 756 | goto cleanup_phy; |
79ad3b5a | 757 | } |
79ad3b5a | 758 | |
79ad3b5a | 759 | if (pdata->operating_mode == TEGRA_USB_OTG) { |
bc2ff98f JL |
760 | tegra->transceiver = |
761 | devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); | |
4261b8f3 | 762 | if (!IS_ERR(tegra->transceiver)) |
6e13c650 | 763 | otg_set_host(tegra->transceiver->otg, &hcd->self); |
369a9a9d TR |
764 | } else { |
765 | tegra->transceiver = ERR_PTR(-ENODEV); | |
79ad3b5a | 766 | } |
79ad3b5a | 767 | |
2d22b42d VB |
768 | platform_set_drvdata(pdev, tegra); |
769 | ||
b5dd18d8 | 770 | err = usb_add_hcd(hcd, irq, IRQF_SHARED); |
79ad3b5a BG |
771 | if (err) { |
772 | dev_err(&pdev->dev, "Failed to add USB HCD\n"); | |
2d22b42d | 773 | goto cleanup_phy; |
79ad3b5a BG |
774 | } |
775 | ||
ebf20de4 AS |
776 | pm_runtime_set_active(&pdev->dev); |
777 | pm_runtime_get_noresume(&pdev->dev); | |
778 | ||
779 | /* Don't skip the pm_runtime_forbid call if wakeup isn't working */ | |
780 | /* if (!pdata->power_down_on_bus_suspend) */ | |
781 | pm_runtime_forbid(&pdev->dev); | |
782 | pm_runtime_enable(&pdev->dev); | |
783 | pm_runtime_put_sync(&pdev->dev); | |
79ad3b5a BG |
784 | return err; |
785 | ||
2d22b42d | 786 | cleanup_phy: |
4261b8f3 | 787 | if (!IS_ERR(tegra->transceiver)) |
6e13c650 | 788 | otg_set_host(tegra->transceiver->otg, NULL); |
2d22b42d | 789 | |
ab137d04 | 790 | usb_phy_shutdown(hcd->phy); |
2d22b42d | 791 | cleanup_hcd_create: |
79ad3b5a | 792 | usb_put_hcd(hcd); |
2d22b42d VB |
793 | cleanup_clk: |
794 | clk_disable_unprepare(tegra->clk); | |
79ad3b5a BG |
795 | return err; |
796 | } | |
797 | ||
79ad3b5a BG |
798 | static int tegra_ehci_remove(struct platform_device *pdev) |
799 | { | |
800 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | |
801 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
802 | ||
ebf20de4 AS |
803 | pm_runtime_get_sync(&pdev->dev); |
804 | pm_runtime_disable(&pdev->dev); | |
805 | pm_runtime_put_noidle(&pdev->dev); | |
806 | ||
4261b8f3 | 807 | if (!IS_ERR(tegra->transceiver)) |
6e13c650 | 808 | otg_set_host(tegra->transceiver->otg, NULL); |
79ad3b5a | 809 | |
ab137d04 | 810 | usb_phy_shutdown(hcd->phy); |
79ad3b5a | 811 | usb_remove_hcd(hcd); |
ecc8a0cd VB |
812 | usb_put_hcd(hcd); |
813 | ||
20de12cc | 814 | clk_disable_unprepare(tegra->clk); |
79ad3b5a | 815 | |
79ad3b5a BG |
816 | return 0; |
817 | } | |
818 | ||
819 | static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) | |
820 | { | |
821 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | |
822 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
823 | ||
824 | if (hcd->driver->shutdown) | |
825 | hcd->driver->shutdown(hcd); | |
826 | } | |
827 | ||
d3608b6d | 828 | static struct of_device_id tegra_ehci_of_match[] = { |
4a53f4e6 OJ |
829 | { .compatible = "nvidia,tegra20-ehci", }, |
830 | { }, | |
831 | }; | |
832 | ||
79ad3b5a BG |
833 | static struct platform_driver tegra_ehci_driver = { |
834 | .probe = tegra_ehci_probe, | |
835 | .remove = tegra_ehci_remove, | |
79ad3b5a BG |
836 | .shutdown = tegra_ehci_hcd_shutdown, |
837 | .driver = { | |
838 | .name = "tegra-ehci", | |
4a53f4e6 | 839 | .of_match_table = tegra_ehci_of_match, |
ebf20de4 AS |
840 | #ifdef CONFIG_PM |
841 | .pm = &tegra_ehci_pm_ops, | |
842 | #endif | |
79ad3b5a BG |
843 | } |
844 | }; |