[linux-block.git] / drivers / usb / host / ehci-tegra.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
 *
 * Copyright (C) 2010 Google, Inc.
 * Copyright (C) 2009 - 2013 NVIDIA Corporation
 */

#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/usb/ehci_def.h>
#include <linux/usb/tegra_usb_phy.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>
#include <linux/usb/otg.h>

#include "ehci.h"

#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)

#define TEGRA_USB_DMA_ALIGN 32

#define DRIVER_DESC "Tegra EHCI driver"
#define DRV_NAME "tegra-ehci"

static struct hc_driver __read_mostly tegra_ehci_hc_driver;

struct tegra_ehci_soc_config {
	bool has_hostpc;
};

struct tegra_ehci_hcd {
	struct clk *clk;
	struct reset_control *rst;
	int port_resuming;
	bool needs_double_reset;
};

static int tegra_reset_usb_controller(struct platform_device *pdev)
{
	struct device_node *phy_np;
	struct usb_hcd *hcd = platform_get_drvdata(pdev);
	struct tegra_ehci_hcd *tegra =
		(struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
	struct reset_control *rst;
	int err;

	phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
	if (!phy_np)
		return -ENOENT;

	/*
	 * The 1st USB controller contains some UTMI pad registers that are
	 * global for all the controllers on the chip. Those registers are
	 * also cleared when reset is asserted to the 1st controller.
	 */
	rst = of_reset_control_get_shared(phy_np, "utmi-pads");
	if (IS_ERR(rst)) {
		dev_warn(&pdev->dev,
			 "can't get utmi-pads reset from the PHY\n");
		dev_warn(&pdev->dev,
			 "continuing, but please update your DT\n");
	} else {
		/*
		 * PHY driver performs UTMI-pads reset in a case of
		 * non-legacy DT.
		 */
		reset_control_put(rst);
	}

	of_node_put(phy_np);

	/* reset control is shared, hence initialize it first */
	err = reset_control_deassert(tegra->rst);
	if (err)
		return err;

	err = reset_control_assert(tegra->rst);
	if (err)
		return err;

	udelay(1);

	err = reset_control_deassert(tegra->rst);
	if (err)
		return err;

	return 0;
}

static int tegra_ehci_internal_port_reset(
	struct ehci_hcd	*ehci,
	u32 __iomem	*portsc_reg
)
{
	u32		temp;
	unsigned long	flags;
	int		retval = 0;
	int		i, tries;
	u32		saved_usbintr;

	spin_lock_irqsave(&ehci->lock, flags);
	saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
	/* disable USB interrupt */
	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
	spin_unlock_irqrestore(&ehci->lock, flags);

	/*
	 * Here we have to do Port Reset at most twice for
	 * Port Enable bit to be set.
	 */
	for (i = 0; i < 2; i++) {
		temp = ehci_readl(ehci, portsc_reg);
		temp |= PORT_RESET;
		ehci_writel(ehci, temp, portsc_reg);
		mdelay(10);
		temp &= ~PORT_RESET;
		ehci_writel(ehci, temp, portsc_reg);
		mdelay(1);
		tries = 100;
		do {
			mdelay(1);
			/*
			 * Up to this point, Port Enable bit is
			 * expected to be set after 2 ms waiting.
			 * USB1 usually takes extra 45 ms, for safety,
			 * we take 100 ms as timeout.
			 */
			temp = ehci_readl(ehci, portsc_reg);
		} while (!(temp & PORT_PE) && tries--);
		if (temp & PORT_PE)
			break;
	}
	if (i == 2)
		retval = -ETIMEDOUT;

	/*
	 * Clear Connect Status Change bit if it's set.
	 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
	 */
	if (temp & PORT_CSC)
		ehci_writel(ehci, PORT_CSC, portsc_reg);

	/*
	 * Write to clear any interrupt status bits that might be set
	 * during port reset.
	 */
	temp = ehci_readl(ehci, &ehci->regs->status);
	ehci_writel(ehci, temp, &ehci->regs->status);

	/* restore original interrupt enable bits */
	ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
	return retval;
}

static int tegra_ehci_hub_control(
	struct usb_hcd	*hcd,
	u16		typeReq,
	u16		wValue,
	u16		wIndex,
	char		*buf,
	u16		wLength
)
{
	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
	struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
	u32 __iomem	*status_reg;
	u32		temp;
	unsigned long	flags;
	int		retval = 0;

	status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];

	spin_lock_irqsave(&ehci->lock, flags);

	if (typeReq == GetPortStatus) {
		temp = ehci_readl(ehci, status_reg);
		if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
			/* Resume completed, re-enable disconnect detection */
			tegra->port_resuming = 0;
			tegra_usb_phy_postresume(hcd->usb_phy);
		}
	}

	else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
		temp = ehci_readl(ehci, status_reg);
		if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
			retval = -EPIPE;
			goto done;
		}

		temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
		temp |= PORT_WKDISC_E | PORT_WKOC_E;
		ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);

		/*
		 * If a transaction is in progress, there may be a delay in
		 * suspending the port. Poll until the port is suspended.
		 */
		if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
						PORT_SUSPEND, 5000))
			pr_err("%s: timeout waiting for SUSPEND\n", __func__);

		set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
		goto done;
	}

	/* For USB1 port we need to issue Port Reset twice internally */
	if (tegra->needs_double_reset &&
	   (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
		spin_unlock_irqrestore(&ehci->lock, flags);
		return tegra_ehci_internal_port_reset(ehci, status_reg);
	}

	/*
	 * Tegra host controller will time the resume operation to clear the bit
	 * when the port control state switches to HS or FS Idle. This behavior
	 * is different from EHCI where the host controller driver is required
	 * to set this bit to a zero after the resume duration is timed in the
	 * driver.
	 */
	else if (typeReq == ClearPortFeature &&
					wValue == USB_PORT_FEAT_SUSPEND) {
		temp = ehci_readl(ehci, status_reg);
		if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
			retval = -EPIPE;
			goto done;
		}

		if (!(temp & PORT_SUSPEND))
			goto done;

		/* Disable disconnect detection during port resume */
		tegra_usb_phy_preresume(hcd->usb_phy);

		ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);

		temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
		/* start resume signalling */
		ehci_writel(ehci, temp | PORT_RESUME, status_reg);
		set_bit(wIndex-1, &ehci->resuming_ports);

		spin_unlock_irqrestore(&ehci->lock, flags);
		msleep(20);
		spin_lock_irqsave(&ehci->lock, flags);

		/* Poll until the controller clears RESUME and SUSPEND */
		if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
			pr_err("%s: timeout waiting for RESUME\n", __func__);
		if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
			pr_err("%s: timeout waiting for SUSPEND\n", __func__);

		ehci->reset_done[wIndex-1] = 0;
		clear_bit(wIndex-1, &ehci->resuming_ports);

		tegra->port_resuming = 1;
		goto done;
	}

	spin_unlock_irqrestore(&ehci->lock, flags);

	/* Handle the hub control events here */
	return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);

done:
	spin_unlock_irqrestore(&ehci->lock, flags);
	return retval;
}

struct dma_aligned_buffer {
	void *kmalloc_ptr;
	void *old_xfer_buffer;
	u8 data[];
};

static void free_dma_aligned_buffer(struct urb *urb)
{
	struct dma_aligned_buffer *temp;
	size_t length;

	if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
		return;

	temp = container_of(urb->transfer_buffer,
		struct dma_aligned_buffer, data);

	if (usb_urb_dir_in(urb)) {
		if (usb_pipeisoc(urb->pipe))
			length = urb->transfer_buffer_length;
		else
			length = urb->actual_length;

		memcpy(temp->old_xfer_buffer, temp->data, length);
	}
	urb->transfer_buffer = temp->old_xfer_buffer;
	kfree(temp->kmalloc_ptr);

	urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
}

static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
{
	struct dma_aligned_buffer *temp, *kmalloc_ptr;
	size_t kmalloc_size;

	if (urb->num_sgs || urb->sg ||
	    urb->transfer_buffer_length == 0 ||
	    !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
		return 0;

	/* Allocate a buffer with enough padding for alignment */
	kmalloc_size = urb->transfer_buffer_length +
		sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;

	kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
	if (!kmalloc_ptr)
		return -ENOMEM;

	/* Position our struct dma_aligned_buffer such that data is aligned */
	temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
	temp->kmalloc_ptr = kmalloc_ptr;
	temp->old_xfer_buffer = urb->transfer_buffer;
	if (usb_urb_dir_out(urb))
		memcpy(temp->data, urb->transfer_buffer,
		       urb->transfer_buffer_length);
	urb->transfer_buffer = temp->data;

	urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;

	return 0;
}

static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
				      gfp_t mem_flags)
{
	int ret;

	ret = alloc_dma_aligned_buffer(urb, mem_flags);
	if (ret)
		return ret;

	ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
	if (ret)
		free_dma_aligned_buffer(urb);

	return ret;
}

static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
{
	usb_hcd_unmap_urb_for_dma(hcd, urb);
	free_dma_aligned_buffer(urb);
}

static const struct tegra_ehci_soc_config tegra30_soc_config = {
	.has_hostpc = true,
};

static const struct tegra_ehci_soc_config tegra20_soc_config = {
	.has_hostpc = false,
};

static const struct of_device_id tegra_ehci_of_match[] = {
	{ .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
	{ .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
	{ },
};

static int tegra_ehci_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	const struct tegra_ehci_soc_config *soc_config;
	struct resource *res;
	struct usb_hcd *hcd;
	struct ehci_hcd *ehci;
	struct tegra_ehci_hcd *tegra;
	int err = 0;
	int irq;
	struct usb_phy *u_phy;

	match = of_match_device(tegra_ehci_of_match, &pdev->dev);
	if (!match) {
		dev_err(&pdev->dev, "Error: No device match found\n");
		return -ENODEV;
	}
	soc_config = match->data;

	/* Right now device-tree probed devices don't get dma_mask set.
	 * Since shared usb code relies on it, set it here for now.
	 * Once we have dma capability bindings this can go away.
	 */
	err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
	if (err)
		return err;

	hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
					dev_name(&pdev->dev));
	if (!hcd) {
		dev_err(&pdev->dev, "Unable to create HCD\n");
		return -ENOMEM;
	}
	platform_set_drvdata(pdev, hcd);
	ehci = hcd_to_ehci(hcd);
	tegra = (struct tegra_ehci_hcd *)ehci->priv;

	hcd->has_tt = 1;

	tegra->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(tegra->clk)) {
		dev_err(&pdev->dev, "Can't get ehci clock\n");
		err = PTR_ERR(tegra->clk);
		goto cleanup_hcd_create;
	}

	tegra->rst = devm_reset_control_get_shared(&pdev->dev, "usb");
	if (IS_ERR(tegra->rst)) {
		dev_err(&pdev->dev, "Can't get ehci reset\n");
		err = PTR_ERR(tegra->rst);
		goto cleanup_hcd_create;
	}

	err = clk_prepare_enable(tegra->clk);
	if (err)
		goto cleanup_hcd_create;

	err = tegra_reset_usb_controller(pdev);
	if (err) {
		dev_err(&pdev->dev, "Failed to reset controller\n");
		goto cleanup_clk_en;
	}

	u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
	if (IS_ERR(u_phy)) {
		err = -EPROBE_DEFER;
		goto cleanup_clk_en;
	}
	hcd->usb_phy = u_phy;
	hcd->skip_phy_initialization = 1;

	tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
		"nvidia,needs-double-reset");

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	hcd->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(hcd->regs)) {
		err = PTR_ERR(hcd->regs);
		goto cleanup_clk_en;
	}
	hcd->rsrc_start = res->start;
	hcd->rsrc_len = resource_size(res);

	ehci->caps = hcd->regs + 0x100;
	ehci->has_hostpc = soc_config->has_hostpc;

	err = usb_phy_init(hcd->usb_phy);
	if (err) {
		dev_err(&pdev->dev, "Failed to initialize phy\n");
		goto cleanup_clk_en;
	}

	u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
			     GFP_KERNEL);
	if (!u_phy->otg) {
		err = -ENOMEM;
		goto cleanup_phy;
	}
	u_phy->otg->host = hcd_to_bus(hcd);

	irq = platform_get_irq(pdev, 0);
	if (!irq) {
		dev_err(&pdev->dev, "Failed to get IRQ\n");
		err = -ENODEV;
		goto cleanup_phy;
	}

	otg_set_host(u_phy->otg, &hcd->self);

	err = usb_add_hcd(hcd, irq, IRQF_SHARED);
	if (err) {
		dev_err(&pdev->dev, "Failed to add USB HCD\n");
		goto cleanup_otg_set_host;
	}
	device_wakeup_enable(hcd->self.controller);

	return err;

cleanup_otg_set_host:
	otg_set_host(u_phy->otg, NULL);
cleanup_phy:
	usb_phy_shutdown(hcd->usb_phy);
cleanup_clk_en:
	clk_disable_unprepare(tegra->clk);
cleanup_hcd_create:
	usb_put_hcd(hcd);
	return err;
}

static int tegra_ehci_remove(struct platform_device *pdev)
{
	struct usb_hcd *hcd = platform_get_drvdata(pdev);
	struct tegra_ehci_hcd *tegra =
		(struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;

	usb_remove_hcd(hcd);
	otg_set_host(hcd->usb_phy->otg, NULL);
	usb_phy_shutdown(hcd->usb_phy);
	clk_disable_unprepare(tegra->clk);
	usb_put_hcd(hcd);

	return 0;
}

static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
{
	struct usb_hcd *hcd = platform_get_drvdata(pdev);

	if (hcd->driver->shutdown)
		hcd->driver->shutdown(hcd);
}

static struct platform_driver tegra_ehci_driver = {
	.probe		= tegra_ehci_probe,
	.remove		= tegra_ehci_remove,
	.shutdown	= tegra_ehci_hcd_shutdown,
	.driver		= {
		.name	= DRV_NAME,
		.of_match_table = tegra_ehci_of_match,
	}
};

static int tegra_ehci_reset(struct usb_hcd *hcd)
{
	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
	int retval;
	int txfifothresh;

	retval = ehci_setup(hcd);
	if (retval)
		return retval;

	/*
	 * We should really pull this value out of tegra_ehci_soc_config, but
	 * to avoid needing access to it, make use of the fact that Tegra20 is
	 * the only one so far that needs a value of 10, and Tegra20 is the
	 * only one which doesn't set has_hostpc.
	 */
	txfifothresh = ehci->has_hostpc ? 0x10 : 10;
	ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);

	return 0;
}

static const struct ehci_driver_overrides tegra_overrides __initconst = {
	.extra_priv_size	= sizeof(struct tegra_ehci_hcd),
	.reset			= tegra_ehci_reset,
};

static int __init ehci_tegra_init(void)
{
	if (usb_disabled())
		return -ENODEV;

	pr_info(DRV_NAME ": " DRIVER_DESC "\n");

	ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);

	/*
	 * The Tegra HW has some unusual quirks, which require Tegra-specific
	 * workarounds. We override certain hc_driver functions here to
	 * achieve that. We explicitly do not enhance ehci_driver_overrides to
	 * allow this more easily, since this is an unusual case, and we don't
	 * want to encourage others to override these functions by making it
	 * too easy.
	 */

	tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
	tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
	tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;

	return platform_driver_register(&tegra_ehci_driver);
}
module_init(ehci_tegra_init);

static void __exit ehci_tegra_cleanup(void)
{
	platform_driver_unregister(&tegra_ehci_driver);
}
module_exit(ehci_tegra_cleanup);

MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0+
79ad3b5a BG	2	/*
	3	* EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
	4	*
	5	* Copyright (C) 2010 Google, Inc.
bbdabdb6	6	* Copyright (C) 2009 - 2013 NVIDIA Corporation
79ad3b5a BG	7	*/
	8
	9	#include <linux/clk.h>
9fc5f24e	10	#include <linux/dma-mapping.h>
ded017ee	11	#include <linux/err.h>
4a53f4e6	12	#include <linux/gpio.h>
9fc5f24e MG	13	#include <linux/io.h>
	14	#include <linux/irq.h>
	15	#include <linux/module.h>
4a53f4e6	16	#include <linux/of.h>
327d8b42	17	#include <linux/of_device.h>
4a53f4e6	18	#include <linux/of_gpio.h>
9fc5f24e	19	#include <linux/platform_device.h>
ebf20de4	20	#include <linux/pm_runtime.h>
75606f5d	21	#include <linux/reset.h>
9fc5f24e	22	#include <linux/slab.h>
bbdabdb6	23	#include <linux/usb/ehci_def.h>
1ba8216f	24	#include <linux/usb/tegra_usb_phy.h>
9fc5f24e MG	25	#include <linux/usb.h>
	26	#include <linux/usb/hcd.h>
	27	#include <linux/usb/otg.h>
	28
	29	#include "ehci.h"
54388b28	30
9fc5f24e MG	31	#define PORT_WAKE_BITS (PORT_WKOC_E\|PORT_WKDISC_E\|PORT_WKCONN_E)
9fc5f24e MG	32
fbf9865c RM	33	#define TEGRA_USB_DMA_ALIGN 32
fbf9865c RM	34
9fc5f24e MG	35	#define DRIVER_DESC "Tegra EHCI driver"
	36	#define DRV_NAME "tegra-ehci"
	37
	38	static struct hc_driver __read_mostly tegra_ehci_hc_driver;
	39
327d8b42 TT	40	struct tegra_ehci_soc_config {
	41	bool has_hostpc;
	42	};
	43
79ad3b5a	44	struct tegra_ehci_hcd {
79ad3b5a	45	struct clk *clk;
75606f5d	46	struct reset_control *rst;
79ad3b5a	47	int port_resuming;
585355c5	48	bool needs_double_reset;
79ad3b5a BG	49	};
79ad3b5a BG	50
a47cc24c TT	51	static int tegra_reset_usb_controller(struct platform_device *pdev)
	52	{
	53	struct device_node *phy_np;
	54	struct usb_hcd *hcd = platform_get_drvdata(pdev);
	55	struct tegra_ehci_hcd *tegra =
	56	(struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
14347036 DO	57	struct reset_control *rst;
14347036 DO	58	int err;
a47cc24c TT	59
	60	phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
	61	if (!phy_np)
	62	return -ENOENT;
	63
14347036 DO	64	/*
	65	* The 1st USB controller contains some UTMI pad registers that are
	66	* global for all the controllers on the chip. Those registers are
	67	* also cleared when reset is asserted to the 1st controller.
	68	*/
	69	rst = of_reset_control_get_shared(phy_np, "utmi-pads");
	70	if (IS_ERR(rst)) {
	71	dev_warn(&pdev->dev,
	72	"can't get utmi-pads reset from the PHY\n");
	73	dev_warn(&pdev->dev,
	74	"continuing, but please update your DT\n");
	75	} else {
	76	/*
	77	* PHY driver performs UTMI-pads reset in a case of
	78	* non-legacy DT.
	79	*/
	80	reset_control_put(rst);
	81	}
7cc9ca5a	82
14347036	83	of_node_put(phy_np);
a47cc24c	84
14347036 DO	85	/* reset control is shared, hence initialize it first */
	86	err = reset_control_deassert(tegra->rst);
	87	if (err)
	88	return err;
a47cc24c	89
14347036 DO	90	err = reset_control_assert(tegra->rst);
	91	if (err)
	92	return err;
a47cc24c	93
14347036	94	udelay(1);
a47cc24c	95
14347036 DO	96	err = reset_control_deassert(tegra->rst);
	97	if (err)
	98	return err;
a47cc24c TT	99
	100	return 0;
	101	}
	102
1f594b64 JL	103	static int tegra_ehci_internal_port_reset(
	104	struct ehci_hcd *ehci,
	105	u32 __iomem *portsc_reg
	106	)
	107	{
	108	u32 temp;
	109	unsigned long flags;
	110	int retval = 0;
	111	int i, tries;
	112	u32 saved_usbintr;
	113
	114	spin_lock_irqsave(&ehci->lock, flags);
	115	saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
	116	/* disable USB interrupt */
	117	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
	118	spin_unlock_irqrestore(&ehci->lock, flags);
	119
	120	/*
	121	* Here we have to do Port Reset at most twice for
	122	* Port Enable bit to be set.
	123	*/
	124	for (i = 0; i < 2; i++) {
	125	temp = ehci_readl(ehci, portsc_reg);
	126	temp \|= PORT_RESET;
	127	ehci_writel(ehci, temp, portsc_reg);
	128	mdelay(10);
	129	temp &= ~PORT_RESET;
	130	ehci_writel(ehci, temp, portsc_reg);
	131	mdelay(1);
	132	tries = 100;
	133	do {
	134	mdelay(1);
	135	/*
	136	* Up to this point, Port Enable bit is
	137	* expected to be set after 2 ms waiting.
	138	* USB1 usually takes extra 45 ms, for safety,
	139	* we take 100 ms as timeout.
	140	*/
	141	temp = ehci_readl(ehci, portsc_reg);
	142	} while (!(temp & PORT_PE) && tries--);
	143	if (temp & PORT_PE)
	144	break;
	145	}
	146	if (i == 2)
	147	retval = -ETIMEDOUT;
	148
	149	/*
	150	* Clear Connect Status Change bit if it's set.
	151	* We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
	152	*/
	153	if (temp & PORT_CSC)
	154	ehci_writel(ehci, PORT_CSC, portsc_reg);
	155
	156	/*
	157	* Write to clear any interrupt status bits that might be set
	158	* during port reset.
	159	*/
	160	temp = ehci_readl(ehci, &ehci->regs->status);
	161	ehci_writel(ehci, temp, &ehci->regs->status);
	162
	163	/* restore original interrupt enable bits */
	164	ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
	165	return retval;
	166	}
167
79ad3b5a BG	168	static int tegra_ehci_hub_control(
	169	struct usb_hcd *hcd,
	170	u16 typeReq,
	171	u16 wValue,
	172	u16 wIndex,
	173	char *buf,
	174	u16 wLength
	175	)
	176	{
c19d14d6 SW	177	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
c19d14d6 SW	178	struct tegra_ehci_hcd tegra = (struct tegra_ehci_hcd )ehci->priv;
79ad3b5a BG	179	u32 __iomem *status_reg;
	180	u32 temp;
	181	unsigned long flags;
	182	int retval = 0;
	183
	184	status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
	185
	186	spin_lock_irqsave(&ehci->lock, flags);
	187
6d5f89c7	188	if (typeReq == GetPortStatus) {
79ad3b5a BG	189	temp = ehci_readl(ehci, status_reg);
	190	if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
	191	/* Resume completed, re-enable disconnect detection */
	192	tegra->port_resuming = 0;
3d46e73d	193	tegra_usb_phy_postresume(hcd->usb_phy);
79ad3b5a BG	194	}
	195	}
	196
	197	else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
	198	temp = ehci_readl(ehci, status_reg);
	199	if ((temp & PORT_PE) == 0 \|\| (temp & PORT_RESET) != 0) {
	200	retval = -EPIPE;
	201	goto done;
	202	}
	203
b0876574	204	temp &= ~(PORT_RWC_BITS \| PORT_WKCONN_E);
79ad3b5a BG	205	temp \|= PORT_WKDISC_E \| PORT_WKOC_E;
	206	ehci_writel(ehci, temp \| PORT_SUSPEND, status_reg);
	207
	208	/*
	209	* If a transaction is in progress, there may be a delay in
	210	* suspending the port. Poll until the port is suspended.
	211	*/
2f3a6b86	212	if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
79ad3b5a BG	213	PORT_SUSPEND, 5000))
	214	pr_err("%s: timeout waiting for SUSPEND\n", __func__);
	215
	216	set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
	217	goto done;
	218	}
	219
1f594b64	220	/* For USB1 port we need to issue Port Reset twice internally */
585355c5	221	if (tegra->needs_double_reset &&
1f594b64 JL	222	(typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
	223	spin_unlock_irqrestore(&ehci->lock, flags);
	224	return tegra_ehci_internal_port_reset(ehci, status_reg);
	225	}
	226
79ad3b5a BG	227	/*
	228	* Tegra host controller will time the resume operation to clear the bit
	229	* when the port control state switches to HS or FS Idle. This behavior
	230	* is different from EHCI where the host controller driver is required
	231	* to set this bit to a zero after the resume duration is timed in the
	232	* driver.
	233	*/
	234	else if (typeReq == ClearPortFeature &&
	235	wValue == USB_PORT_FEAT_SUSPEND) {
	236	temp = ehci_readl(ehci, status_reg);
	237	if ((temp & PORT_RESET) \|\| !(temp & PORT_PE)) {
	238	retval = -EPIPE;
	239	goto done;
	240	}
	241
	242	if (!(temp & PORT_SUSPEND))
	243	goto done;
	244
	245	/* Disable disconnect detection during port resume */
3d46e73d	246	tegra_usb_phy_preresume(hcd->usb_phy);
79ad3b5a BG	247
	248	ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
	249
	250	temp &= ~(PORT_RWC_BITS \| PORT_WAKE_BITS);
	251	/* start resume signalling */
	252	ehci_writel(ehci, temp \| PORT_RESUME, status_reg);
a448e4dc	253	set_bit(wIndex-1, &ehci->resuming_ports);
79ad3b5a BG	254
	255	spin_unlock_irqrestore(&ehci->lock, flags);
	256	msleep(20);
	257	spin_lock_irqsave(&ehci->lock, flags);
	258
	259	/* Poll until the controller clears RESUME and SUSPEND */
2f3a6b86	260	if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
79ad3b5a	261	pr_err("%s: timeout waiting for RESUME\n", __func__);
2f3a6b86	262	if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
79ad3b5a BG	263	pr_err("%s: timeout waiting for SUSPEND\n", __func__);
	264
	265	ehci->reset_done[wIndex-1] = 0;
a448e4dc	266	clear_bit(wIndex-1, &ehci->resuming_ports);
79ad3b5a BG	267
	268	tegra->port_resuming = 1;
	269	goto done;
	270	}
	271
	272	spin_unlock_irqrestore(&ehci->lock, flags);
	273
	274	/* Handle the hub control events here */
37769939	275	return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
9fc5f24e	276
79ad3b5a BG	277	done:
	278	spin_unlock_irqrestore(&ehci->lock, flags);
	279	return retval;
	280	}
	281
fe375774	282	struct dma_aligned_buffer {
fbf9865c RM	283	void *kmalloc_ptr;
fbf9865c RM	284	void *old_xfer_buffer;
6bc3f397	285	u8 data[];
fbf9865c RM	286	};
fbf9865c RM	287
fe375774	288	static void free_dma_aligned_buffer(struct urb *urb)
fbf9865c	289	{
fe375774	290	struct dma_aligned_buffer *temp;
0efd937e	291	size_t length;
fbf9865c RM	292
	293	if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
	294	return;
	295
fe375774 VB	296	temp = container_of(urb->transfer_buffer,
fe375774 VB	297	struct dma_aligned_buffer, data);
fbf9865c	298
0efd937e JH	299	if (usb_urb_dir_in(urb)) {
	300	if (usb_pipeisoc(urb->pipe))
	301	length = urb->transfer_buffer_length;
	302	else
	303	length = urb->actual_length;
	304
	305	memcpy(temp->old_xfer_buffer, temp->data, length);
	306	}
fbf9865c RM	307	urb->transfer_buffer = temp->old_xfer_buffer;
	308	kfree(temp->kmalloc_ptr);
	309
	310	urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
	311	}
	312
fe375774	313	static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
fbf9865c	314	{
fe375774	315	struct dma_aligned_buffer temp, kmalloc_ptr;
fbf9865c RM	316	size_t kmalloc_size;
	317
	318	if (urb->num_sgs \|\| urb->sg \|\|
	319	urb->transfer_buffer_length == 0 \|\|
	320	!((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
	321	return 0;
	322
fbf9865c RM	323	/* Allocate a buffer with enough padding for alignment */
fbf9865c RM	324	kmalloc_size = urb->transfer_buffer_length +
fe375774	325	sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
fbf9865c RM	326
	327	kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
	328	if (!kmalloc_ptr)
	329	return -ENOMEM;
	330
fe375774	331	/* Position our struct dma_aligned_buffer such that data is aligned */
fbf9865c	332	temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
fbf9865c RM	333	temp->kmalloc_ptr = kmalloc_ptr;
fbf9865c RM	334	temp->old_xfer_buffer = urb->transfer_buffer;
fe375774	335	if (usb_urb_dir_out(urb))
fbf9865c RM	336	memcpy(temp->data, urb->transfer_buffer,
	337	urb->transfer_buffer_length);
	338	urb->transfer_buffer = temp->data;
	339
	340	urb->transfer_flags \|= URB_ALIGNED_TEMP_BUFFER;
	341
	342	return 0;
	343	}
	344
	345	static int tegra_ehci_map_urb_for_dma(struct usb_hcd hcd, struct urb urb,
	346	gfp_t mem_flags)
	347	{
	348	int ret;
	349
fe375774	350	ret = alloc_dma_aligned_buffer(urb, mem_flags);
fbf9865c RM	351	if (ret)
	352	return ret;
	353
	354	ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
	355	if (ret)
fe375774	356	free_dma_aligned_buffer(urb);
fbf9865c RM	357
	358	return ret;
	359	}
	360
	361	static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd hcd, struct urb urb)
	362	{
	363	usb_hcd_unmap_urb_for_dma(hcd, urb);
fe375774	364	free_dma_aligned_buffer(urb);
fbf9865c RM	365	}
fbf9865c RM	366
327d8b42 TT	367	static const struct tegra_ehci_soc_config tegra30_soc_config = {
	368	.has_hostpc = true,
	369	};
	370
	371	static const struct tegra_ehci_soc_config tegra20_soc_config = {
	372	.has_hostpc = false,
	373	};
	374
1b45049a	375	static const struct of_device_id tegra_ehci_of_match[] = {
327d8b42 TT	376	{ .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
	377	{ .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
	378	{ },
	379	};
	380
79ad3b5a BG	381	static int tegra_ehci_probe(struct platform_device *pdev)
79ad3b5a BG	382	{
327d8b42 TT	383	const struct of_device_id *match;
327d8b42 TT	384	const struct tegra_ehci_soc_config *soc_config;
79ad3b5a BG	385	struct resource *res;
79ad3b5a BG	386	struct usb_hcd *hcd;
c19d14d6	387	struct ehci_hcd *ehci;
79ad3b5a	388	struct tegra_ehci_hcd *tegra;
79ad3b5a BG	389	int err = 0;
79ad3b5a BG	390	int irq;
bbdabdb6	391	struct usb_phy *u_phy;
79ad3b5a	392
327d8b42 TT	393	match = of_match_device(tegra_ehci_of_match, &pdev->dev);
	394	if (!match) {
	395	dev_err(&pdev->dev, "Error: No device match found\n");
	396	return -ENODEV;
	397	}
	398	soc_config = match->data;
	399
4a53f4e6 OJ	400	/* Right now device-tree probed devices don't get dma_mask set.
	401	* Since shared usb code relies on it, set it here for now.
	402	* Once we have dma capability bindings this can go away.
	403	*/
e1fd7341	404	err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
22d9d8e8 RK	405	if (err)
22d9d8e8 RK	406	return err;
4a53f4e6	407
c19d14d6 SW	408	hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
	409	dev_name(&pdev->dev));
	410	if (!hcd) {
	411	dev_err(&pdev->dev, "Unable to create HCD\n");
f5b8c8b6	412	return -ENOMEM;
c19d14d6 SW	413	}
	414	platform_set_drvdata(pdev, hcd);
	415	ehci = hcd_to_ehci(hcd);
	416	tegra = (struct tegra_ehci_hcd *)ehci->priv;
	417
	418	hcd->has_tt = 1;
79ad3b5a	419
bc2ff98f	420	tegra->clk = devm_clk_get(&pdev->dev, NULL);
79ad3b5a BG	421	if (IS_ERR(tegra->clk)) {
79ad3b5a BG	422	dev_err(&pdev->dev, "Can't get ehci clock\n");
c19d14d6 SW	423	err = PTR_ERR(tegra->clk);
c19d14d6 SW	424	goto cleanup_hcd_create;
79ad3b5a BG	425	}
79ad3b5a BG	426
14347036	427	tegra->rst = devm_reset_control_get_shared(&pdev->dev, "usb");
75606f5d SW	428	if (IS_ERR(tegra->rst)) {
	429	dev_err(&pdev->dev, "Can't get ehci reset\n");
	430	err = PTR_ERR(tegra->rst);
	431	goto cleanup_hcd_create;
	432	}
	433
20de12cc	434	err = clk_prepare_enable(tegra->clk);
79ad3b5a	435	if (err)
dafbe92e	436	goto cleanup_hcd_create;
79ad3b5a	437
a47cc24c	438	err = tegra_reset_usb_controller(pdev);
14347036 DO	439	if (err) {
14347036 DO	440	dev_err(&pdev->dev, "Failed to reset controller\n");
a47cc24c	441	goto cleanup_clk_en;
14347036	442	}
eb5369ed	443
7db71a9a	444	u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
2d22b42d	445	if (IS_ERR(u_phy)) {
f56e67f0	446	err = -EPROBE_DEFER;
c19d14d6	447	goto cleanup_clk_en;
2d22b42d	448	}
3d46e73d	449	hcd->usb_phy = u_phy;
4e88d4c0	450	hcd->skip_phy_initialization = 1;
2d22b42d	451
585355c5 VB	452	tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
	453	"nvidia,needs-double-reset");
	454
79ad3b5a	455	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6ba96dce VG	456	hcd->regs = devm_ioremap_resource(&pdev->dev, res);
	457	if (IS_ERR(hcd->regs)) {
	458	err = PTR_ERR(hcd->regs);
c19d14d6	459	goto cleanup_clk_en;
4a53f4e6	460	}
a36cc423 VB	461	hcd->rsrc_start = res->start;
	462	hcd->rsrc_len = resource_size(res);
	463
c19d14d6	464	ehci->caps = hcd->regs + 0x100;
327d8b42	465	ehci->has_hostpc = soc_config->has_hostpc;
4a53f4e6	466
3d46e73d	467	err = usb_phy_init(hcd->usb_phy);
2d22b42d VB	468	if (err) {
2d22b42d VB	469	dev_err(&pdev->dev, "Failed to initialize phy\n");
c19d14d6	470	goto cleanup_clk_en;
79ad3b5a BG	471	}
79ad3b5a BG	472
bbdabdb6 VB	473	u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
	474	GFP_KERNEL);
	475	if (!u_phy->otg) {
bbdabdb6	476	err = -ENOMEM;
2d22b42d	477	goto cleanup_phy;
bbdabdb6 VB	478	}
	479	u_phy->otg->host = hcd_to_bus(hcd);
	480
79ad3b5a BG	481	irq = platform_get_irq(pdev, 0);
	482	if (!irq) {
	483	dev_err(&pdev->dev, "Failed to get IRQ\n");
	484	err = -ENODEV;
2d22b42d	485	goto cleanup_phy;
79ad3b5a	486	}
79ad3b5a	487
de3f2337	488	otg_set_host(u_phy->otg, &hcd->self);
79ad3b5a	489
b5dd18d8	490	err = usb_add_hcd(hcd, irq, IRQF_SHARED);
79ad3b5a BG	491	if (err) {
79ad3b5a BG	492	dev_err(&pdev->dev, "Failed to add USB HCD\n");
de3f2337	493	goto cleanup_otg_set_host;
79ad3b5a	494	}
3c9740a1	495	device_wakeup_enable(hcd->self.controller);
79ad3b5a BG	496
	497	return err;
	498
de3f2337 TT	499	cleanup_otg_set_host:
de3f2337 TT	500	otg_set_host(u_phy->otg, NULL);
8fefcfdd	501	cleanup_phy:
3d46e73d	502	usb_phy_shutdown(hcd->usb_phy);
c19d14d6 SW	503	cleanup_clk_en:
c19d14d6 SW	504	clk_disable_unprepare(tegra->clk);
2d22b42d	505	cleanup_hcd_create:
79ad3b5a	506	usb_put_hcd(hcd);
79ad3b5a BG	507	return err;
	508	}
	509
79ad3b5a BG	510	static int tegra_ehci_remove(struct platform_device *pdev)
79ad3b5a BG	511	{
c19d14d6 SW	512	struct usb_hcd *hcd = platform_get_drvdata(pdev);
	513	struct tegra_ehci_hcd *tegra =
	514	(struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
79ad3b5a	515
62a7f628	516	usb_remove_hcd(hcd);
3d46e73d	517	otg_set_host(hcd->usb_phy->otg, NULL);
3d46e73d	518	usb_phy_shutdown(hcd->usb_phy);
20de12cc	519	clk_disable_unprepare(tegra->clk);
6a70b621 TT	520	usb_put_hcd(hcd);
6a70b621 TT	521
79ad3b5a BG	522	return 0;
	523	}
	524
	525	static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
	526	{
c19d14d6	527	struct usb_hcd *hcd = platform_get_drvdata(pdev);
79ad3b5a BG	528
	529	if (hcd->driver->shutdown)
	530	hcd->driver->shutdown(hcd);
	531	}
	532
	533	static struct platform_driver tegra_ehci_driver = {
	534	.probe = tegra_ehci_probe,
	535	.remove = tegra_ehci_remove,
79ad3b5a BG	536	.shutdown = tegra_ehci_hcd_shutdown,
79ad3b5a BG	537	.driver = {
9fc5f24e	538	.name = DRV_NAME,
4a53f4e6	539	.of_match_table = tegra_ehci_of_match,
79ad3b5a BG	540	}
79ad3b5a BG	541	};
9fc5f24e	542
4f2fe2d2 SW	543	static int tegra_ehci_reset(struct usb_hcd *hcd)
	544	{
	545	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
	546	int retval;
	547	int txfifothresh;
	548
	549	retval = ehci_setup(hcd);
	550	if (retval)
	551	return retval;
	552
	553	/*
	554	* We should really pull this value out of tegra_ehci_soc_config, but
	555	* to avoid needing access to it, make use of the fact that Tegra20 is
	556	* the only one so far that needs a value of 10, and Tegra20 is the
	557	* only one which doesn't set has_hostpc.
	558	*/
	559	txfifothresh = ehci->has_hostpc ? 0x10 : 10;
	560	ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
	561
	562	return 0;
	563	}
	564
9fc5f24e MG	565	static const struct ehci_driver_overrides tegra_overrides __initconst = {
9fc5f24e MG	566	.extra_priv_size = sizeof(struct tegra_ehci_hcd),
4f2fe2d2	567	.reset = tegra_ehci_reset,
9fc5f24e MG	568	};
	569
	570	static int __init ehci_tegra_init(void)
	571	{
	572	if (usb_disabled())
	573	return -ENODEV;
	574
	575	pr_info(DRV_NAME ": " DRIVER_DESC "\n");
	576
	577	ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
	578
	579	/*
	580	* The Tegra HW has some unusual quirks, which require Tegra-specific
	581	* workarounds. We override certain hc_driver functions here to
	582	* achieve that. We explicitly do not enhance ehci_driver_overrides to
	583	* allow this more easily, since this is an unusual case, and we don't
	584	* want to encourage others to override these functions by making it
	585	* too easy.
	586	*/
	587
9fc5f24e MG	588	tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
	589	tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
	590	tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
	591
	592	return platform_driver_register(&tegra_ehci_driver);
	593	}
	594	module_init(ehci_tegra_init);
	595
	596	static void __exit ehci_tegra_cleanup(void)
	597	{
	598	platform_driver_unregister(&tegra_ehci_driver);
	599	}
	600	module_exit(ehci_tegra_cleanup);
	601
	602	MODULE_DESCRIPTION(DRIVER_DESC);
	603	MODULE_LICENSE("GPL");
	604	MODULE_ALIAS("platform:" DRV_NAME);
	605	MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);