Commit | Line | Data |
---|---|---|
7ff71d6a MP |
1 | /* |
2 | * EHCI HCD (Host Controller Driver) PCI Bus Glue. | |
3 | * | |
4 | * Copyright (c) 2000-2004 by David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
21 | #ifndef CONFIG_PCI | |
22 | #error "This file is PCI bus glue. CONFIG_PCI must be defined." | |
23 | #endif | |
24 | ||
25 | /*-------------------------------------------------------------------------*/ | |
26 | ||
18807521 DB |
27 | /* called after powerup, by probe or system-pm "wakeup" */ |
28 | static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) | |
29 | { | |
30 | u32 temp; | |
31 | int retval; | |
18807521 DB |
32 | |
33 | /* optional debug port, normally in the first BAR */ | |
34 | temp = pci_find_capability(pdev, 0x0a); | |
35 | if (temp) { | |
36 | pci_read_config_dword(pdev, temp, &temp); | |
37 | temp >>= 16; | |
38 | if ((temp & (3 << 13)) == (1 << 13)) { | |
39 | temp &= 0x1fff; | |
40 | ehci->debug = ehci_to_hcd(ehci)->regs + temp; | |
41 | temp = readl(&ehci->debug->control); | |
42 | ehci_info(ehci, "debug port %d%s\n", | |
43 | HCS_DEBUG_PORT(ehci->hcs_params), | |
44 | (temp & DBGP_ENABLED) | |
45 | ? " IN USE" | |
46 | : ""); | |
47 | if (!(temp & DBGP_ENABLED)) | |
48 | ehci->debug = NULL; | |
49 | } | |
50 | } | |
51 | ||
401feafa DB |
52 | /* we expect static quirk code to handle the "extended capabilities" |
53 | * (currently just BIOS handoff) allowed starting with EHCI 0.96 | |
54 | */ | |
18807521 DB |
55 | |
56 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
57 | retval = pci_set_mwi(pdev); | |
58 | if (!retval) | |
59 | ehci_dbg(ehci, "MWI active\n"); | |
60 | ||
61 | ehci_port_power(ehci, 0); | |
62 | ||
63 | return 0; | |
64 | } | |
65 | ||
8926bfa7 DB |
66 | /* called during probe() after chip reset completes */ |
67 | static int ehci_pci_setup(struct usb_hcd *hcd) | |
7ff71d6a | 68 | { |
abcc9448 DB |
69 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
70 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
7ff71d6a | 71 | u32 temp; |
18807521 | 72 | int retval; |
7ff71d6a MP |
73 | |
74 | ehci->caps = hcd->regs; | |
abcc9448 DB |
75 | ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase)); |
76 | dbg_hcs_params(ehci, "reset"); | |
77 | dbg_hcc_params(ehci, "reset"); | |
7ff71d6a MP |
78 | |
79 | /* cache this readonly data; minimize chip reads */ | |
abcc9448 | 80 | ehci->hcs_params = readl(&ehci->caps->hcs_params); |
7ff71d6a | 81 | |
18807521 DB |
82 | retval = ehci_halt(ehci); |
83 | if (retval) | |
84 | return retval; | |
85 | ||
8926bfa7 DB |
86 | /* data structure init */ |
87 | retval = ehci_init(hcd); | |
88 | if (retval) | |
89 | return retval; | |
90 | ||
abcc9448 | 91 | /* NOTE: only the parts below this line are PCI-specific */ |
7ff71d6a | 92 | |
abcc9448 DB |
93 | switch (pdev->vendor) { |
94 | case PCI_VENDOR_ID_TDI: | |
95 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { | |
96 | ehci->is_tdi_rh_tt = 1; | |
97 | tdi_reset(ehci); | |
98 | } | |
99 | break; | |
100 | case PCI_VENDOR_ID_AMD: | |
101 | /* AMD8111 EHCI doesn't work, according to AMD errata */ | |
102 | if (pdev->device == 0x7463) { | |
103 | ehci_info(ehci, "ignoring AMD8111 (errata)\n"); | |
8926bfa7 DB |
104 | retval = -EIO; |
105 | goto done; | |
abcc9448 DB |
106 | } |
107 | break; | |
108 | case PCI_VENDOR_ID_NVIDIA: | |
109 | /* NVidia reports that certain chips don't handle | |
110 | * QH, ITD, or SITD addresses above 2GB. (But TD, | |
111 | * data buffer, and periodic schedule are normal.) | |
112 | */ | |
113 | switch (pdev->device) { | |
114 | case 0x003c: /* MCP04 */ | |
115 | case 0x005b: /* CK804 */ | |
116 | case 0x00d8: /* CK8 */ | |
117 | case 0x00e8: /* CK8S */ | |
118 | if (pci_set_consistent_dma_mask(pdev, | |
119 | DMA_31BIT_MASK) < 0) | |
120 | ehci_warn(ehci, "can't enable NVidia " | |
121 | "workaround for >2GB RAM\n"); | |
7ff71d6a MP |
122 | break; |
123 | } | |
abcc9448 DB |
124 | break; |
125 | } | |
7ff71d6a | 126 | |
7ff71d6a | 127 | if (ehci_is_TDI(ehci)) |
abcc9448 | 128 | ehci_reset(ehci); |
7ff71d6a | 129 | |
7ff71d6a MP |
130 | /* at least the Genesys GL880S needs fixup here */ |
131 | temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); | |
132 | temp &= 0x0f; | |
133 | if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { | |
abcc9448 | 134 | ehci_dbg(ehci, "bogus port configuration: " |
7ff71d6a MP |
135 | "cc=%d x pcc=%d < ports=%d\n", |
136 | HCS_N_CC(ehci->hcs_params), | |
137 | HCS_N_PCC(ehci->hcs_params), | |
138 | HCS_N_PORTS(ehci->hcs_params)); | |
139 | ||
abcc9448 DB |
140 | switch (pdev->vendor) { |
141 | case 0x17a0: /* GENESYS */ | |
142 | /* GL880S: should be PORTS=2 */ | |
143 | temp |= (ehci->hcs_params & ~0xf); | |
144 | ehci->hcs_params = temp; | |
145 | break; | |
146 | case PCI_VENDOR_ID_NVIDIA: | |
147 | /* NF4: should be PCC=10 */ | |
148 | break; | |
7ff71d6a MP |
149 | } |
150 | } | |
151 | ||
abcc9448 DB |
152 | /* Serial Bus Release Number is at PCI 0x60 offset */ |
153 | pci_read_config_byte(pdev, 0x60, &ehci->sbrn); | |
7ff71d6a | 154 | |
2c1c3c4c DB |
155 | /* Workaround current PCI init glitch: wakeup bits aren't |
156 | * being set from PCI PM capability. | |
157 | */ | |
158 | if (!device_can_wakeup(&pdev->dev)) { | |
159 | u16 port_wake; | |
160 | ||
161 | pci_read_config_word(pdev, 0x62, &port_wake); | |
162 | if (port_wake & 0x0001) | |
163 | device_init_wakeup(&pdev->dev, 1); | |
164 | } | |
7ff71d6a | 165 | |
18807521 | 166 | retval = ehci_pci_reinit(ehci, pdev); |
8926bfa7 DB |
167 | done: |
168 | return retval; | |
7ff71d6a MP |
169 | } |
170 | ||
171 | /*-------------------------------------------------------------------------*/ | |
172 | ||
173 | #ifdef CONFIG_PM | |
174 | ||
175 | /* suspend/resume, section 4.3 */ | |
176 | ||
f03c17fc | 177 | /* These routines rely on the PCI bus glue |
7ff71d6a MP |
178 | * to handle powerdown and wakeup, and currently also on |
179 | * transceivers that don't need any software attention to set up | |
180 | * the right sort of wakeup. | |
f03c17fc | 181 | * Also they depend on separate root hub suspend/resume. |
7ff71d6a MP |
182 | */ |
183 | ||
abcc9448 | 184 | static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message) |
7ff71d6a | 185 | { |
abcc9448 | 186 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
8de98402 BH |
187 | unsigned long flags; |
188 | int rc = 0; | |
7ff71d6a | 189 | |
abcc9448 DB |
190 | if (time_before(jiffies, ehci->next_statechange)) |
191 | msleep(10); | |
7ff71d6a | 192 | |
8de98402 BH |
193 | /* Root hub was already suspended. Disable irq emission and |
194 | * mark HW unaccessible, bail out if RH has been resumed. Use | |
195 | * the spinlock to properly synchronize with possible pending | |
196 | * RH suspend or resume activity. | |
197 | * | |
198 | * This is still racy as hcd->state is manipulated outside of | |
199 | * any locks =P But that will be a different fix. | |
200 | */ | |
201 | spin_lock_irqsave (&ehci->lock, flags); | |
202 | if (hcd->state != HC_STATE_SUSPENDED) { | |
203 | rc = -EINVAL; | |
204 | goto bail; | |
205 | } | |
206 | writel (0, &ehci->regs->intr_enable); | |
207 | (void)readl(&ehci->regs->intr_enable); | |
208 | ||
209 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
210 | bail: | |
211 | spin_unlock_irqrestore (&ehci->lock, flags); | |
212 | ||
f03c17fc | 213 | // could save FLADJ in case of Vaux power loss |
7ff71d6a MP |
214 | // ... we'd only use it to handle clock skew |
215 | ||
8de98402 | 216 | return rc; |
7ff71d6a MP |
217 | } |
218 | ||
abcc9448 | 219 | static int ehci_pci_resume(struct usb_hcd *hcd) |
7ff71d6a | 220 | { |
abcc9448 | 221 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
7ff71d6a | 222 | unsigned port; |
18807521 | 223 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
7ff71d6a MP |
224 | int retval = -EINVAL; |
225 | ||
f03c17fc | 226 | // maybe restore FLADJ |
7ff71d6a | 227 | |
abcc9448 DB |
228 | if (time_before(jiffies, ehci->next_statechange)) |
229 | msleep(100); | |
7ff71d6a | 230 | |
8de98402 BH |
231 | /* Mark hardware accessible again as we are out of D3 state by now */ |
232 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
233 | ||
f03c17fc | 234 | /* If CF is clear, we lost PCI Vaux power and need to restart. */ |
18807521 | 235 | if (readl(&ehci->regs->configured_flag) != FLAG_CF) |
f03c17fc DB |
236 | goto restart; |
237 | ||
7ff71d6a MP |
238 | /* If any port is suspended (or owned by the companion), |
239 | * we know we can/must resume the HC (and mustn't reset it). | |
f03c17fc | 240 | * We just defer that to the root hub code. |
7ff71d6a | 241 | */ |
abcc9448 | 242 | for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) { |
7ff71d6a MP |
243 | u32 status; |
244 | port--; | |
abcc9448 | 245 | status = readl(&ehci->regs->port_status [port]); |
7ff71d6a MP |
246 | if (!(status & PORT_POWER)) |
247 | continue; | |
f03c17fc DB |
248 | if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) { |
249 | usb_hcd_resume_root_hub(hcd); | |
250 | return 0; | |
7ff71d6a | 251 | } |
f03c17fc DB |
252 | } |
253 | ||
254 | restart: | |
255 | ehci_dbg(ehci, "lost power, restarting\n"); | |
1c50c317 | 256 | usb_root_hub_lost_power(hcd->self.root_hub); |
7ff71d6a MP |
257 | |
258 | /* Else reset, to cope with power loss or flush-to-storage | |
f03c17fc | 259 | * style "resume" having let BIOS kick in during reboot. |
7ff71d6a | 260 | */ |
abcc9448 DB |
261 | (void) ehci_halt(ehci); |
262 | (void) ehci_reset(ehci); | |
18807521 | 263 | (void) ehci_pci_reinit(ehci, pdev); |
f03c17fc DB |
264 | |
265 | /* emptying the schedule aborts any urbs */ | |
abcc9448 | 266 | spin_lock_irq(&ehci->lock); |
f03c17fc DB |
267 | if (ehci->reclaim) |
268 | ehci->reclaim_ready = 1; | |
abcc9448 DB |
269 | ehci_work(ehci, NULL); |
270 | spin_unlock_irq(&ehci->lock); | |
f03c17fc DB |
271 | |
272 | /* restart; khubd will disconnect devices */ | |
abcc9448 | 273 | retval = ehci_run(hcd); |
f03c17fc | 274 | |
18807521 | 275 | /* here we "know" root ports should always stay powered */ |
abcc9448 | 276 | ehci_port_power(ehci, 1); |
7ff71d6a MP |
277 | |
278 | return retval; | |
279 | } | |
280 | #endif | |
281 | ||
282 | static const struct hc_driver ehci_pci_hc_driver = { | |
283 | .description = hcd_name, | |
284 | .product_desc = "EHCI Host Controller", | |
285 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
286 | ||
287 | /* | |
288 | * generic hardware linkage | |
289 | */ | |
290 | .irq = ehci_irq, | |
291 | .flags = HCD_MEMORY | HCD_USB2, | |
292 | ||
293 | /* | |
294 | * basic lifecycle operations | |
295 | */ | |
8926bfa7 | 296 | .reset = ehci_pci_setup, |
18807521 | 297 | .start = ehci_run, |
7ff71d6a MP |
298 | #ifdef CONFIG_PM |
299 | .suspend = ehci_pci_suspend, | |
300 | .resume = ehci_pci_resume, | |
301 | #endif | |
18807521 | 302 | .stop = ehci_stop, |
7ff71d6a MP |
303 | |
304 | /* | |
305 | * managing i/o requests and associated device resources | |
306 | */ | |
307 | .urb_enqueue = ehci_urb_enqueue, | |
308 | .urb_dequeue = ehci_urb_dequeue, | |
309 | .endpoint_disable = ehci_endpoint_disable, | |
310 | ||
311 | /* | |
312 | * scheduling support | |
313 | */ | |
314 | .get_frame_number = ehci_get_frame, | |
315 | ||
316 | /* | |
317 | * root hub support | |
318 | */ | |
319 | .hub_status_data = ehci_hub_status_data, | |
320 | .hub_control = ehci_hub_control, | |
0c0382e3 AS |
321 | .bus_suspend = ehci_bus_suspend, |
322 | .bus_resume = ehci_bus_resume, | |
7ff71d6a MP |
323 | }; |
324 | ||
325 | /*-------------------------------------------------------------------------*/ | |
326 | ||
327 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
328 | static const struct pci_device_id pci_ids [] = { { | |
329 | /* handle any USB 2.0 EHCI controller */ | |
330 | PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0), | |
331 | .driver_data = (unsigned long) &ehci_pci_hc_driver, | |
332 | }, | |
333 | { /* end: all zeroes */ } | |
334 | }; | |
abcc9448 | 335 | MODULE_DEVICE_TABLE(pci, pci_ids); |
7ff71d6a MP |
336 | |
337 | /* pci driver glue; this is a "new style" PCI driver module */ | |
338 | static struct pci_driver ehci_pci_driver = { | |
339 | .name = (char *) hcd_name, | |
340 | .id_table = pci_ids, | |
341 | ||
342 | .probe = usb_hcd_pci_probe, | |
343 | .remove = usb_hcd_pci_remove, | |
344 | ||
345 | #ifdef CONFIG_PM | |
346 | .suspend = usb_hcd_pci_suspend, | |
347 | .resume = usb_hcd_pci_resume, | |
348 | #endif | |
349 | }; | |
350 | ||
abcc9448 | 351 | static int __init ehci_hcd_pci_init(void) |
7ff71d6a MP |
352 | { |
353 | if (usb_disabled()) | |
354 | return -ENODEV; | |
355 | ||
abcc9448 | 356 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", |
7ff71d6a | 357 | hcd_name, |
abcc9448 DB |
358 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), |
359 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
7ff71d6a | 360 | |
abcc9448 | 361 | return pci_register_driver(&ehci_pci_driver); |
7ff71d6a | 362 | } |
abcc9448 | 363 | module_init(ehci_hcd_pci_init); |
7ff71d6a | 364 | |
abcc9448 | 365 | static void __exit ehci_hcd_pci_cleanup(void) |
7ff71d6a | 366 | { |
abcc9448 | 367 | pci_unregister_driver(&ehci_pci_driver); |
7ff71d6a | 368 | } |
abcc9448 | 369 | module_exit(ehci_hcd_pci_cleanup); |