Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
578333ab AS |
2 | * Enhanced Host Controller Interface (EHCI) driver for USB. |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
1da177e4 | 6 | * Copyright (c) 2000-2004 by David Brownell |
53bd6a60 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
1da177e4 LT |
23 | #include <linux/module.h> |
24 | #include <linux/pci.h> | |
25 | #include <linux/dmapool.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/sched.h> | |
3c04e20e | 30 | #include <linux/vmalloc.h> |
1da177e4 LT |
31 | #include <linux/errno.h> |
32 | #include <linux/init.h> | |
d58b4bcc | 33 | #include <linux/hrtimer.h> |
1da177e4 LT |
34 | #include <linux/list.h> |
35 | #include <linux/interrupt.h> | |
1da177e4 | 36 | #include <linux/usb.h> |
27729aad | 37 | #include <linux/usb/hcd.h> |
1da177e4 LT |
38 | #include <linux/moduleparam.h> |
39 | #include <linux/dma-mapping.h> | |
694cc208 | 40 | #include <linux/debugfs.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
aa4d8342 | 42 | #include <linux/uaccess.h> |
1da177e4 | 43 | |
1da177e4 LT |
44 | #include <asm/byteorder.h> |
45 | #include <asm/io.h> | |
46 | #include <asm/irq.h> | |
1da177e4 | 47 | #include <asm/unaligned.h> |
1da177e4 | 48 | |
df7c1ca2 GL |
49 | #if defined(CONFIG_PPC_PS3) |
50 | #include <asm/firmware.h> | |
51 | #endif | |
52 | ||
1da177e4 LT |
53 | /*-------------------------------------------------------------------------*/ |
54 | ||
55 | /* | |
56 | * EHCI hc_driver implementation ... experimental, incomplete. | |
57 | * Based on the final 1.0 register interface specification. | |
58 | * | |
59 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
60 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
61 | * Next comes "CardBay", using USB 2.0 signals. | |
62 | * | |
63 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
64 | * Special thanks to Intel and VIA for providing host controllers to | |
65 | * test this driver on, and Cypress (including In-System Design) for | |
66 | * providing early devices for those host controllers to talk to! | |
1da177e4 LT |
67 | */ |
68 | ||
1da177e4 LT |
69 | #define DRIVER_AUTHOR "David Brownell" |
70 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
71 | ||
72 | static const char hcd_name [] = "ehci_hcd"; | |
73 | ||
74 | ||
9776afc8 | 75 | #undef VERBOSE_DEBUG |
1da177e4 LT |
76 | #undef EHCI_URB_TRACE |
77 | ||
78 | #ifdef DEBUG | |
79 | #define EHCI_STATS | |
80 | #endif | |
81 | ||
82 | /* magic numbers that can affect system performance */ | |
83 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
84 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
85 | #define EHCI_TUNE_RL_TT 0 | |
86 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
87 | #define EHCI_TUNE_MULT_TT 1 | |
ffda0803 AS |
88 | /* |
89 | * Some drivers think it's safe to schedule isochronous transfers more than | |
90 | * 256 ms into the future (partly as a result of an old bug in the scheduling | |
91 | * code). In an attempt to avoid trouble, we will use a minimum scheduling | |
92 | * length of 512 frames instead of 256. | |
93 | */ | |
94 | #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ | |
1da177e4 | 95 | |
1da177e4 | 96 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ |
004c1968 | 97 | #define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1) |
fcda37cb | 98 | /* 5-ms async qh unlink delay */ |
1da177e4 LT |
99 | |
100 | /* Initial IRQ latency: faster than hw default */ | |
101 | static int log2_irq_thresh = 0; // 0 to 6 | |
102 | module_param (log2_irq_thresh, int, S_IRUGO); | |
103 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
104 | ||
105 | /* initial park setting: slower than hw default */ | |
106 | static unsigned park = 0; | |
107 | module_param (park, uint, S_IRUGO); | |
108 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
109 | ||
93f1a47c | 110 | /* for flakey hardware, ignore overcurrent indicators */ |
90ab5ee9 | 111 | static bool ignore_oc = 0; |
93f1a47c DB |
112 | module_param (ignore_oc, bool, S_IRUGO); |
113 | MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); | |
114 | ||
48f24970 AD |
115 | /* for link power management(LPM) feature */ |
116 | static unsigned int hird; | |
117 | module_param(hird, int, S_IRUGO); | |
cc556871 | 118 | MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us"); |
48f24970 | 119 | |
1da177e4 LT |
120 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) |
121 | ||
122 | /*-------------------------------------------------------------------------*/ | |
123 | ||
124 | #include "ehci.h" | |
125 | #include "ehci-dbg.c" | |
ad93562b | 126 | #include "pci-quirks.h" |
1da177e4 LT |
127 | |
128 | /*-------------------------------------------------------------------------*/ | |
129 | ||
bc29847e AS |
130 | static void |
131 | timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) | |
132 | { | |
133 | /* Don't override timeouts which shrink or (later) disable | |
134 | * the async ring; just the I/O watchdog. Note that if a | |
135 | * SHRINK were pending, OFF would never be requested. | |
136 | */ | |
137 | if (timer_pending(&ehci->watchdog) | |
31446610 | 138 | && (BIT(TIMER_ASYNC_SHRINK) |
bc29847e AS |
139 | & ehci->actions)) |
140 | return; | |
141 | ||
142 | if (!test_and_set_bit(action, &ehci->actions)) { | |
143 | unsigned long t; | |
144 | ||
145 | switch (action) { | |
146 | case TIMER_IO_WATCHDOG: | |
403dbd36 AD |
147 | if (!ehci->need_io_watchdog) |
148 | return; | |
bc29847e AS |
149 | t = EHCI_IO_JIFFIES; |
150 | break; | |
bc29847e AS |
151 | /* case TIMER_ASYNC_SHRINK: */ |
152 | default: | |
004c1968 | 153 | t = EHCI_SHRINK_JIFFIES; |
bc29847e AS |
154 | break; |
155 | } | |
156 | mod_timer(&ehci->watchdog, t + jiffies); | |
157 | } | |
158 | } | |
159 | ||
160 | /*-------------------------------------------------------------------------*/ | |
161 | ||
1da177e4 LT |
162 | /* |
163 | * handshake - spin reading hc until handshake completes or fails | |
164 | * @ptr: address of hc register to be read | |
165 | * @mask: bits to look at in result of read | |
166 | * @done: value of those bits when handshake succeeds | |
167 | * @usec: timeout in microseconds | |
168 | * | |
169 | * Returns negative errno, or zero on success | |
170 | * | |
171 | * Success happens when the "mask" bits have the specified value (hardware | |
172 | * handshake done). There are two failure modes: "usec" have passed (major | |
173 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
174 | * | |
175 | * That last failure should_only happen in cases like physical cardbus eject | |
176 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
177 | * bridge shutdown: shutting down the bridge before the devices using it. | |
178 | */ | |
083522d7 BH |
179 | static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, |
180 | u32 mask, u32 done, int usec) | |
1da177e4 LT |
181 | { |
182 | u32 result; | |
183 | ||
184 | do { | |
083522d7 | 185 | result = ehci_readl(ehci, ptr); |
1da177e4 LT |
186 | if (result == ~(u32)0) /* card removed */ |
187 | return -ENODEV; | |
188 | result &= mask; | |
189 | if (result == done) | |
190 | return 0; | |
191 | udelay (1); | |
192 | usec--; | |
193 | } while (usec > 0); | |
194 | return -ETIMEDOUT; | |
195 | } | |
196 | ||
65fd4272 MC |
197 | /* check TDI/ARC silicon is in host mode */ |
198 | static int tdi_in_host_mode (struct ehci_hcd *ehci) | |
199 | { | |
65fd4272 MC |
200 | u32 tmp; |
201 | ||
a46af4eb | 202 | tmp = ehci_readl(ehci, &ehci->regs->usbmode); |
65fd4272 MC |
203 | return (tmp & 3) == USBMODE_CM_HC; |
204 | } | |
205 | ||
1da177e4 LT |
206 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ |
207 | static int ehci_halt (struct ehci_hcd *ehci) | |
208 | { | |
083522d7 | 209 | u32 temp = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 | 210 | |
72f30b6f | 211 | /* disable any irqs left enabled by previous code */ |
083522d7 | 212 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
72f30b6f | 213 | |
65fd4272 MC |
214 | if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { |
215 | return 0; | |
216 | } | |
217 | ||
1da177e4 LT |
218 | if ((temp & STS_HALT) != 0) |
219 | return 0; | |
220 | ||
3d9545cc AS |
221 | /* |
222 | * This routine gets called during probe before ehci->command | |
223 | * has been initialized, so we can't rely on its value. | |
224 | */ | |
225 | ehci->command &= ~CMD_RUN; | |
083522d7 | 226 | temp = ehci_readl(ehci, &ehci->regs->command); |
3d9545cc | 227 | temp &= ~(CMD_RUN | CMD_IAAD); |
083522d7 BH |
228 | ehci_writel(ehci, temp, &ehci->regs->command); |
229 | return handshake (ehci, &ehci->regs->status, | |
230 | STS_HALT, STS_HALT, 16 * 125); | |
1da177e4 LT |
231 | } |
232 | ||
233 | /* put TDI/ARC silicon into EHCI mode */ | |
234 | static void tdi_reset (struct ehci_hcd *ehci) | |
235 | { | |
1da177e4 LT |
236 | u32 tmp; |
237 | ||
a46af4eb | 238 | tmp = ehci_readl(ehci, &ehci->regs->usbmode); |
d23a1377 VB |
239 | tmp |= USBMODE_CM_HC; |
240 | /* The default byte access to MMR space is LE after | |
241 | * controller reset. Set the required endian mode | |
242 | * for transfer buffers to match the host microprocessor | |
243 | */ | |
244 | if (ehci_big_endian_mmio(ehci)) | |
245 | tmp |= USBMODE_BE; | |
a46af4eb | 246 | ehci_writel(ehci, tmp, &ehci->regs->usbmode); |
1da177e4 LT |
247 | } |
248 | ||
249 | /* reset a non-running (STS_HALT == 1) controller */ | |
250 | static int ehci_reset (struct ehci_hcd *ehci) | |
251 | { | |
252 | int retval; | |
083522d7 | 253 | u32 command = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 254 | |
8d053c79 JW |
255 | /* If the EHCI debug controller is active, special care must be |
256 | * taken before and after a host controller reset */ | |
257 | if (ehci->debug && !dbgp_reset_prep()) | |
258 | ehci->debug = NULL; | |
259 | ||
1da177e4 LT |
260 | command |= CMD_RESET; |
261 | dbg_cmd (ehci, "reset", command); | |
083522d7 | 262 | ehci_writel(ehci, command, &ehci->regs->command); |
e8799906 | 263 | ehci->rh_state = EHCI_RH_HALTED; |
1da177e4 | 264 | ehci->next_statechange = jiffies; |
083522d7 BH |
265 | retval = handshake (ehci, &ehci->regs->command, |
266 | CMD_RESET, 0, 250 * 1000); | |
1da177e4 | 267 | |
331ac6b2 AD |
268 | if (ehci->has_hostpc) { |
269 | ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, | |
a46af4eb AS |
270 | &ehci->regs->usbmode_ex); |
271 | ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning); | |
331ac6b2 | 272 | } |
1da177e4 LT |
273 | if (retval) |
274 | return retval; | |
275 | ||
276 | if (ehci_is_TDI(ehci)) | |
277 | tdi_reset (ehci); | |
278 | ||
8d053c79 JW |
279 | if (ehci->debug) |
280 | dbgp_external_startup(); | |
281 | ||
a448e4dc AS |
282 | ehci->port_c_suspend = ehci->suspended_ports = |
283 | ehci->resuming_ports = 0; | |
1da177e4 LT |
284 | return retval; |
285 | } | |
286 | ||
287 | /* idle the controller (from running) */ | |
288 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
289 | { | |
290 | u32 temp; | |
291 | ||
e8799906 | 292 | if (ehci->rh_state != EHCI_RH_RUNNING) |
c0c53dbc | 293 | return; |
1da177e4 LT |
294 | |
295 | /* wait for any schedule enables/disables to take effect */ | |
3d9545cc | 296 | temp = (ehci->command << 10) & (STS_ASS | STS_PSS); |
9671cd7a | 297 | handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp, 16 * 125); |
1da177e4 LT |
298 | |
299 | /* then disable anything that's still active */ | |
3d9545cc AS |
300 | ehci->command &= ~(CMD_ASE | CMD_PSE); |
301 | ehci_writel(ehci, ehci->command, &ehci->regs->command); | |
1da177e4 LT |
302 | |
303 | /* hardware can take 16 microframes to turn off ... */ | |
9671cd7a | 304 | handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0, 16 * 125); |
1da177e4 LT |
305 | } |
306 | ||
307 | /*-------------------------------------------------------------------------*/ | |
308 | ||
07d29b63 | 309 | static void end_unlink_async(struct ehci_hcd *ehci); |
7d12e780 | 310 | static void ehci_work(struct ehci_hcd *ehci); |
df202255 AS |
311 | static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh); |
312 | static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh); | |
1da177e4 | 313 | |
d58b4bcc | 314 | #include "ehci-timer.c" |
1da177e4 | 315 | #include "ehci-hub.c" |
48f24970 | 316 | #include "ehci-lpm.c" |
1da177e4 LT |
317 | #include "ehci-mem.c" |
318 | #include "ehci-q.c" | |
319 | #include "ehci-sched.c" | |
4c67045b | 320 | #include "ehci-sysfs.c" |
1da177e4 LT |
321 | |
322 | /*-------------------------------------------------------------------------*/ | |
323 | ||
07d29b63 AS |
324 | static void ehci_watchdog(unsigned long param) |
325 | { | |
326 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
327 | unsigned long flags; | |
328 | ||
329 | spin_lock_irqsave(&ehci->lock, flags); | |
330 | ||
1da177e4 | 331 | /* ehci could run by timer, without IRQs ... */ |
7d12e780 | 332 | ehci_work (ehci); |
1da177e4 LT |
333 | |
334 | spin_unlock_irqrestore (&ehci->lock, flags); | |
335 | } | |
336 | ||
8903795a AS |
337 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
338 | * The firmware seems to think that powering off is a wakeup event! | |
339 | * This routine turns off remote wakeup and everything else, on all ports. | |
340 | */ | |
341 | static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) | |
342 | { | |
343 | int port = HCS_N_PORTS(ehci->hcs_params); | |
344 | ||
345 | while (port--) | |
346 | ehci_writel(ehci, PORT_RWC_BITS, | |
347 | &ehci->regs->port_status[port]); | |
348 | } | |
349 | ||
21da84a8 SS |
350 | /* |
351 | * Halt HC, turn off all ports, and let the BIOS use the companion controllers. | |
352 | * Should be called with ehci->lock held. | |
72f30b6f | 353 | */ |
21da84a8 | 354 | static void ehci_silence_controller(struct ehci_hcd *ehci) |
1da177e4 | 355 | { |
21da84a8 | 356 | ehci_halt(ehci); |
8903795a | 357 | ehci_turn_off_all_ports(ehci); |
1da177e4 LT |
358 | |
359 | /* make BIOS/etc use companion controller during reboot */ | |
083522d7 | 360 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
8903795a AS |
361 | |
362 | /* unblock posted writes */ | |
363 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
1da177e4 LT |
364 | } |
365 | ||
21da84a8 SS |
366 | /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). |
367 | * This forcibly disables dma and IRQs, helping kexec and other cases | |
368 | * where the next system software may expect clean state. | |
369 | */ | |
370 | static void ehci_shutdown(struct usb_hcd *hcd) | |
371 | { | |
372 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
373 | ||
374 | del_timer_sync(&ehci->watchdog); | |
21da84a8 SS |
375 | |
376 | spin_lock_irq(&ehci->lock); | |
c0c53dbc | 377 | ehci->rh_state = EHCI_RH_STOPPING; |
21da84a8 | 378 | ehci_silence_controller(ehci); |
d58b4bcc | 379 | ehci->enabled_hrtimer_events = 0; |
21da84a8 | 380 | spin_unlock_irq(&ehci->lock); |
d58b4bcc AS |
381 | |
382 | hrtimer_cancel(&ehci->hrtimer); | |
21da84a8 SS |
383 | } |
384 | ||
56c1e26d DB |
385 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
386 | { | |
387 | unsigned port; | |
388 | ||
389 | if (!HCS_PPC (ehci->hcs_params)) | |
390 | return; | |
391 | ||
392 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
393 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
394 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
395 | is_on ? SetPortFeature : ClearPortFeature, | |
396 | USB_PORT_FEAT_POWER, | |
397 | port--, NULL, 0); | |
383975d7 AS |
398 | /* Flush those writes */ |
399 | ehci_readl(ehci, &ehci->regs->command); | |
56c1e26d DB |
400 | msleep(20); |
401 | } | |
402 | ||
7ff71d6a | 403 | /*-------------------------------------------------------------------------*/ |
1da177e4 | 404 | |
7ff71d6a MP |
405 | /* |
406 | * ehci_work is called from some interrupts, timers, and so on. | |
407 | * it calls driver completion functions, after dropping ehci->lock. | |
408 | */ | |
7d12e780 | 409 | static void ehci_work (struct ehci_hcd *ehci) |
7ff71d6a MP |
410 | { |
411 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
7ff71d6a MP |
412 | |
413 | /* another CPU may drop ehci->lock during a schedule scan while | |
414 | * it reports urb completions. this flag guards against bogus | |
415 | * attempts at re-entrant schedule scanning. | |
416 | */ | |
417 | if (ehci->scanning) | |
418 | return; | |
419 | ehci->scanning = 1; | |
31446610 AS |
420 | if (ehci->async_count) |
421 | scan_async(ehci); | |
7ff71d6a | 422 | if (ehci->next_uframe != -1) |
7d12e780 | 423 | scan_periodic (ehci); |
7ff71d6a MP |
424 | ehci->scanning = 0; |
425 | ||
426 | /* the IO watchdog guards against hardware or driver bugs that | |
427 | * misplace IRQs, and should let us run completely without IRQs. | |
428 | * such lossage has been observed on both VT6202 and VT8235. | |
429 | */ | |
e8799906 | 430 | if (ehci->rh_state == EHCI_RH_RUNNING && |
7ff71d6a | 431 | (ehci->async->qh_next.ptr != NULL || |
3ca9aeba | 432 | ehci->periodic_count != 0)) |
7ff71d6a MP |
433 | timer_action (ehci, TIMER_IO_WATCHDOG); |
434 | } | |
1da177e4 | 435 | |
21da84a8 SS |
436 | /* |
437 | * Called when the ehci_hcd module is removed. | |
438 | */ | |
7ff71d6a | 439 | static void ehci_stop (struct usb_hcd *hcd) |
1da177e4 LT |
440 | { |
441 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 | 442 | |
7ff71d6a | 443 | ehci_dbg (ehci, "stop\n"); |
1da177e4 | 444 | |
7ff71d6a MP |
445 | /* no more interrupts ... */ |
446 | del_timer_sync (&ehci->watchdog); | |
56c1e26d | 447 | |
7ff71d6a | 448 | spin_lock_irq(&ehci->lock); |
d58b4bcc | 449 | ehci->enabled_hrtimer_events = 0; |
c0c53dbc | 450 | ehci_quiesce(ehci); |
1da177e4 | 451 | |
21da84a8 | 452 | ehci_silence_controller(ehci); |
7ff71d6a | 453 | ehci_reset (ehci); |
7ff71d6a | 454 | spin_unlock_irq(&ehci->lock); |
1da177e4 | 455 | |
d58b4bcc | 456 | hrtimer_cancel(&ehci->hrtimer); |
4c67045b | 457 | remove_sysfs_files(ehci); |
7ff71d6a | 458 | remove_debug_files (ehci); |
1da177e4 | 459 | |
7ff71d6a MP |
460 | /* root hub is shut down separately (first, when possible) */ |
461 | spin_lock_irq (&ehci->lock); | |
462 | if (ehci->async) | |
7d12e780 | 463 | ehci_work (ehci); |
55934eb3 | 464 | end_free_itds(ehci); |
7ff71d6a MP |
465 | spin_unlock_irq (&ehci->lock); |
466 | ehci_mem_cleanup (ehci); | |
1da177e4 | 467 | |
ad93562b AX |
468 | if (ehci->amd_pll_fix == 1) |
469 | usb_amd_dev_put(); | |
05570297 | 470 | |
7ff71d6a | 471 | #ifdef EHCI_STATS |
99ac5b1e AS |
472 | ehci_dbg(ehci, "irq normal %ld err %ld iaa %ld (lost %ld)\n", |
473 | ehci->stats.normal, ehci->stats.error, ehci->stats.iaa, | |
7ff71d6a MP |
474 | ehci->stats.lost_iaa); |
475 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
476 | ehci->stats.complete, ehci->stats.unlink); | |
1da177e4 | 477 | #endif |
1da177e4 | 478 | |
083522d7 BH |
479 | dbg_status (ehci, "ehci_stop completed", |
480 | ehci_readl(ehci, &ehci->regs->status)); | |
1da177e4 LT |
481 | } |
482 | ||
18807521 DB |
483 | /* one-time init, only for memory state */ |
484 | static int ehci_init(struct usb_hcd *hcd) | |
1da177e4 | 485 | { |
18807521 | 486 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
1da177e4 | 487 | u32 temp; |
1da177e4 LT |
488 | int retval; |
489 | u32 hcc_params; | |
3807e26d | 490 | struct ehci_qh_hw *hw; |
18807521 DB |
491 | |
492 | spin_lock_init(&ehci->lock); | |
493 | ||
403dbd36 AD |
494 | /* |
495 | * keep io watchdog by default, those good HCDs could turn off it later | |
496 | */ | |
497 | ehci->need_io_watchdog = 1; | |
18807521 DB |
498 | init_timer(&ehci->watchdog); |
499 | ehci->watchdog.function = ehci_watchdog; | |
500 | ehci->watchdog.data = (unsigned long) ehci; | |
1da177e4 | 501 | |
d58b4bcc AS |
502 | hrtimer_init(&ehci->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); |
503 | ehci->hrtimer.function = ehci_hrtimer_func; | |
504 | ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT; | |
505 | ||
f75593ce AS |
506 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
507 | ||
cc62a7eb KS |
508 | /* |
509 | * by default set standard 80% (== 100 usec/uframe) max periodic | |
510 | * bandwidth as required by USB 2.0 | |
511 | */ | |
512 | ehci->uframe_periodic_max = 100; | |
513 | ||
1da177e4 LT |
514 | /* |
515 | * hw default: 1K periodic list heads, one per frame. | |
516 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
517 | */ | |
518 | ehci->periodic_size = DEFAULT_I_TDPS; | |
9aa09d2f | 519 | INIT_LIST_HEAD(&ehci->cached_itd_list); |
0e5f231b | 520 | INIT_LIST_HEAD(&ehci->cached_sitd_list); |
f75593ce | 521 | |
8e192910 | 522 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
f75593ce AS |
523 | /* periodic schedule size can be smaller than default */ |
524 | switch (EHCI_TUNE_FLS) { | |
525 | case 0: ehci->periodic_size = 1024; break; | |
526 | case 1: ehci->periodic_size = 512; break; | |
527 | case 2: ehci->periodic_size = 256; break; | |
528 | default: BUG(); | |
529 | } | |
530 | } | |
18807521 | 531 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
1da177e4 LT |
532 | return retval; |
533 | ||
534 | /* controllers may cache some of the periodic schedule ... */ | |
53bd6a60 | 535 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
dccd574c | 536 | ehci->i_thresh = 2 + 8; |
1da177e4 | 537 | else // N microframes cached |
18807521 | 538 | ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
1da177e4 | 539 | |
1da177e4 | 540 | ehci->next_uframe = -1; |
9aa09d2f | 541 | ehci->clock_frame = -1; |
1da177e4 | 542 | |
1da177e4 LT |
543 | /* |
544 | * dedicate a qh for the async ring head, since we couldn't unlink | |
545 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
546 | * as the 'reclamation list head' too. | |
547 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
548 | * from automatically advancing to the next td after short reads. | |
549 | */ | |
18807521 | 550 | ehci->async->qh_next.qh = NULL; |
3807e26d AD |
551 | hw = ehci->async->hw; |
552 | hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); | |
553 | hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); | |
4f7a67e2 | 554 | #if defined(CONFIG_PPC_PS3) |
4c53de72 | 555 | hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE); |
4f7a67e2 | 556 | #endif |
3807e26d AD |
557 | hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); |
558 | hw->hw_qtd_next = EHCI_LIST_END(ehci); | |
18807521 | 559 | ehci->async->qh_state = QH_STATE_LINKED; |
3807e26d | 560 | hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); |
1da177e4 LT |
561 | |
562 | /* clear interrupt enables, set irq latency */ | |
563 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
564 | log2_irq_thresh = 0; | |
565 | temp = 1 << (16 + log2_irq_thresh); | |
5a9cdf33 AD |
566 | if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { |
567 | ehci->has_ppcd = 1; | |
568 | ehci_dbg(ehci, "enable per-port change event\n"); | |
569 | temp |= CMD_PPCEE; | |
570 | } | |
1da177e4 LT |
571 | if (HCC_CANPARK(hcc_params)) { |
572 | /* HW default park == 3, on hardware that supports it (like | |
573 | * NVidia and ALI silicon), maximizes throughput on the async | |
574 | * schedule by avoiding QH fetches between transfers. | |
575 | * | |
576 | * With fast usb storage devices and NForce2, "park" seems to | |
577 | * make problems: throughput reduction (!), data errors... | |
578 | */ | |
579 | if (park) { | |
18807521 | 580 | park = min(park, (unsigned) 3); |
1da177e4 LT |
581 | temp |= CMD_PARK; |
582 | temp |= park << 8; | |
583 | } | |
18807521 | 584 | ehci_dbg(ehci, "park %d\n", park); |
1da177e4 | 585 | } |
18807521 | 586 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
1da177e4 LT |
587 | /* periodic schedule size can be smaller than default */ |
588 | temp &= ~(3 << 2); | |
589 | temp |= (EHCI_TUNE_FLS << 2); | |
1da177e4 | 590 | } |
48f24970 AD |
591 | if (HCC_LPM(hcc_params)) { |
592 | /* support link power management EHCI 1.1 addendum */ | |
593 | ehci_dbg(ehci, "support lpm\n"); | |
594 | ehci->has_lpm = 1; | |
595 | if (hird > 0xf) { | |
596 | ehci_dbg(ehci, "hird %d invalid, use default 0", | |
597 | hird); | |
598 | hird = 0; | |
599 | } | |
600 | temp |= hird << 24; | |
601 | } | |
18807521 DB |
602 | ehci->command = temp; |
603 | ||
40f8db8f | 604 | /* Accept arbitrarily long scatter-gather lists */ |
4307a28e AR |
605 | if (!(hcd->driver->flags & HCD_LOCAL_MEM)) |
606 | hcd->self.sg_tablesize = ~0; | |
18807521 DB |
607 | return 0; |
608 | } | |
609 | ||
610 | /* start HC running; it's halted, ehci_init() has been run (once) */ | |
611 | static int ehci_run (struct usb_hcd *hcd) | |
612 | { | |
613 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
18807521 DB |
614 | u32 temp; |
615 | u32 hcc_params; | |
616 | ||
1d619f12 | 617 | hcd->uses_new_polling = 1; |
1d619f12 | 618 | |
18807521 | 619 | /* EHCI spec section 4.1 */ |
876e0df9 | 620 | |
083522d7 BH |
621 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
622 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
18807521 DB |
623 | |
624 | /* | |
625 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
626 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
627 | * pci_pool consistent memory always uses segment zero. | |
628 | * streaming mappings for I/O buffers, like pci_map_single(), | |
629 | * can return segments above 4GB, if the device allows. | |
630 | * | |
631 | * NOTE: the dma mask is visible through dma_supported(), so | |
632 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
633 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
634 | * host side drivers though. | |
635 | */ | |
083522d7 | 636 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
18807521 | 637 | if (HCC_64BIT_ADDR(hcc_params)) { |
083522d7 | 638 | ehci_writel(ehci, 0, &ehci->regs->segment); |
18807521 DB |
639 | #if 0 |
640 | // this is deeply broken on almost all architectures | |
6a35528a | 641 | if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) |
18807521 DB |
642 | ehci_info(ehci, "enabled 64bit DMA\n"); |
643 | #endif | |
644 | } | |
645 | ||
646 | ||
1da177e4 LT |
647 | // Philips, Intel, and maybe others need CMD_RUN before the |
648 | // root hub will detect new devices (why?); NEC doesn't | |
18807521 DB |
649 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
650 | ehci->command |= CMD_RUN; | |
083522d7 | 651 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
18807521 | 652 | dbg_cmd (ehci, "init", ehci->command); |
1da177e4 | 653 | |
1da177e4 LT |
654 | /* |
655 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
656 | * are explicitly handed to companion controller(s), so no TT is | |
657 | * involved with the root hub. (Except where one is integrated, | |
658 | * and there's no companion controller unless maybe for USB OTG.) | |
32fe0198 AS |
659 | * |
660 | * Turning on the CF flag will transfer ownership of all ports | |
661 | * from the companions to the EHCI controller. If any of the | |
662 | * companions are in the middle of a port reset at the time, it | |
663 | * could cause trouble. Write-locking ehci_cf_port_reset_rwsem | |
1cb52658 DB |
664 | * guarantees that no resets are in progress. After we set CF, |
665 | * a short delay lets the hardware catch up; new resets shouldn't | |
666 | * be started before the port switching actions could complete. | |
1da177e4 | 667 | */ |
32fe0198 | 668 | down_write(&ehci_cf_port_reset_rwsem); |
e8799906 | 669 | ehci->rh_state = EHCI_RH_RUNNING; |
083522d7 BH |
670 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
671 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1cb52658 | 672 | msleep(5); |
32fe0198 | 673 | up_write(&ehci_cf_port_reset_rwsem); |
ee4ecb8a | 674 | ehci->last_periodic_enable = ktime_get_real(); |
1da177e4 | 675 | |
c430131a | 676 | temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
1da177e4 | 677 | ehci_info (ehci, |
2b70f073 | 678 | "USB %x.%x started, EHCI %x.%02x%s\n", |
7ff71d6a | 679 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
2b70f073 | 680 | temp >> 8, temp & 0xff, |
93f1a47c | 681 | ignore_oc ? ", overcurrent ignored" : ""); |
1da177e4 | 682 | |
083522d7 BH |
683 | ehci_writel(ehci, INTR_MASK, |
684 | &ehci->regs->intr_enable); /* Turn On Interrupts */ | |
1da177e4 | 685 | |
18807521 DB |
686 | /* GRR this is run-once init(), being done every time the HC starts. |
687 | * So long as they're part of class devices, we can't do it init() | |
688 | * since the class device isn't created that early. | |
689 | */ | |
690 | create_debug_files(ehci); | |
4c67045b | 691 | create_sysfs_files(ehci); |
1da177e4 LT |
692 | |
693 | return 0; | |
694 | } | |
695 | ||
1a49e2ac | 696 | static int ehci_setup(struct usb_hcd *hcd) |
2093c6b4 MC |
697 | { |
698 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
699 | int retval; | |
700 | ||
701 | ehci->regs = (void __iomem *)ehci->caps + | |
702 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); | |
703 | dbg_hcs_params(ehci, "reset"); | |
704 | dbg_hcc_params(ehci, "reset"); | |
705 | ||
706 | /* cache this readonly data; minimize chip reads */ | |
707 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | |
708 | ||
709 | ehci->sbrn = HCD_USB2; | |
710 | ||
631fe9d9 AS |
711 | /* data structure init */ |
712 | retval = ehci_init(hcd); | |
2093c6b4 MC |
713 | if (retval) |
714 | return retval; | |
715 | ||
631fe9d9 | 716 | retval = ehci_halt(ehci); |
2093c6b4 MC |
717 | if (retval) |
718 | return retval; | |
719 | ||
1a49e2ac AS |
720 | if (ehci_is_TDI(ehci)) |
721 | tdi_reset(ehci); | |
722 | ||
2093c6b4 MC |
723 | ehci_reset(ehci); |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
1da177e4 LT |
728 | /*-------------------------------------------------------------------------*/ |
729 | ||
7d12e780 | 730 | static irqreturn_t ehci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
731 | { |
732 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
67b2e029 | 733 | u32 status, masked_status, pcd_status = 0, cmd; |
1da177e4 LT |
734 | int bh; |
735 | ||
736 | spin_lock (&ehci->lock); | |
737 | ||
083522d7 | 738 | status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
739 | |
740 | /* e.g. cardbus physical eject */ | |
741 | if (status == ~(u32) 0) { | |
742 | ehci_dbg (ehci, "device removed\n"); | |
743 | goto dead; | |
744 | } | |
745 | ||
2fbe2bf1 AS |
746 | /* |
747 | * We don't use STS_FLR, but some controllers don't like it to | |
748 | * remain on, so mask it out along with the other status bits. | |
749 | */ | |
750 | masked_status = status & (INTR_MASK | STS_FLR); | |
751 | ||
69fff59d | 752 | /* Shared IRQ? */ |
e8799906 | 753 | if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { |
1da177e4 LT |
754 | spin_unlock(&ehci->lock); |
755 | return IRQ_NONE; | |
756 | } | |
757 | ||
758 | /* clear (just) interrupts */ | |
67b2e029 | 759 | ehci_writel(ehci, masked_status, &ehci->regs->status); |
e82cc128 | 760 | cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
761 | bh = 0; |
762 | ||
9776afc8 | 763 | #ifdef VERBOSE_DEBUG |
1da177e4 LT |
764 | /* unrequested/ignored: Frame List Rollover */ |
765 | dbg_status (ehci, "irq", status); | |
766 | #endif | |
767 | ||
768 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
769 | ||
770 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
771 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
772 | if (likely ((status & STS_ERR) == 0)) | |
773 | COUNT (ehci->stats.normal); | |
774 | else | |
775 | COUNT (ehci->stats.error); | |
776 | bh = 1; | |
777 | } | |
778 | ||
779 | /* complete the unlinking of some qh [4.15.2.3] */ | |
780 | if (status & STS_IAA) { | |
9d938747 AS |
781 | |
782 | /* Turn off the IAA watchdog */ | |
783 | ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG); | |
784 | ||
785 | /* | |
786 | * Mild optimization: Allow another IAAD to reset the | |
787 | * hrtimer, if one occurs before the next expiration. | |
788 | * In theory we could always cancel the hrtimer, but | |
789 | * tests show that about half the time it will be reset | |
790 | * for some other event anyway. | |
791 | */ | |
792 | if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG) | |
793 | ++ehci->next_hrtimer_event; | |
794 | ||
e82cc128 | 795 | /* guard against (alleged) silicon errata */ |
6feff1b9 | 796 | if (cmd & CMD_IAAD) |
e82cc128 | 797 | ehci_dbg(ehci, "IAA with IAAD still set?\n"); |
3c273a05 | 798 | if (ehci->async_iaa) { |
99ac5b1e | 799 | COUNT(ehci->stats.iaa); |
e82cc128 DB |
800 | end_unlink_async(ehci); |
801 | } else | |
99ac5b1e | 802 | ehci_dbg(ehci, "IAA with nothing unlinked?\n"); |
1da177e4 LT |
803 | } |
804 | ||
805 | /* remote wakeup [4.3.1] */ | |
d97cc2f2 | 806 | if (status & STS_PCD) { |
1da177e4 | 807 | unsigned i = HCS_N_PORTS (ehci->hcs_params); |
5a9cdf33 | 808 | u32 ppcd = 0; |
d1b1842c DB |
809 | |
810 | /* kick root hub later */ | |
1d619f12 | 811 | pcd_status = status; |
1da177e4 LT |
812 | |
813 | /* resume root hub? */ | |
dc75ce9d | 814 | if (ehci->rh_state == EHCI_RH_SUSPENDED) |
8c03356a | 815 | usb_hcd_resume_root_hub(hcd); |
1da177e4 | 816 | |
5a9cdf33 AD |
817 | /* get per-port change detect bits */ |
818 | if (ehci->has_ppcd) | |
819 | ppcd = status >> 16; | |
820 | ||
1da177e4 | 821 | while (i--) { |
5a9cdf33 AD |
822 | int pstatus; |
823 | ||
824 | /* leverage per-port change bits feature */ | |
825 | if (ehci->has_ppcd && !(ppcd & (1 << i))) | |
826 | continue; | |
827 | pstatus = ehci_readl(ehci, | |
828 | &ehci->regs->port_status[i]); | |
b972b68c DB |
829 | |
830 | if (pstatus & PORT_OWNER) | |
1da177e4 | 831 | continue; |
eafe5b99 AS |
832 | if (!(test_bit(i, &ehci->suspended_ports) && |
833 | ((pstatus & PORT_RESUME) || | |
834 | !(pstatus & PORT_SUSPEND)) && | |
835 | (pstatus & PORT_PE) && | |
836 | ehci->reset_done[i] == 0)) | |
1da177e4 LT |
837 | continue; |
838 | ||
839 | /* start 20 msec resume signaling from this port, | |
840 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
49d0f078 AS |
841 | * stop that signaling. Use 5 ms extra for safety, |
842 | * like usb_port_resume() does. | |
1da177e4 | 843 | */ |
49d0f078 | 844 | ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); |
a448e4dc | 845 | set_bit(i, &ehci->resuming_ports); |
1da177e4 | 846 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); |
61e8b858 | 847 | mod_timer(&hcd->rh_timer, ehci->reset_done[i]); |
1da177e4 LT |
848 | } |
849 | } | |
850 | ||
851 | /* PCI errors [4.15.2.4] */ | |
852 | if (unlikely ((status & STS_FATAL) != 0)) { | |
67b2e029 | 853 | ehci_err(ehci, "fatal error\n"); |
eafe5b99 AS |
854 | dbg_cmd(ehci, "fatal", cmd); |
855 | dbg_status(ehci, "fatal", status); | |
1da177e4 | 856 | dead: |
69fff59d | 857 | usb_hc_died(hcd); |
bf6387bc AS |
858 | |
859 | /* Don't let the controller do anything more */ | |
860 | ehci->rh_state = EHCI_RH_STOPPING; | |
861 | ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE); | |
862 | ehci_writel(ehci, ehci->command, &ehci->regs->command); | |
863 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | |
864 | ehci_handle_controller_death(ehci); | |
865 | ||
866 | /* Handle completions when the controller stops */ | |
867 | bh = 0; | |
1da177e4 LT |
868 | } |
869 | ||
870 | if (bh) | |
7d12e780 | 871 | ehci_work (ehci); |
1da177e4 | 872 | spin_unlock (&ehci->lock); |
d1b1842c | 873 | if (pcd_status) |
1d619f12 | 874 | usb_hcd_poll_rh_status(hcd); |
1da177e4 LT |
875 | return IRQ_HANDLED; |
876 | } | |
877 | ||
878 | /*-------------------------------------------------------------------------*/ | |
879 | ||
880 | /* | |
881 | * non-error returns are a promise to giveback() the urb later | |
882 | * we drop ownership so next owner (or urb unlink) can get it | |
883 | * | |
884 | * urb + dev is in hcd.self.controller.urb_list | |
885 | * we're queueing TDs onto software and hardware lists | |
886 | * | |
887 | * hcd-specific init for hcpriv hasn't been done yet | |
888 | * | |
889 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
890 | * to a (possibly active) QH, and the same QH scanning code. | |
891 | */ | |
892 | static int ehci_urb_enqueue ( | |
893 | struct usb_hcd *hcd, | |
1da177e4 | 894 | struct urb *urb, |
55016f10 | 895 | gfp_t mem_flags |
1da177e4 LT |
896 | ) { |
897 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
898 | struct list_head qtd_list; | |
899 | ||
900 | INIT_LIST_HEAD (&qtd_list); | |
901 | ||
902 | switch (usb_pipetype (urb->pipe)) { | |
25b70a86 DB |
903 | case PIPE_CONTROL: |
904 | /* qh_completions() code doesn't handle all the fault cases | |
905 | * in multi-TD control transfers. Even 1KB is rare anyway. | |
906 | */ | |
907 | if (urb->transfer_buffer_length > (16 * 1024)) | |
908 | return -EMSGSIZE; | |
909 | /* FALLTHROUGH */ | |
910 | /* case PIPE_BULK: */ | |
1da177e4 LT |
911 | default: |
912 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
913 | return -ENOMEM; | |
e9df41c5 | 914 | return submit_async(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
915 | |
916 | case PIPE_INTERRUPT: | |
917 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
918 | return -ENOMEM; | |
e9df41c5 | 919 | return intr_submit(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
920 | |
921 | case PIPE_ISOCHRONOUS: | |
922 | if (urb->dev->speed == USB_SPEED_HIGH) | |
923 | return itd_submit (ehci, urb, mem_flags); | |
924 | else | |
925 | return sitd_submit (ehci, urb, mem_flags); | |
926 | } | |
927 | } | |
928 | ||
1da177e4 LT |
929 | /* remove from hardware lists |
930 | * completions normally happen asynchronously | |
931 | */ | |
932 | ||
e9df41c5 | 933 | static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
934 | { |
935 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
936 | struct ehci_qh *qh; | |
937 | unsigned long flags; | |
e9df41c5 | 938 | int rc; |
1da177e4 LT |
939 | |
940 | spin_lock_irqsave (&ehci->lock, flags); | |
e9df41c5 AS |
941 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
942 | if (rc) | |
943 | goto done; | |
944 | ||
1da177e4 LT |
945 | switch (usb_pipetype (urb->pipe)) { |
946 | // case PIPE_CONTROL: | |
947 | // case PIPE_BULK: | |
948 | default: | |
949 | qh = (struct ehci_qh *) urb->hcpriv; | |
950 | if (!qh) | |
951 | break; | |
07d29b63 AS |
952 | switch (qh->qh_state) { |
953 | case QH_STATE_LINKED: | |
954 | case QH_STATE_COMPLETING: | |
3c273a05 | 955 | start_unlink_async(ehci, qh); |
07d29b63 AS |
956 | break; |
957 | case QH_STATE_UNLINK: | |
958 | case QH_STATE_UNLINK_WAIT: | |
959 | /* already started */ | |
960 | break; | |
961 | case QH_STATE_IDLE: | |
7a0f0d95 AS |
962 | /* QH might be waiting for a Clear-TT-Buffer */ |
963 | qh_completions(ehci, qh); | |
07d29b63 AS |
964 | break; |
965 | } | |
1da177e4 LT |
966 | break; |
967 | ||
968 | case PIPE_INTERRUPT: | |
969 | qh = (struct ehci_qh *) urb->hcpriv; | |
970 | if (!qh) | |
971 | break; | |
972 | switch (qh->qh_state) { | |
973 | case QH_STATE_LINKED: | |
a448c9d8 | 974 | case QH_STATE_COMPLETING: |
df202255 | 975 | start_unlink_intr(ehci, qh); |
a448c9d8 | 976 | break; |
1da177e4 | 977 | case QH_STATE_IDLE: |
7d12e780 | 978 | qh_completions (ehci, qh); |
1da177e4 LT |
979 | break; |
980 | default: | |
981 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
982 | qh, qh->qh_state); | |
983 | goto done; | |
984 | } | |
1da177e4 LT |
985 | break; |
986 | ||
987 | case PIPE_ISOCHRONOUS: | |
988 | // itd or sitd ... | |
989 | ||
990 | // wait till next completion, do it then. | |
991 | // completion irqs can wait up to 1024 msec, | |
992 | break; | |
993 | } | |
994 | done: | |
995 | spin_unlock_irqrestore (&ehci->lock, flags); | |
e9df41c5 | 996 | return rc; |
1da177e4 LT |
997 | } |
998 | ||
999 | /*-------------------------------------------------------------------------*/ | |
1000 | ||
1001 | // bulk qh holds the data toggle | |
1002 | ||
1003 | static void | |
1004 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1005 | { | |
1006 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1007 | unsigned long flags; | |
1008 | struct ehci_qh *qh, *tmp; | |
1009 | ||
1010 | /* ASSERT: any requests/urbs are being unlinked */ | |
1011 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
1012 | ||
1013 | rescan: | |
1014 | spin_lock_irqsave (&ehci->lock, flags); | |
1015 | qh = ep->hcpriv; | |
1016 | if (!qh) | |
1017 | goto done; | |
1018 | ||
1019 | /* endpoints can be iso streams. for now, we don't | |
1020 | * accelerate iso completions ... so spin a while. | |
1021 | */ | |
1082f57a | 1022 | if (qh->hw == NULL) { |
8c5bf7be AS |
1023 | struct ehci_iso_stream *stream = ep->hcpriv; |
1024 | ||
1025 | if (!list_empty(&stream->td_list)) | |
1026 | goto idle_timeout; | |
1027 | ||
1028 | /* BUG_ON(!list_empty(&stream->free_list)); */ | |
1029 | kfree(stream); | |
1030 | goto done; | |
1da177e4 LT |
1031 | } |
1032 | ||
c0c53dbc | 1033 | if (ehci->rh_state < EHCI_RH_RUNNING) |
1da177e4 LT |
1034 | qh->qh_state = QH_STATE_IDLE; |
1035 | switch (qh->qh_state) { | |
1036 | case QH_STATE_LINKED: | |
3a44494e | 1037 | case QH_STATE_COMPLETING: |
1da177e4 LT |
1038 | for (tmp = ehci->async->qh_next.qh; |
1039 | tmp && tmp != qh; | |
1040 | tmp = tmp->qh_next.qh) | |
1041 | continue; | |
02e2c51b AS |
1042 | /* periodic qh self-unlinks on empty, and a COMPLETING qh |
1043 | * may already be unlinked. | |
1044 | */ | |
1045 | if (tmp) | |
3c273a05 | 1046 | start_unlink_async(ehci, qh); |
1da177e4 LT |
1047 | /* FALL THROUGH */ |
1048 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
07d29b63 | 1049 | case QH_STATE_UNLINK_WAIT: |
1da177e4 LT |
1050 | idle_timeout: |
1051 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 1052 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
1053 | goto rescan; |
1054 | case QH_STATE_IDLE: /* fully unlinked */ | |
914b7012 AS |
1055 | if (qh->clearing_tt) |
1056 | goto idle_timeout; | |
1da177e4 | 1057 | if (list_empty (&qh->qtd_list)) { |
c83e1a9f | 1058 | qh_destroy(ehci, qh); |
1da177e4 LT |
1059 | break; |
1060 | } | |
1061 | /* else FALL THROUGH */ | |
1062 | default: | |
1da177e4 LT |
1063 | /* caller was supposed to have unlinked any requests; |
1064 | * that's not our job. just leak this memory. | |
1065 | */ | |
1066 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
1067 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
1068 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
1069 | break; | |
1070 | } | |
8c5bf7be | 1071 | done: |
1da177e4 | 1072 | ep->hcpriv = NULL; |
1da177e4 | 1073 | spin_unlock_irqrestore (&ehci->lock, flags); |
1da177e4 LT |
1074 | } |
1075 | ||
b18ffd49 AS |
1076 | static void |
1077 | ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1078 | { | |
1079 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
1080 | struct ehci_qh *qh; | |
1081 | int eptype = usb_endpoint_type(&ep->desc); | |
a455212d AS |
1082 | int epnum = usb_endpoint_num(&ep->desc); |
1083 | int is_out = usb_endpoint_dir_out(&ep->desc); | |
1084 | unsigned long flags; | |
b18ffd49 AS |
1085 | |
1086 | if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) | |
1087 | return; | |
1088 | ||
a455212d | 1089 | spin_lock_irqsave(&ehci->lock, flags); |
b18ffd49 AS |
1090 | qh = ep->hcpriv; |
1091 | ||
1092 | /* For Bulk and Interrupt endpoints we maintain the toggle state | |
1093 | * in the hardware; the toggle bits in udev aren't used at all. | |
1094 | * When an endpoint is reset by usb_clear_halt() we must reset | |
1095 | * the toggle bit in the QH. | |
1096 | */ | |
1097 | if (qh) { | |
a455212d | 1098 | usb_settoggle(qh->dev, epnum, is_out, 0); |
b18ffd49 AS |
1099 | if (!list_empty(&qh->qtd_list)) { |
1100 | WARN_ONCE(1, "clear_halt for a busy endpoint\n"); | |
3a44494e AS |
1101 | } else if (qh->qh_state == QH_STATE_LINKED || |
1102 | qh->qh_state == QH_STATE_COMPLETING) { | |
a455212d AS |
1103 | |
1104 | /* The toggle value in the QH can't be updated | |
1105 | * while the QH is active. Unlink it now; | |
1106 | * re-linking will call qh_refresh(). | |
b18ffd49 | 1107 | */ |
a448c9d8 | 1108 | if (eptype == USB_ENDPOINT_XFER_BULK) |
3c273a05 | 1109 | start_unlink_async(ehci, qh); |
a448c9d8 | 1110 | else |
df202255 | 1111 | start_unlink_intr(ehci, qh); |
b18ffd49 AS |
1112 | } |
1113 | } | |
a455212d | 1114 | spin_unlock_irqrestore(&ehci->lock, flags); |
b18ffd49 AS |
1115 | } |
1116 | ||
7ff71d6a MP |
1117 | static int ehci_get_frame (struct usb_hcd *hcd) |
1118 | { | |
1119 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
68aa95d5 | 1120 | return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size; |
7ff71d6a | 1121 | } |
1da177e4 LT |
1122 | |
1123 | /*-------------------------------------------------------------------------*/ | |
c5cf9212 AS |
1124 | |
1125 | #ifdef CONFIG_PM | |
1126 | ||
1127 | /* suspend/resume, section 4.3 */ | |
1128 | ||
1129 | /* These routines handle the generic parts of controller suspend/resume */ | |
1130 | ||
1131 | static int __maybe_unused ehci_suspend(struct usb_hcd *hcd, bool do_wakeup) | |
1132 | { | |
1133 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
1134 | ||
1135 | if (time_before(jiffies, ehci->next_statechange)) | |
1136 | msleep(10); | |
1137 | ||
1138 | /* | |
1139 | * Root hub was already suspended. Disable IRQ emission and | |
1140 | * mark HW unaccessible. The PM and USB cores make sure that | |
1141 | * the root hub is either suspended or stopped. | |
1142 | */ | |
1143 | ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup); | |
1144 | ||
1145 | spin_lock_irq(&ehci->lock); | |
1146 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | |
1147 | (void) ehci_readl(ehci, &ehci->regs->intr_enable); | |
1148 | ||
1149 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
1150 | spin_unlock_irq(&ehci->lock); | |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | /* Returns 0 if power was preserved, 1 if power was lost */ | |
1156 | static int __maybe_unused ehci_resume(struct usb_hcd *hcd, bool hibernated) | |
1157 | { | |
1158 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
1159 | ||
1160 | if (time_before(jiffies, ehci->next_statechange)) | |
1161 | msleep(100); | |
1162 | ||
1163 | /* Mark hardware accessible again as we are back to full power by now */ | |
1164 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
1165 | ||
1166 | /* | |
1167 | * If CF is still set and we aren't resuming from hibernation | |
1168 | * then we maintained suspend power. | |
1169 | * Just undo the effect of ehci_suspend(). | |
1170 | */ | |
1171 | if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF && | |
1172 | !hibernated) { | |
1173 | int mask = INTR_MASK; | |
1174 | ||
1175 | ehci_prepare_ports_for_controller_resume(ehci); | |
1176 | if (!hcd->self.root_hub->do_remote_wakeup) | |
1177 | mask &= ~STS_PCD; | |
1178 | ehci_writel(ehci, mask, &ehci->regs->intr_enable); | |
1179 | ehci_readl(ehci, &ehci->regs->intr_enable); | |
1180 | return 0; | |
1181 | } | |
1182 | ||
1183 | /* | |
1184 | * Else reset, to cope with power loss or resume from hibernation | |
1185 | * having let the firmware kick in during reboot. | |
1186 | */ | |
1187 | usb_root_hub_lost_power(hcd->self.root_hub); | |
1188 | (void) ehci_halt(ehci); | |
1189 | (void) ehci_reset(ehci); | |
1190 | ||
c5cf9212 AS |
1191 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
1192 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); | |
1193 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1194 | ||
1195 | /* here we "know" root ports should always stay powered */ | |
1196 | ehci_port_power(ehci, 1); | |
1197 | ||
1198 | ehci->rh_state = EHCI_RH_SUSPENDED; | |
1199 | return 1; | |
1200 | } | |
1201 | ||
1202 | #endif | |
1203 | ||
1204 | /*-------------------------------------------------------------------------*/ | |
1205 | ||
eb70e5ab AS |
1206 | /* |
1207 | * The EHCI in ChipIdea HDRC cannot be a separate module or device, | |
1208 | * because its registers (and irq) are shared between host/gadget/otg | |
1209 | * functions and in order to facilitate role switching we cannot | |
1210 | * give the ehci driver exclusive access to those. | |
1211 | */ | |
1212 | #ifndef CHIPIDEA_EHCI | |
1da177e4 | 1213 | |
2b70f073 | 1214 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
1215 | MODULE_AUTHOR (DRIVER_AUTHOR); |
1216 | MODULE_LICENSE ("GPL"); | |
1217 | ||
7ff71d6a MP |
1218 | #ifdef CONFIG_PCI |
1219 | #include "ehci-pci.c" | |
01cced25 | 1220 | #define PCI_DRIVER ehci_pci_driver |
7ff71d6a | 1221 | #endif |
1da177e4 | 1222 | |
ba02978a | 1223 | #ifdef CONFIG_USB_EHCI_FSL |
80cb9aee | 1224 | #include "ehci-fsl.c" |
01cced25 | 1225 | #define PLATFORM_DRIVER ehci_fsl_driver |
80cb9aee RV |
1226 | #endif |
1227 | ||
7e8d5cd9 DM |
1228 | #ifdef CONFIG_USB_EHCI_MXC |
1229 | #include "ehci-mxc.c" | |
1230 | #define PLATFORM_DRIVER ehci_mxc_driver | |
1231 | #endif | |
1232 | ||
60b0bf0f | 1233 | #ifdef CONFIG_USB_EHCI_SH |
63c84552 PM |
1234 | #include "ehci-sh.c" |
1235 | #define PLATFORM_DRIVER ehci_hcd_sh_driver | |
1236 | #endif | |
1237 | ||
37663860 | 1238 | #ifdef CONFIG_MIPS_ALCHEMY |
76fa9a24 | 1239 | #include "ehci-au1xxx.c" |
01cced25 | 1240 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver |
76fa9a24 JC |
1241 | #endif |
1242 | ||
7f124f4b | 1243 | #ifdef CONFIG_USB_EHCI_HCD_OMAP |
54ab2b02 FB |
1244 | #include "ehci-omap.c" |
1245 | #define PLATFORM_DRIVER ehci_hcd_omap_driver | |
1246 | #endif | |
1247 | ||
ad75a410 GL |
1248 | #ifdef CONFIG_PPC_PS3 |
1249 | #include "ehci-ps3.c" | |
7a4eb7fd | 1250 | #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver |
ad75a410 GL |
1251 | #endif |
1252 | ||
da0e8fb0 VB |
1253 | #ifdef CONFIG_USB_EHCI_HCD_PPC_OF |
1254 | #include "ehci-ppc-of.c" | |
1255 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver | |
1256 | #endif | |
1257 | ||
08d3c18e JZ |
1258 | #ifdef CONFIG_XPS_USB_HCD_XILINX |
1259 | #include "ehci-xilinx-of.c" | |
1f23b2d9 | 1260 | #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver |
08d3c18e JZ |
1261 | #endif |
1262 | ||
705a7521 | 1263 | #ifdef CONFIG_PLAT_ORION |
e96ffe2f TP |
1264 | #include "ehci-orion.c" |
1265 | #define PLATFORM_DRIVER ehci_orion_driver | |
1266 | #endif | |
1267 | ||
91bc4d31 VB |
1268 | #ifdef CONFIG_ARCH_IXP4XX |
1269 | #include "ehci-ixp4xx.c" | |
1270 | #define PLATFORM_DRIVER ixp4xx_ehci_driver | |
1271 | #endif | |
1272 | ||
586dfc8c WZ |
1273 | #ifdef CONFIG_USB_W90X900_EHCI |
1274 | #include "ehci-w90x900.c" | |
1275 | #define PLATFORM_DRIVER ehci_hcd_w90x900_driver | |
1276 | #endif | |
1277 | ||
501c9c08 NF |
1278 | #ifdef CONFIG_ARCH_AT91 |
1279 | #include "ehci-atmel.c" | |
1280 | #define PLATFORM_DRIVER ehci_atmel_driver | |
1281 | #endif | |
1282 | ||
1643accd DD |
1283 | #ifdef CONFIG_USB_OCTEON_EHCI |
1284 | #include "ehci-octeon.c" | |
1285 | #define PLATFORM_DRIVER ehci_octeon_driver | |
1286 | #endif | |
1287 | ||
760efe69 ML |
1288 | #ifdef CONFIG_USB_CNS3XXX_EHCI |
1289 | #include "ehci-cns3xxx.c" | |
1290 | #define PLATFORM_DRIVER cns3xxx_ehci_driver | |
1291 | #endif | |
1292 | ||
ad78acaf AC |
1293 | #ifdef CONFIG_ARCH_VT8500 |
1294 | #include "ehci-vt8500.c" | |
1295 | #define PLATFORM_DRIVER vt8500_ehci_driver | |
1296 | #endif | |
1297 | ||
c8c38de9 DS |
1298 | #ifdef CONFIG_PLAT_SPEAR |
1299 | #include "ehci-spear.c" | |
1300 | #define PLATFORM_DRIVER spear_ehci_hcd_driver | |
1301 | #endif | |
1302 | ||
b0848aea PK |
1303 | #ifdef CONFIG_USB_EHCI_MSM |
1304 | #include "ehci-msm.c" | |
1305 | #define PLATFORM_DRIVER ehci_msm_driver | |
1306 | #endif | |
1307 | ||
22ced687 A |
1308 | #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP |
1309 | #include "ehci-pmcmsp.c" | |
1310 | #define PLATFORM_DRIVER ehci_hcd_msp_driver | |
1311 | #endif | |
1312 | ||
79ad3b5a BG |
1313 | #ifdef CONFIG_USB_EHCI_TEGRA |
1314 | #include "ehci-tegra.c" | |
1315 | #define PLATFORM_DRIVER tegra_ehci_driver | |
1316 | #endif | |
1317 | ||
1bcc5aa8 JS |
1318 | #ifdef CONFIG_USB_EHCI_S5P |
1319 | #include "ehci-s5p.c" | |
1320 | #define PLATFORM_DRIVER s5p_ehci_driver | |
1321 | #endif | |
1322 | ||
9be03929 JA |
1323 | #ifdef CONFIG_SPARC_LEON |
1324 | #include "ehci-grlib.c" | |
1325 | #define PLATFORM_DRIVER ehci_grlib_driver | |
1326 | #endif | |
1327 | ||
3af5154a | 1328 | #ifdef CONFIG_CPU_XLR |
23106343 J |
1329 | #include "ehci-xls.c" |
1330 | #define PLATFORM_DRIVER ehci_xls_driver | |
1331 | #endif | |
1332 | ||
3a082ec9 NZ |
1333 | #ifdef CONFIG_USB_EHCI_MV |
1334 | #include "ehci-mv.c" | |
1335 | #define PLATFORM_DRIVER ehci_mv_driver | |
1336 | #endif | |
1337 | ||
f30cdbcb KC |
1338 | #ifdef CONFIG_MACH_LOONGSON1 |
1339 | #include "ehci-ls1x.c" | |
1340 | #define PLATFORM_DRIVER ehci_ls1x_driver | |
1341 | #endif | |
1342 | ||
c256667f SH |
1343 | #ifdef CONFIG_MIPS_SEAD3 |
1344 | #include "ehci-sead3.c" | |
1345 | #define PLATFORM_DRIVER ehci_hcd_sead3_driver | |
1346 | #endif | |
1347 | ||
7a7a4a59 HM |
1348 | #ifdef CONFIG_USB_EHCI_HCD_PLATFORM |
1349 | #include "ehci-platform.c" | |
1350 | #define PLATFORM_DRIVER ehci_platform_driver | |
1351 | #endif | |
1352 | ||
ad75a410 | 1353 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ |
1f23b2d9 GL |
1354 | !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ |
1355 | !defined(XILINX_OF_PLATFORM_DRIVER) | |
7ff71d6a MP |
1356 | #error "missing bus glue for ehci-hcd" |
1357 | #endif | |
01cced25 KG |
1358 | |
1359 | static int __init ehci_hcd_init(void) | |
1360 | { | |
1361 | int retval = 0; | |
1362 | ||
2b70f073 AS |
1363 | if (usb_disabled()) |
1364 | return -ENODEV; | |
1365 | ||
1366 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); | |
9beeee65 AS |
1367 | set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
1368 | if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || | |
1369 | test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) | |
1370 | printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" | |
1371 | " before uhci_hcd and ohci_hcd, not after\n"); | |
1372 | ||
01cced25 KG |
1373 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", |
1374 | hcd_name, | |
1375 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), | |
1376 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
1377 | ||
694cc208 | 1378 | #ifdef DEBUG |
08f4e586 | 1379 | ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); |
9beeee65 AS |
1380 | if (!ehci_debug_root) { |
1381 | retval = -ENOENT; | |
1382 | goto err_debug; | |
1383 | } | |
694cc208 TJ |
1384 | #endif |
1385 | ||
01cced25 KG |
1386 | #ifdef PLATFORM_DRIVER |
1387 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
da0e8fb0 VB |
1388 | if (retval < 0) |
1389 | goto clean0; | |
01cced25 KG |
1390 | #endif |
1391 | ||
1392 | #ifdef PCI_DRIVER | |
1393 | retval = pci_register_driver(&PCI_DRIVER); | |
da0e8fb0 VB |
1394 | if (retval < 0) |
1395 | goto clean1; | |
ad75a410 GL |
1396 | #endif |
1397 | ||
1398 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
7a4eb7fd | 1399 | retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
da0e8fb0 VB |
1400 | if (retval < 0) |
1401 | goto clean2; | |
694cc208 | 1402 | #endif |
da0e8fb0 VB |
1403 | |
1404 | #ifdef OF_PLATFORM_DRIVER | |
d35fb641 | 1405 | retval = platform_driver_register(&OF_PLATFORM_DRIVER); |
da0e8fb0 VB |
1406 | if (retval < 0) |
1407 | goto clean3; | |
1408 | #endif | |
1f23b2d9 GL |
1409 | |
1410 | #ifdef XILINX_OF_PLATFORM_DRIVER | |
d35fb641 | 1411 | retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); |
1f23b2d9 GL |
1412 | if (retval < 0) |
1413 | goto clean4; | |
1414 | #endif | |
da0e8fb0 VB |
1415 | return retval; |
1416 | ||
1f23b2d9 | 1417 | #ifdef XILINX_OF_PLATFORM_DRIVER |
d35fb641 | 1418 | /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ |
1f23b2d9 GL |
1419 | clean4: |
1420 | #endif | |
da0e8fb0 | 1421 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1422 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
da0e8fb0 VB |
1423 | clean3: |
1424 | #endif | |
1425 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
1426 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
1427 | clean2: | |
ad75a410 GL |
1428 | #endif |
1429 | #ifdef PCI_DRIVER | |
da0e8fb0 VB |
1430 | pci_unregister_driver(&PCI_DRIVER); |
1431 | clean1: | |
ad75a410 | 1432 | #endif |
da0e8fb0 VB |
1433 | #ifdef PLATFORM_DRIVER |
1434 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1435 | clean0: | |
1436 | #endif | |
1437 | #ifdef DEBUG | |
1438 | debugfs_remove(ehci_debug_root); | |
1439 | ehci_debug_root = NULL; | |
9beeee65 | 1440 | err_debug: |
a9b6148d | 1441 | #endif |
9beeee65 | 1442 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1443 | return retval; |
1444 | } | |
1445 | module_init(ehci_hcd_init); | |
1446 | ||
1447 | static void __exit ehci_hcd_cleanup(void) | |
1448 | { | |
1f23b2d9 | 1449 | #ifdef XILINX_OF_PLATFORM_DRIVER |
d35fb641 | 1450 | platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); |
1f23b2d9 | 1451 | #endif |
da0e8fb0 | 1452 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1453 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
da0e8fb0 | 1454 | #endif |
01cced25 KG |
1455 | #ifdef PLATFORM_DRIVER |
1456 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1457 | #endif | |
1458 | #ifdef PCI_DRIVER | |
1459 | pci_unregister_driver(&PCI_DRIVER); | |
1460 | #endif | |
ad75a410 | 1461 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1462 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
ad75a410 | 1463 | #endif |
694cc208 TJ |
1464 | #ifdef DEBUG |
1465 | debugfs_remove(ehci_debug_root); | |
1466 | #endif | |
9beeee65 | 1467 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1468 | } |
1469 | module_exit(ehci_hcd_cleanup); | |
1470 | ||
eb70e5ab | 1471 | #endif /* CHIPIDEA_EHCI */ |