Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 LT |
2 | /* |
3 | * omap_udc.c -- for OMAP full speed udc; most chips support OTG. | |
4 | * | |
5 | * Copyright (C) 2004 Texas Instruments, Inc. | |
6 | * Copyright (C) 2004-2005 David Brownell | |
7 | * | |
527ea73e | 8 | * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com> |
1da177e4 LT |
9 | */ |
10 | ||
11 | #undef DEBUG | |
12 | #undef VERBOSE | |
13 | ||
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/types.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/delay.h> | |
1da177e4 | 20 | #include <linux/slab.h> |
1da177e4 LT |
21 | #include <linux/timer.h> |
22 | #include <linux/list.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/proc_fs.h> | |
25 | #include <linux/mm.h> | |
26 | #include <linux/moduleparam.h> | |
d052d1be | 27 | #include <linux/platform_device.h> |
5f848137 | 28 | #include <linux/usb/ch9.h> |
9454a57a | 29 | #include <linux/usb/gadget.h> |
3a16f7b4 | 30 | #include <linux/usb/otg.h> |
1da177e4 | 31 | #include <linux/dma-mapping.h> |
e6a6e472 | 32 | #include <linux/clk.h> |
ded017ee | 33 | #include <linux/err.h> |
268bb0ce | 34 | #include <linux/prefetch.h> |
80dd1358 | 35 | #include <linux/io.h> |
1da177e4 LT |
36 | |
37 | #include <asm/byteorder.h> | |
1da177e4 | 38 | #include <asm/irq.h> |
1da177e4 LT |
39 | #include <asm/unaligned.h> |
40 | #include <asm/mach-types.h> | |
41 | ||
45c3eb7d | 42 | #include <linux/omap-dma.h> |
b924b204 TL |
43 | |
44 | #include <mach/usb.h> | |
1da177e4 LT |
45 | |
46 | #include "omap_udc.h" | |
47 | ||
48 | #undef USB_TRACE | |
49 | ||
50 | /* bulk DMA seems to be behaving for both IN and OUT */ | |
51 | #define USE_DMA | |
52 | ||
53 | /* ISO too */ | |
54 | #define USE_ISO | |
55 | ||
56 | #define DRIVER_DESC "OMAP UDC driver" | |
57 | #define DRIVER_VERSION "4 October 2004" | |
58 | ||
8c4cc005 | 59 | #define OMAP_DMA_USB_W2FC_TX0 29 |
518868c8 | 60 | #define OMAP_DMA_USB_W2FC_RX0 26 |
8c4cc005 | 61 | |
1da177e4 LT |
62 | /* |
63 | * The OMAP UDC needs _very_ early endpoint setup: before enabling the | |
64 | * D+ pullup to allow enumeration. That's too early for the gadget | |
65 | * framework to use from usb_endpoint_enable(), which happens after | |
66 | * enumeration as part of activating an interface. (But if we add an | |
67 | * optional new "UDC not yet running" state to the gadget driver model, | |
68 | * even just during driver binding, the endpoint autoconfig logic is the | |
69 | * natural spot to manufacture new endpoints.) | |
70 | * | |
71 | * So instead of using endpoint enable calls to control the hardware setup, | |
72 | * this driver defines a "fifo mode" parameter. It's used during driver | |
73 | * initialization to choose among a set of pre-defined endpoint configs. | |
74 | * See omap_udc_setup() for available modes, or to add others. That code | |
75 | * lives in an init section, so use this driver as a module if you need | |
76 | * to change the fifo mode after the kernel boots. | |
77 | * | |
78 | * Gadget drivers normally ignore endpoints they don't care about, and | |
79 | * won't include them in configuration descriptors. That means only | |
80 | * misbehaving hosts would even notice they exist. | |
81 | */ | |
82 | #ifdef USE_ISO | |
83 | static unsigned fifo_mode = 3; | |
84 | #else | |
80dd1358 | 85 | static unsigned fifo_mode; |
1da177e4 LT |
86 | #endif |
87 | ||
88 | /* "modprobe omap_udc fifo_mode=42", or else as a kernel | |
89 | * boot parameter "omap_udc:fifo_mode=42" | |
90 | */ | |
80dd1358 FB |
91 | module_param(fifo_mode, uint, 0); |
92 | MODULE_PARM_DESC(fifo_mode, "endpoint configuration"); | |
1da177e4 LT |
93 | |
94 | #ifdef USE_DMA | |
90ab5ee9 | 95 | static bool use_dma = 1; |
1da177e4 LT |
96 | |
97 | /* "modprobe omap_udc use_dma=y", or else as a kernel | |
98 | * boot parameter "omap_udc:use_dma=y" | |
99 | */ | |
80dd1358 FB |
100 | module_param(use_dma, bool, 0); |
101 | MODULE_PARM_DESC(use_dma, "enable/disable DMA"); | |
1da177e4 LT |
102 | #else /* !USE_DMA */ |
103 | ||
104 | /* save a bit of code */ | |
105 | #define use_dma 0 | |
106 | #endif /* !USE_DMA */ | |
107 | ||
108 | ||
80dd1358 FB |
109 | static const char driver_name[] = "omap_udc"; |
110 | static const char driver_desc[] = DRIVER_DESC; | |
1da177e4 LT |
111 | |
112 | /*-------------------------------------------------------------------------*/ | |
113 | ||
114 | /* there's a notion of "current endpoint" for modifying endpoint | |
e6a6e472 | 115 | * state, and PIO access to its FIFO. |
1da177e4 LT |
116 | */ |
117 | ||
118 | static void use_ep(struct omap_ep *ep, u16 select) | |
119 | { | |
120 | u16 num = ep->bEndpointAddress & 0x0f; | |
121 | ||
122 | if (ep->bEndpointAddress & USB_DIR_IN) | |
123 | num |= UDC_EP_DIR; | |
f35ae634 | 124 | omap_writew(num | select, UDC_EP_NUM); |
1da177e4 LT |
125 | /* when select, MUST deselect later !! */ |
126 | } | |
127 | ||
128 | static inline void deselect_ep(void) | |
129 | { | |
f35ae634 TL |
130 | u16 w; |
131 | ||
132 | w = omap_readw(UDC_EP_NUM); | |
133 | w &= ~UDC_EP_SEL; | |
134 | omap_writew(w, UDC_EP_NUM); | |
1da177e4 LT |
135 | /* 6 wait states before TX will happen */ |
136 | } | |
137 | ||
138 | static void dma_channel_claim(struct omap_ep *ep, unsigned preferred); | |
139 | ||
140 | /*-------------------------------------------------------------------------*/ | |
141 | ||
142 | static int omap_ep_enable(struct usb_ep *_ep, | |
143 | const struct usb_endpoint_descriptor *desc) | |
144 | { | |
145 | struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); | |
146 | struct omap_udc *udc; | |
147 | unsigned long flags; | |
148 | u16 maxp; | |
149 | ||
150 | /* catch various bogus parameters */ | |
77964b3c | 151 | if (!_ep || !desc |
1da177e4 LT |
152 | || desc->bDescriptorType != USB_DT_ENDPOINT |
153 | || ep->bEndpointAddress != desc->bEndpointAddress | |
29cc8897 | 154 | || ep->maxpacket < usb_endpoint_maxp(desc)) { |
441b62c1 | 155 | DBG("%s, bad ep or descriptor\n", __func__); |
1da177e4 LT |
156 | return -EINVAL; |
157 | } | |
29cc8897 | 158 | maxp = usb_endpoint_maxp(desc); |
1da177e4 LT |
159 | if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK |
160 | && maxp != ep->maxpacket) | |
29cc8897 | 161 | || usb_endpoint_maxp(desc) > ep->maxpacket |
1da177e4 | 162 | || !desc->wMaxPacketSize) { |
441b62c1 | 163 | DBG("%s, bad %s maxpacket\n", __func__, _ep->name); |
1da177e4 LT |
164 | return -ERANGE; |
165 | } | |
166 | ||
167 | #ifdef USE_ISO | |
168 | if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC | |
169 | && desc->bInterval != 1)) { | |
170 | /* hardware wants period = 1; USB allows 2^(Interval-1) */ | |
171 | DBG("%s, unsupported ISO period %dms\n", _ep->name, | |
172 | 1 << (desc->bInterval - 1)); | |
173 | return -EDOM; | |
174 | } | |
175 | #else | |
176 | if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
177 | DBG("%s, ISO nyet\n", _ep->name); | |
178 | return -EDOM; | |
179 | } | |
180 | #endif | |
181 | ||
182 | /* xfer types must match, except that interrupt ~= bulk */ | |
183 | if (ep->bmAttributes != desc->bmAttributes | |
184 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK | |
185 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { | |
441b62c1 | 186 | DBG("%s, %s type mismatch\n", __func__, _ep->name); |
1da177e4 LT |
187 | return -EINVAL; |
188 | } | |
189 | ||
190 | udc = ep->udc; | |
191 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { | |
441b62c1 | 192 | DBG("%s, bogus device state\n", __func__); |
1da177e4 LT |
193 | return -ESHUTDOWN; |
194 | } | |
195 | ||
196 | spin_lock_irqsave(&udc->lock, flags); | |
197 | ||
f8bdae06 | 198 | ep->ep.desc = desc; |
1da177e4 LT |
199 | ep->irqs = 0; |
200 | ep->stopped = 0; | |
201 | ep->ep.maxpacket = maxp; | |
202 | ||
203 | /* set endpoint to initial state */ | |
204 | ep->dma_channel = 0; | |
205 | ep->has_dma = 0; | |
206 | ep->lch = -1; | |
207 | use_ep(ep, UDC_EP_SEL); | |
f35ae634 | 208 | omap_writew(udc->clr_halt, UDC_CTRL); |
1da177e4 LT |
209 | ep->ackwait = 0; |
210 | deselect_ep(); | |
211 | ||
212 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) | |
213 | list_add(&ep->iso, &udc->iso); | |
214 | ||
215 | /* maybe assign a DMA channel to this endpoint */ | |
216 | if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK) | |
217 | /* FIXME ISO can dma, but prefers first channel */ | |
218 | dma_channel_claim(ep, 0); | |
219 | ||
220 | /* PIO OUT may RX packets */ | |
221 | if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC | |
222 | && !ep->has_dma | |
223 | && !(ep->bEndpointAddress & USB_DIR_IN)) { | |
f35ae634 | 224 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
225 | ep->ackwait = 1 + ep->double_buf; |
226 | } | |
227 | ||
228 | spin_unlock_irqrestore(&udc->lock, flags); | |
229 | VDBG("%s enabled\n", _ep->name); | |
230 | return 0; | |
231 | } | |
232 | ||
233 | static void nuke(struct omap_ep *, int status); | |
234 | ||
235 | static int omap_ep_disable(struct usb_ep *_ep) | |
236 | { | |
237 | struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); | |
238 | unsigned long flags; | |
239 | ||
f8bdae06 | 240 | if (!_ep || !ep->ep.desc) { |
441b62c1 | 241 | DBG("%s, %s not enabled\n", __func__, |
1da177e4 LT |
242 | _ep ? ep->ep.name : NULL); |
243 | return -EINVAL; | |
244 | } | |
245 | ||
246 | spin_lock_irqsave(&ep->udc->lock, flags); | |
f9c56cdd | 247 | ep->ep.desc = NULL; |
80dd1358 | 248 | nuke(ep, -ESHUTDOWN); |
1da177e4 LT |
249 | ep->ep.maxpacket = ep->maxpacket; |
250 | ep->has_dma = 0; | |
f35ae634 | 251 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1da177e4 LT |
252 | list_del_init(&ep->iso); |
253 | del_timer(&ep->timer); | |
254 | ||
255 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
256 | ||
257 | VDBG("%s disabled\n", _ep->name); | |
258 | return 0; | |
259 | } | |
260 | ||
261 | /*-------------------------------------------------------------------------*/ | |
262 | ||
263 | static struct usb_request * | |
55016f10 | 264 | omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) |
1da177e4 LT |
265 | { |
266 | struct omap_req *req; | |
267 | ||
7039f422 | 268 | req = kzalloc(sizeof(*req), gfp_flags); |
70617db7 FB |
269 | if (!req) |
270 | return NULL; | |
271 | ||
70617db7 FB |
272 | INIT_LIST_HEAD(&req->queue); |
273 | ||
1da177e4 LT |
274 | return &req->req; |
275 | } | |
276 | ||
277 | static void | |
278 | omap_free_request(struct usb_ep *ep, struct usb_request *_req) | |
279 | { | |
280 | struct omap_req *req = container_of(_req, struct omap_req, req); | |
281 | ||
23673d7d | 282 | kfree(req); |
1da177e4 LT |
283 | } |
284 | ||
285 | /*-------------------------------------------------------------------------*/ | |
286 | ||
1da177e4 LT |
287 | static void |
288 | done(struct omap_ep *ep, struct omap_req *req, int status) | |
289 | { | |
dd8e9381 | 290 | struct omap_udc *udc = ep->udc; |
1da177e4 LT |
291 | unsigned stopped = ep->stopped; |
292 | ||
293 | list_del_init(&req->queue); | |
294 | ||
295 | if (req->req.status == -EINPROGRESS) | |
296 | req->req.status = status; | |
297 | else | |
298 | status = req->req.status; | |
299 | ||
dd8e9381 FB |
300 | if (use_dma && ep->has_dma) |
301 | usb_gadget_unmap_request(&udc->gadget, &req->req, | |
302 | (ep->bEndpointAddress & USB_DIR_IN)); | |
1da177e4 LT |
303 | |
304 | #ifndef USB_TRACE | |
305 | if (status && status != -ESHUTDOWN) | |
306 | #endif | |
307 | VDBG("complete %s req %p stat %d len %u/%u\n", | |
308 | ep->ep.name, &req->req, status, | |
309 | req->req.actual, req->req.length); | |
310 | ||
311 | /* don't modify queue heads during completion callback */ | |
312 | ep->stopped = 1; | |
313 | spin_unlock(&ep->udc->lock); | |
304f7e5e | 314 | usb_gadget_giveback_request(&ep->ep, &req->req); |
1da177e4 LT |
315 | spin_lock(&ep->udc->lock); |
316 | ep->stopped = stopped; | |
317 | } | |
318 | ||
319 | /*-------------------------------------------------------------------------*/ | |
320 | ||
313980c9 DB |
321 | #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL) |
322 | #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL) | |
1da177e4 LT |
323 | |
324 | #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY) | |
325 | #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY) | |
326 | ||
e6a6e472 | 327 | static inline int |
1da177e4 LT |
328 | write_packet(u8 *buf, struct omap_req *req, unsigned max) |
329 | { | |
330 | unsigned len; | |
331 | u16 *wp; | |
332 | ||
333 | len = min(req->req.length - req->req.actual, max); | |
334 | req->req.actual += len; | |
335 | ||
336 | max = len; | |
337 | if (likely((((int)buf) & 1) == 0)) { | |
338 | wp = (u16 *)buf; | |
339 | while (max >= 2) { | |
f35ae634 | 340 | omap_writew(*wp++, UDC_DATA); |
1da177e4 LT |
341 | max -= 2; |
342 | } | |
343 | buf = (u8 *)wp; | |
344 | } | |
345 | while (max--) | |
f35ae634 | 346 | omap_writeb(*buf++, UDC_DATA); |
1da177e4 LT |
347 | return len; |
348 | } | |
349 | ||
80dd1358 | 350 | /* FIXME change r/w fifo calling convention */ |
1da177e4 LT |
351 | |
352 | ||
80dd1358 | 353 | /* return: 0 = still running, 1 = completed, negative = errno */ |
1da177e4 LT |
354 | static int write_fifo(struct omap_ep *ep, struct omap_req *req) |
355 | { | |
356 | u8 *buf; | |
357 | unsigned count; | |
358 | int is_last; | |
359 | u16 ep_stat; | |
360 | ||
361 | buf = req->req.buf + req->req.actual; | |
362 | prefetch(buf); | |
363 | ||
364 | /* PIO-IN isn't double buffered except for iso */ | |
f35ae634 | 365 | ep_stat = omap_readw(UDC_STAT_FLG); |
313980c9 | 366 | if (ep_stat & UDC_FIFO_UNWRITABLE) |
1da177e4 LT |
367 | return 0; |
368 | ||
369 | count = ep->ep.maxpacket; | |
370 | count = write_packet(buf, req, count); | |
f35ae634 | 371 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
372 | ep->ackwait = 1; |
373 | ||
374 | /* last packet is often short (sometimes a zlp) */ | |
375 | if (count != ep->ep.maxpacket) | |
376 | is_last = 1; | |
377 | else if (req->req.length == req->req.actual | |
378 | && !req->req.zero) | |
379 | is_last = 1; | |
380 | else | |
381 | is_last = 0; | |
382 | ||
383 | /* NOTE: requests complete when all IN data is in a | |
384 | * FIFO (or sometimes later, if a zlp was needed). | |
385 | * Use usb_ep_fifo_status() where needed. | |
386 | */ | |
387 | if (is_last) | |
388 | done(ep, req, 0); | |
389 | return is_last; | |
390 | } | |
391 | ||
e6a6e472 | 392 | static inline int |
1da177e4 LT |
393 | read_packet(u8 *buf, struct omap_req *req, unsigned avail) |
394 | { | |
395 | unsigned len; | |
396 | u16 *wp; | |
397 | ||
398 | len = min(req->req.length - req->req.actual, avail); | |
399 | req->req.actual += len; | |
400 | avail = len; | |
401 | ||
402 | if (likely((((int)buf) & 1) == 0)) { | |
403 | wp = (u16 *)buf; | |
404 | while (avail >= 2) { | |
f35ae634 | 405 | *wp++ = omap_readw(UDC_DATA); |
1da177e4 LT |
406 | avail -= 2; |
407 | } | |
408 | buf = (u8 *)wp; | |
409 | } | |
410 | while (avail--) | |
f35ae634 | 411 | *buf++ = omap_readb(UDC_DATA); |
1da177e4 LT |
412 | return len; |
413 | } | |
414 | ||
80dd1358 | 415 | /* return: 0 = still running, 1 = queue empty, negative = errno */ |
1da177e4 LT |
416 | static int read_fifo(struct omap_ep *ep, struct omap_req *req) |
417 | { | |
418 | u8 *buf; | |
419 | unsigned count, avail; | |
420 | int is_last; | |
421 | ||
422 | buf = req->req.buf + req->req.actual; | |
423 | prefetchw(buf); | |
424 | ||
425 | for (;;) { | |
f35ae634 | 426 | u16 ep_stat = omap_readw(UDC_STAT_FLG); |
1da177e4 LT |
427 | |
428 | is_last = 0; | |
429 | if (ep_stat & FIFO_EMPTY) { | |
430 | if (!ep->double_buf) | |
431 | break; | |
432 | ep->fnf = 1; | |
433 | } | |
434 | if (ep_stat & UDC_EP_HALTED) | |
435 | break; | |
436 | ||
313980c9 | 437 | if (ep_stat & UDC_FIFO_FULL) |
1da177e4 LT |
438 | avail = ep->ep.maxpacket; |
439 | else { | |
f35ae634 | 440 | avail = omap_readw(UDC_RXFSTAT); |
1da177e4 LT |
441 | ep->fnf = ep->double_buf; |
442 | } | |
443 | count = read_packet(buf, req, avail); | |
444 | ||
445 | /* partial packet reads may not be errors */ | |
446 | if (count < ep->ep.maxpacket) { | |
447 | is_last = 1; | |
448 | /* overflowed this request? flush extra data */ | |
449 | if (count != avail) { | |
450 | req->req.status = -EOVERFLOW; | |
451 | avail -= count; | |
452 | while (avail--) | |
f35ae634 | 453 | omap_readw(UDC_DATA); |
1da177e4 LT |
454 | } |
455 | } else if (req->req.length == req->req.actual) | |
456 | is_last = 1; | |
457 | else | |
458 | is_last = 0; | |
459 | ||
460 | if (!ep->bEndpointAddress) | |
461 | break; | |
462 | if (is_last) | |
463 | done(ep, req, 0); | |
464 | break; | |
465 | } | |
466 | return is_last; | |
467 | } | |
468 | ||
469 | /*-------------------------------------------------------------------------*/ | |
470 | ||
471 | static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) | |
472 | { | |
473 | dma_addr_t end; | |
474 | ||
475 | /* IN-DMA needs this on fault/cancel paths, so 15xx misreports | |
476 | * the last transfer's bytecount by more than a FIFO's worth. | |
477 | */ | |
478 | if (cpu_is_omap15xx()) | |
479 | return 0; | |
480 | ||
0499bdeb | 481 | end = omap_get_dma_src_pos(ep->lch); |
1da177e4 LT |
482 | if (end == ep->dma_counter) |
483 | return 0; | |
484 | ||
485 | end |= start & (0xffff << 16); | |
486 | if (end < start) | |
487 | end += 0x10000; | |
488 | return end - start; | |
489 | } | |
490 | ||
1da177e4 LT |
491 | static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) |
492 | { | |
493 | dma_addr_t end; | |
494 | ||
0499bdeb | 495 | end = omap_get_dma_dst_pos(ep->lch); |
1da177e4 LT |
496 | if (end == ep->dma_counter) |
497 | return 0; | |
498 | ||
499 | end |= start & (0xffff << 16); | |
500 | if (cpu_is_omap15xx()) | |
501 | end++; | |
502 | if (end < start) | |
503 | end += 0x10000; | |
504 | return end - start; | |
505 | } | |
506 | ||
507 | ||
508 | /* Each USB transfer request using DMA maps to one or more DMA transfers. | |
509 | * When DMA completion isn't request completion, the UDC continues with | |
510 | * the next DMA transfer for that USB transfer. | |
511 | */ | |
512 | ||
513 | static void next_in_dma(struct omap_ep *ep, struct omap_req *req) | |
514 | { | |
f35ae634 | 515 | u16 txdma_ctrl, w; |
1da177e4 LT |
516 | unsigned length = req->req.length - req->req.actual; |
517 | const int sync_mode = cpu_is_omap15xx() | |
518 | ? OMAP_DMA_SYNC_FRAME | |
519 | : OMAP_DMA_SYNC_ELEMENT; | |
527ea73e KP |
520 | int dma_trigger = 0; |
521 | ||
1da177e4 | 522 | /* measure length in either bytes or packets */ |
65111084 | 523 | if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC) |
1da177e4 LT |
524 | || (cpu_is_omap15xx() && length < ep->maxpacket)) { |
525 | txdma_ctrl = UDC_TXN_EOT | length; | |
526 | omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8, | |
527ea73e | 527 | length, 1, sync_mode, dma_trigger, 0); |
1da177e4 LT |
528 | } else { |
529 | length = min(length / ep->maxpacket, | |
530 | (unsigned) UDC_TXN_TSC + 1); | |
e6a6e472 | 531 | txdma_ctrl = length; |
65111084 | 532 | omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16, |
e6a6e472 | 533 | ep->ep.maxpacket >> 1, length, sync_mode, |
527ea73e | 534 | dma_trigger, 0); |
1da177e4 LT |
535 | length *= ep->maxpacket; |
536 | } | |
537 | omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF, | |
e6a6e472 DB |
538 | OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, |
539 | 0, 0); | |
1da177e4 LT |
540 | |
541 | omap_start_dma(ep->lch); | |
0499bdeb | 542 | ep->dma_counter = omap_get_dma_src_pos(ep->lch); |
f35ae634 TL |
543 | w = omap_readw(UDC_DMA_IRQ_EN); |
544 | w |= UDC_TX_DONE_IE(ep->dma_channel); | |
545 | omap_writew(w, UDC_DMA_IRQ_EN); | |
546 | omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel)); | |
1da177e4 LT |
547 | req->dma_bytes = length; |
548 | } | |
549 | ||
550 | static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) | |
551 | { | |
f35ae634 TL |
552 | u16 w; |
553 | ||
1da177e4 LT |
554 | if (status == 0) { |
555 | req->req.actual += req->dma_bytes; | |
556 | ||
557 | /* return if this request needs to send data or zlp */ | |
558 | if (req->req.actual < req->req.length) | |
559 | return; | |
560 | if (req->req.zero | |
561 | && req->dma_bytes != 0 | |
562 | && (req->req.actual % ep->maxpacket) == 0) | |
563 | return; | |
564 | } else | |
565 | req->req.actual += dma_src_len(ep, req->req.dma | |
566 | + req->req.actual); | |
567 | ||
568 | /* tx completion */ | |
569 | omap_stop_dma(ep->lch); | |
f35ae634 TL |
570 | w = omap_readw(UDC_DMA_IRQ_EN); |
571 | w &= ~UDC_TX_DONE_IE(ep->dma_channel); | |
572 | omap_writew(w, UDC_DMA_IRQ_EN); | |
1da177e4 LT |
573 | done(ep, req, status); |
574 | } | |
575 | ||
576 | static void next_out_dma(struct omap_ep *ep, struct omap_req *req) | |
577 | { | |
527ea73e KP |
578 | unsigned packets = req->req.length - req->req.actual; |
579 | int dma_trigger = 0; | |
f35ae634 | 580 | u16 w; |
527ea73e | 581 | |
ae372571 TL |
582 | /* set up this DMA transfer, enable the fifo, start */ |
583 | packets /= ep->ep.maxpacket; | |
584 | packets = min(packets, (unsigned)UDC_RXN_TC + 1); | |
585 | req->dma_bytes = packets * ep->ep.maxpacket; | |
586 | omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16, | |
587 | ep->ep.maxpacket >> 1, packets, | |
588 | OMAP_DMA_SYNC_ELEMENT, | |
589 | dma_trigger, 0); | |
1da177e4 | 590 | omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF, |
e6a6e472 DB |
591 | OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, |
592 | 0, 0); | |
0499bdeb | 593 | ep->dma_counter = omap_get_dma_dst_pos(ep->lch); |
1da177e4 | 594 | |
f35ae634 TL |
595 | omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel)); |
596 | w = omap_readw(UDC_DMA_IRQ_EN); | |
597 | w |= UDC_RX_EOT_IE(ep->dma_channel); | |
598 | omap_writew(w, UDC_DMA_IRQ_EN); | |
599 | omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM); | |
600 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1da177e4 LT |
601 | |
602 | omap_start_dma(ep->lch); | |
603 | } | |
604 | ||
605 | static void | |
cb97c5c9 | 606 | finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) |
1da177e4 | 607 | { |
f35ae634 | 608 | u16 count, w; |
1da177e4 LT |
609 | |
610 | if (status == 0) | |
611 | ep->dma_counter = (u16) (req->req.dma + req->req.actual); | |
612 | count = dma_dest_len(ep, req->req.dma + req->req.actual); | |
613 | count += req->req.actual; | |
cb97c5c9 DB |
614 | if (one) |
615 | count--; | |
1da177e4 LT |
616 | if (count <= req->req.length) |
617 | req->req.actual = count; | |
618 | ||
619 | if (count != req->dma_bytes || status) | |
620 | omap_stop_dma(ep->lch); | |
621 | ||
622 | /* if this wasn't short, request may need another transfer */ | |
623 | else if (req->req.actual < req->req.length) | |
624 | return; | |
625 | ||
626 | /* rx completion */ | |
f35ae634 TL |
627 | w = omap_readw(UDC_DMA_IRQ_EN); |
628 | w &= ~UDC_RX_EOT_IE(ep->dma_channel); | |
629 | omap_writew(w, UDC_DMA_IRQ_EN); | |
1da177e4 LT |
630 | done(ep, req, status); |
631 | } | |
632 | ||
633 | static void dma_irq(struct omap_udc *udc, u16 irq_src) | |
634 | { | |
f35ae634 | 635 | u16 dman_stat = omap_readw(UDC_DMAN_STAT); |
1da177e4 LT |
636 | struct omap_ep *ep; |
637 | struct omap_req *req; | |
638 | ||
639 | /* IN dma: tx to host */ | |
640 | if (irq_src & UDC_TXN_DONE) { | |
641 | ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)]; | |
642 | ep->irqs++; | |
643 | /* can see TXN_DONE after dma abort */ | |
644 | if (!list_empty(&ep->queue)) { | |
645 | req = container_of(ep->queue.next, | |
646 | struct omap_req, queue); | |
647 | finish_in_dma(ep, req, 0); | |
648 | } | |
f35ae634 | 649 | omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC); |
1da177e4 | 650 | |
80dd1358 | 651 | if (!list_empty(&ep->queue)) { |
1da177e4 LT |
652 | req = container_of(ep->queue.next, |
653 | struct omap_req, queue); | |
654 | next_in_dma(ep, req); | |
655 | } | |
656 | } | |
657 | ||
658 | /* OUT dma: rx from host */ | |
659 | if (irq_src & UDC_RXN_EOT) { | |
660 | ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)]; | |
661 | ep->irqs++; | |
662 | /* can see RXN_EOT after dma abort */ | |
663 | if (!list_empty(&ep->queue)) { | |
664 | req = container_of(ep->queue.next, | |
665 | struct omap_req, queue); | |
cb97c5c9 | 666 | finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); |
1da177e4 | 667 | } |
f35ae634 | 668 | omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC); |
1da177e4 | 669 | |
80dd1358 | 670 | if (!list_empty(&ep->queue)) { |
1da177e4 LT |
671 | req = container_of(ep->queue.next, |
672 | struct omap_req, queue); | |
673 | next_out_dma(ep, req); | |
674 | } | |
675 | } | |
676 | ||
677 | if (irq_src & UDC_RXN_CNT) { | |
678 | ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)]; | |
679 | ep->irqs++; | |
680 | /* omap15xx does this unasked... */ | |
681 | VDBG("%s, RX_CNT irq?\n", ep->ep.name); | |
f35ae634 | 682 | omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC); |
1da177e4 LT |
683 | } |
684 | } | |
685 | ||
686 | static void dma_error(int lch, u16 ch_status, void *data) | |
687 | { | |
688 | struct omap_ep *ep = data; | |
689 | ||
690 | /* if ch_status & OMAP_DMA_DROP_IRQ ... */ | |
7ff879db | 691 | /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */ |
1da177e4 LT |
692 | ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status); |
693 | ||
694 | /* complete current transfer ... */ | |
695 | } | |
696 | ||
697 | static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |
698 | { | |
699 | u16 reg; | |
700 | int status, restart, is_in; | |
527ea73e | 701 | int dma_channel; |
1da177e4 LT |
702 | |
703 | is_in = ep->bEndpointAddress & USB_DIR_IN; | |
704 | if (is_in) | |
f35ae634 | 705 | reg = omap_readw(UDC_TXDMA_CFG); |
1da177e4 | 706 | else |
f35ae634 | 707 | reg = omap_readw(UDC_RXDMA_CFG); |
65111084 | 708 | reg |= UDC_DMA_REQ; /* "pulse" activated */ |
1da177e4 LT |
709 | |
710 | ep->dma_channel = 0; | |
711 | ep->lch = -1; | |
712 | if (channel == 0 || channel > 3) { | |
713 | if ((reg & 0x0f00) == 0) | |
714 | channel = 3; | |
715 | else if ((reg & 0x00f0) == 0) | |
716 | channel = 2; | |
717 | else if ((reg & 0x000f) == 0) /* preferred for ISO */ | |
718 | channel = 1; | |
719 | else { | |
720 | status = -EMLINK; | |
721 | goto just_restart; | |
722 | } | |
723 | } | |
724 | reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1)); | |
725 | ep->dma_channel = channel; | |
726 | ||
727 | if (is_in) { | |
ae372571 | 728 | dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel; |
527ea73e | 729 | status = omap_request_dma(dma_channel, |
1da177e4 LT |
730 | ep->ep.name, dma_error, ep, &ep->lch); |
731 | if (status == 0) { | |
f35ae634 | 732 | omap_writew(reg, UDC_TXDMA_CFG); |
527ea73e | 733 | /* EMIFF or SDRC */ |
65111084 DB |
734 | omap_set_dma_src_burst_mode(ep->lch, |
735 | OMAP_DMA_DATA_BURST_4); | |
736 | omap_set_dma_src_data_pack(ep->lch, 1); | |
737 | /* TIPB */ | |
1da177e4 LT |
738 | omap_set_dma_dest_params(ep->lch, |
739 | OMAP_DMA_PORT_TIPB, | |
740 | OMAP_DMA_AMODE_CONSTANT, | |
c3e3208e | 741 | UDC_DATA_DMA, |
e6a6e472 | 742 | 0, 0); |
1da177e4 LT |
743 | } |
744 | } else { | |
ae372571 | 745 | dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel; |
527ea73e | 746 | status = omap_request_dma(dma_channel, |
1da177e4 LT |
747 | ep->ep.name, dma_error, ep, &ep->lch); |
748 | if (status == 0) { | |
f35ae634 | 749 | omap_writew(reg, UDC_RXDMA_CFG); |
65111084 | 750 | /* TIPB */ |
1da177e4 LT |
751 | omap_set_dma_src_params(ep->lch, |
752 | OMAP_DMA_PORT_TIPB, | |
753 | OMAP_DMA_AMODE_CONSTANT, | |
c3e3208e | 754 | UDC_DATA_DMA, |
e6a6e472 | 755 | 0, 0); |
527ea73e | 756 | /* EMIFF or SDRC */ |
65111084 DB |
757 | omap_set_dma_dest_burst_mode(ep->lch, |
758 | OMAP_DMA_DATA_BURST_4); | |
759 | omap_set_dma_dest_data_pack(ep->lch, 1); | |
1da177e4 LT |
760 | } |
761 | } | |
762 | if (status) | |
763 | ep->dma_channel = 0; | |
764 | else { | |
765 | ep->has_dma = 1; | |
766 | omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ); | |
767 | ||
768 | /* channel type P: hw synch (fifo) */ | |
ae372571 | 769 | if (!cpu_is_omap15xx()) |
0499bdeb | 770 | omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P); |
1da177e4 LT |
771 | } |
772 | ||
773 | just_restart: | |
774 | /* restart any queue, even if the claim failed */ | |
775 | restart = !ep->stopped && !list_empty(&ep->queue); | |
776 | ||
777 | if (status) | |
778 | DBG("%s no dma channel: %d%s\n", ep->ep.name, status, | |
779 | restart ? " (restart)" : ""); | |
780 | else | |
781 | DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name, | |
782 | is_in ? 't' : 'r', | |
783 | ep->dma_channel - 1, ep->lch, | |
784 | restart ? " (restart)" : ""); | |
785 | ||
786 | if (restart) { | |
787 | struct omap_req *req; | |
788 | req = container_of(ep->queue.next, struct omap_req, queue); | |
789 | if (ep->has_dma) | |
790 | (is_in ? next_in_dma : next_out_dma)(ep, req); | |
791 | else { | |
792 | use_ep(ep, UDC_EP_SEL); | |
793 | (is_in ? write_fifo : read_fifo)(ep, req); | |
794 | deselect_ep(); | |
795 | if (!is_in) { | |
f35ae634 | 796 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
797 | ep->ackwait = 1 + ep->double_buf; |
798 | } | |
799 | /* IN: 6 wait states before it'll tx */ | |
800 | } | |
801 | } | |
802 | } | |
803 | ||
804 | static void dma_channel_release(struct omap_ep *ep) | |
805 | { | |
806 | int shift = 4 * (ep->dma_channel - 1); | |
807 | u16 mask = 0x0f << shift; | |
808 | struct omap_req *req; | |
809 | int active; | |
810 | ||
811 | /* abort any active usb transfer request */ | |
812 | if (!list_empty(&ep->queue)) | |
813 | req = container_of(ep->queue.next, struct omap_req, queue); | |
814 | else | |
313980c9 | 815 | req = NULL; |
1da177e4 | 816 | |
0499bdeb | 817 | active = omap_get_dma_active_status(ep->lch); |
1da177e4 LT |
818 | |
819 | DBG("%s release %s %cxdma%d %p\n", ep->ep.name, | |
820 | active ? "active" : "idle", | |
821 | (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', | |
822 | ep->dma_channel - 1, req); | |
823 | ||
65111084 DB |
824 | /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before |
825 | * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them. | |
826 | */ | |
827 | ||
1da177e4 LT |
828 | /* wait till current packet DMA finishes, and fifo empties */ |
829 | if (ep->bEndpointAddress & USB_DIR_IN) { | |
f35ae634 TL |
830 | omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ, |
831 | UDC_TXDMA_CFG); | |
1da177e4 LT |
832 | |
833 | if (req) { | |
834 | finish_in_dma(ep, req, -ECONNRESET); | |
835 | ||
836 | /* clear FIFO; hosts probably won't empty it */ | |
837 | use_ep(ep, UDC_EP_SEL); | |
f35ae634 | 838 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1da177e4 LT |
839 | deselect_ep(); |
840 | } | |
f35ae634 | 841 | while (omap_readw(UDC_TXDMA_CFG) & mask) |
1da177e4 LT |
842 | udelay(10); |
843 | } else { | |
f35ae634 TL |
844 | omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ, |
845 | UDC_RXDMA_CFG); | |
1da177e4 LT |
846 | |
847 | /* dma empties the fifo */ | |
f35ae634 | 848 | while (omap_readw(UDC_RXDMA_CFG) & mask) |
1da177e4 LT |
849 | udelay(10); |
850 | if (req) | |
cb97c5c9 | 851 | finish_out_dma(ep, req, -ECONNRESET, 0); |
1da177e4 LT |
852 | } |
853 | omap_free_dma(ep->lch); | |
854 | ep->dma_channel = 0; | |
855 | ep->lch = -1; | |
856 | /* has_dma still set, till endpoint is fully quiesced */ | |
857 | } | |
858 | ||
859 | ||
860 | /*-------------------------------------------------------------------------*/ | |
861 | ||
862 | static int | |
55016f10 | 863 | omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) |
1da177e4 LT |
864 | { |
865 | struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); | |
866 | struct omap_req *req = container_of(_req, struct omap_req, req); | |
867 | struct omap_udc *udc; | |
868 | unsigned long flags; | |
869 | int is_iso = 0; | |
870 | ||
871 | /* catch various bogus parameters */ | |
872 | if (!_req || !req->req.complete || !req->req.buf | |
873 | || !list_empty(&req->queue)) { | |
441b62c1 | 874 | DBG("%s, bad params\n", __func__); |
1da177e4 LT |
875 | return -EINVAL; |
876 | } | |
f8bdae06 | 877 | if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) { |
441b62c1 | 878 | DBG("%s, bad ep\n", __func__); |
1da177e4 LT |
879 | return -EINVAL; |
880 | } | |
881 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
882 | if (req->req.length > ep->ep.maxpacket) | |
883 | return -EMSGSIZE; | |
884 | is_iso = 1; | |
885 | } | |
886 | ||
887 | /* this isn't bogus, but OMAP DMA isn't the only hardware to | |
888 | * have a hard time with partial packet reads... reject it. | |
889 | */ | |
890 | if (use_dma | |
891 | && ep->has_dma | |
892 | && ep->bEndpointAddress != 0 | |
893 | && (ep->bEndpointAddress & USB_DIR_IN) == 0 | |
894 | && (req->req.length % ep->ep.maxpacket) != 0) { | |
441b62c1 | 895 | DBG("%s, no partial packet OUT reads\n", __func__); |
1da177e4 LT |
896 | return -EMSGSIZE; |
897 | } | |
898 | ||
899 | udc = ep->udc; | |
900 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) | |
901 | return -ESHUTDOWN; | |
902 | ||
dd8e9381 FB |
903 | if (use_dma && ep->has_dma) |
904 | usb_gadget_map_request(&udc->gadget, &req->req, | |
905 | (ep->bEndpointAddress & USB_DIR_IN)); | |
1da177e4 LT |
906 | |
907 | VDBG("%s queue req %p, len %d buf %p\n", | |
908 | ep->ep.name, _req, _req->length, _req->buf); | |
909 | ||
910 | spin_lock_irqsave(&udc->lock, flags); | |
911 | ||
912 | req->req.status = -EINPROGRESS; | |
913 | req->req.actual = 0; | |
914 | ||
915 | /* maybe kickstart non-iso i/o queues */ | |
f35ae634 TL |
916 | if (is_iso) { |
917 | u16 w; | |
918 | ||
919 | w = omap_readw(UDC_IRQ_EN); | |
920 | w |= UDC_SOF_IE; | |
921 | omap_writew(w, UDC_IRQ_EN); | |
922 | } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { | |
1da177e4 LT |
923 | int is_in; |
924 | ||
925 | if (ep->bEndpointAddress == 0) { | |
80dd1358 | 926 | if (!udc->ep0_pending || !list_empty(&ep->queue)) { |
1da177e4 LT |
927 | spin_unlock_irqrestore(&udc->lock, flags); |
928 | return -EL2HLT; | |
929 | } | |
930 | ||
931 | /* empty DATA stage? */ | |
932 | is_in = udc->ep0_in; | |
933 | if (!req->req.length) { | |
934 | ||
935 | /* chip became CONFIGURED or ADDRESSED | |
936 | * earlier; drivers may already have queued | |
937 | * requests to non-control endpoints | |
938 | */ | |
939 | if (udc->ep0_set_config) { | |
f35ae634 | 940 | u16 irq_en = omap_readw(UDC_IRQ_EN); |
1da177e4 LT |
941 | |
942 | irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; | |
943 | if (!udc->ep0_reset_config) | |
944 | irq_en |= UDC_EPN_RX_IE | |
945 | | UDC_EPN_TX_IE; | |
f35ae634 | 946 | omap_writew(irq_en, UDC_IRQ_EN); |
1da177e4 LT |
947 | } |
948 | ||
313980c9 DB |
949 | /* STATUS for zero length DATA stages is |
950 | * always an IN ... even for IN transfers, | |
dc0d5c1e | 951 | * a weird case which seem to stall OMAP. |
313980c9 | 952 | */ |
80dd1358 FB |
953 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, |
954 | UDC_EP_NUM); | |
f35ae634 TL |
955 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
956 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
957 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 LT |
958 | |
959 | /* cleanup */ | |
960 | udc->ep0_pending = 0; | |
961 | done(ep, req, 0); | |
313980c9 | 962 | req = NULL; |
1da177e4 LT |
963 | |
964 | /* non-empty DATA stage */ | |
965 | } else if (is_in) { | |
80dd1358 FB |
966 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, |
967 | UDC_EP_NUM); | |
1da177e4 LT |
968 | } else { |
969 | if (udc->ep0_setup) | |
970 | goto irq_wait; | |
f35ae634 | 971 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); |
1da177e4 LT |
972 | } |
973 | } else { | |
974 | is_in = ep->bEndpointAddress & USB_DIR_IN; | |
975 | if (!ep->has_dma) | |
976 | use_ep(ep, UDC_EP_SEL); | |
977 | /* if ISO: SOF IRQs must be enabled/disabled! */ | |
978 | } | |
979 | ||
980 | if (ep->has_dma) | |
981 | (is_in ? next_in_dma : next_out_dma)(ep, req); | |
982 | else if (req) { | |
983 | if ((is_in ? write_fifo : read_fifo)(ep, req) == 1) | |
313980c9 | 984 | req = NULL; |
1da177e4 LT |
985 | deselect_ep(); |
986 | if (!is_in) { | |
f35ae634 | 987 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
988 | ep->ackwait = 1 + ep->double_buf; |
989 | } | |
990 | /* IN: 6 wait states before it'll tx */ | |
991 | } | |
992 | } | |
993 | ||
994 | irq_wait: | |
995 | /* irq handler advances the queue */ | |
313980c9 | 996 | if (req != NULL) |
1da177e4 LT |
997 | list_add_tail(&req->queue, &ep->queue); |
998 | spin_unlock_irqrestore(&udc->lock, flags); | |
999 | ||
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
1004 | { | |
1005 | struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); | |
1006 | struct omap_req *req; | |
1007 | unsigned long flags; | |
1008 | ||
1009 | if (!_ep || !_req) | |
1010 | return -EINVAL; | |
1011 | ||
1012 | spin_lock_irqsave(&ep->udc->lock, flags); | |
1013 | ||
1014 | /* make sure it's actually queued on this endpoint */ | |
80dd1358 | 1015 | list_for_each_entry(req, &ep->queue, queue) { |
1da177e4 LT |
1016 | if (&req->req == _req) |
1017 | break; | |
1018 | } | |
1019 | if (&req->req != _req) { | |
1020 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1021 | return -EINVAL; | |
1022 | } | |
1023 | ||
1024 | if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) { | |
1025 | int channel = ep->dma_channel; | |
1026 | ||
1027 | /* releasing the channel cancels the request, | |
1028 | * reclaiming the channel restarts the queue | |
1029 | */ | |
1030 | dma_channel_release(ep); | |
1031 | dma_channel_claim(ep, channel); | |
e6a6e472 | 1032 | } else |
1da177e4 LT |
1033 | done(ep, req, -ECONNRESET); |
1034 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | /*-------------------------------------------------------------------------*/ | |
1039 | ||
1040 | static int omap_ep_set_halt(struct usb_ep *_ep, int value) | |
1041 | { | |
1042 | struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); | |
1043 | unsigned long flags; | |
1044 | int status = -EOPNOTSUPP; | |
1045 | ||
1046 | spin_lock_irqsave(&ep->udc->lock, flags); | |
1047 | ||
1048 | /* just use protocol stalls for ep0; real halts are annoying */ | |
1049 | if (ep->bEndpointAddress == 0) { | |
1050 | if (!ep->udc->ep0_pending) | |
1051 | status = -EINVAL; | |
1052 | else if (value) { | |
1053 | if (ep->udc->ep0_set_config) { | |
b6c63937 | 1054 | WARNING("error changing config?\n"); |
f35ae634 | 1055 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1da177e4 | 1056 | } |
f35ae634 | 1057 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1da177e4 LT |
1058 | ep->udc->ep0_pending = 0; |
1059 | status = 0; | |
1060 | } else /* NOP */ | |
1061 | status = 0; | |
1062 | ||
1063 | /* otherwise, all active non-ISO endpoints can halt */ | |
f8bdae06 | 1064 | } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) { |
1da177e4 LT |
1065 | |
1066 | /* IN endpoints must already be idle */ | |
1067 | if ((ep->bEndpointAddress & USB_DIR_IN) | |
e6a6e472 | 1068 | && !list_empty(&ep->queue)) { |
1da177e4 LT |
1069 | status = -EAGAIN; |
1070 | goto done; | |
1071 | } | |
1072 | ||
1073 | if (value) { | |
1074 | int channel; | |
1075 | ||
1076 | if (use_dma && ep->dma_channel | |
1077 | && !list_empty(&ep->queue)) { | |
1078 | channel = ep->dma_channel; | |
1079 | dma_channel_release(ep); | |
1080 | } else | |
1081 | channel = 0; | |
1082 | ||
1083 | use_ep(ep, UDC_EP_SEL); | |
f35ae634 TL |
1084 | if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) { |
1085 | omap_writew(UDC_SET_HALT, UDC_CTRL); | |
1da177e4 LT |
1086 | status = 0; |
1087 | } else | |
1088 | status = -EAGAIN; | |
1089 | deselect_ep(); | |
1090 | ||
1091 | if (channel) | |
1092 | dma_channel_claim(ep, channel); | |
1093 | } else { | |
1094 | use_ep(ep, 0); | |
f35ae634 | 1095 | omap_writew(ep->udc->clr_halt, UDC_CTRL); |
1da177e4 LT |
1096 | ep->ackwait = 0; |
1097 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { | |
f35ae634 | 1098 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
1099 | ep->ackwait = 1 + ep->double_buf; |
1100 | } | |
1101 | } | |
1102 | } | |
1103 | done: | |
1104 | VDBG("%s %s halt stat %d\n", ep->ep.name, | |
1105 | value ? "set" : "clear", status); | |
1106 | ||
1107 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1108 | return status; | |
1109 | } | |
1110 | ||
977ac789 | 1111 | static const struct usb_ep_ops omap_ep_ops = { |
1da177e4 LT |
1112 | .enable = omap_ep_enable, |
1113 | .disable = omap_ep_disable, | |
1114 | ||
1115 | .alloc_request = omap_alloc_request, | |
1116 | .free_request = omap_free_request, | |
1117 | ||
1da177e4 LT |
1118 | .queue = omap_ep_queue, |
1119 | .dequeue = omap_ep_dequeue, | |
1120 | ||
1121 | .set_halt = omap_ep_set_halt, | |
80dd1358 FB |
1122 | /* fifo_status ... report bytes in fifo */ |
1123 | /* fifo_flush ... flush fifo */ | |
1da177e4 LT |
1124 | }; |
1125 | ||
1126 | /*-------------------------------------------------------------------------*/ | |
1127 | ||
1128 | static int omap_get_frame(struct usb_gadget *gadget) | |
1129 | { | |
f35ae634 | 1130 | u16 sof = omap_readw(UDC_SOF); |
1da177e4 LT |
1131 | return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; |
1132 | } | |
1133 | ||
1134 | static int omap_wakeup(struct usb_gadget *gadget) | |
1135 | { | |
1136 | struct omap_udc *udc; | |
1137 | unsigned long flags; | |
1138 | int retval = -EHOSTUNREACH; | |
1139 | ||
1140 | udc = container_of(gadget, struct omap_udc, gadget); | |
1141 | ||
1142 | spin_lock_irqsave(&udc->lock, flags); | |
1143 | if (udc->devstat & UDC_SUS) { | |
1144 | /* NOTE: OTG spec erratum says that OTG devices may | |
1145 | * issue wakeups without host enable. | |
1146 | */ | |
1147 | if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { | |
1148 | DBG("remote wakeup...\n"); | |
f35ae634 | 1149 | omap_writew(UDC_RMT_WKP, UDC_SYSCON2); |
1da177e4 LT |
1150 | retval = 0; |
1151 | } | |
1152 | ||
1153 | /* NOTE: non-OTG systems may use SRP TOO... */ | |
1154 | } else if (!(udc->devstat & UDC_ATT)) { | |
ded017ee | 1155 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
6e13c650 | 1156 | retval = otg_start_srp(udc->transceiver->otg); |
1da177e4 LT |
1157 | } |
1158 | spin_unlock_irqrestore(&udc->lock, flags); | |
1159 | ||
1160 | return retval; | |
1161 | } | |
1162 | ||
1163 | static int | |
1164 | omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) | |
1165 | { | |
1166 | struct omap_udc *udc; | |
1167 | unsigned long flags; | |
1168 | u16 syscon1; | |
1169 | ||
58ae8e0b | 1170 | gadget->is_selfpowered = (is_selfpowered != 0); |
1da177e4 LT |
1171 | udc = container_of(gadget, struct omap_udc, gadget); |
1172 | spin_lock_irqsave(&udc->lock, flags); | |
f35ae634 | 1173 | syscon1 = omap_readw(UDC_SYSCON1); |
1da177e4 LT |
1174 | if (is_selfpowered) |
1175 | syscon1 |= UDC_SELF_PWR; | |
1176 | else | |
1177 | syscon1 &= ~UDC_SELF_PWR; | |
f35ae634 | 1178 | omap_writew(syscon1, UDC_SYSCON1); |
1da177e4 LT |
1179 | spin_unlock_irqrestore(&udc->lock, flags); |
1180 | ||
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | static int can_pullup(struct omap_udc *udc) | |
1185 | { | |
1186 | return udc->driver && udc->softconnect && udc->vbus_active; | |
1187 | } | |
1188 | ||
1189 | static void pullup_enable(struct omap_udc *udc) | |
1190 | { | |
f35ae634 TL |
1191 | u16 w; |
1192 | ||
1193 | w = omap_readw(UDC_SYSCON1); | |
1194 | w |= UDC_PULLUP_EN; | |
1195 | omap_writew(w, UDC_SYSCON1); | |
1196 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { | |
1197 | u32 l; | |
1198 | ||
1199 | l = omap_readl(OTG_CTRL); | |
1200 | l |= OTG_BSESSVLD; | |
1201 | omap_writel(l, OTG_CTRL); | |
1202 | } | |
1203 | omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); | |
1da177e4 LT |
1204 | } |
1205 | ||
1206 | static void pullup_disable(struct omap_udc *udc) | |
1207 | { | |
f35ae634 TL |
1208 | u16 w; |
1209 | ||
1210 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { | |
1211 | u32 l; | |
1212 | ||
1213 | l = omap_readl(OTG_CTRL); | |
1214 | l &= ~OTG_BSESSVLD; | |
1215 | omap_writel(l, OTG_CTRL); | |
1216 | } | |
1217 | omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); | |
1218 | w = omap_readw(UDC_SYSCON1); | |
1219 | w &= ~UDC_PULLUP_EN; | |
1220 | omap_writew(w, UDC_SYSCON1); | |
1da177e4 LT |
1221 | } |
1222 | ||
e6a6e472 DB |
1223 | static struct omap_udc *udc; |
1224 | ||
1225 | static void omap_udc_enable_clock(int enable) | |
1226 | { | |
1227 | if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL) | |
1228 | return; | |
1229 | ||
1230 | if (enable) { | |
1231 | clk_enable(udc->dc_clk); | |
1232 | clk_enable(udc->hhc_clk); | |
1233 | udelay(100); | |
1234 | } else { | |
1235 | clk_disable(udc->hhc_clk); | |
1236 | clk_disable(udc->dc_clk); | |
1237 | } | |
1238 | } | |
1239 | ||
1da177e4 LT |
1240 | /* |
1241 | * Called by whatever detects VBUS sessions: external transceiver | |
1242 | * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock. | |
1243 | */ | |
1244 | static int omap_vbus_session(struct usb_gadget *gadget, int is_active) | |
1245 | { | |
1246 | struct omap_udc *udc; | |
1247 | unsigned long flags; | |
f35ae634 | 1248 | u32 l; |
1da177e4 LT |
1249 | |
1250 | udc = container_of(gadget, struct omap_udc, gadget); | |
1251 | spin_lock_irqsave(&udc->lock, flags); | |
1252 | VDBG("VBUS %s\n", is_active ? "on" : "off"); | |
1253 | udc->vbus_active = (is_active != 0); | |
1254 | if (cpu_is_omap15xx()) { | |
1255 | /* "software" detect, ignored if !VBUS_MODE_1510 */ | |
f35ae634 | 1256 | l = omap_readl(FUNC_MUX_CTRL_0); |
1da177e4 | 1257 | if (is_active) |
f35ae634 | 1258 | l |= VBUS_CTRL_1510; |
1da177e4 | 1259 | else |
f35ae634 TL |
1260 | l &= ~VBUS_CTRL_1510; |
1261 | omap_writel(l, FUNC_MUX_CTRL_0); | |
1da177e4 | 1262 | } |
e6a6e472 DB |
1263 | if (udc->dc_clk != NULL && is_active) { |
1264 | if (!udc->clk_requested) { | |
1265 | omap_udc_enable_clock(1); | |
1266 | udc->clk_requested = 1; | |
1267 | } | |
1268 | } | |
1da177e4 LT |
1269 | if (can_pullup(udc)) |
1270 | pullup_enable(udc); | |
1271 | else | |
1272 | pullup_disable(udc); | |
e6a6e472 DB |
1273 | if (udc->dc_clk != NULL && !is_active) { |
1274 | if (udc->clk_requested) { | |
1275 | omap_udc_enable_clock(0); | |
1276 | udc->clk_requested = 0; | |
1277 | } | |
1278 | } | |
1da177e4 LT |
1279 | spin_unlock_irqrestore(&udc->lock, flags); |
1280 | return 0; | |
1281 | } | |
1282 | ||
1283 | static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1284 | { | |
1285 | struct omap_udc *udc; | |
1286 | ||
1287 | udc = container_of(gadget, struct omap_udc, gadget); | |
ded017ee | 1288 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
b96d3b08 | 1289 | return usb_phy_set_power(udc->transceiver, mA); |
1da177e4 LT |
1290 | return -EOPNOTSUPP; |
1291 | } | |
1292 | ||
1293 | static int omap_pullup(struct usb_gadget *gadget, int is_on) | |
1294 | { | |
1295 | struct omap_udc *udc; | |
1296 | unsigned long flags; | |
1297 | ||
1298 | udc = container_of(gadget, struct omap_udc, gadget); | |
1299 | spin_lock_irqsave(&udc->lock, flags); | |
1300 | udc->softconnect = (is_on != 0); | |
1301 | if (can_pullup(udc)) | |
1302 | pullup_enable(udc); | |
1303 | else | |
1304 | pullup_disable(udc); | |
1305 | spin_unlock_irqrestore(&udc->lock, flags); | |
1306 | return 0; | |
1307 | } | |
1308 | ||
1bf0cf60 | 1309 | static int omap_udc_start(struct usb_gadget *g, |
518868c8 | 1310 | struct usb_gadget_driver *driver); |
22835b80 | 1311 | static int omap_udc_stop(struct usb_gadget *g); |
0f91349b | 1312 | |
eeef4587 | 1313 | static const struct usb_gadget_ops omap_gadget_ops = { |
1da177e4 LT |
1314 | .get_frame = omap_get_frame, |
1315 | .wakeup = omap_wakeup, | |
1316 | .set_selfpowered = omap_set_selfpowered, | |
1317 | .vbus_session = omap_vbus_session, | |
1318 | .vbus_draw = omap_vbus_draw, | |
1319 | .pullup = omap_pullup, | |
1bf0cf60 FB |
1320 | .udc_start = omap_udc_start, |
1321 | .udc_stop = omap_udc_stop, | |
1da177e4 LT |
1322 | }; |
1323 | ||
1324 | /*-------------------------------------------------------------------------*/ | |
1325 | ||
1326 | /* dequeue ALL requests; caller holds udc->lock */ | |
1327 | static void nuke(struct omap_ep *ep, int status) | |
1328 | { | |
1329 | struct omap_req *req; | |
1330 | ||
1331 | ep->stopped = 1; | |
1332 | ||
1333 | if (use_dma && ep->dma_channel) | |
1334 | dma_channel_release(ep); | |
1335 | ||
1336 | use_ep(ep, 0); | |
f35ae634 | 1337 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1da177e4 | 1338 | if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) |
f35ae634 | 1339 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1da177e4 LT |
1340 | |
1341 | while (!list_empty(&ep->queue)) { | |
1342 | req = list_entry(ep->queue.next, struct omap_req, queue); | |
1343 | done(ep, req, status); | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | /* caller holds udc->lock */ | |
1348 | static void udc_quiesce(struct omap_udc *udc) | |
1349 | { | |
1350 | struct omap_ep *ep; | |
1351 | ||
1352 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
1353 | nuke(&udc->ep[0], -ESHUTDOWN); | |
80dd1358 | 1354 | list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) |
1da177e4 LT |
1355 | nuke(ep, -ESHUTDOWN); |
1356 | } | |
1357 | ||
1358 | /*-------------------------------------------------------------------------*/ | |
1359 | ||
1360 | static void update_otg(struct omap_udc *udc) | |
1361 | { | |
1362 | u16 devstat; | |
1363 | ||
9cfbba73 | 1364 | if (!gadget_is_otg(&udc->gadget)) |
1da177e4 LT |
1365 | return; |
1366 | ||
f35ae634 TL |
1367 | if (omap_readl(OTG_CTRL) & OTG_ID) |
1368 | devstat = omap_readw(UDC_DEVSTAT); | |
1da177e4 LT |
1369 | else |
1370 | devstat = 0; | |
1371 | ||
1372 | udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE); | |
1373 | udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT); | |
1374 | udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT); | |
1375 | ||
1376 | /* Enable HNP early, avoiding races on suspend irq path. | |
1377 | * ASSUMES OTG state machine B_BUS_REQ input is true. | |
1378 | */ | |
f35ae634 TL |
1379 | if (udc->gadget.b_hnp_enable) { |
1380 | u32 l; | |
1381 | ||
1382 | l = omap_readl(OTG_CTRL); | |
1383 | l |= OTG_B_HNPEN | OTG_B_BUSREQ; | |
1384 | l &= ~OTG_PULLUP; | |
1385 | omap_writel(l, OTG_CTRL); | |
1386 | } | |
1da177e4 LT |
1387 | } |
1388 | ||
1389 | static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |
1390 | { | |
1391 | struct omap_ep *ep0 = &udc->ep[0]; | |
313980c9 | 1392 | struct omap_req *req = NULL; |
1da177e4 LT |
1393 | |
1394 | ep0->irqs++; | |
1395 | ||
1396 | /* Clear any pending requests and then scrub any rx/tx state | |
1397 | * before starting to handle the SETUP request. | |
1398 | */ | |
1399 | if (irq_src & UDC_SETUP) { | |
1400 | u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX); | |
1401 | ||
1402 | nuke(ep0, 0); | |
1403 | if (ack) { | |
f35ae634 | 1404 | omap_writew(ack, UDC_IRQ_SRC); |
1da177e4 LT |
1405 | irq_src = UDC_SETUP; |
1406 | } | |
1407 | } | |
1408 | ||
e6a6e472 | 1409 | /* IN/OUT packets mean we're in the DATA or STATUS stage. |
1da177e4 LT |
1410 | * This driver uses only uses protocol stalls (ep0 never halts), |
1411 | * and if we got this far the gadget driver already had a | |
1412 | * chance to stall. Tries to be forgiving of host oddities. | |
1413 | * | |
1414 | * NOTE: the last chance gadget drivers have to stall control | |
1415 | * requests is during their request completion callback. | |
1416 | */ | |
1417 | if (!list_empty(&ep0->queue)) | |
1418 | req = container_of(ep0->queue.next, struct omap_req, queue); | |
1419 | ||
1420 | /* IN == TX to host */ | |
1421 | if (irq_src & UDC_EP0_TX) { | |
1422 | int stat; | |
1423 | ||
f35ae634 TL |
1424 | omap_writew(UDC_EP0_TX, UDC_IRQ_SRC); |
1425 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); | |
1426 | stat = omap_readw(UDC_STAT_FLG); | |
1da177e4 LT |
1427 | if (stat & UDC_ACK) { |
1428 | if (udc->ep0_in) { | |
1429 | /* write next IN packet from response, | |
1430 | * or set up the status stage. | |
1431 | */ | |
1432 | if (req) | |
1433 | stat = write_fifo(ep0, req); | |
f35ae634 | 1434 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1da177e4 | 1435 | if (!req && udc->ep0_pending) { |
f35ae634 TL |
1436 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); |
1437 | omap_writew(UDC_CLR_EP, UDC_CTRL); | |
1438 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1439 | omap_writew(0, UDC_EP_NUM); | |
1da177e4 LT |
1440 | udc->ep0_pending = 0; |
1441 | } /* else: 6 wait states before it'll tx */ | |
1442 | } else { | |
1443 | /* ack status stage of OUT transfer */ | |
f35ae634 | 1444 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1da177e4 LT |
1445 | if (req) |
1446 | done(ep0, req, 0); | |
1447 | } | |
313980c9 | 1448 | req = NULL; |
1da177e4 | 1449 | } else if (stat & UDC_STALL) { |
f35ae634 TL |
1450 | omap_writew(UDC_CLR_HALT, UDC_CTRL); |
1451 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 | 1452 | } else { |
f35ae634 | 1453 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1da177e4 LT |
1454 | } |
1455 | } | |
1456 | ||
1457 | /* OUT == RX from host */ | |
1458 | if (irq_src & UDC_EP0_RX) { | |
1459 | int stat; | |
1460 | ||
f35ae634 TL |
1461 | omap_writew(UDC_EP0_RX, UDC_IRQ_SRC); |
1462 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); | |
1463 | stat = omap_readw(UDC_STAT_FLG); | |
1da177e4 LT |
1464 | if (stat & UDC_ACK) { |
1465 | if (!udc->ep0_in) { | |
1466 | stat = 0; | |
1467 | /* read next OUT packet of request, maybe | |
1468 | * reactiviting the fifo; stall on errors. | |
1469 | */ | |
80dd1358 FB |
1470 | stat = read_fifo(ep0, req); |
1471 | if (!req || stat < 0) { | |
f35ae634 | 1472 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1da177e4 LT |
1473 | udc->ep0_pending = 0; |
1474 | stat = 0; | |
1475 | } else if (stat == 0) | |
f35ae634 TL |
1476 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1477 | omap_writew(0, UDC_EP_NUM); | |
e6a6e472 | 1478 | |
1da177e4 LT |
1479 | /* activate status stage */ |
1480 | if (stat == 1) { | |
1481 | done(ep0, req, 0); | |
1482 | /* that may have STALLed ep0... */ | |
f35ae634 TL |
1483 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, |
1484 | UDC_EP_NUM); | |
1485 | omap_writew(UDC_CLR_EP, UDC_CTRL); | |
1486 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1487 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 LT |
1488 | udc->ep0_pending = 0; |
1489 | } | |
1490 | } else { | |
1491 | /* ack status stage of IN transfer */ | |
f35ae634 | 1492 | omap_writew(0, UDC_EP_NUM); |
1da177e4 LT |
1493 | if (req) |
1494 | done(ep0, req, 0); | |
1495 | } | |
1496 | } else if (stat & UDC_STALL) { | |
f35ae634 TL |
1497 | omap_writew(UDC_CLR_HALT, UDC_CTRL); |
1498 | omap_writew(0, UDC_EP_NUM); | |
1da177e4 | 1499 | } else { |
f35ae634 | 1500 | omap_writew(0, UDC_EP_NUM); |
1da177e4 LT |
1501 | } |
1502 | } | |
1503 | ||
1504 | /* SETUP starts all control transfers */ | |
1505 | if (irq_src & UDC_SETUP) { | |
1506 | union u { | |
1507 | u16 word[4]; | |
1508 | struct usb_ctrlrequest r; | |
1509 | } u; | |
1510 | int status = -EINVAL; | |
1511 | struct omap_ep *ep; | |
1512 | ||
1513 | /* read the (latest) SETUP message */ | |
1514 | do { | |
f35ae634 | 1515 | omap_writew(UDC_SETUP_SEL, UDC_EP_NUM); |
1da177e4 | 1516 | /* two bytes at a time */ |
f35ae634 TL |
1517 | u.word[0] = omap_readw(UDC_DATA); |
1518 | u.word[1] = omap_readw(UDC_DATA); | |
1519 | u.word[2] = omap_readw(UDC_DATA); | |
1520 | u.word[3] = omap_readw(UDC_DATA); | |
1521 | omap_writew(0, UDC_EP_NUM); | |
1522 | } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP); | |
1da177e4 | 1523 | |
01ee7d70 DB |
1524 | #define w_value le16_to_cpu(u.r.wValue) |
1525 | #define w_index le16_to_cpu(u.r.wIndex) | |
1526 | #define w_length le16_to_cpu(u.r.wLength) | |
65111084 | 1527 | |
1da177e4 LT |
1528 | /* Delegate almost all control requests to the gadget driver, |
1529 | * except for a handful of ch9 status/feature requests that | |
1530 | * hardware doesn't autodecode _and_ the gadget API hides. | |
1531 | */ | |
1532 | udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0; | |
1533 | udc->ep0_set_config = 0; | |
1534 | udc->ep0_pending = 1; | |
1535 | ep0->stopped = 0; | |
1536 | ep0->ackwait = 0; | |
1537 | switch (u.r.bRequest) { | |
1538 | case USB_REQ_SET_CONFIGURATION: | |
1539 | /* udc needs to know when ep != 0 is valid */ | |
1540 | if (u.r.bRequestType != USB_RECIP_DEVICE) | |
1541 | goto delegate; | |
65111084 | 1542 | if (w_length != 0) |
1da177e4 LT |
1543 | goto do_stall; |
1544 | udc->ep0_set_config = 1; | |
65111084 DB |
1545 | udc->ep0_reset_config = (w_value == 0); |
1546 | VDBG("set config %d\n", w_value); | |
1da177e4 LT |
1547 | |
1548 | /* update udc NOW since gadget driver may start | |
1549 | * queueing requests immediately; clear config | |
1550 | * later if it fails the request. | |
1551 | */ | |
1552 | if (udc->ep0_reset_config) | |
f35ae634 | 1553 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1da177e4 | 1554 | else |
f35ae634 | 1555 | omap_writew(UDC_DEV_CFG, UDC_SYSCON2); |
1da177e4 LT |
1556 | update_otg(udc); |
1557 | goto delegate; | |
1558 | case USB_REQ_CLEAR_FEATURE: | |
1559 | /* clear endpoint halt */ | |
1560 | if (u.r.bRequestType != USB_RECIP_ENDPOINT) | |
1561 | goto delegate; | |
65111084 DB |
1562 | if (w_value != USB_ENDPOINT_HALT |
1563 | || w_length != 0) | |
1da177e4 | 1564 | goto do_stall; |
65111084 | 1565 | ep = &udc->ep[w_index & 0xf]; |
1da177e4 | 1566 | if (ep != ep0) { |
65111084 | 1567 | if (w_index & USB_DIR_IN) |
1da177e4 LT |
1568 | ep += 16; |
1569 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC | |
f8bdae06 | 1570 | || !ep->ep.desc) |
1da177e4 LT |
1571 | goto do_stall; |
1572 | use_ep(ep, 0); | |
f35ae634 | 1573 | omap_writew(udc->clr_halt, UDC_CTRL); |
1da177e4 LT |
1574 | ep->ackwait = 0; |
1575 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { | |
f35ae634 | 1576 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
1577 | ep->ackwait = 1 + ep->double_buf; |
1578 | } | |
313980c9 DB |
1579 | /* NOTE: assumes the host behaves sanely, |
1580 | * only clearing real halts. Else we may | |
1581 | * need to kill pending transfers and then | |
1582 | * restart the queue... very messy for DMA! | |
1583 | */ | |
1da177e4 LT |
1584 | } |
1585 | VDBG("%s halt cleared by host\n", ep->name); | |
1586 | goto ep0out_status_stage; | |
1587 | case USB_REQ_SET_FEATURE: | |
1588 | /* set endpoint halt */ | |
1589 | if (u.r.bRequestType != USB_RECIP_ENDPOINT) | |
1590 | goto delegate; | |
65111084 DB |
1591 | if (w_value != USB_ENDPOINT_HALT |
1592 | || w_length != 0) | |
1da177e4 | 1593 | goto do_stall; |
65111084 DB |
1594 | ep = &udc->ep[w_index & 0xf]; |
1595 | if (w_index & USB_DIR_IN) | |
1da177e4 LT |
1596 | ep += 16; |
1597 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC | |
f8bdae06 | 1598 | || ep == ep0 || !ep->ep.desc) |
1da177e4 LT |
1599 | goto do_stall; |
1600 | if (use_dma && ep->has_dma) { | |
1601 | /* this has rude side-effects (aborts) and | |
1602 | * can't really work if DMA-IN is active | |
1603 | */ | |
80dd1358 | 1604 | DBG("%s host set_halt, NYET\n", ep->name); |
1da177e4 LT |
1605 | goto do_stall; |
1606 | } | |
1607 | use_ep(ep, 0); | |
1608 | /* can't halt if fifo isn't empty... */ | |
f35ae634 TL |
1609 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1610 | omap_writew(UDC_SET_HALT, UDC_CTRL); | |
1da177e4 LT |
1611 | VDBG("%s halted by host\n", ep->name); |
1612 | ep0out_status_stage: | |
1613 | status = 0; | |
f35ae634 TL |
1614 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); |
1615 | omap_writew(UDC_CLR_EP, UDC_CTRL); | |
1616 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1617 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 LT |
1618 | udc->ep0_pending = 0; |
1619 | break; | |
1620 | case USB_REQ_GET_STATUS: | |
8a3c1f57 DB |
1621 | /* USB_ENDPOINT_HALT status? */ |
1622 | if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT)) | |
1623 | goto intf_status; | |
1624 | ||
1625 | /* ep0 never stalls */ | |
1626 | if (!(w_index & 0xf)) | |
1627 | goto zero_status; | |
1628 | ||
1629 | /* only active endpoints count */ | |
1630 | ep = &udc->ep[w_index & 0xf]; | |
1631 | if (w_index & USB_DIR_IN) | |
1632 | ep += 16; | |
f8bdae06 | 1633 | if (!ep->ep.desc) |
8a3c1f57 DB |
1634 | goto do_stall; |
1635 | ||
1636 | /* iso never stalls */ | |
1637 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) | |
1638 | goto zero_status; | |
1639 | ||
1640 | /* FIXME don't assume non-halted endpoints!! */ | |
1641 | ERR("%s status, can't report\n", ep->ep.name); | |
1642 | goto do_stall; | |
1643 | ||
1644 | intf_status: | |
1da177e4 LT |
1645 | /* return interface status. if we were pedantic, |
1646 | * we'd detect non-existent interfaces, and stall. | |
1647 | */ | |
1648 | if (u.r.bRequestType | |
1649 | != (USB_DIR_IN|USB_RECIP_INTERFACE)) | |
1650 | goto delegate; | |
8a3c1f57 DB |
1651 | |
1652 | zero_status: | |
1da177e4 | 1653 | /* return two zero bytes */ |
f35ae634 TL |
1654 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); |
1655 | omap_writew(0, UDC_DATA); | |
1656 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1657 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 | 1658 | status = 0; |
65111084 | 1659 | VDBG("GET_STATUS, interface %d\n", w_index); |
1da177e4 LT |
1660 | /* next, status stage */ |
1661 | break; | |
1662 | default: | |
1663 | delegate: | |
1664 | /* activate the ep0out fifo right away */ | |
65111084 | 1665 | if (!udc->ep0_in && w_length) { |
f35ae634 TL |
1666 | omap_writew(0, UDC_EP_NUM); |
1667 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1da177e4 LT |
1668 | } |
1669 | ||
1670 | /* gadget drivers see class/vendor specific requests, | |
1671 | * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION}, | |
1672 | * and more | |
1673 | */ | |
1674 | VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n", | |
1675 | u.r.bRequestType, u.r.bRequest, | |
65111084 DB |
1676 | w_value, w_index, w_length); |
1677 | ||
1678 | #undef w_value | |
1679 | #undef w_index | |
1680 | #undef w_length | |
1da177e4 LT |
1681 | |
1682 | /* The gadget driver may return an error here, | |
1683 | * causing an immediate protocol stall. | |
1684 | * | |
1685 | * Else it must issue a response, either queueing a | |
1686 | * response buffer for the DATA stage, or halting ep0 | |
1687 | * (causing a protocol stall, not a real halt). A | |
1688 | * zero length buffer means no DATA stage. | |
1689 | * | |
1690 | * It's fine to issue that response after the setup() | |
1691 | * call returns, and this IRQ was handled. | |
1692 | */ | |
1693 | udc->ep0_setup = 1; | |
1694 | spin_unlock(&udc->lock); | |
80dd1358 | 1695 | status = udc->driver->setup(&udc->gadget, &u.r); |
1da177e4 LT |
1696 | spin_lock(&udc->lock); |
1697 | udc->ep0_setup = 0; | |
1698 | } | |
1699 | ||
1700 | if (status < 0) { | |
1701 | do_stall: | |
1702 | VDBG("req %02x.%02x protocol STALL; stat %d\n", | |
1703 | u.r.bRequestType, u.r.bRequest, status); | |
1704 | if (udc->ep0_set_config) { | |
1705 | if (udc->ep0_reset_config) | |
b6c63937 | 1706 | WARNING("error resetting config?\n"); |
1da177e4 | 1707 | else |
f35ae634 | 1708 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1da177e4 | 1709 | } |
f35ae634 | 1710 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1da177e4 LT |
1711 | udc->ep0_pending = 0; |
1712 | } | |
1713 | } | |
1714 | } | |
1715 | ||
1716 | /*-------------------------------------------------------------------------*/ | |
1717 | ||
1718 | #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT) | |
1719 | ||
1720 | static void devstate_irq(struct omap_udc *udc, u16 irq_src) | |
1721 | { | |
1722 | u16 devstat, change; | |
1723 | ||
f35ae634 | 1724 | devstat = omap_readw(UDC_DEVSTAT); |
1da177e4 LT |
1725 | change = devstat ^ udc->devstat; |
1726 | udc->devstat = devstat; | |
1727 | ||
1728 | if (change & (UDC_USB_RESET|UDC_ATT)) { | |
1729 | udc_quiesce(udc); | |
1730 | ||
1731 | if (change & UDC_ATT) { | |
1732 | /* driver for any external transceiver will | |
1733 | * have called omap_vbus_session() already | |
1734 | */ | |
1735 | if (devstat & UDC_ATT) { | |
1736 | udc->gadget.speed = USB_SPEED_FULL; | |
1737 | VDBG("connect\n"); | |
ded017ee | 1738 | if (IS_ERR_OR_NULL(udc->transceiver)) |
1da177e4 | 1739 | pullup_enable(udc); |
80dd1358 | 1740 | /* if (driver->connect) call it */ |
1da177e4 LT |
1741 | } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) { |
1742 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
ded017ee | 1743 | if (IS_ERR_OR_NULL(udc->transceiver)) |
1da177e4 LT |
1744 | pullup_disable(udc); |
1745 | DBG("disconnect, gadget %s\n", | |
1746 | udc->driver->driver.name); | |
1747 | if (udc->driver->disconnect) { | |
1748 | spin_unlock(&udc->lock); | |
1749 | udc->driver->disconnect(&udc->gadget); | |
1750 | spin_lock(&udc->lock); | |
1751 | } | |
1752 | } | |
1753 | change &= ~UDC_ATT; | |
1754 | } | |
1755 | ||
1756 | if (change & UDC_USB_RESET) { | |
1757 | if (devstat & UDC_USB_RESET) { | |
1758 | VDBG("RESET=1\n"); | |
1759 | } else { | |
1760 | udc->gadget.speed = USB_SPEED_FULL; | |
1761 | INFO("USB reset done, gadget %s\n", | |
1762 | udc->driver->driver.name); | |
1763 | /* ep0 traffic is legal from now on */ | |
f35ae634 TL |
1764 | omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE, |
1765 | UDC_IRQ_EN); | |
1da177e4 LT |
1766 | } |
1767 | change &= ~UDC_USB_RESET; | |
1768 | } | |
1769 | } | |
1770 | if (change & UDC_SUS) { | |
1771 | if (udc->gadget.speed != USB_SPEED_UNKNOWN) { | |
80dd1358 | 1772 | /* FIXME tell isp1301 to suspend/resume (?) */ |
1da177e4 LT |
1773 | if (devstat & UDC_SUS) { |
1774 | VDBG("suspend\n"); | |
1775 | update_otg(udc); | |
1776 | /* HNP could be under way already */ | |
1777 | if (udc->gadget.speed == USB_SPEED_FULL | |
1778 | && udc->driver->suspend) { | |
1779 | spin_unlock(&udc->lock); | |
1780 | udc->driver->suspend(&udc->gadget); | |
1781 | spin_lock(&udc->lock); | |
1782 | } | |
ded017ee | 1783 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
b96d3b08 HK |
1784 | usb_phy_set_suspend( |
1785 | udc->transceiver, 1); | |
1da177e4 LT |
1786 | } else { |
1787 | VDBG("resume\n"); | |
ded017ee | 1788 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
b96d3b08 HK |
1789 | usb_phy_set_suspend( |
1790 | udc->transceiver, 0); | |
1da177e4 LT |
1791 | if (udc->gadget.speed == USB_SPEED_FULL |
1792 | && udc->driver->resume) { | |
1793 | spin_unlock(&udc->lock); | |
1794 | udc->driver->resume(&udc->gadget); | |
1795 | spin_lock(&udc->lock); | |
1796 | } | |
1797 | } | |
1798 | } | |
1799 | change &= ~UDC_SUS; | |
1800 | } | |
1801 | if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) { | |
1802 | update_otg(udc); | |
1803 | change &= ~OTG_FLAGS; | |
1804 | } | |
1805 | ||
1806 | change &= ~(UDC_CFG|UDC_DEF|UDC_ADD); | |
1807 | if (change) | |
1808 | VDBG("devstat %03x, ignore change %03x\n", | |
1809 | devstat, change); | |
1810 | ||
f35ae634 | 1811 | omap_writew(UDC_DS_CHG, UDC_IRQ_SRC); |
1da177e4 LT |
1812 | } |
1813 | ||
7d12e780 | 1814 | static irqreturn_t omap_udc_irq(int irq, void *_udc) |
1da177e4 LT |
1815 | { |
1816 | struct omap_udc *udc = _udc; | |
1817 | u16 irq_src; | |
1818 | irqreturn_t status = IRQ_NONE; | |
1819 | unsigned long flags; | |
1820 | ||
1821 | spin_lock_irqsave(&udc->lock, flags); | |
f35ae634 | 1822 | irq_src = omap_readw(UDC_IRQ_SRC); |
1da177e4 LT |
1823 | |
1824 | /* Device state change (usb ch9 stuff) */ | |
1825 | if (irq_src & UDC_DS_CHG) { | |
1826 | devstate_irq(_udc, irq_src); | |
1827 | status = IRQ_HANDLED; | |
1828 | irq_src &= ~UDC_DS_CHG; | |
1829 | } | |
1830 | ||
1831 | /* EP0 control transfers */ | |
1832 | if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) { | |
1833 | ep0_irq(_udc, irq_src); | |
1834 | status = IRQ_HANDLED; | |
1835 | irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX); | |
1836 | } | |
1837 | ||
1838 | /* DMA transfer completion */ | |
1839 | if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) { | |
1840 | dma_irq(_udc, irq_src); | |
1841 | status = IRQ_HANDLED; | |
1842 | irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); | |
1843 | } | |
1844 | ||
f35ae634 | 1845 | irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX); |
1da177e4 LT |
1846 | if (irq_src) |
1847 | DBG("udc_irq, unhandled %03x\n", irq_src); | |
1848 | spin_unlock_irqrestore(&udc->lock, flags); | |
1849 | ||
1850 | return status; | |
1851 | } | |
1852 | ||
1853 | /* workaround for seemingly-lost IRQs for RX ACKs... */ | |
1854 | #define PIO_OUT_TIMEOUT (jiffies + HZ/3) | |
1855 | #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY))) | |
1856 | ||
e99e88a9 | 1857 | static void pio_out_timer(struct timer_list *t) |
1da177e4 | 1858 | { |
e99e88a9 | 1859 | struct omap_ep *ep = from_timer(ep, t, timer); |
1da177e4 LT |
1860 | unsigned long flags; |
1861 | u16 stat_flg; | |
1862 | ||
1863 | spin_lock_irqsave(&ep->udc->lock, flags); | |
1864 | if (!list_empty(&ep->queue) && ep->ackwait) { | |
e6a6e472 | 1865 | use_ep(ep, UDC_EP_SEL); |
f35ae634 | 1866 | stat_flg = omap_readw(UDC_STAT_FLG); |
1da177e4 LT |
1867 | |
1868 | if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) | |
1869 | || (ep->double_buf && HALF_FULL(stat_flg)))) { | |
1870 | struct omap_req *req; | |
1871 | ||
1872 | VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg); | |
1873 | req = container_of(ep->queue.next, | |
1874 | struct omap_req, queue); | |
1da177e4 | 1875 | (void) read_fifo(ep, req); |
f35ae634 TL |
1876 | omap_writew(ep->bEndpointAddress, UDC_EP_NUM); |
1877 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | |
1da177e4 | 1878 | ep->ackwait = 1 + ep->double_buf; |
e6a6e472 DB |
1879 | } else |
1880 | deselect_ep(); | |
1da177e4 LT |
1881 | } |
1882 | mod_timer(&ep->timer, PIO_OUT_TIMEOUT); | |
1883 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1884 | } | |
1885 | ||
7d12e780 | 1886 | static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) |
1da177e4 LT |
1887 | { |
1888 | u16 epn_stat, irq_src; | |
1889 | irqreturn_t status = IRQ_NONE; | |
1890 | struct omap_ep *ep; | |
1891 | int epnum; | |
1892 | struct omap_udc *udc = _dev; | |
1893 | struct omap_req *req; | |
1894 | unsigned long flags; | |
1895 | ||
1896 | spin_lock_irqsave(&udc->lock, flags); | |
f35ae634 TL |
1897 | epn_stat = omap_readw(UDC_EPN_STAT); |
1898 | irq_src = omap_readw(UDC_IRQ_SRC); | |
1da177e4 LT |
1899 | |
1900 | /* handle OUT first, to avoid some wasteful NAKs */ | |
1901 | if (irq_src & UDC_EPN_RX) { | |
1902 | epnum = (epn_stat >> 8) & 0x0f; | |
f35ae634 | 1903 | omap_writew(UDC_EPN_RX, UDC_IRQ_SRC); |
1da177e4 LT |
1904 | status = IRQ_HANDLED; |
1905 | ep = &udc->ep[epnum]; | |
1906 | ep->irqs++; | |
1907 | ||
f35ae634 | 1908 | omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM); |
1da177e4 | 1909 | ep->fnf = 0; |
f35ae634 | 1910 | if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { |
1da177e4 LT |
1911 | ep->ackwait--; |
1912 | if (!list_empty(&ep->queue)) { | |
1913 | int stat; | |
1914 | req = container_of(ep->queue.next, | |
1915 | struct omap_req, queue); | |
1916 | stat = read_fifo(ep, req); | |
1917 | if (!ep->double_buf) | |
1918 | ep->fnf = 1; | |
1919 | } | |
1920 | } | |
1921 | /* min 6 clock delay before clearing EP_SEL ... */ | |
f35ae634 TL |
1922 | epn_stat = omap_readw(UDC_EPN_STAT); |
1923 | epn_stat = omap_readw(UDC_EPN_STAT); | |
1924 | omap_writew(epnum, UDC_EP_NUM); | |
1da177e4 LT |
1925 | |
1926 | /* enabling fifo _after_ clearing ACK, contrary to docs, | |
1927 | * reduces lossage; timer still needed though (sigh). | |
1928 | */ | |
1929 | if (ep->fnf) { | |
f35ae634 | 1930 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1da177e4 LT |
1931 | ep->ackwait = 1 + ep->double_buf; |
1932 | } | |
1933 | mod_timer(&ep->timer, PIO_OUT_TIMEOUT); | |
1934 | } | |
1935 | ||
1936 | /* then IN transfers */ | |
1937 | else if (irq_src & UDC_EPN_TX) { | |
1938 | epnum = epn_stat & 0x0f; | |
f35ae634 | 1939 | omap_writew(UDC_EPN_TX, UDC_IRQ_SRC); |
1da177e4 LT |
1940 | status = IRQ_HANDLED; |
1941 | ep = &udc->ep[16 + epnum]; | |
1942 | ep->irqs++; | |
1943 | ||
f35ae634 TL |
1944 | omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM); |
1945 | if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { | |
1da177e4 LT |
1946 | ep->ackwait = 0; |
1947 | if (!list_empty(&ep->queue)) { | |
1948 | req = container_of(ep->queue.next, | |
1949 | struct omap_req, queue); | |
1950 | (void) write_fifo(ep, req); | |
1951 | } | |
1952 | } | |
1953 | /* min 6 clock delay before clearing EP_SEL ... */ | |
f35ae634 TL |
1954 | epn_stat = omap_readw(UDC_EPN_STAT); |
1955 | epn_stat = omap_readw(UDC_EPN_STAT); | |
1956 | omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM); | |
1da177e4 LT |
1957 | /* then 6 clocks before it'd tx */ |
1958 | } | |
1959 | ||
1960 | spin_unlock_irqrestore(&udc->lock, flags); | |
1961 | return status; | |
1962 | } | |
1963 | ||
1964 | #ifdef USE_ISO | |
7d12e780 | 1965 | static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) |
1da177e4 LT |
1966 | { |
1967 | struct omap_udc *udc = _dev; | |
1968 | struct omap_ep *ep; | |
1969 | int pending = 0; | |
1970 | unsigned long flags; | |
1971 | ||
1972 | spin_lock_irqsave(&udc->lock, flags); | |
1973 | ||
1974 | /* handle all non-DMA ISO transfers */ | |
80dd1358 | 1975 | list_for_each_entry(ep, &udc->iso, iso) { |
1da177e4 LT |
1976 | u16 stat; |
1977 | struct omap_req *req; | |
1978 | ||
1979 | if (ep->has_dma || list_empty(&ep->queue)) | |
1980 | continue; | |
1981 | req = list_entry(ep->queue.next, struct omap_req, queue); | |
1982 | ||
1983 | use_ep(ep, UDC_EP_SEL); | |
f35ae634 | 1984 | stat = omap_readw(UDC_STAT_FLG); |
1da177e4 LT |
1985 | |
1986 | /* NOTE: like the other controller drivers, this isn't | |
1987 | * currently reporting lost or damaged frames. | |
1988 | */ | |
1989 | if (ep->bEndpointAddress & USB_DIR_IN) { | |
1990 | if (stat & UDC_MISS_IN) | |
1991 | /* done(ep, req, -EPROTO) */; | |
1992 | else | |
1993 | write_fifo(ep, req); | |
1994 | } else { | |
1995 | int status = 0; | |
1996 | ||
1997 | if (stat & UDC_NO_RXPACKET) | |
1998 | status = -EREMOTEIO; | |
1999 | else if (stat & UDC_ISO_ERR) | |
2000 | status = -EILSEQ; | |
2001 | else if (stat & UDC_DATA_FLUSH) | |
2002 | status = -ENOSR; | |
2003 | ||
2004 | if (status) | |
2005 | /* done(ep, req, status) */; | |
2006 | else | |
2007 | read_fifo(ep, req); | |
2008 | } | |
2009 | deselect_ep(); | |
2010 | /* 6 wait states before next EP */ | |
2011 | ||
2012 | ep->irqs++; | |
2013 | if (!list_empty(&ep->queue)) | |
2014 | pending = 1; | |
2015 | } | |
f35ae634 TL |
2016 | if (!pending) { |
2017 | u16 w; | |
2018 | ||
2019 | w = omap_readw(UDC_IRQ_EN); | |
2020 | w &= ~UDC_SOF_IE; | |
2021 | omap_writew(w, UDC_IRQ_EN); | |
2022 | } | |
2023 | omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC); | |
1da177e4 LT |
2024 | |
2025 | spin_unlock_irqrestore(&udc->lock, flags); | |
2026 | return IRQ_HANDLED; | |
2027 | } | |
2028 | #endif | |
2029 | ||
2030 | /*-------------------------------------------------------------------------*/ | |
2031 | ||
8a3c1f57 | 2032 | static inline int machine_without_vbus_sense(void) |
e6a6e472 | 2033 | { |
80dd1358 | 2034 | return machine_is_omap_innovator() |
e6a6e472 | 2035 | || machine_is_omap_osk() |
e6a6e472 | 2036 | || machine_is_sx1() |
80dd1358 FB |
2037 | /* No known omap7xx boards with vbus sense */ |
2038 | || cpu_is_omap7xx(); | |
e6a6e472 | 2039 | } |
1da177e4 | 2040 | |
1bf0cf60 FB |
2041 | static int omap_udc_start(struct usb_gadget *g, |
2042 | struct usb_gadget_driver *driver) | |
1da177e4 LT |
2043 | { |
2044 | int status = -ENODEV; | |
2045 | struct omap_ep *ep; | |
2046 | unsigned long flags; | |
2047 | ||
1da177e4 LT |
2048 | |
2049 | spin_lock_irqsave(&udc->lock, flags); | |
1da177e4 | 2050 | /* reset state */ |
80dd1358 | 2051 | list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { |
1da177e4 LT |
2052 | ep->irqs = 0; |
2053 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) | |
2054 | continue; | |
2055 | use_ep(ep, 0); | |
f35ae634 | 2056 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1da177e4 LT |
2057 | } |
2058 | udc->ep0_pending = 0; | |
2059 | udc->ep[0].irqs = 0; | |
2060 | udc->softconnect = 1; | |
2061 | ||
2062 | /* hook up the driver */ | |
313980c9 | 2063 | driver->driver.bus = NULL; |
1da177e4 | 2064 | udc->driver = driver; |
1da177e4 LT |
2065 | spin_unlock_irqrestore(&udc->lock, flags); |
2066 | ||
e6a6e472 DB |
2067 | if (udc->dc_clk != NULL) |
2068 | omap_udc_enable_clock(1); | |
2069 | ||
f35ae634 | 2070 | omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); |
1da177e4 LT |
2071 | |
2072 | /* connect to bus through transceiver */ | |
ded017ee | 2073 | if (!IS_ERR_OR_NULL(udc->transceiver)) { |
6e13c650 HK |
2074 | status = otg_set_peripheral(udc->transceiver->otg, |
2075 | &udc->gadget); | |
1da177e4 LT |
2076 | if (status < 0) { |
2077 | ERR("can't bind to transceiver\n"); | |
50f741c8 | 2078 | udc->driver = NULL; |
1da177e4 LT |
2079 | goto done; |
2080 | } | |
2081 | } else { | |
2082 | if (can_pullup(udc)) | |
80dd1358 | 2083 | pullup_enable(udc); |
1da177e4 | 2084 | else |
80dd1358 | 2085 | pullup_disable(udc); |
1da177e4 LT |
2086 | } |
2087 | ||
2088 | /* boards that don't have VBUS sensing can't autogate 48MHz; | |
2089 | * can't enter deep sleep while a gadget driver is active. | |
2090 | */ | |
8a3c1f57 | 2091 | if (machine_without_vbus_sense()) |
1da177e4 LT |
2092 | omap_vbus_session(&udc->gadget, 1); |
2093 | ||
2094 | done: | |
e6a6e472 DB |
2095 | if (udc->dc_clk != NULL) |
2096 | omap_udc_enable_clock(0); | |
1bf0cf60 | 2097 | |
1da177e4 LT |
2098 | return status; |
2099 | } | |
1da177e4 | 2100 | |
22835b80 | 2101 | static int omap_udc_stop(struct usb_gadget *g) |
1da177e4 LT |
2102 | { |
2103 | unsigned long flags; | |
2104 | int status = -ENODEV; | |
2105 | ||
e6a6e472 DB |
2106 | if (udc->dc_clk != NULL) |
2107 | omap_udc_enable_clock(1); | |
2108 | ||
8a3c1f57 | 2109 | if (machine_without_vbus_sense()) |
1da177e4 LT |
2110 | omap_vbus_session(&udc->gadget, 0); |
2111 | ||
ded017ee | 2112 | if (!IS_ERR_OR_NULL(udc->transceiver)) |
6e13c650 | 2113 | (void) otg_set_peripheral(udc->transceiver->otg, NULL); |
1da177e4 LT |
2114 | else |
2115 | pullup_disable(udc); | |
2116 | ||
2117 | spin_lock_irqsave(&udc->lock, flags); | |
2118 | udc_quiesce(udc); | |
2119 | spin_unlock_irqrestore(&udc->lock, flags); | |
2120 | ||
313980c9 | 2121 | udc->driver = NULL; |
1da177e4 | 2122 | |
e6a6e472 DB |
2123 | if (udc->dc_clk != NULL) |
2124 | omap_udc_enable_clock(0); | |
1bf0cf60 | 2125 | |
1da177e4 LT |
2126 | return status; |
2127 | } | |
1da177e4 LT |
2128 | |
2129 | /*-------------------------------------------------------------------------*/ | |
2130 | ||
2131 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
2132 | ||
2133 | #include <linux/seq_file.h> | |
2134 | ||
2135 | static const char proc_filename[] = "driver/udc"; | |
2136 | ||
2137 | #define FOURBITS "%s%s%s%s" | |
80dd1358 | 2138 | #define EIGHTBITS "%s%s%s%s%s%s%s%s" |
1da177e4 LT |
2139 | |
2140 | static void proc_ep_show(struct seq_file *s, struct omap_ep *ep) | |
2141 | { | |
2142 | u16 stat_flg; | |
2143 | struct omap_req *req; | |
2144 | char buf[20]; | |
2145 | ||
2146 | use_ep(ep, 0); | |
2147 | ||
2148 | if (use_dma && ep->has_dma) | |
2149 | snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ", | |
2150 | (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r', | |
2151 | ep->dma_channel - 1, ep->lch); | |
2152 | else | |
2153 | buf[0] = 0; | |
2154 | ||
f35ae634 | 2155 | stat_flg = omap_readw(UDC_STAT_FLG); |
1da177e4 LT |
2156 | seq_printf(s, |
2157 | "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", | |
2158 | ep->name, buf, | |
2159 | ep->double_buf ? "dbuf " : "", | |
80dd1358 FB |
2160 | ({ char *s; |
2161 | switch (ep->ackwait) { | |
2162 | case 0: | |
2163 | s = ""; | |
2164 | break; | |
2165 | case 1: | |
2166 | s = "(ackw) "; | |
2167 | break; | |
2168 | case 2: | |
2169 | s = "(ackw2) "; | |
2170 | break; | |
2171 | default: | |
2172 | s = "(?) "; | |
2173 | break; | |
2174 | } s; }), | |
1da177e4 LT |
2175 | ep->irqs, stat_flg, |
2176 | (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "", | |
2177 | (stat_flg & UDC_MISS_IN) ? "miss_in " : "", | |
2178 | (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "", | |
2179 | (stat_flg & UDC_ISO_ERR) ? "iso_err " : "", | |
2180 | (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "", | |
2181 | (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "", | |
2182 | (stat_flg & UDC_EP_HALTED) ? "HALT " : "", | |
2183 | (stat_flg & UDC_STALL) ? "STALL " : "", | |
2184 | (stat_flg & UDC_NAK) ? "NAK " : "", | |
2185 | (stat_flg & UDC_ACK) ? "ACK " : "", | |
2186 | (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "", | |
2187 | (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "", | |
2188 | (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : ""); | |
2189 | ||
80dd1358 | 2190 | if (list_empty(&ep->queue)) |
1da177e4 LT |
2191 | seq_printf(s, "\t(queue empty)\n"); |
2192 | else | |
80dd1358 | 2193 | list_for_each_entry(req, &ep->queue, queue) { |
1da177e4 LT |
2194 | unsigned length = req->req.actual; |
2195 | ||
2196 | if (use_dma && buf[0]) { | |
2197 | length += ((ep->bEndpointAddress & USB_DIR_IN) | |
2198 | ? dma_src_len : dma_dest_len) | |
2199 | (ep, req->req.dma + length); | |
2200 | buf[0] = 0; | |
2201 | } | |
2202 | seq_printf(s, "\treq %p len %d/%d buf %p\n", | |
2203 | &req->req, length, | |
2204 | req->req.length, req->req.buf); | |
2205 | } | |
2206 | } | |
2207 | ||
2208 | static char *trx_mode(unsigned m, int enabled) | |
2209 | { | |
2210 | switch (m) { | |
80dd1358 FB |
2211 | case 0: |
2212 | return enabled ? "*6wire" : "unused"; | |
2213 | case 1: | |
2214 | return "4wire"; | |
2215 | case 2: | |
2216 | return "3wire"; | |
2217 | case 3: | |
2218 | return "6wire"; | |
2219 | default: | |
2220 | return "unknown"; | |
1da177e4 LT |
2221 | } |
2222 | } | |
2223 | ||
2224 | static int proc_otg_show(struct seq_file *s) | |
2225 | { | |
2226 | u32 tmp; | |
4814ced5 PW |
2227 | u32 trans = 0; |
2228 | char *ctrl_name = "(UNKNOWN)"; | |
1da177e4 | 2229 | |
e12cc345 | 2230 | tmp = omap_readl(OTG_REV); |
ae372571 TL |
2231 | ctrl_name = "tranceiver_ctrl"; |
2232 | trans = omap_readw(USB_TRANSCEIVER_CTRL); | |
e6a6e472 DB |
2233 | seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", |
2234 | tmp >> 4, tmp & 0xf, ctrl_name, trans); | |
f35ae634 | 2235 | tmp = omap_readw(OTG_SYSCON_1); |
1da177e4 LT |
2236 | seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," |
2237 | FOURBITS "\n", tmp, | |
2238 | trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), | |
2239 | trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R), | |
65111084 | 2240 | (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710()) |
1da177e4 LT |
2241 | ? "internal" |
2242 | : trx_mode(USB0_TRX_MODE(tmp), 1), | |
2243 | (tmp & OTG_IDLE_EN) ? " !otg" : "", | |
2244 | (tmp & HST_IDLE_EN) ? " !host" : "", | |
2245 | (tmp & DEV_IDLE_EN) ? " !dev" : "", | |
2246 | (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); | |
f35ae634 | 2247 | tmp = omap_readl(OTG_SYSCON_2); |
1da177e4 LT |
2248 | seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS |
2249 | " b_ase_brst=%d hmc=%d\n", tmp, | |
2250 | (tmp & OTG_EN) ? " otg_en" : "", | |
2251 | (tmp & USBX_SYNCHRO) ? " synchro" : "", | |
80dd1358 | 2252 | /* much more SRP stuff */ |
1da177e4 LT |
2253 | (tmp & SRP_DATA) ? " srp_data" : "", |
2254 | (tmp & SRP_VBUS) ? " srp_vbus" : "", | |
2255 | (tmp & OTG_PADEN) ? " otg_paden" : "", | |
2256 | (tmp & HMC_PADEN) ? " hmc_paden" : "", | |
2257 | (tmp & UHOST_EN) ? " uhost_en" : "", | |
2258 | (tmp & HMC_TLLSPEED) ? " tllspeed" : "", | |
2259 | (tmp & HMC_TLLATTACH) ? " tllattach" : "", | |
2260 | B_ASE_BRST(tmp), | |
2261 | OTG_HMC(tmp)); | |
f35ae634 | 2262 | tmp = omap_readl(OTG_CTRL); |
1da177e4 LT |
2263 | seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, |
2264 | (tmp & OTG_ASESSVLD) ? " asess" : "", | |
2265 | (tmp & OTG_BSESSEND) ? " bsess_end" : "", | |
2266 | (tmp & OTG_BSESSVLD) ? " bsess" : "", | |
2267 | (tmp & OTG_VBUSVLD) ? " vbus" : "", | |
2268 | (tmp & OTG_ID) ? " id" : "", | |
2269 | (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST", | |
2270 | (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "", | |
2271 | (tmp & OTG_A_BUSREQ) ? " a_bus" : "", | |
2272 | (tmp & OTG_B_HNPEN) ? " b_hnpen" : "", | |
2273 | (tmp & OTG_B_BUSREQ) ? " b_bus" : "", | |
2274 | (tmp & OTG_BUSDROP) ? " busdrop" : "", | |
2275 | (tmp & OTG_PULLDOWN) ? " down" : "", | |
2276 | (tmp & OTG_PULLUP) ? " up" : "", | |
2277 | (tmp & OTG_DRV_VBUS) ? " drv" : "", | |
2278 | (tmp & OTG_PD_VBUS) ? " pd_vb" : "", | |
2279 | (tmp & OTG_PU_VBUS) ? " pu_vb" : "", | |
2280 | (tmp & OTG_PU_ID) ? " pu_id" : "" | |
2281 | ); | |
f35ae634 | 2282 | tmp = omap_readw(OTG_IRQ_EN); |
1da177e4 | 2283 | seq_printf(s, "otg_irq_en %04x" "\n", tmp); |
f35ae634 | 2284 | tmp = omap_readw(OTG_IRQ_SRC); |
1da177e4 | 2285 | seq_printf(s, "otg_irq_src %04x" "\n", tmp); |
f35ae634 | 2286 | tmp = omap_readw(OTG_OUTCTRL); |
1da177e4 | 2287 | seq_printf(s, "otg_outctrl %04x" "\n", tmp); |
f35ae634 | 2288 | tmp = omap_readw(OTG_TEST); |
1da177e4 | 2289 | seq_printf(s, "otg_test %04x" "\n", tmp); |
313980c9 | 2290 | return 0; |
1da177e4 LT |
2291 | } |
2292 | ||
2293 | static int proc_udc_show(struct seq_file *s, void *_) | |
2294 | { | |
2295 | u32 tmp; | |
2296 | struct omap_ep *ep; | |
2297 | unsigned long flags; | |
2298 | ||
2299 | spin_lock_irqsave(&udc->lock, flags); | |
2300 | ||
2301 | seq_printf(s, "%s, version: " DRIVER_VERSION | |
2302 | #ifdef USE_ISO | |
2303 | " (iso)" | |
2304 | #endif | |
2305 | "%s\n", | |
2306 | driver_desc, | |
2307 | use_dma ? " (dma)" : ""); | |
2308 | ||
f35ae634 | 2309 | tmp = omap_readw(UDC_REV) & 0xff; |
1da177e4 LT |
2310 | seq_printf(s, |
2311 | "UDC rev %d.%d, fifo mode %d, gadget %s\n" | |
2312 | "hmc %d, transceiver %s\n", | |
2313 | tmp >> 4, tmp & 0xf, | |
2314 | fifo_mode, | |
2315 | udc->driver ? udc->driver->driver.name : "(none)", | |
2316 | HMC, | |
e6a6e472 DB |
2317 | udc->transceiver |
2318 | ? udc->transceiver->label | |
ae372571 | 2319 | : (cpu_is_omap1710() |
e6a6e472 | 2320 | ? "external" : "(none)")); |
ae372571 TL |
2321 | seq_printf(s, "ULPD control %04x req %04x status %04x\n", |
2322 | omap_readw(ULPD_CLOCK_CTRL), | |
2323 | omap_readw(ULPD_SOFT_REQ), | |
2324 | omap_readw(ULPD_STATUS_REQ)); | |
1da177e4 LT |
2325 | |
2326 | /* OTG controller registers */ | |
2327 | if (!cpu_is_omap15xx()) | |
2328 | proc_otg_show(s); | |
2329 | ||
f35ae634 | 2330 | tmp = omap_readw(UDC_SYSCON1); |
1da177e4 LT |
2331 | seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, |
2332 | (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", | |
2333 | (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", | |
2334 | (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "", | |
2335 | (tmp & UDC_NAK_EN) ? " nak" : "", | |
2336 | (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "", | |
2337 | (tmp & UDC_SELF_PWR) ? " self_pwr" : "", | |
2338 | (tmp & UDC_SOFF_DIS) ? " soff_dis" : "", | |
2339 | (tmp & UDC_PULLUP_EN) ? " PULLUP" : ""); | |
80dd1358 | 2340 | /* syscon2 is write-only */ |
1da177e4 LT |
2341 | |
2342 | /* UDC controller registers */ | |
2343 | if (!(tmp & UDC_PULLUP_EN)) { | |
2344 | seq_printf(s, "(suspended)\n"); | |
2345 | spin_unlock_irqrestore(&udc->lock, flags); | |
2346 | return 0; | |
2347 | } | |
2348 | ||
f35ae634 | 2349 | tmp = omap_readw(UDC_DEVSTAT); |
1da177e4 LT |
2350 | seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, |
2351 | (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", | |
2352 | (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", | |
2353 | (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "", | |
2354 | (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "", | |
2355 | (tmp & UDC_USB_RESET) ? " usb_reset" : "", | |
2356 | (tmp & UDC_SUS) ? " SUS" : "", | |
2357 | (tmp & UDC_CFG) ? " CFG" : "", | |
2358 | (tmp & UDC_ADD) ? " ADD" : "", | |
2359 | (tmp & UDC_DEF) ? " DEF" : "", | |
2360 | (tmp & UDC_ATT) ? " ATT" : ""); | |
f35ae634 TL |
2361 | seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF)); |
2362 | tmp = omap_readw(UDC_IRQ_EN); | |
1da177e4 LT |
2363 | seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, |
2364 | (tmp & UDC_SOF_IE) ? " sof" : "", | |
2365 | (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", | |
2366 | (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", | |
2367 | (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", | |
2368 | (tmp & UDC_EP0_IE) ? " ep0" : ""); | |
f35ae634 | 2369 | tmp = omap_readw(UDC_IRQ_SRC); |
1da177e4 LT |
2370 | seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, |
2371 | (tmp & UDC_TXN_DONE) ? " txn_done" : "", | |
2372 | (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", | |
2373 | (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", | |
f35ae634 | 2374 | (tmp & UDC_IRQ_SOF) ? " sof" : "", |
1da177e4 LT |
2375 | (tmp & UDC_EPN_RX) ? " epn_rx" : "", |
2376 | (tmp & UDC_EPN_TX) ? " epn_tx" : "", | |
2377 | (tmp & UDC_DS_CHG) ? " ds_chg" : "", | |
2378 | (tmp & UDC_SETUP) ? " setup" : "", | |
2379 | (tmp & UDC_EP0_RX) ? " ep0out" : "", | |
2380 | (tmp & UDC_EP0_TX) ? " ep0in" : ""); | |
2381 | if (use_dma) { | |
2382 | unsigned i; | |
2383 | ||
f35ae634 | 2384 | tmp = omap_readw(UDC_DMA_IRQ_EN); |
1da177e4 LT |
2385 | seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, |
2386 | (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", | |
2387 | (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", | |
2388 | (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "", | |
2389 | ||
2390 | (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "", | |
2391 | (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "", | |
2392 | (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "", | |
2393 | ||
2394 | (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "", | |
2395 | (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", | |
2396 | (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); | |
2397 | ||
f35ae634 | 2398 | tmp = omap_readw(UDC_RXDMA_CFG); |
1da177e4 LT |
2399 | seq_printf(s, "rxdma_cfg %04x\n", tmp); |
2400 | if (tmp) { | |
2401 | for (i = 0; i < 3; i++) { | |
2402 | if ((tmp & (0x0f << (i * 4))) == 0) | |
2403 | continue; | |
2404 | seq_printf(s, "rxdma[%d] %04x\n", i, | |
f35ae634 | 2405 | omap_readw(UDC_RXDMA(i + 1))); |
1da177e4 LT |
2406 | } |
2407 | } | |
f35ae634 | 2408 | tmp = omap_readw(UDC_TXDMA_CFG); |
1da177e4 LT |
2409 | seq_printf(s, "txdma_cfg %04x\n", tmp); |
2410 | if (tmp) { | |
2411 | for (i = 0; i < 3; i++) { | |
2412 | if (!(tmp & (0x0f << (i * 4)))) | |
2413 | continue; | |
2414 | seq_printf(s, "txdma[%d] %04x\n", i, | |
f35ae634 | 2415 | omap_readw(UDC_TXDMA(i + 1))); |
1da177e4 LT |
2416 | } |
2417 | } | |
2418 | } | |
2419 | ||
f35ae634 | 2420 | tmp = omap_readw(UDC_DEVSTAT); |
1da177e4 LT |
2421 | if (tmp & UDC_ATT) { |
2422 | proc_ep_show(s, &udc->ep[0]); | |
2423 | if (tmp & UDC_ADD) { | |
80dd1358 | 2424 | list_for_each_entry(ep, &udc->gadget.ep_list, |
1da177e4 | 2425 | ep.ep_list) { |
f8bdae06 | 2426 | if (ep->ep.desc) |
1da177e4 LT |
2427 | proc_ep_show(s, ep); |
2428 | } | |
2429 | } | |
2430 | } | |
2431 | spin_unlock_irqrestore(&udc->lock, flags); | |
2432 | return 0; | |
2433 | } | |
2434 | ||
1da177e4 LT |
2435 | static void create_proc_file(void) |
2436 | { | |
3f3942ac | 2437 | proc_create_single(proc_filename, 0, NULL, proc_udc_show); |
1da177e4 LT |
2438 | } |
2439 | ||
2440 | static void remove_proc_file(void) | |
2441 | { | |
313980c9 | 2442 | remove_proc_entry(proc_filename, NULL); |
1da177e4 LT |
2443 | } |
2444 | ||
2445 | #else | |
2446 | ||
2447 | static inline void create_proc_file(void) {} | |
2448 | static inline void remove_proc_file(void) {} | |
2449 | ||
2450 | #endif | |
2451 | ||
2452 | /*-------------------------------------------------------------------------*/ | |
2453 | ||
2454 | /* Before this controller can enumerate, we need to pick an endpoint | |
2455 | * configuration, or "fifo_mode" That involves allocating 2KB of packet | |
2456 | * buffer space among the endpoints we'll be operating. | |
65111084 DB |
2457 | * |
2458 | * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when | |
f35ae634 | 2459 | * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that |
65111084 | 2460 | * capability yet though. |
1da177e4 | 2461 | */ |
41ac7b3a | 2462 | static unsigned |
1da177e4 LT |
2463 | omap_ep_setup(char *name, u8 addr, u8 type, |
2464 | unsigned buf, unsigned maxp, int dbuf) | |
2465 | { | |
2466 | struct omap_ep *ep; | |
2467 | u16 epn_rxtx = 0; | |
2468 | ||
2469 | /* OUT endpoints first, then IN */ | |
2470 | ep = &udc->ep[addr & 0xf]; | |
2471 | if (addr & USB_DIR_IN) | |
2472 | ep += 16; | |
2473 | ||
2474 | /* in case of ep init table bugs */ | |
2475 | BUG_ON(ep->name[0]); | |
2476 | ||
2477 | /* chip setup ... bit values are same for IN, OUT */ | |
2478 | if (type == USB_ENDPOINT_XFER_ISOC) { | |
2479 | switch (maxp) { | |
80dd1358 FB |
2480 | case 8: |
2481 | epn_rxtx = 0 << 12; | |
2482 | break; | |
2483 | case 16: | |
2484 | epn_rxtx = 1 << 12; | |
2485 | break; | |
2486 | case 32: | |
2487 | epn_rxtx = 2 << 12; | |
2488 | break; | |
2489 | case 64: | |
2490 | epn_rxtx = 3 << 12; | |
2491 | break; | |
2492 | case 128: | |
2493 | epn_rxtx = 4 << 12; | |
2494 | break; | |
2495 | case 256: | |
2496 | epn_rxtx = 5 << 12; | |
2497 | break; | |
2498 | case 512: | |
2499 | epn_rxtx = 6 << 12; | |
2500 | break; | |
2501 | default: | |
2502 | BUG(); | |
1da177e4 LT |
2503 | } |
2504 | epn_rxtx |= UDC_EPN_RX_ISO; | |
2505 | dbuf = 1; | |
2506 | } else { | |
2507 | /* double-buffering "not supported" on 15xx, | |
e6a6e472 DB |
2508 | * and ignored for PIO-IN on newer chips |
2509 | * (for more reliable behavior) | |
1da177e4 | 2510 | */ |
ae372571 | 2511 | if (!use_dma || cpu_is_omap15xx()) |
1da177e4 LT |
2512 | dbuf = 0; |
2513 | ||
2514 | switch (maxp) { | |
80dd1358 FB |
2515 | case 8: |
2516 | epn_rxtx = 0 << 12; | |
2517 | break; | |
2518 | case 16: | |
2519 | epn_rxtx = 1 << 12; | |
2520 | break; | |
2521 | case 32: | |
2522 | epn_rxtx = 2 << 12; | |
2523 | break; | |
2524 | case 64: | |
2525 | epn_rxtx = 3 << 12; | |
2526 | break; | |
2527 | default: | |
2528 | BUG(); | |
1da177e4 LT |
2529 | } |
2530 | if (dbuf && addr) | |
2531 | epn_rxtx |= UDC_EPN_RX_DB; | |
e99e88a9 | 2532 | timer_setup(&ep->timer, pio_out_timer, 0); |
1da177e4 LT |
2533 | } |
2534 | if (addr) | |
2535 | epn_rxtx |= UDC_EPN_RX_VALID; | |
2536 | BUG_ON(buf & 0x07); | |
2537 | epn_rxtx |= buf >> 3; | |
2538 | ||
2539 | DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n", | |
2540 | name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); | |
2541 | ||
2542 | if (addr & USB_DIR_IN) | |
f35ae634 | 2543 | omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf)); |
1da177e4 | 2544 | else |
f35ae634 | 2545 | omap_writew(epn_rxtx, UDC_EP_RX(addr)); |
1da177e4 LT |
2546 | |
2547 | /* next endpoint's buffer starts after this one's */ | |
2548 | buf += maxp; | |
2549 | if (dbuf) | |
2550 | buf += maxp; | |
2551 | BUG_ON(buf > 2048); | |
2552 | ||
2553 | /* set up driver data structures */ | |
2554 | BUG_ON(strlen(name) >= sizeof ep->name); | |
2555 | strlcpy(ep->name, name, sizeof ep->name); | |
2556 | INIT_LIST_HEAD(&ep->queue); | |
2557 | INIT_LIST_HEAD(&ep->iso); | |
2558 | ep->bEndpointAddress = addr; | |
2559 | ep->bmAttributes = type; | |
2560 | ep->double_buf = dbuf; | |
e6a6e472 | 2561 | ep->udc = udc; |
1da177e4 | 2562 | |
7d4ba80d RB |
2563 | switch (type) { |
2564 | case USB_ENDPOINT_XFER_CONTROL: | |
2565 | ep->ep.caps.type_control = true; | |
2566 | ep->ep.caps.dir_in = true; | |
2567 | ep->ep.caps.dir_out = true; | |
2568 | break; | |
2569 | case USB_ENDPOINT_XFER_ISOC: | |
2570 | ep->ep.caps.type_iso = true; | |
2571 | break; | |
2572 | case USB_ENDPOINT_XFER_BULK: | |
2573 | ep->ep.caps.type_bulk = true; | |
2574 | break; | |
2575 | case USB_ENDPOINT_XFER_INT: | |
2576 | ep->ep.caps.type_int = true; | |
2577 | break; | |
2578 | }; | |
2579 | ||
2580 | if (addr & USB_DIR_IN) | |
2581 | ep->ep.caps.dir_in = true; | |
2582 | else | |
2583 | ep->ep.caps.dir_out = true; | |
2584 | ||
1da177e4 LT |
2585 | ep->ep.name = ep->name; |
2586 | ep->ep.ops = &omap_ep_ops; | |
e117e742 RB |
2587 | ep->maxpacket = maxp; |
2588 | usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket); | |
80dd1358 | 2589 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); |
1da177e4 LT |
2590 | |
2591 | return buf; | |
2592 | } | |
2593 | ||
2594 | static void omap_udc_release(struct device *dev) | |
2595 | { | |
2596 | complete(udc->done); | |
80dd1358 | 2597 | kfree(udc); |
313980c9 | 2598 | udc = NULL; |
1da177e4 LT |
2599 | } |
2600 | ||
41ac7b3a | 2601 | static int |
86753811 | 2602 | omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv) |
1da177e4 LT |
2603 | { |
2604 | unsigned tmp, buf; | |
2605 | ||
2606 | /* abolish any previous hardware state */ | |
f35ae634 TL |
2607 | omap_writew(0, UDC_SYSCON1); |
2608 | omap_writew(0, UDC_IRQ_EN); | |
2609 | omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); | |
2610 | omap_writew(0, UDC_DMA_IRQ_EN); | |
2611 | omap_writew(0, UDC_RXDMA_CFG); | |
2612 | omap_writew(0, UDC_TXDMA_CFG); | |
1da177e4 LT |
2613 | |
2614 | /* UDC_PULLUP_EN gates the chip clock */ | |
80dd1358 | 2615 | /* OTG_SYSCON_1 |= DEV_IDLE_EN; */ |
1da177e4 | 2616 | |
e94b1766 | 2617 | udc = kzalloc(sizeof(*udc), GFP_KERNEL); |
1da177e4 LT |
2618 | if (!udc) |
2619 | return -ENOMEM; | |
2620 | ||
80dd1358 | 2621 | spin_lock_init(&udc->lock); |
1da177e4 LT |
2622 | |
2623 | udc->gadget.ops = &omap_gadget_ops; | |
2624 | udc->gadget.ep0 = &udc->ep[0].ep; | |
2625 | INIT_LIST_HEAD(&udc->gadget.ep_list); | |
2626 | INIT_LIST_HEAD(&udc->iso); | |
2627 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
d327ab5b | 2628 | udc->gadget.max_speed = USB_SPEED_FULL; |
1da177e4 | 2629 | udc->gadget.name = driver_name; |
1da177e4 LT |
2630 | udc->transceiver = xceiv; |
2631 | ||
2632 | /* ep0 is special; put it right after the SETUP buffer */ | |
2633 | buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL, | |
2634 | 8 /* after SETUP */, 64 /* maxpacket */, 0); | |
2635 | list_del_init(&udc->ep[0].ep.ep_list); | |
2636 | ||
2637 | /* initially disable all non-ep0 endpoints */ | |
2638 | for (tmp = 1; tmp < 15; tmp++) { | |
f35ae634 TL |
2639 | omap_writew(0, UDC_EP_RX(tmp)); |
2640 | omap_writew(0, UDC_EP_TX(tmp)); | |
1da177e4 LT |
2641 | } |
2642 | ||
80dd1358 | 2643 | #define OMAP_BULK_EP(name, addr) \ |
1da177e4 LT |
2644 | buf = omap_ep_setup(name "-bulk", addr, \ |
2645 | USB_ENDPOINT_XFER_BULK, buf, 64, 1); | |
80dd1358 | 2646 | #define OMAP_INT_EP(name, addr, maxp) \ |
1da177e4 LT |
2647 | buf = omap_ep_setup(name "-int", addr, \ |
2648 | USB_ENDPOINT_XFER_INT, buf, maxp, 0); | |
80dd1358 | 2649 | #define OMAP_ISO_EP(name, addr, maxp) \ |
1da177e4 LT |
2650 | buf = omap_ep_setup(name "-iso", addr, \ |
2651 | USB_ENDPOINT_XFER_ISOC, buf, maxp, 1); | |
2652 | ||
2653 | switch (fifo_mode) { | |
2654 | case 0: | |
2655 | OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); | |
2656 | OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); | |
2657 | OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16); | |
2658 | break; | |
2659 | case 1: | |
2660 | OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); | |
2661 | OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); | |
313980c9 DB |
2662 | OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16); |
2663 | ||
1da177e4 LT |
2664 | OMAP_BULK_EP("ep3in", USB_DIR_IN | 3); |
2665 | OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4); | |
313980c9 | 2666 | OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16); |
1da177e4 LT |
2667 | |
2668 | OMAP_BULK_EP("ep5in", USB_DIR_IN | 5); | |
2669 | OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); | |
313980c9 DB |
2670 | OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16); |
2671 | ||
1da177e4 LT |
2672 | OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); |
2673 | OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6); | |
313980c9 | 2674 | OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16); |
1da177e4 LT |
2675 | |
2676 | OMAP_BULK_EP("ep7in", USB_DIR_IN | 7); | |
2677 | OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); | |
313980c9 DB |
2678 | OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16); |
2679 | OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16); | |
2680 | ||
1da177e4 LT |
2681 | OMAP_BULK_EP("ep8in", USB_DIR_IN | 8); |
2682 | OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8); | |
313980c9 DB |
2683 | OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16); |
2684 | OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16); | |
2685 | ||
2686 | OMAP_BULK_EP("ep15in", USB_DIR_IN | 15); | |
2687 | OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15); | |
1da177e4 | 2688 | |
1da177e4 LT |
2689 | break; |
2690 | ||
2691 | #ifdef USE_ISO | |
2692 | case 2: /* mixed iso/bulk */ | |
2693 | OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256); | |
2694 | OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256); | |
2695 | OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128); | |
2696 | OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128); | |
2697 | ||
2698 | OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16); | |
2699 | ||
2700 | OMAP_BULK_EP("ep6in", USB_DIR_IN | 6); | |
2701 | OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7); | |
2702 | OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16); | |
2703 | break; | |
2704 | case 3: /* mixed bulk/iso */ | |
2705 | OMAP_BULK_EP("ep1in", USB_DIR_IN | 1); | |
2706 | OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2); | |
2707 | OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16); | |
2708 | ||
2709 | OMAP_BULK_EP("ep4in", USB_DIR_IN | 4); | |
2710 | OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5); | |
2711 | OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16); | |
2712 | ||
2713 | OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256); | |
2714 | OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256); | |
2715 | OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16); | |
2716 | break; | |
2717 | #endif | |
2718 | ||
2719 | /* add more modes as needed */ | |
2720 | ||
2721 | default: | |
2722 | ERR("unsupported fifo_mode #%d\n", fifo_mode); | |
2723 | return -ENODEV; | |
2724 | } | |
f35ae634 | 2725 | omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1); |
1da177e4 LT |
2726 | INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); |
2727 | return 0; | |
2728 | } | |
2729 | ||
41ac7b3a | 2730 | static int omap_udc_probe(struct platform_device *pdev) |
1da177e4 | 2731 | { |
1da177e4 LT |
2732 | int status = -ENODEV; |
2733 | int hmc; | |
86753811 | 2734 | struct usb_phy *xceiv = NULL; |
313980c9 | 2735 | const char *type = NULL; |
e01ee9f5 | 2736 | struct omap_usb_config *config = dev_get_platdata(&pdev->dev); |
ae372571 TL |
2737 | struct clk *dc_clk = NULL; |
2738 | struct clk *hhc_clk = NULL; | |
1da177e4 | 2739 | |
5b6d84b7 FB |
2740 | if (cpu_is_omap7xx()) |
2741 | use_dma = 0; | |
1da177e4 LT |
2742 | |
2743 | /* NOTE: "knows" the order of the resources! */ | |
e6a6e472 | 2744 | if (!request_mem_region(pdev->resource[0].start, |
3ae5eaec | 2745 | pdev->resource[0].end - pdev->resource[0].start + 1, |
1da177e4 LT |
2746 | driver_name)) { |
2747 | DBG("request_mem_region failed\n"); | |
2748 | return -EBUSY; | |
2749 | } | |
2750 | ||
e6a6e472 DB |
2751 | if (cpu_is_omap16xx()) { |
2752 | dc_clk = clk_get(&pdev->dev, "usb_dc_ck"); | |
2753 | hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck"); | |
2754 | BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); | |
2755 | /* can't use omap_udc_enable_clock yet */ | |
2756 | clk_enable(dc_clk); | |
2757 | clk_enable(hhc_clk); | |
2758 | udelay(100); | |
2759 | } | |
2760 | ||
45f780a0 CM |
2761 | if (cpu_is_omap7xx()) { |
2762 | dc_clk = clk_get(&pdev->dev, "usb_dc_ck"); | |
2763 | hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck"); | |
2764 | BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); | |
2765 | /* can't use omap_udc_enable_clock yet */ | |
2766 | clk_enable(dc_clk); | |
2767 | clk_enable(hhc_clk); | |
2768 | udelay(100); | |
2769 | } | |
2770 | ||
1da177e4 | 2771 | INFO("OMAP UDC rev %d.%d%s\n", |
f35ae634 | 2772 | omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf, |
1da177e4 LT |
2773 | config->otg ? ", Mini-AB" : ""); |
2774 | ||
2775 | /* use the mode given to us by board init code */ | |
2776 | if (cpu_is_omap15xx()) { | |
2777 | hmc = HMC_1510; | |
2778 | type = "(unknown)"; | |
2779 | ||
8a3c1f57 | 2780 | if (machine_without_vbus_sense()) { |
1da177e4 LT |
2781 | /* just set up software VBUS detect, and then |
2782 | * later rig it so we always report VBUS. | |
2783 | * FIXME without really sensing VBUS, we can't | |
2784 | * know when to turn PULLUP_EN on/off; and that | |
2785 | * means we always "need" the 48MHz clock. | |
2786 | */ | |
f35ae634 TL |
2787 | u32 tmp = omap_readl(FUNC_MUX_CTRL_0); |
2788 | tmp &= ~VBUS_CTRL_1510; | |
2789 | omap_writel(tmp, FUNC_MUX_CTRL_0); | |
1da177e4 LT |
2790 | tmp |= VBUS_MODE_1510; |
2791 | tmp &= ~VBUS_CTRL_1510; | |
f35ae634 | 2792 | omap_writel(tmp, FUNC_MUX_CTRL_0); |
1da177e4 LT |
2793 | } |
2794 | } else { | |
65111084 DB |
2795 | /* The transceiver may package some GPIO logic or handle |
2796 | * loopback and/or transceiverless setup; if we find one, | |
2797 | * use it. Except for OTG, we don't _need_ to talk to one; | |
2798 | * but not having one probably means no VBUS detection. | |
2799 | */ | |
662dca54 | 2800 | xceiv = usb_get_phy(USB_PHY_TYPE_USB2); |
ded017ee | 2801 | if (!IS_ERR_OR_NULL(xceiv)) |
65111084 DB |
2802 | type = xceiv->label; |
2803 | else if (config->otg) { | |
2804 | DBG("OTG requires external transceiver!\n"); | |
2805 | goto cleanup0; | |
2806 | } | |
2807 | ||
1da177e4 | 2808 | hmc = HMC_1610; |
e6a6e472 | 2809 | |
1da177e4 | 2810 | switch (hmc) { |
313980c9 DB |
2811 | case 0: /* POWERUP DEFAULT == 0 */ |
2812 | case 4: | |
2813 | case 12: | |
2814 | case 20: | |
2815 | if (!cpu_is_omap1710()) { | |
2816 | type = "integrated"; | |
2817 | break; | |
2818 | } | |
2819 | /* FALL THROUGH */ | |
1da177e4 LT |
2820 | case 3: |
2821 | case 11: | |
2822 | case 16: | |
2823 | case 19: | |
2824 | case 25: | |
ded017ee | 2825 | if (IS_ERR_OR_NULL(xceiv)) { |
1da177e4 | 2826 | DBG("external transceiver not registered!\n"); |
313980c9 | 2827 | type = "unknown"; |
65111084 | 2828 | } |
1da177e4 | 2829 | break; |
1da177e4 | 2830 | case 21: /* internal loopback */ |
313980c9 | 2831 | type = "loopback"; |
1da177e4 LT |
2832 | break; |
2833 | case 14: /* transceiverless */ | |
65111084 DB |
2834 | if (cpu_is_omap1710()) |
2835 | goto bad_on_1710; | |
2836 | /* FALL THROUGH */ | |
2837 | case 13: | |
2838 | case 15: | |
313980c9 | 2839 | type = "no"; |
1da177e4 LT |
2840 | break; |
2841 | ||
2842 | default: | |
65111084 | 2843 | bad_on_1710: |
1da177e4 | 2844 | ERR("unrecognized UDC HMC mode %d\n", hmc); |
65111084 | 2845 | goto cleanup0; |
1da177e4 LT |
2846 | } |
2847 | } | |
ae372571 | 2848 | |
313980c9 | 2849 | INFO("hmc mode %d, %s transceiver\n", hmc, type); |
1da177e4 LT |
2850 | |
2851 | /* a "gadget" abstracts/virtualizes the controller */ | |
3ae5eaec | 2852 | status = omap_udc_setup(pdev, xceiv); |
80dd1358 | 2853 | if (status) |
1da177e4 | 2854 | goto cleanup0; |
80dd1358 | 2855 | |
313980c9 | 2856 | xceiv = NULL; |
80dd1358 | 2857 | /* "udc" is now valid */ |
1da177e4 | 2858 | pullup_disable(udc); |
3112fdde | 2859 | #if IS_ENABLED(CONFIG_USB_OHCI_HCD) |
1da177e4 LT |
2860 | udc->gadget.is_otg = (config->otg != 0); |
2861 | #endif | |
2862 | ||
65111084 | 2863 | /* starting with omap1710 es2.0, clear toggle is a separate bit */ |
f35ae634 | 2864 | if (omap_readw(UDC_REV) >= 0x61) |
65111084 DB |
2865 | udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; |
2866 | else | |
2867 | udc->clr_halt = UDC_RESET_EP; | |
2868 | ||
1da177e4 | 2869 | /* USB general purpose IRQ: ep0, state changes, dma, etc */ |
3ae5eaec | 2870 | status = request_irq(pdev->resource[1].start, omap_udc_irq, |
80dd1358 | 2871 | 0, driver_name, udc); |
1da177e4 | 2872 | if (status != 0) { |
e6a6e472 DB |
2873 | ERR("can't get irq %d, err %d\n", |
2874 | (int) pdev->resource[1].start, status); | |
1da177e4 LT |
2875 | goto cleanup1; |
2876 | } | |
2877 | ||
2878 | /* USB "non-iso" IRQ (PIO for all but ep0) */ | |
3ae5eaec | 2879 | status = request_irq(pdev->resource[2].start, omap_udc_pio_irq, |
80dd1358 | 2880 | 0, "omap_udc pio", udc); |
1da177e4 | 2881 | if (status != 0) { |
e6a6e472 DB |
2882 | ERR("can't get irq %d, err %d\n", |
2883 | (int) pdev->resource[2].start, status); | |
1da177e4 LT |
2884 | goto cleanup2; |
2885 | } | |
2886 | #ifdef USE_ISO | |
3ae5eaec | 2887 | status = request_irq(pdev->resource[3].start, omap_udc_iso_irq, |
b5dd18d8 | 2888 | 0, "omap_udc iso", udc); |
1da177e4 | 2889 | if (status != 0) { |
e6a6e472 DB |
2890 | ERR("can't get irq %d, err %d\n", |
2891 | (int) pdev->resource[3].start, status); | |
1da177e4 LT |
2892 | goto cleanup3; |
2893 | } | |
2894 | #endif | |
45f780a0 | 2895 | if (cpu_is_omap16xx() || cpu_is_omap7xx()) { |
e6a6e472 DB |
2896 | udc->dc_clk = dc_clk; |
2897 | udc->hhc_clk = hhc_clk; | |
2898 | clk_disable(hhc_clk); | |
2899 | clk_disable(dc_clk); | |
2900 | } | |
2901 | ||
1da177e4 | 2902 | create_proc_file(); |
2fb29f21 FB |
2903 | status = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget, |
2904 | omap_udc_release); | |
0f91349b SAS |
2905 | if (status) |
2906 | goto cleanup4; | |
2907 | ||
6dfc84fc FB |
2908 | return 0; |
2909 | ||
0f91349b SAS |
2910 | cleanup4: |
2911 | remove_proc_file(); | |
2912 | ||
1da177e4 LT |
2913 | #ifdef USE_ISO |
2914 | cleanup3: | |
3ae5eaec | 2915 | free_irq(pdev->resource[2].start, udc); |
1da177e4 LT |
2916 | #endif |
2917 | ||
2918 | cleanup2: | |
3ae5eaec | 2919 | free_irq(pdev->resource[1].start, udc); |
1da177e4 LT |
2920 | |
2921 | cleanup1: | |
80dd1358 | 2922 | kfree(udc); |
313980c9 | 2923 | udc = NULL; |
1da177e4 LT |
2924 | |
2925 | cleanup0: | |
ded017ee | 2926 | if (!IS_ERR_OR_NULL(xceiv)) |
721002ec | 2927 | usb_put_phy(xceiv); |
e6a6e472 | 2928 | |
ae372571 | 2929 | if (cpu_is_omap16xx() || cpu_is_omap7xx()) { |
e6a6e472 DB |
2930 | clk_disable(hhc_clk); |
2931 | clk_disable(dc_clk); | |
2932 | clk_put(hhc_clk); | |
2933 | clk_put(dc_clk); | |
2934 | } | |
2935 | ||
3ae5eaec RK |
2936 | release_mem_region(pdev->resource[0].start, |
2937 | pdev->resource[0].end - pdev->resource[0].start + 1); | |
e6a6e472 | 2938 | |
1da177e4 LT |
2939 | return status; |
2940 | } | |
2941 | ||
fb4e98ab | 2942 | static int omap_udc_remove(struct platform_device *pdev) |
1da177e4 | 2943 | { |
6e9a4738 | 2944 | DECLARE_COMPLETION_ONSTACK(done); |
1da177e4 LT |
2945 | |
2946 | if (!udc) | |
2947 | return -ENODEV; | |
0f91349b SAS |
2948 | |
2949 | usb_del_gadget_udc(&udc->gadget); | |
6bea476c DB |
2950 | if (udc->driver) |
2951 | return -EBUSY; | |
1da177e4 LT |
2952 | |
2953 | udc->done = &done; | |
2954 | ||
2955 | pullup_disable(udc); | |
ded017ee | 2956 | if (!IS_ERR_OR_NULL(udc->transceiver)) { |
721002ec | 2957 | usb_put_phy(udc->transceiver); |
313980c9 | 2958 | udc->transceiver = NULL; |
1da177e4 | 2959 | } |
f35ae634 | 2960 | omap_writew(0, UDC_SYSCON1); |
1da177e4 LT |
2961 | |
2962 | remove_proc_file(); | |
2963 | ||
2964 | #ifdef USE_ISO | |
3ae5eaec | 2965 | free_irq(pdev->resource[3].start, udc); |
1da177e4 | 2966 | #endif |
3ae5eaec RK |
2967 | free_irq(pdev->resource[2].start, udc); |
2968 | free_irq(pdev->resource[1].start, udc); | |
1da177e4 | 2969 | |
e6a6e472 DB |
2970 | if (udc->dc_clk) { |
2971 | if (udc->clk_requested) | |
2972 | omap_udc_enable_clock(0); | |
2973 | clk_put(udc->hhc_clk); | |
2974 | clk_put(udc->dc_clk); | |
2975 | } | |
2976 | ||
3ae5eaec RK |
2977 | release_mem_region(pdev->resource[0].start, |
2978 | pdev->resource[0].end - pdev->resource[0].start + 1); | |
1da177e4 | 2979 | |
1da177e4 LT |
2980 | wait_for_completion(&done); |
2981 | ||
2982 | return 0; | |
2983 | } | |
2984 | ||
313980c9 DB |
2985 | /* suspend/resume/wakeup from sysfs (echo > power/state) or when the |
2986 | * system is forced into deep sleep | |
2987 | * | |
2988 | * REVISIT we should probably reject suspend requests when there's a host | |
2989 | * session active, rather than disconnecting, at least on boards that can | |
f35ae634 | 2990 | * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to |
313980c9 DB |
2991 | * make host resumes and VBUS detection trigger OMAP wakeup events; that |
2992 | * may involve talking to an external transceiver (e.g. isp1301). | |
2993 | */ | |
1d7beee3 | 2994 | |
3ae5eaec | 2995 | static int omap_udc_suspend(struct platform_device *dev, pm_message_t message) |
1da177e4 | 2996 | { |
313980c9 DB |
2997 | u32 devstat; |
2998 | ||
f35ae634 | 2999 | devstat = omap_readw(UDC_DEVSTAT); |
313980c9 DB |
3000 | |
3001 | /* we're requesting 48 MHz clock if the pullup is enabled | |
3002 | * (== we're attached to the host) and we're not suspended, | |
3003 | * which would prevent entry to deep sleep... | |
3004 | */ | |
3005 | if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) { | |
b6c63937 | 3006 | WARNING("session active; suspend requires disconnect\n"); |
313980c9 DB |
3007 | omap_pullup(&udc->gadget, 0); |
3008 | } | |
1da177e4 | 3009 | |
1da177e4 LT |
3010 | return 0; |
3011 | } | |
3012 | ||
3ae5eaec | 3013 | static int omap_udc_resume(struct platform_device *dev) |
1da177e4 | 3014 | { |
1da177e4 | 3015 | DBG("resume + wakeup/SRP\n"); |
1da177e4 LT |
3016 | omap_pullup(&udc->gadget, 1); |
3017 | ||
3018 | /* maybe the host would enumerate us if we nudged it */ | |
3019 | msleep(100); | |
3020 | return omap_wakeup(&udc->gadget); | |
3021 | } | |
3022 | ||
3023 | /*-------------------------------------------------------------------------*/ | |
3024 | ||
3ae5eaec | 3025 | static struct platform_driver udc_driver = { |
dc1737cd | 3026 | .probe = omap_udc_probe, |
7690417d | 3027 | .remove = omap_udc_remove, |
1da177e4 LT |
3028 | .suspend = omap_udc_suspend, |
3029 | .resume = omap_udc_resume, | |
3ae5eaec | 3030 | .driver = { |
3ae5eaec RK |
3031 | .name = (char *) driver_name, |
3032 | }, | |
1da177e4 LT |
3033 | }; |
3034 | ||
dc1737cd | 3035 | module_platform_driver(udc_driver); |
1da177e4 LT |
3036 | |
3037 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3038 | MODULE_LICENSE("GPL"); | |
f34c32f1 | 3039 | MODULE_ALIAS("platform:omap_udc"); |