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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0+ |
ceb80363 SL |
2 | /* |
3 | * PLX NET2272 high/full speed USB device controller | |
4 | * | |
5 | * Copyright (C) 2005-2006 PLX Technology, Inc. | |
6 | * Copyright (C) 2006-2011 Analog Devices, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #ifndef __NET2272_H__ | |
24 | #define __NET2272_H__ | |
25 | ||
26 | /* Main Registers */ | |
27 | #define REGADDRPTR 0x00 | |
28 | #define REGDATA 0x01 | |
29 | #define IRQSTAT0 0x02 | |
30 | #define ENDPOINT_0_INTERRUPT 0 | |
31 | #define ENDPOINT_A_INTERRUPT 1 | |
32 | #define ENDPOINT_B_INTERRUPT 2 | |
33 | #define ENDPOINT_C_INTERRUPT 3 | |
34 | #define VIRTUALIZED_ENDPOINT_INTERRUPT 4 | |
35 | #define SETUP_PACKET_INTERRUPT 5 | |
36 | #define DMA_DONE_INTERRUPT 6 | |
37 | #define SOF_INTERRUPT 7 | |
38 | #define IRQSTAT1 0x03 | |
39 | #define CONTROL_STATUS_INTERRUPT 1 | |
40 | #define VBUS_INTERRUPT 2 | |
41 | #define SUSPEND_REQUEST_INTERRUPT 3 | |
42 | #define SUSPEND_REQUEST_CHANGE_INTERRUPT 4 | |
43 | #define RESUME_INTERRUPT 5 | |
44 | #define ROOT_PORT_RESET_INTERRUPT 6 | |
45 | #define RESET_STATUS 7 | |
46 | #define PAGESEL 0x04 | |
47 | #define DMAREQ 0x1c | |
48 | #define DMA_ENDPOINT_SELECT 0 | |
49 | #define DREQ_POLARITY 1 | |
50 | #define DACK_POLARITY 2 | |
51 | #define EOT_POLARITY 3 | |
52 | #define DMA_CONTROL_DACK 4 | |
53 | #define DMA_REQUEST_ENABLE 5 | |
54 | #define DMA_REQUEST 6 | |
55 | #define DMA_BUFFER_VALID 7 | |
56 | #define SCRATCH 0x1d | |
57 | #define IRQENB0 0x20 | |
58 | #define ENDPOINT_0_INTERRUPT_ENABLE 0 | |
59 | #define ENDPOINT_A_INTERRUPT_ENABLE 1 | |
60 | #define ENDPOINT_B_INTERRUPT_ENABLE 2 | |
61 | #define ENDPOINT_C_INTERRUPT_ENABLE 3 | |
62 | #define VIRTUALIZED_ENDPOINT_INTERRUPT_ENABLE 4 | |
63 | #define SETUP_PACKET_INTERRUPT_ENABLE 5 | |
64 | #define DMA_DONE_INTERRUPT_ENABLE 6 | |
65 | #define SOF_INTERRUPT_ENABLE 7 | |
66 | #define IRQENB1 0x21 | |
67 | #define VBUS_INTERRUPT_ENABLE 2 | |
68 | #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 | |
69 | #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 4 | |
70 | #define RESUME_INTERRUPT_ENABLE 5 | |
71 | #define ROOT_PORT_RESET_INTERRUPT_ENABLE 6 | |
72 | #define LOCCTL 0x22 | |
73 | #define DATA_WIDTH 0 | |
74 | #define LOCAL_CLOCK_OUTPUT 1 | |
75 | #define LOCAL_CLOCK_OUTPUT_OFF 0 | |
76 | #define LOCAL_CLOCK_OUTPUT_3_75MHZ 1 | |
77 | #define LOCAL_CLOCK_OUTPUT_7_5MHZ 2 | |
78 | #define LOCAL_CLOCK_OUTPUT_15MHZ 3 | |
79 | #define LOCAL_CLOCK_OUTPUT_30MHZ 4 | |
80 | #define LOCAL_CLOCK_OUTPUT_60MHZ 5 | |
81 | #define DMA_SPLIT_BUS_MODE 4 | |
82 | #define BYTE_SWAP 5 | |
83 | #define BUFFER_CONFIGURATION 6 | |
84 | #define BUFFER_CONFIGURATION_EPA512_EPB512 0 | |
85 | #define BUFFER_CONFIGURATION_EPA1024_EPB512 1 | |
86 | #define BUFFER_CONFIGURATION_EPA1024_EPB1024 2 | |
87 | #define BUFFER_CONFIGURATION_EPA1024DB 3 | |
88 | #define CHIPREV_LEGACY 0x23 | |
89 | #define NET2270_LEGACY_REV 0x40 | |
90 | #define LOCCTL1 0x24 | |
91 | #define DMA_MODE 0 | |
92 | #define SLOW_DREQ 0 | |
93 | #define FAST_DREQ 1 | |
94 | #define BURST_MODE 2 | |
95 | #define DMA_DACK_ENABLE 2 | |
96 | #define CHIPREV_2272 0x25 | |
97 | #define CHIPREV_NET2272_R1 0x10 | |
98 | #define CHIPREV_NET2272_R1A 0x11 | |
99 | /* USB Registers */ | |
100 | #define USBCTL0 0x18 | |
101 | #define IO_WAKEUP_ENABLE 1 | |
102 | #define USB_DETECT_ENABLE 3 | |
103 | #define USB_ROOT_PORT_WAKEUP_ENABLE 5 | |
104 | #define USBCTL1 0x19 | |
105 | #define VBUS_PIN 0 | |
106 | #define USB_FULL_SPEED 1 | |
107 | #define USB_HIGH_SPEED 2 | |
108 | #define GENERATE_RESUME 3 | |
109 | #define VIRTUAL_ENDPOINT_ENABLE 4 | |
110 | #define FRAME0 0x1a | |
111 | #define FRAME1 0x1b | |
112 | #define OURADDR 0x30 | |
113 | #define FORCE_IMMEDIATE 7 | |
114 | #define USBDIAG 0x31 | |
115 | #define FORCE_TRANSMIT_CRC_ERROR 0 | |
116 | #define PREVENT_TRANSMIT_BIT_STUFF 1 | |
117 | #define FORCE_RECEIVE_ERROR 2 | |
118 | #define FAST_TIMES 4 | |
119 | #define USBTEST 0x32 | |
120 | #define TEST_MODE_SELECT 0 | |
121 | #define NORMAL_OPERATION 0 | |
122 | #define TEST_J 1 | |
123 | #define TEST_K 2 | |
124 | #define TEST_SE0_NAK 3 | |
125 | #define TEST_PACKET 4 | |
126 | #define TEST_FORCE_ENABLE 5 | |
127 | #define XCVRDIAG 0x33 | |
128 | #define FORCE_FULL_SPEED 2 | |
129 | #define FORCE_HIGH_SPEED 3 | |
130 | #define OPMODE 4 | |
131 | #define NORMAL_OPERATION 0 | |
132 | #define NON_DRIVING 1 | |
133 | #define DISABLE_BITSTUFF_AND_NRZI_ENCODE 2 | |
134 | #define LINESTATE 6 | |
135 | #define SE0_STATE 0 | |
136 | #define J_STATE 1 | |
137 | #define K_STATE 2 | |
138 | #define SE1_STATE 3 | |
139 | #define VIRTOUT0 0x34 | |
140 | #define VIRTOUT1 0x35 | |
141 | #define VIRTIN0 0x36 | |
142 | #define VIRTIN1 0x37 | |
143 | #define SETUP0 0x40 | |
144 | #define SETUP1 0x41 | |
145 | #define SETUP2 0x42 | |
146 | #define SETUP3 0x43 | |
147 | #define SETUP4 0x44 | |
148 | #define SETUP5 0x45 | |
149 | #define SETUP6 0x46 | |
150 | #define SETUP7 0x47 | |
151 | /* Endpoint Registers (Paged via PAGESEL) */ | |
152 | #define EP_DATA 0x05 | |
153 | #define EP_STAT0 0x06 | |
154 | #define DATA_IN_TOKEN_INTERRUPT 0 | |
155 | #define DATA_OUT_TOKEN_INTERRUPT 1 | |
156 | #define DATA_PACKET_TRANSMITTED_INTERRUPT 2 | |
157 | #define DATA_PACKET_RECEIVED_INTERRUPT 3 | |
158 | #define SHORT_PACKET_TRANSFERRED_INTERRUPT 4 | |
159 | #define NAK_OUT_PACKETS 5 | |
160 | #define BUFFER_EMPTY 6 | |
161 | #define BUFFER_FULL 7 | |
162 | #define EP_STAT1 0x07 | |
163 | #define TIMEOUT 0 | |
164 | #define USB_OUT_ACK_SENT 1 | |
165 | #define USB_OUT_NAK_SENT 2 | |
166 | #define USB_IN_ACK_RCVD 3 | |
167 | #define USB_IN_NAK_SENT 4 | |
168 | #define USB_STALL_SENT 5 | |
169 | #define LOCAL_OUT_ZLP 6 | |
170 | #define BUFFER_FLUSH 7 | |
171 | #define EP_TRANSFER0 0x08 | |
172 | #define EP_TRANSFER1 0x09 | |
173 | #define EP_TRANSFER2 0x0a | |
174 | #define EP_IRQENB 0x0b | |
175 | #define DATA_IN_TOKEN_INTERRUPT_ENABLE 0 | |
176 | #define DATA_OUT_TOKEN_INTERRUPT_ENABLE 1 | |
177 | #define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2 | |
178 | #define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3 | |
179 | #define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 4 | |
180 | #define EP_AVAIL0 0x0c | |
181 | #define EP_AVAIL1 0x0d | |
182 | #define EP_RSPCLR 0x0e | |
183 | #define EP_RSPSET 0x0f | |
184 | #define ENDPOINT_HALT 0 | |
185 | #define ENDPOINT_TOGGLE 1 | |
186 | #define NAK_OUT_PACKETS_MODE 2 | |
187 | #define CONTROL_STATUS_PHASE_HANDSHAKE 3 | |
188 | #define INTERRUPT_MODE 4 | |
189 | #define AUTOVALIDATE 5 | |
190 | #define HIDE_STATUS_PHASE 6 | |
191 | #define ALT_NAK_OUT_PACKETS 7 | |
192 | #define EP_MAXPKT0 0x28 | |
193 | #define EP_MAXPKT1 0x29 | |
194 | #define ADDITIONAL_TRANSACTION_OPPORTUNITIES 3 | |
195 | #define NONE_ADDITIONAL_TRANSACTION 0 | |
196 | #define ONE_ADDITIONAL_TRANSACTION 1 | |
197 | #define TWO_ADDITIONAL_TRANSACTION 2 | |
198 | #define EP_CFG 0x2a | |
199 | #define ENDPOINT_NUMBER 0 | |
200 | #define ENDPOINT_DIRECTION 4 | |
201 | #define ENDPOINT_TYPE 5 | |
202 | #define ENDPOINT_ENABLE 7 | |
203 | #define EP_HBW 0x2b | |
204 | #define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 0 | |
205 | #define DATA0_PID 0 | |
206 | #define DATA1_PID 1 | |
207 | #define DATA2_PID 2 | |
208 | #define MDATA_PID 3 | |
209 | #define EP_BUFF_STATES 0x2c | |
210 | #define BUFFER_A_STATE 0 | |
211 | #define BUFFER_B_STATE 2 | |
212 | #define BUFF_FREE 0 | |
213 | #define BUFF_VALID 1 | |
214 | #define BUFF_LCL 2 | |
215 | #define BUFF_USB 3 | |
216 | ||
217 | /*---------------------------------------------------------------------------*/ | |
218 | ||
219 | #define PCI_DEVICE_ID_RDK1 0x9054 | |
220 | ||
221 | /* PCI-RDK EPLD Registers */ | |
222 | #define RDK_EPLD_IO_REGISTER1 0x00000000 | |
223 | #define RDK_EPLD_USB_RESET 0 | |
224 | #define RDK_EPLD_USB_POWERDOWN 1 | |
225 | #define RDK_EPLD_USB_WAKEUP 2 | |
226 | #define RDK_EPLD_USB_EOT 3 | |
227 | #define RDK_EPLD_DPPULL 4 | |
228 | #define RDK_EPLD_IO_REGISTER2 0x00000004 | |
229 | #define RDK_EPLD_BUSWIDTH 0 | |
230 | #define RDK_EPLD_USER 2 | |
231 | #define RDK_EPLD_RESET_INTERRUPT_ENABLE 3 | |
232 | #define RDK_EPLD_DMA_TIMEOUT_ENABLE 4 | |
233 | #define RDK_EPLD_STATUS_REGISTER 0x00000008 | |
234 | #define RDK_EPLD_USB_LRESET 0 | |
235 | #define RDK_EPLD_REVISION_REGISTER 0x0000000c | |
236 | ||
237 | /* PCI-RDK PLX 9054 Registers */ | |
238 | #define INTCSR 0x68 | |
239 | #define PCI_INTERRUPT_ENABLE 8 | |
240 | #define LOCAL_INTERRUPT_INPUT_ENABLE 11 | |
241 | #define LOCAL_INPUT_INTERRUPT_ACTIVE 15 | |
242 | #define LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE 18 | |
243 | #define LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE 19 | |
244 | #define DMA_CHANNEL_0_INTERRUPT_ACTIVE 21 | |
245 | #define DMA_CHANNEL_1_INTERRUPT_ACTIVE 22 | |
246 | #define CNTRL 0x6C | |
247 | #define RELOAD_CONFIGURATION_REGISTERS 29 | |
248 | #define PCI_ADAPTER_SOFTWARE_RESET 30 | |
249 | #define DMAMODE0 0x80 | |
250 | #define LOCAL_BUS_WIDTH 0 | |
251 | #define INTERNAL_WAIT_STATES 2 | |
252 | #define TA_READY_INPUT_ENABLE 6 | |
253 | #define LOCAL_BURST_ENABLE 8 | |
254 | #define SCATTER_GATHER_MODE 9 | |
255 | #define DONE_INTERRUPT_ENABLE 10 | |
256 | #define LOCAL_ADDRESSING_MODE 11 | |
257 | #define DEMAND_MODE 12 | |
258 | #define DMA_EOT_ENABLE 14 | |
259 | #define FAST_SLOW_TERMINATE_MODE_SELECT 15 | |
260 | #define DMA_CHANNEL_INTERRUPT_SELECT 17 | |
261 | #define DMAPADR0 0x84 | |
262 | #define DMALADR0 0x88 | |
263 | #define DMASIZ0 0x8c | |
264 | #define DMADPR0 0x90 | |
265 | #define DESCRIPTOR_LOCATION 0 | |
266 | #define END_OF_CHAIN 1 | |
267 | #define INTERRUPT_AFTER_TERMINAL_COUNT 2 | |
268 | #define DIRECTION_OF_TRANSFER 3 | |
269 | #define DMACSR0 0xa8 | |
270 | #define CHANNEL_ENABLE 0 | |
271 | #define CHANNEL_START 1 | |
272 | #define CHANNEL_ABORT 2 | |
273 | #define CHANNEL_CLEAR_INTERRUPT 3 | |
274 | #define CHANNEL_DONE 4 | |
275 | #define DMATHR 0xb0 | |
276 | #define LBRD1 0xf8 | |
277 | #define MEMORY_SPACE_LOCAL_BUS_WIDTH 0 | |
278 | #define W8_BIT 0 | |
279 | #define W16_BIT 1 | |
280 | ||
281 | /* Special OR'ing of INTCSR bits */ | |
282 | #define LOCAL_INTERRUPT_TEST \ | |
283 | ((1 << LOCAL_INPUT_INTERRUPT_ACTIVE) | \ | |
284 | (1 << LOCAL_INTERRUPT_INPUT_ENABLE)) | |
285 | ||
286 | #define DMA_CHANNEL_0_TEST \ | |
287 | ((1 << DMA_CHANNEL_0_INTERRUPT_ACTIVE) | \ | |
288 | (1 << LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE)) | |
289 | ||
290 | #define DMA_CHANNEL_1_TEST \ | |
291 | ((1 << DMA_CHANNEL_1_INTERRUPT_ACTIVE) | \ | |
292 | (1 << LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE)) | |
293 | ||
294 | /* EPLD Registers */ | |
295 | #define RDK_EPLD_IO_REGISTER1 0x00000000 | |
296 | #define RDK_EPLD_USB_RESET 0 | |
297 | #define RDK_EPLD_USB_POWERDOWN 1 | |
298 | #define RDK_EPLD_USB_WAKEUP 2 | |
299 | #define RDK_EPLD_USB_EOT 3 | |
300 | #define RDK_EPLD_DPPULL 4 | |
301 | #define RDK_EPLD_IO_REGISTER2 0x00000004 | |
302 | #define RDK_EPLD_BUSWIDTH 0 | |
303 | #define RDK_EPLD_USER 2 | |
304 | #define RDK_EPLD_RESET_INTERRUPT_ENABLE 3 | |
305 | #define RDK_EPLD_DMA_TIMEOUT_ENABLE 4 | |
306 | #define RDK_EPLD_STATUS_REGISTER 0x00000008 | |
307 | #define RDK_EPLD_USB_LRESET 0 | |
308 | #define RDK_EPLD_REVISION_REGISTER 0x0000000c | |
309 | ||
310 | #define EPLD_IO_CONTROL_REGISTER 0x400 | |
311 | #define NET2272_RESET 0 | |
312 | #define BUSWIDTH 1 | |
313 | #define MPX_MODE 3 | |
314 | #define USER 4 | |
315 | #define DMA_TIMEOUT_ENABLE 5 | |
316 | #define DMA_CTL_DACK 6 | |
317 | #define EPLD_DMA_ENABLE 7 | |
318 | #define EPLD_DMA_CONTROL_REGISTER 0x800 | |
319 | #define SPLIT_DMA_MODE 0 | |
320 | #define SPLIT_DMA_DIRECTION 1 | |
321 | #define SPLIT_DMA_ENABLE 2 | |
322 | #define SPLIT_DMA_INTERRUPT_ENABLE 3 | |
323 | #define SPLIT_DMA_INTERRUPT 4 | |
324 | #define EPLD_DMA_MODE 5 | |
325 | #define EPLD_DMA_CONTROLLER_ENABLE 7 | |
326 | #define SPLIT_DMA_ADDRESS_LOW 0xc00 | |
327 | #define SPLIT_DMA_ADDRESS_HIGH 0x1000 | |
328 | #define SPLIT_DMA_BYTE_COUNT_LOW 0x1400 | |
329 | #define SPLIT_DMA_BYTE_COUNT_HIGH 0x1800 | |
330 | #define EPLD_REVISION_REGISTER 0x1c00 | |
331 | #define SPLIT_DMA_RAM 0x4000 | |
332 | #define DMA_RAM_SIZE 0x1000 | |
333 | ||
334 | /*---------------------------------------------------------------------------*/ | |
335 | ||
336 | #define PCI_DEVICE_ID_RDK2 0x3272 | |
337 | ||
338 | /* PCI-RDK version 2 registers */ | |
339 | ||
340 | /* Main Control Registers */ | |
341 | ||
342 | #define RDK2_IRQENB 0x00 | |
343 | #define RDK2_IRQSTAT 0x04 | |
344 | #define PB7 23 | |
345 | #define PB6 22 | |
346 | #define PB5 21 | |
347 | #define PB4 20 | |
348 | #define PB3 19 | |
349 | #define PB2 18 | |
350 | #define PB1 17 | |
351 | #define PB0 16 | |
352 | #define GP3 23 | |
353 | #define GP2 23 | |
354 | #define GP1 23 | |
355 | #define GP0 23 | |
356 | #define DMA_RETRY_ABORT 6 | |
357 | #define DMA_PAUSE_DONE 5 | |
358 | #define DMA_ABORT_DONE 4 | |
359 | #define DMA_OUT_FIFO_TRANSFER_DONE 3 | |
360 | #define DMA_LOCAL_DONE 2 | |
361 | #define DMA_PCI_DONE 1 | |
362 | #define NET2272_PCI_IRQ 0 | |
363 | ||
364 | #define RDK2_LOCCTLRDK 0x08 | |
365 | #define CHIP_RESET 3 | |
366 | #define SPLIT_DMA 2 | |
367 | #define MULTIPLEX_MODE 1 | |
368 | #define BUS_WIDTH 0 | |
369 | ||
370 | #define RDK2_GPIOCTL 0x10 | |
371 | #define GP3_OUT_ENABLE 7 | |
372 | #define GP2_OUT_ENABLE 6 | |
373 | #define GP1_OUT_ENABLE 5 | |
374 | #define GP0_OUT_ENABLE 4 | |
375 | #define GP3_DATA 3 | |
376 | #define GP2_DATA 2 | |
377 | #define GP1_DATA 1 | |
378 | #define GP0_DATA 0 | |
379 | ||
380 | #define RDK2_LEDSW 0x14 | |
381 | #define LED3 27 | |
382 | #define LED2 26 | |
383 | #define LED1 25 | |
384 | #define LED0 24 | |
385 | #define PBUTTON 16 | |
386 | #define DIPSW 0 | |
387 | ||
388 | #define RDK2_DIAG 0x18 | |
389 | #define RDK2_FAST_TIMES 2 | |
390 | #define FORCE_PCI_SERR 1 | |
391 | #define FORCE_PCI_INT 0 | |
392 | #define RDK2_FPGAREV 0x1C | |
393 | ||
394 | /* Dma Control registers */ | |
395 | #define RDK2_DMACTL 0x80 | |
396 | #define ADDR_HOLD 24 | |
397 | #define RETRY_COUNT 16 /* 23:16 */ | |
398 | #define FIFO_THRESHOLD 11 /* 15:11 */ | |
399 | #define MEM_WRITE_INVALIDATE 10 | |
400 | #define READ_MULTIPLE 9 | |
401 | #define READ_LINE 8 | |
402 | #define RDK2_DMA_MODE 6 /* 7:6 */ | |
403 | #define CONTROL_DACK 5 | |
404 | #define EOT_ENABLE 4 | |
405 | #define EOT_POLARITY 3 | |
406 | #define DACK_POLARITY 2 | |
407 | #define DREQ_POLARITY 1 | |
408 | #define DMA_ENABLE 0 | |
409 | ||
410 | #define RDK2_DMASTAT 0x84 | |
411 | #define GATHER_COUNT 12 /* 14:12 */ | |
412 | #define FIFO_COUNT 6 /* 11:6 */ | |
413 | #define FIFO_FLUSH 5 | |
414 | #define FIFO_TRANSFER 4 | |
415 | #define PAUSE_DONE 3 | |
416 | #define ABORT_DONE 2 | |
417 | #define DMA_ABORT 1 | |
418 | #define DMA_START 0 | |
419 | ||
420 | #define RDK2_DMAPCICOUNT 0x88 | |
421 | #define DMA_DIRECTION 31 | |
422 | #define DMA_PCI_BYTE_COUNT 0 /* 0:23 */ | |
423 | ||
424 | #define RDK2_DMALOCCOUNT 0x8C /* 0:23 dma local byte count */ | |
425 | ||
426 | #define RDK2_DMAADDR 0x90 /* 2:31 PCI bus starting address */ | |
427 | ||
428 | /*---------------------------------------------------------------------------*/ | |
429 | ||
430 | #define REG_INDEXED_THRESHOLD (1 << 5) | |
431 | ||
432 | /* DRIVER DATA STRUCTURES and UTILITIES */ | |
433 | struct net2272_ep { | |
434 | struct usb_ep ep; | |
435 | struct net2272 *dev; | |
436 | unsigned long irqs; | |
437 | ||
438 | /* analogous to a host-side qh */ | |
439 | struct list_head queue; | |
440 | const struct usb_endpoint_descriptor *desc; | |
441 | unsigned num:8, | |
442 | fifo_size:12, | |
443 | stopped:1, | |
444 | wedged:1, | |
445 | is_in:1, | |
446 | is_iso:1, | |
447 | dma:1, | |
448 | not_empty:1; | |
449 | }; | |
450 | ||
451 | struct net2272 { | |
452 | /* each device provides one gadget, several endpoints */ | |
453 | struct usb_gadget gadget; | |
454 | struct device *dev; | |
455 | unsigned short dev_id; | |
456 | ||
457 | spinlock_t lock; | |
458 | struct net2272_ep ep[4]; | |
459 | struct usb_gadget_driver *driver; | |
460 | unsigned protocol_stall:1, | |
461 | softconnect:1, | |
ceb80363 SL |
462 | wakeup:1, |
463 | dma_eot_polarity:1, | |
464 | dma_dack_polarity:1, | |
465 | dma_dreq_polarity:1, | |
466 | dma_busy:1; | |
467 | u16 chiprev; | |
468 | u8 pagesel; | |
469 | ||
470 | unsigned int irq; | |
471 | unsigned short fifo_mode; | |
472 | ||
473 | unsigned int base_shift; | |
474 | u16 __iomem *base_addr; | |
475 | union { | |
2c93e790 | 476 | #ifdef CONFIG_USB_PCI |
ceb80363 SL |
477 | struct { |
478 | void __iomem *plx9054_base_addr; | |
479 | void __iomem *epld_base_addr; | |
480 | } rdk1; | |
481 | struct { | |
482 | /* Bar0, Bar1 is base_addr both mem-mapped */ | |
483 | void __iomem *fpga_base_addr; | |
484 | } rdk2; | |
485 | #endif | |
486 | }; | |
487 | }; | |
488 | ||
489 | static void __iomem * | |
490 | net2272_reg_addr(struct net2272 *dev, unsigned int reg) | |
491 | { | |
492 | return dev->base_addr + (reg << dev->base_shift); | |
493 | } | |
494 | ||
495 | static void | |
496 | net2272_write(struct net2272 *dev, unsigned int reg, u8 value) | |
497 | { | |
498 | if (reg >= REG_INDEXED_THRESHOLD) { | |
499 | /* | |
500 | * Indexed register; use REGADDRPTR/REGDATA | |
501 | * - Save and restore REGADDRPTR. This prevents REGADDRPTR from | |
502 | * changes between other code sections, but it is time consuming. | |
503 | * - Performance tips: either do not save and restore REGADDRPTR (if it | |
504 | * is safe) or do save/restore operations only in critical sections. | |
505 | u8 tmp = readb(dev->base_addr + REGADDRPTR); | |
506 | */ | |
507 | writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR)); | |
508 | writeb(value, net2272_reg_addr(dev, REGDATA)); | |
509 | /* writeb(tmp, net2272_reg_addr(dev, REGADDRPTR)); */ | |
510 | } else | |
511 | writeb(value, net2272_reg_addr(dev, reg)); | |
512 | } | |
513 | ||
514 | static u8 | |
515 | net2272_read(struct net2272 *dev, unsigned int reg) | |
516 | { | |
517 | u8 ret; | |
518 | ||
519 | if (reg >= REG_INDEXED_THRESHOLD) { | |
520 | /* | |
521 | * Indexed register; use REGADDRPTR/REGDATA | |
522 | * - Save and restore REGADDRPTR. This prevents REGADDRPTR from | |
523 | * changes between other code sections, but it is time consuming. | |
524 | * - Performance tips: either do not save and restore REGADDRPTR (if it | |
525 | * is safe) or do save/restore operations only in critical sections. | |
526 | u8 tmp = readb(dev->base_addr + REGADDRPTR); | |
527 | */ | |
528 | writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR)); | |
529 | ret = readb(net2272_reg_addr(dev, REGDATA)); | |
530 | /* writeb(tmp, net2272_reg_addr(dev, REGADDRPTR)); */ | |
531 | } else | |
532 | ret = readb(net2272_reg_addr(dev, reg)); | |
533 | ||
534 | return ret; | |
535 | } | |
536 | ||
537 | static void | |
538 | net2272_ep_write(struct net2272_ep *ep, unsigned int reg, u8 value) | |
539 | { | |
540 | struct net2272 *dev = ep->dev; | |
541 | ||
542 | if (dev->pagesel != ep->num) { | |
543 | net2272_write(dev, PAGESEL, ep->num); | |
544 | dev->pagesel = ep->num; | |
545 | } | |
546 | net2272_write(dev, reg, value); | |
547 | } | |
548 | ||
549 | static u8 | |
550 | net2272_ep_read(struct net2272_ep *ep, unsigned int reg) | |
551 | { | |
552 | struct net2272 *dev = ep->dev; | |
553 | ||
554 | if (dev->pagesel != ep->num) { | |
555 | net2272_write(dev, PAGESEL, ep->num); | |
556 | dev->pagesel = ep->num; | |
557 | } | |
558 | return net2272_read(dev, reg); | |
559 | } | |
560 | ||
561 | static void allow_status(struct net2272_ep *ep) | |
562 | { | |
563 | /* ep0 only */ | |
564 | net2272_ep_write(ep, EP_RSPCLR, | |
565 | (1 << CONTROL_STATUS_PHASE_HANDSHAKE) | | |
566 | (1 << ALT_NAK_OUT_PACKETS) | | |
567 | (1 << NAK_OUT_PACKETS_MODE)); | |
568 | ep->stopped = 1; | |
569 | } | |
570 | ||
571 | static void set_halt(struct net2272_ep *ep) | |
572 | { | |
573 | /* ep0 and bulk/intr endpoints */ | |
574 | net2272_ep_write(ep, EP_RSPCLR, 1 << CONTROL_STATUS_PHASE_HANDSHAKE); | |
575 | net2272_ep_write(ep, EP_RSPSET, 1 << ENDPOINT_HALT); | |
576 | } | |
577 | ||
578 | static void clear_halt(struct net2272_ep *ep) | |
579 | { | |
580 | /* ep0 and bulk/intr endpoints */ | |
581 | net2272_ep_write(ep, EP_RSPCLR, | |
582 | (1 << ENDPOINT_HALT) | (1 << ENDPOINT_TOGGLE)); | |
583 | } | |
584 | ||
585 | /* count (<= 4) bytes in the next fifo write will be valid */ | |
586 | static void set_fifo_bytecount(struct net2272_ep *ep, unsigned count) | |
587 | { | |
588 | /* net2272_ep_write will truncate to u8 for us */ | |
589 | net2272_ep_write(ep, EP_TRANSFER2, count >> 16); | |
590 | net2272_ep_write(ep, EP_TRANSFER1, count >> 8); | |
591 | net2272_ep_write(ep, EP_TRANSFER0, count); | |
592 | } | |
593 | ||
594 | struct net2272_request { | |
595 | struct usb_request req; | |
596 | struct list_head queue; | |
597 | unsigned mapped:1, | |
598 | valid:1; | |
599 | }; | |
600 | ||
601 | #endif |