[linux-2.6-block.git] / drivers / usb / gadget / udc / fsl_mxc_udc.c

/*
 * Copyright (C) 2009
 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
 *
 * Description:
 * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
 * driver to function correctly on these systems.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/fsl_devices.h>
#include <linux/platform_device.h>
#include <linux/io.h>

#include "fsl_usb2_udc.h"

static struct clk *mxc_ahb_clk;
static struct clk *mxc_per_clk;
static struct clk *mxc_ipg_clk;

/* workaround ENGcm09152 for i.MX35 */
#define MX35_USBPHYCTRL_OFFSET		0x600
#define USBPHYCTRL_OTGBASE_OFFSET	0x8
#define USBPHYCTRL_EVDO			(1 << 23)

int fsl_udc_clk_init(struct platform_device *pdev)
{
	struct fsl_usb2_platform_data *pdata;
	unsigned long freq;
	int ret;

	pdata = dev_get_platdata(&pdev->dev);

	mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	if (IS_ERR(mxc_ipg_clk)) {
		dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n");
		return PTR_ERR(mxc_ipg_clk);
	}

	mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(mxc_ahb_clk)) {
		dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n");
		return PTR_ERR(mxc_ahb_clk);
	}

	mxc_per_clk = devm_clk_get(&pdev->dev, "per");
	if (IS_ERR(mxc_per_clk)) {
		dev_err(&pdev->dev, "clk_get(\"per\") failed\n");
		return PTR_ERR(mxc_per_clk);
	}

	clk_prepare_enable(mxc_ipg_clk);
	clk_prepare_enable(mxc_ahb_clk);
	clk_prepare_enable(mxc_per_clk);

	/* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
	if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) {
		freq = clk_get_rate(mxc_per_clk);
		if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
		    (freq < 59999000 || freq > 60001000)) {
			dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
			ret = -EINVAL;
			goto eclkrate;
		}
	}

	return 0;

eclkrate:
	clk_disable_unprepare(mxc_ipg_clk);
	clk_disable_unprepare(mxc_ahb_clk);
	clk_disable_unprepare(mxc_per_clk);
	mxc_per_clk = NULL;
	return ret;
}

int fsl_udc_clk_finalize(struct platform_device *pdev)
{
	struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
	int ret = 0;

	/* workaround ENGcm09152 for i.MX35 */
	if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
		unsigned int v;
		struct resource *res = platform_get_resource
			(pdev, IORESOURCE_MEM, 0);
		void __iomem *phy_regs = ioremap(res->start +
						MX35_USBPHYCTRL_OFFSET, 512);
		if (!phy_regs) {
			dev_err(&pdev->dev, "ioremap for phy address fails\n");
			ret = -EINVAL;
			goto ioremap_err;
		}

		v = readl(phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
		writel(v | USBPHYCTRL_EVDO,
			phy_regs + USBPHYCTRL_OTGBASE_OFFSET);

		iounmap(phy_regs);
	}


ioremap_err:
	/* ULPI transceivers don't need usbpll */
	if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
		clk_disable_unprepare(mxc_per_clk);
		mxc_per_clk = NULL;
	}

	return ret;
}

void fsl_udc_clk_release(void)
{
	if (mxc_per_clk)
		clk_disable_unprepare(mxc_per_clk);
	clk_disable_unprepare(mxc_ahb_clk);
	clk_disable_unprepare(mxc_ipg_clk);
}
Commit	Line	Data
54e4026b GL	1	/*
	2	* Copyright (C) 2009
	3	* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
	4	*
	5	* Description:
	6	* Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
	7	* driver to function correctly on these systems.
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*/
	14	#include <linux/clk.h>
	15	#include <linux/delay.h>
	16	#include <linux/err.h>
	17	#include <linux/fsl_devices.h>
	18	#include <linux/platform_device.h>
65cd5c4d	19	#include <linux/io.h>
54e4026b	20
c9d87259 FB	21	#include "fsl_usb2_udc.h"
c9d87259 FB	22
54e4026b	23	static struct clk *mxc_ahb_clk;
ba789170 FE	24	static struct clk *mxc_per_clk;
ba789170 FE	25	static struct clk *mxc_ipg_clk;
54e4026b	26
69cb1ec4	27	/* workaround ENGcm09152 for i.MX35 */
c2c9caa9 PC	28	#define MX35_USBPHYCTRL_OFFSET 0x600
c2c9caa9 PC	29	#define USBPHYCTRL_OTGBASE_OFFSET 0x8
69cb1ec4 EB	30	#define USBPHYCTRL_EVDO (1 << 23)
69cb1ec4 EB	31
54e4026b GL	32	int fsl_udc_clk_init(struct platform_device *pdev)
	33	{
	34	struct fsl_usb2_platform_data *pdata;
	35	unsigned long freq;
	36	int ret;
	37
e01ee9f5	38	pdata = dev_get_platdata(&pdev->dev);
54e4026b	39
ba789170 FE	40	mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	41	if (IS_ERR(mxc_ipg_clk)) {
	42	dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n");
	43	return PTR_ERR(mxc_ipg_clk);
	44	}
54e4026b	45
ba789170 FE	46	mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb");
	47	if (IS_ERR(mxc_ahb_clk)) {
	48	dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n");
	49	return PTR_ERR(mxc_ahb_clk);
54e4026b GL	50	}
54e4026b GL	51
ba789170 FE	52	mxc_per_clk = devm_clk_get(&pdev->dev, "per");
	53	if (IS_ERR(mxc_per_clk)) {
	54	dev_err(&pdev->dev, "clk_get(\"per\") failed\n");
	55	return PTR_ERR(mxc_per_clk);
54e4026b GL	56	}
54e4026b GL	57
ba789170 FE	58	clk_prepare_enable(mxc_ipg_clk);
	59	clk_prepare_enable(mxc_ahb_clk);
	60	clk_prepare_enable(mxc_per_clk);
	61
	62	/* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
f0ea8834	63	if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) {
ba789170	64	freq = clk_get_rate(mxc_per_clk);
73a0bd77 DN	65	if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
	66	(freq < 59999000 \|\| freq > 60001000)) {
	67	dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
	68	ret = -EINVAL;
	69	goto eclkrate;
	70	}
54e4026b GL	71	}
54e4026b GL	72
54e4026b GL	73	return 0;
54e4026b GL	74
54e4026b	75	eclkrate:
ba789170 FE	76	clk_disable_unprepare(mxc_ipg_clk);
	77	clk_disable_unprepare(mxc_ahb_clk);
	78	clk_disable_unprepare(mxc_per_clk);
	79	mxc_per_clk = NULL;
54e4026b GL	80	return ret;
	81	}
	82
c2c9caa9	83	int fsl_udc_clk_finalize(struct platform_device *pdev)
54e4026b	84	{
e01ee9f5	85	struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
c2c9caa9	86	int ret = 0;
f0ea8834 PC	87
	88	/* workaround ENGcm09152 for i.MX35 */
	89	if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
c2c9caa9 PC	90	unsigned int v;
	91	struct resource *res = platform_get_resource
	92	(pdev, IORESOURCE_MEM, 0);
	93	void __iomem *phy_regs = ioremap(res->start +
	94	MX35_USBPHYCTRL_OFFSET, 512);
	95	if (!phy_regs) {
	96	dev_err(&pdev->dev, "ioremap for phy address fails\n");
	97	ret = -EINVAL;
	98	goto ioremap_err;
	99	}
	100
	101	v = readl(phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
f0ea8834	102	writel(v \| USBPHYCTRL_EVDO,
c2c9caa9 PC	103	phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
	104
	105	iounmap(phy_regs);
69cb1ec4	106	}
54e4026b	107
c2c9caa9 PC	108
c2c9caa9 PC	109	ioremap_err:
54e4026b GL	110	/* ULPI transceivers don't need usbpll */
54e4026b GL	111	if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
ba789170 FE	112	clk_disable_unprepare(mxc_per_clk);
ba789170 FE	113	mxc_per_clk = NULL;
54e4026b	114	}
c2c9caa9 PC	115
c2c9caa9 PC	116	return ret;
54e4026b GL	117	}
	118
	119	void fsl_udc_clk_release(void)
	120	{
ba789170 FE	121	if (mxc_per_clk)
	122	clk_disable_unprepare(mxc_per_clk);
	123	clk_disable_unprepare(mxc_ahb_clk);
	124	clk_disable_unprepare(mxc_ipg_clk);
54e4026b	125	}